Magnetic memory device and preparation method thereof
By setting up a multi-layer dielectric layer structure in the magnetic memory device and controlling the etching rate, the problem of top metal overetching is solved, the stability and storage density of the device are improved, and the reliability risks and production costs are reduced.
Patent Information
- Application Number
- CN202311012500.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-10
- Publication Date
- 2025-02-18
AI Technical Summary
During the production of magnetic memory devices, the overetching problem of the top metal leads to irregular morphology of the dielectric layer, affecting the reliability and storage density of the device.
By providing a multi-layer dielectric layer structure in the array region and the logic region, including a first dielectric layer, a second dielectric layer and a third dielectric layer, and controlling the etching rate of the first dielectric layer to the second and third dielectric layers More than five times to avoid overetching.
It effectively avoids overetching of top metal, improves device stability and storage density, and reduces the number of masks used, reducing reliability risks and production costs.
Smart Images
Figure CN119486573A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the semiconductor field, and in particular to a magnetic storage device and a preparation method thereof. Background Art
[0002] In magnetic memory devices, the top metal width is usually larger than the diameter of the magnetic tunnel junction (MTJ), which results in over-etching in the dielectric layer around the MTJ when etching the top metal groove, making the etching morphology irregular, affecting the subsequent metal barrier layer and metal filling, and thus affecting the device reliability.
[0003] In order to prevent the top metal from being over-etched, the top electrode diameter can usually be increased. A larger top electrode can prevent over-etching of the dielectric layer to a certain extent. However, when making a larger top electrode, an additional mask is required. At the same time, after the top electrode is etched, it will affect the surrounding dielectric filling, resulting in reliability failure, which is not conducive to improving the density of magnetic storage devices.
[0004] Therefore, how to solve the above technical problems should be the focus of technical personnel in this field. Summary of the invention
[0005] The purpose of the present application is to provide a magnetic storage device and a method for preparing the same, so as to improve the stability and storage density of the device and reduce the number of masks used.
[0006] In order to solve the above technical problems, the present application provides a magnetic storage device, including an array area and a logic area; wherein:
[0007] The array region includes a magnetic tunnel junction, a top electrode, a top metal, a first dielectric layer, a second dielectric layer, and a third dielectric layer; the logic region includes a logic via, a top metal, a first dielectric layer, and a second dielectric layer;
[0008] The first dielectric layer and the second dielectric layer surround the top metal of the array region and the logic region, the third dielectric layer surrounds at least the sidewalls of the magnetic tunnel junction and the top electrode, and the second dielectric layer surrounds the magnetic tunnel junction, the top electrode and the logic via;
[0009] The etching rate of the first dielectric layer is more than five times the etching rates of the second dielectric layer and the third dielectric layer.
[0010] Optionally, also include:
[0011] A bottom electrode is disposed in the array region, and the bottom electrode is disposed on the lower surface of the magnetic tunnel junction.
[0012] Optionally, the size of the bottom electrode is equal to the size of the magnetic tunnel junction.
[0013] Optionally, the size of the bottom electrode is larger than the size of the magnetic tunnel junction.
[0014] Optionally, when the third dielectric layer is only located in the array region, the third dielectric layer surrounds the side walls of the magnetic tunnel junction and the top electrode, and is distributed on the upper surface of the bottom electrode.
[0015] Optionally, a projection boundary of the bottom electrode on the horizontal plane coincides with a projection outer boundary of the third dielectric layer on the horizontal plane.
[0016] Optionally, a projection boundary of the bottom electrode on the horizontal plane is located within a projection outer boundary range of the third dielectric layer on the horizontal plane.
[0017] Optionally, the third dielectric layer surrounds the sidewalls of the magnetic tunnel junction and the top electrode, and surrounds the logic via.
[0018] Optionally, a lower surface of the third dielectric layer is lower than a lower surface of the magnetic tunnel junction.
[0019] Optionally, a lower surface of the third dielectric layer is flush with a lower surface of the magnetic tunnel junction.
[0020] Optionally, the top metal in the array area and the top metal in the logic area are of equal height.
[0021] The present application also provides a method for preparing a magnetic storage device, comprising:
[0022] Prepare a device prefabricated structure; wherein the device prefabricated structure includes an array area and a logic area, the array area includes a magnetic tunnel junction, a top electrode, a second dielectric layer and a third dielectric layer, the logic area includes a second dielectric layer and a through hole; the third dielectric layer at least surrounds the side walls of the magnetic tunnel junction and the top electrode, and the upper surface of the top electrode, the through hole penetrates the second dielectric layer; the upper surface of the second dielectric layer is not lower than the upper surface of the third dielectric layer;
[0023] Fabricating a first dielectric layer in the through hole and on the upper surfaces of the array area and the logic area;
[0024] Etching the first dielectric layer to form top metal grooves in the array area and the logic area, and etching and removing the first dielectric layer in the through hole; the etching rate of the first dielectric layer is more than five times the etching rate of the second dielectric layer and the third dielectric layer, and the etching is stopped to the upper surface of the second dielectric layer and the third dielectric layer in the array area, and the etching is stopped to the upper surface of the second dielectric layer in the logic area;
[0025] At least etching the third dielectric layer located on the upper surface of the top electrode, and etching the fourth dielectric layer between the through hole and the bottom metal;
[0026] Metal is deposited in the through hole and the top metal groove to form a logic through hole and a top metal in the logic area and a top metal in the array area.
[0027] Optionally, before forming the first dielectric layer in the through hole and on the upper surface of the array area and the logic area, the method further comprises:
[0028] Depositing a first etch stop layer on the surface of the device prefabricated structure;
[0029] Accordingly, etching the first dielectric layer to form top metal grooves in the array area and the logic area includes:
[0030] The first dielectric layer and the first etch stop layer are etched to form top metal recesses in the array region and the logic region.
[0031] Optionally, preparing a device prefabricated structure includes:
[0032] Prepare the magnetic tunnel junction and the top electrode in the array area;
[0033] forming the third dielectric layer in the array region;
[0034] forming a second dielectric layer in the array region and the logic region;
[0035] A through hole is formed in the logic area.
[0036] Optionally, after forming the second dielectric layer in the array area and the logic area, the method further comprises:
[0037] Depositing a second etch stop layer on the surface of the second dielectric layer in the array area and the logic area and on the surface of the third dielectric layer;
[0038] Accordingly, etching the first dielectric layer to form top metal grooves in the array area and the logic area includes:
[0039] The first dielectric layer and the second etch stop layer are etched to form top metal recesses in the array region and the logic region.
[0040] Optionally, an upper surface of the second dielectric layer is higher than an upper surface of the third dielectric layer.
[0041] A magnetic memory device provided in the present application includes an array area and a logic area; wherein the array area includes a magnetic tunnel junction, a top electrode, a top metal, a first dielectric layer, a second dielectric layer and a third dielectric layer; the logic area includes a logic through hole, a top metal, a first dielectric layer and a second dielectric layer; the first dielectric layer and the second dielectric layer surround the top metal in the array area and the logic area, the third dielectric layer at least surrounds the side walls of the magnetic tunnel junction and the top electrode, and the second dielectric layer surrounds the magnetic tunnel junction, the top electrode and the logic through hole; the etching rate of the first dielectric layer is more than five times the etching rate of the second dielectric layer and the third dielectric layer.
[0042] It can be seen that in the array area and logic area of the magnetic storage device of the present application, the top metal is surrounded by the first dielectric layer and the second dielectric layer, and the sidewalls of the magnetic tunnel junction and the top electrode are surrounded by the third dielectric layer. Since the etching rate of the first dielectric layer is more than five times that of the second dielectric layer and the third dielectric layer, the etching rate of the first dielectric layer is relatively large, so when etching to form the top metal groove, over-etching can be avoided, that is, etching to the second dielectric layer around the top electrode and the third dielectric layer can be avoided, thereby improving the control window of the top metal etching, making the top metal structure more regular, and reducing the reliability risk. In addition, in the present application, it is not necessary to make large-sized top electrodes and through holes in the array area, so as to avoid affecting the dielectric filling between the magnetic tunnel junctions, which is conducive to improving the storage density; at the same time, it is also not necessary to make a large-sized top electrode mask, thereby reducing the reliability risk and manufacturing cost.
[0043] In addition, the present application also provides a preparation method having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0045] Figures 1 to 5 Schematic diagrams of different structures of magnetic storage devices provided in embodiments of the present application;
[0046] Figure 6 A flow chart of a method for preparing a magnetic storage device provided in an embodiment of the present application;
[0047] Figures 7 to 23 A process flow chart of a magnetic storage device method provided in an embodiment of the present application;
[0048] In the figure, 1, magnetic tunnel junction, 2, top electrode, 3, top metal, 4, first dielectric layer, 5, second dielectric layer, 6, third dielectric layer, 7, logic through hole, 8, bottom metal, 9, bottom through hole, 10, fourth dielectric layer, 11, fifth dielectric layer, 12, sixth dielectric layer, 13, bottom electrode, 14, through hole, 15, photoresist, 16, metal layer, 17, first etch stop layer, 18, second etch stop layer. DETAILED DESCRIPTION
[0049] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.
[0050] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0051] As described in the background technology section, currently the top metal over-etching can be prevented by increasing the top electrode diameter. When making a larger top electrode, an additional mask is required. At the same time, after the top electrode is etched, it will affect the surrounding dielectric filling, resulting in reliability failure, which is not conducive to improving the density of the magnetic storage device.
[0052] In view of this, the present application provides a magnetic storage device, please refer to Figure 1 to Figure 2 , including an array area and a logic area; wherein,
[0053] The array region includes a magnetic tunnel junction 1, a top electrode 2, a top metal 3, a first dielectric layer 4, a second dielectric layer 5, and a third dielectric layer 6; the logic region includes a logic through hole 7, a top metal 3, a first dielectric layer 4, and a second dielectric layer 5;
[0054] The first dielectric layer 4 and the second dielectric layer 5 surround the top metal 3 in the array area and the logic area, the third dielectric layer 6 surrounds at least the sidewalls of the magnetic tunnel junction 1 and the top electrode 2, and the second dielectric layer 5 surrounds the magnetic tunnel junction 1, the top electrode 2 and the logic through hole 7;
[0055] The etching rate of the first dielectric layer 4 is more than five times the etching rate of the second dielectric layer 5 and the third dielectric layer 6 .
[0056] It should be noted that the array area also includes bottom metal 8, bottom via 9, fourth dielectric layer 10, fifth dielectric layer 11 and sixth dielectric layer 12; the logic area also includes bottom metal 8, fourth dielectric layer 10, fifth dielectric layer 11 and sixth dielectric layer 12. The sixth dielectric layer 12 surrounds the bottom metal 8 of the array area and the logic area; in the logic area, the second dielectric layer 5, third dielectric layer 6, fourth dielectric layer 10 and fifth dielectric layer 11 surround the logic via 7; in the array area, the fourth dielectric layer 10 and fifth dielectric layer 11 surround the bottom via 9.
[0057] The bottom metal 8 of the logic area is electrically connected to the logic through hole 7. Usually, the metal of the logic through hole 7 is the same as the material of the top metal 3. The bottom through hole 9 of the array area is electrically connected to the bottom metal 8.
[0058] The size of the logic through hole 7 is smaller than or equal to the size of the bottom metal 8 of the logic area, and the top size of the logic through hole 7 is larger than or equal to the bottom size of the logic through hole 7 .
[0059] The materials of the bottom metal 8 , the bottom via 9 , the logic via 7 , and the top metal 3 include but are not limited to Cu, W, Ru, Co, Al, and the like.
[0060] The material of the first dielectric layer 4 may be a low-k material, and the material of the first dielectric layer 4 includes at least Si and O, and may also include C, N, and H. The materials of the second dielectric layer 5, the third dielectric layer 6, the fourth dielectric layer 10, and the fifth dielectric layer 11 include at least Si and O, and may also include C and N.
[0061] The third dielectric layer 6 and the fourth dielectric layer 10 function to reduce metal diffusion.
[0062] The etching rate of the first dielectric layer 4 is more than five times that of the second dielectric layer 5 and the third dielectric layer 6, that is, the etching rate of the first dielectric layer 4 is much greater than that of the second dielectric layer 5 and the third dielectric layer 6. When manufacturing the top metal 3, it is possible to avoid etching downward to the second dielectric layer 5 around the top electrode 2 and the third dielectric layer 6, thereby improving the control window of etching the top metal 3, making the top metal 3 structure more regular, and reducing reliability risks;
[0063] The third dielectric layer 6 may only surround the sidewalls of the magnetic tunnel junction 1 and the top electrode 2, such as Figure 1 As shown, the third dielectric layer 6 may also be distributed at other locations in the array region, and may also surround the logic through hole 7, which will be specifically described in the following embodiments.
[0064] As an implementation method, the magnetic storage device further includes: a bottom electrode 13 disposed in the array region, and the bottom electrode 13 is disposed on the lower surface of the magnetic tunnel junction 1. However, the present application does not specifically limit this, and the magnetic storage device may not be provided with the bottom electrode 13, such as Figure 2 shown.
[0065] When the magnetic memory device is provided with a bottom electrode 13, as an implementation method, the size of the bottom electrode 13 is equal to the size of the magnetic tunnel junction 1. Alternatively, as another implementation method, the size of the bottom electrode 13 is larger than the size of the magnetic tunnel junction 1.
[0066] In one embodiment of the present application, the heights of the top metal 3 in the array area and the logic area are equal. During the preparation process, the through hole in the logic area and the groove of the top metal 3 can be made separately. After the through hole in the logic area is prepared separately, the depth of the top metal 3 groove in the array area and the logic area is consistent, which can reduce the difficulty of etching.
[0067] In the array area and logic area of the magnetic storage device of this embodiment, the top metal 3 is surrounded by the first dielectric layer 4 and the second dielectric layer 5, and the sidewalls of the magnetic tunnel junction 1 and the top electrode 2 are surrounded by the third dielectric layer 6. Since the etching rate of the first dielectric layer 4 is more than five times the etching rate of the second dielectric layer 5 and the third dielectric layer 6, the etching rate of the first dielectric layer 4 is relatively large, so when etching to form the groove of the top metal 3, over-etching can be avoided, that is, etching to the second dielectric layer 5 around the top electrode 2 and the third dielectric layer 6 is avoided, the control window of the top metal 3 etching is improved, the top metal 3 structure is more regular, and the reliability risk is reduced. In addition, in this application, it is not necessary to make a large-sized top electrode 2 and a through hole in the array area, so as to avoid affecting the dielectric filling between the magnetic tunnel junction 1, which is conducive to improving the storage density; at the same time, it is also not necessary to make a large-sized top electrode 2 mask, which reduces the reliability risk.
[0068] Based on any of the above embodiments, in one embodiment of the present application, when the magnetic memory device is provided with a bottom electrode 13, the size of the bottom electrode 13 is larger than the size of the magnetic tunnel junction 1, and when the third dielectric layer 6 is only located in the array area, the third dielectric layer 6 surrounds the side walls of the magnetic tunnel junction 1 and the top electrode 2, and is distributed on the upper surface of the bottom electrode 13.
[0069] In this embodiment, the distribution range of the third dielectric layer 6 is not limited and can be set at will.
[0070] As an implementation method, Figure 3 As shown, the projection boundary of the bottom electrode 13 on the horizontal plane coincides with the projection outer boundary of the third dielectric layer 6 on the horizontal plane.
[0071] As another possible implementation, the projection boundary of the bottom electrode 13 on the horizontal plane is located within the projection outer boundary range of the third dielectric layer 6 on the horizontal plane.
[0072] Since the third dielectric layer 6 surrounds the magnetic tunnel junction 1 and the top electrode 2, the projection of the third dielectric layer 6 on the horizontal plane is a ring, and the outer boundary of the projection of the third dielectric layer 6 on the horizontal plane is the outer edge of the ring.
[0073] Based on any of the above embodiments, in one embodiment of the present application, the third dielectric layer 6 surrounds the side walls of the magnetic tunnel junction 1 and the top electrode 2 , and surrounds the logic through hole 7 .
[0074] As an implementation option, please refer to Figure 2 and Figure 4 , the lower surface of the third dielectric layer 6 is flush with the lower surface of the magnetic tunnel junction 1 .
[0075] As another possible implementation, please refer to Figure 5 , the lower surface of the third dielectric layer 6 is lower than the lower surface of the magnetic tunnel junction 1 .
[0076] Please refer to Figure 6 The present application also provides a method for preparing a magnetic storage device, comprising:
[0077] Step S101: preparing a device prefabricated structure;
[0078] Please refer to Figure 7 and Figure 8The device prefabricated structure includes an array area and a logic area, the array area includes a magnetic tunnel junction 1, a top electrode 2, a second dielectric layer 5 and a third dielectric layer 6, the logic area includes a second dielectric layer 5 and a through hole 14; the third dielectric layer 6 at least surrounds the side walls of the magnetic tunnel junction 1 and the top electrode 2, and the upper surface of the top electrode 2, and the through hole 14 passes through the second dielectric layer 5; the upper surface of the second dielectric layer 5 is not lower than the upper surface of the third dielectric layer 6.
[0079] The array area further includes a bottom metal 8 , a bottom via 9 , a fourth dielectric layer 10 , a fifth dielectric layer 11 and a sixth dielectric layer 12 ; the logic area further includes a bottom metal 8 , a fourth dielectric layer 10 , a fifth dielectric layer 11 and a sixth dielectric layer 12 .
[0080] It should be noted that Figure 7 and Figure 8 In the example, the array region includes the bottom electrode 13 and the logic region also includes the third dielectric layer 6. When the array region does not include the bottom electrode 13, the logic region does not include the third dielectric layer 6, and the third dielectric layer 6 is not distributed on the upper surface of the bottom electrode 13, according to Figure 7 and Figure 8 Just make the corresponding modifications.
[0081] exist Figure 7 In the embodiment, the upper surface of the second dielectric layer 5 is flush with the upper surface of the third dielectric layer 6. Figure 8 In the embodiment, the upper surface of the second dielectric layer 5 is higher than the upper surface of the third dielectric layer 6.
[0082] When the logic area does not include the third dielectric layer 6 , this can be achieved by etching back after depositing the third dielectric layer 6 .
[0083] The deposition methods of the second dielectric layer 5 , the third dielectric layer 6 , the fourth dielectric layer 10 , the fifth dielectric layer 11 and the sixth dielectric layer 12 include but are not limited to sputtering, chemical vapor deposition and atomic layer deposition.
[0084] Step S102: forming a first dielectric layer in the through hole and on the upper surfaces of the array area and the logic area.
[0085] The first dielectric layer manufacturing process in this step includes:
[0086] Step S1021: depositing a first dielectric layer 4 in the through hole 14 and on the upper surface of the array area and the logic area, such as Fig. 9 and Fig.10 shown.
[0087] The through hole 14 of the logic area is blocked, and the first dielectric layer 4 may be filled or there may be a hole inside the through hole 14. The first dielectric layer 4 may be deposited by, but is not limited to, sputtering, chemical vapor deposition, atomic layer deposition, and the like.
[0088] Step S1022: As an implementation method, Fig.11 As shown, the surface of the first dielectric layer 4 is processed to be flat, wherein the processing method includes but is not limited to chemical mechanical polishing (CMP) and etching. Or, as another possible implementation method, as Fig.12 and 13 As shown, the first dielectric layer 4 on the surface of the second dielectric layer 5 and the third dielectric layer 6 is completely removed by CMP or etching, and then the first dielectric layer 4 is deposited on the surface of the second dielectric layer 5 and the third dielectric layer 6 .
[0089] The second method (removing the first dielectric layer 4 first and then depositing) is beneficial to improving the surface roughness of the second dielectric layer 5 and the third dielectric layer 6, and can more accurately control the thickness of the first dielectric layer 4.
[0090] It should be noted that Figures 11 to 13 So Fig. 9 The following steps are shown as an example, and the figures in the following steps continue to be shown based on this structure. Fig.10 The structure shown can also be processed in the two ways of this step.
[0091] Step S103: etching the first dielectric layer to form top metal grooves in the array area and the logic area, and etching away the first dielectric layer in the through hole;
[0092] The etching rate of the first dielectric layer is more than five times the etching rate of the second dielectric layer and the third dielectric layer. The etching stops at the upper surface of the second dielectric layer and the third dielectric layer in the array area, and stops at the upper surface of the second dielectric layer in the logic area.
[0093] Step S1031: Fig.14 As shown, a photoresist 15 having a top metal 3 pattern is formed on the surface of the first dielectric layer 4;
[0094] The size of the groove of the top metal 3 in the array area is larger than the size of the third dielectric layer 6 located at the top electrode 2 , and the size of the groove of the top metal 3 in the logic area is larger than the size of the through hole 14 .
[0095] Step S1032: Fig.15As shown, the first dielectric layer 4 is etched using an etching method with a large etching selectivity ratio, stopping at the upper surface or inside of the second dielectric layer 5 and the third dielectric layer 6 in the array area, and stopping at the upper surface or inside of the second dielectric layer 5 in the logic area.
[0096] Step S104: at least etching away the third dielectric layer located on the upper surface of the top electrode, and etching away the fourth dielectric layer between the through hole and the bottom metal.
[0097] As an implementation method, Fig.16 As shown, synchronous downward etching is performed to etch the second dielectric layer 5, the third dielectric layer 6, the fourth dielectric layer 10, and the fifth dielectric layer 11 in the logic area, and the second dielectric layer 5 and the third dielectric layer 6 are etched in the array area; wherein the etching method may be IBE (Ion Beam Etching), or RIE (Reactive Ion Etching) with a low etching ratio and a low etching rate for etching the second dielectric layer 5, the third dielectric layer 6, and the fourth dielectric layer 10, or a combination of IBE and RIE. The etching gas may be one or more of Ar, O2, Cl2, HBr, CF4, CHF3, and CH2F2.
[0098] During etching, the fourth dielectric layer 10, the third dielectric layer 6 and the second dielectric layer 5 have a larger etching selectivity, and the etching rate of the fourth dielectric layer 10 and the third dielectric layer 6 is faster; alternatively, the etching selectivity of the fourth dielectric layer 10, the third dielectric layer 6 and the second dielectric layer 5 is basically the same, and the etching rate is low.
[0099] As another possible implementation, Fig.17 As shown, RIE etching with a relatively large etching selectivity is used, wherein the etching rate of the third dielectric layer 6 and the fourth dielectric layer 10 is higher than that of the second dielectric layer 5 .
[0100] In this step, the etching of the array area stops at the top electrode 2, and the etching of the logic area stops at the upper surface of the bottom metal 8.
[0101] After etching is completed, the photoresist 15 is removed.
[0102] Step S105: depositing metal in the through hole and the top metal groove, forming a logic through hole and a top metal in the logic area, and forming a top metal in the array area.
[0103] Below Fig.16 The structure shown illustrates the process of forming the top metal and logic vias.
[0104] Step S1051: Fig.18As shown, a metal layer 16 is deposited in the through hole of the logic area and the top metal 3 grooves of the logic area and the array area, and the upper surface of the metal layer 16 is higher than the upper surface of the first dielectric layer 4;
[0105] Step S1052: Fig.19 As shown, a portion of the metal layer 16 and the first dielectric layer 4 are removed ( Fig.19 The height of the first dielectric layer 4 is less than Fig.18 A top metal 3 is formed in the array area, and a top metal 3 and a logic through hole 7 are formed in the logic area.
[0106] In the magnetic storage device prepared in this embodiment, in the array area and the logic area, the top metal is surrounded by the first dielectric layer and the second dielectric layer, and the sidewalls of the magnetic tunnel junction and the top electrode are surrounded by the third dielectric layer. Since the etching rate of the first dielectric layer is more than five times that of the second dielectric layer and the third dielectric layer, the etching rate of the first dielectric layer is relatively large, so when etching to form the top metal groove, over-etching can be avoided, that is, etching to the second dielectric layer around the top electrode and the third dielectric layer can be avoided, thereby improving the control window of the top metal etching, making the top metal structure more regular, and reducing the reliability risk. In addition, in this application, it is not necessary to make a large-sized top electrode and a through hole in the array area, so as to avoid affecting the dielectric filling between the magnetic tunnel junctions, which is conducive to improving the storage density; at the same time, it is also not necessary to make a large-sized top electrode mask, thereby reducing the reliability risk.
[0107] On the basis of the above embodiment, in one embodiment of the present application, before forming the first dielectric layer in the through hole and on the upper surface of the array area and the logic area, the method further includes:
[0108] Depositing a first etch stop layer on the surface of the device prefabricated structure;
[0109] Accordingly, etching the first dielectric layer to form top metal grooves in the array area and the logic area includes:
[0110] The first dielectric layer and the first etch stop layer are etched to form top metal recesses in the array region and the logic region.
[0111] like Fig. 20 As shown, the first etch stop layer 17 is distributed on the surfaces of the second dielectric layer 5 and the third dielectric layer 6, and in the through holes of the logic area.
[0112] The material of the first etch stop layer 17 includes at least Si and N, and may also include O, H, and C. The thickness of the first etch stop layer 17 is 1-100 nm.
[0113] In this embodiment, by manufacturing the first etching stop layer 17, the etching ratio can be improved and the etching stop position can be easily controlled.
[0114] Based on any of the above embodiments, in one embodiment of the present application, preparing a device prefabricated structure includes:
[0115] Step S201: preparing the magnetic tunnel junction and the top electrode in the array area.
[0116] Step S202: manufacturing the third dielectric layer in the array region.
[0117] Step S203: manufacturing a second dielectric layer in the array area and the logic area.
[0118] For example, the array region includes the bottom electrode 13 and the logic region also includes the third dielectric layer 6. Fig.21 As shown, the logic area includes bottom metal 8, sixth dielectric layer 12, fourth dielectric layer 10, fifth dielectric layer 11, third dielectric layer 6, and second dielectric layer 5, and the array area includes bottom metal 8, bottom via 9, bottom electrode 13, magnetic tunnel junction 1, top electrode 2, sixth dielectric layer 12, fourth dielectric layer 10, fifth dielectric layer 11, third dielectric layer 6, and second dielectric layer 5. The third dielectric layer 6 is also distributed on the upper surface of the top electrode 2.
[0119] After depositing the second dielectric layer 5 , the surfaces of the third dielectric layer 6 and the second dielectric layer 5 are polished flat by CMP or etching, stopping at the upper surface or inside of the third dielectric layer 6 on the top of the top electrode 2 .
[0120] Step S204: making a through hole in the logic area.
[0121] like Fig. 22 As shown, a photoresist 15 having a through-hole pattern of a logic area is first made on the device surface, and then the logic area is etched on the upper surface or inside of the fourth dielectric layer 10. After the etching is completed, the photoresist 15 is removed.
[0122] On the basis of the above embodiment, in one embodiment of the present application, after the second dielectric layer is formed in the array area and the logic area, the method further includes:
[0123] Depositing a second etch stop layer on the surface of the second dielectric layer in the array area and the logic area and on the surface of the third dielectric layer;
[0124] Accordingly, etching the first dielectric layer to form top metal grooves in the array area and the logic area includes:
[0125] The first dielectric layer and the second etch stop layer are etched to form top metal recesses in the array region and the logic region.
[0126] like Fig.23 As shown, the second etch stop layer 18 is located on the surfaces of the second dielectric layer 5 and the third dielectric layer 6 .
[0127] The material of the second etch stop layer 18 includes at least Si and N, and may also include O, H, and C. The thickness of the second etch stop layer 18 is 1-100 nm.
[0128] In this embodiment, by providing the second etch stop layer 18, the etching ratio can be improved and the etching stop position can be easily controlled.
[0129] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0130] The magnetic storage device and the preparation method thereof provided by the present application are introduced in detail above. The principle and implementation method of the present application are explained in this article by using specific examples. The description of the above embodiments is only used to help understand the method and the core idea of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.
Claims
1. A magnetic storage device, characterized in that: It includes an array area and a logic area; wherein, The array region includes a magnetic tunnel junction, a top electrode, a top metal, a first dielectric layer, a second dielectric layer, and a third dielectric layer; the logic region includes a logic via, a top metal, a first dielectric layer, and a second dielectric layer; The first dielectric layer and the second dielectric layer surround the top metal of the array region and the logic region, the third dielectric layer surrounds at least the sidewalls of the magnetic tunnel junction and the top electrode, and the second dielectric layer surrounds the magnetic tunnel junction, the top electrode and the logic via; The etching rate of the first dielectric layer is more than five times the etching rates of the second dielectric layer and the third dielectric layer.
2. The magnetic memory device according to claim 1, wherein: Also includes: A bottom electrode is disposed in the array region, and the bottom electrode is disposed on the lower surface of the magnetic tunnel junction.
3. The magnetic memory device according to claim 2, wherein: The size of the bottom electrode is equal to the size of the magnetic tunnel junction.
4. The magnetic memory device according to claim 2, wherein: The size of the bottom electrode is larger than the size of the magnetic tunnel junction.
5. The magnetic memory device according to claim 4, characterized in that: When the third dielectric layer is only located in the array region, the third dielectric layer surrounds the sidewalls of the magnetic tunnel junction and the top electrode, and is distributed on the upper surface of the bottom electrode.
6. The magnetic memory device according to claim 5, characterized in that: A projection boundary of the bottom electrode on a horizontal plane coincides with a projection outer boundary of the third dielectric layer on a horizontal plane.
7. The magnetic memory device according to claim 5, characterized in that: The projection boundary of the bottom electrode on the horizontal plane is located within the projection outer boundary of the third dielectric layer on the horizontal plane.
8. The magnetic memory device according to claim 1, wherein: The third dielectric layer surrounds the sidewalls of the magnetic tunnel junction and the top electrode, and surrounds the logic via.
9. The magnetic memory device according to claim 8, characterized in that: A lower surface of the third dielectric layer is lower than a lower surface of the magnetic tunnel junction.
10. The magnetic memory device according to claim 8, wherein: A lower surface of the third dielectric layer is flush with a lower surface of the magnetic tunnel junction.
11. The magnetic memory device according to any one of claims 1 to 10, characterized in that: The heights of the top metals in the array region and the logic region are equal.
12. A method for preparing a magnetic storage device, characterized in that: include: Prepare a device prefabricated structure; wherein the device prefabricated structure includes an array area and a logic area, the array area includes a magnetic tunnel junction, a top electrode, a second dielectric layer and a third dielectric layer, the logic area includes a second dielectric layer and a through hole; the third dielectric layer at least surrounds the side walls of the magnetic tunnel junction and the top electrode, and the upper surface of the top electrode, the through hole penetrates the second dielectric layer; the upper surface of the second dielectric layer is not lower than the upper surface of the third dielectric layer; Fabricating a first dielectric layer in the through hole and on the upper surfaces of the array area and the logic area; Etching the first dielectric layer to form top metal grooves in the array area and the logic area, and etching and removing the first dielectric layer in the through hole; the etching rate of the first dielectric layer is more than five times the etching rate of the second dielectric layer and the third dielectric layer, and the etching is stopped to the upper surface of the second dielectric layer and the third dielectric layer in the array area, and the etching is stopped to the upper surface of the second dielectric layer in the logic area; At least etching the third dielectric layer located on the upper surface of the top electrode, and etching the fourth dielectric layer between the through hole and the bottom metal; Metal is deposited in the through hole and the top metal groove to form a logic through hole and a top metal in the logic area and a top metal in the array area.
13. The method for preparing a magnetic memory device according to claim 12, wherein: Before forming the first dielectric layer in the through hole and on the upper surface of the array area and the logic area, the method further comprises: Depositing a first etch stop layer on the surface of the device prefabricated structure; Accordingly, etching the first dielectric layer to form top metal grooves in the array area and the logic area includes: The first dielectric layer and the first etch stop layer are etched to form top metal recesses in the array region and the logic region.
14. The method for preparing a magnetic memory device according to claim 12, wherein: Preparing the device prefabricated structure includes: Prepare the magnetic tunnel junction and the top electrode in the array area; forming the third dielectric layer in the array region; forming a second dielectric layer in the array region and the logic region; A through hole is formed in the logic area.
15. The method for preparing a magnetic memory device according to claim 14, characterized in that: After forming the second dielectric layer in the array area and the logic area, the method further comprises: Depositing a second etch stop layer on the surface of the second dielectric layer in the array area and the logic area and on the surface of the third dielectric layer; Accordingly, etching the first dielectric layer to form top metal grooves in the array area and the logic area includes: The first dielectric layer and the second etch stop layer are etched to form top metal recesses in the array region and the logic region.
16. The method for preparing a magnetic memory device according to any one of claims 11 to 15, characterized in that: An upper surface of the second dielectric layer is higher than an upper surface of the third dielectric layer.