High density 3d magnetic memory device

Abstract

A 3D magnetic memory device includes a stack having dielectric layers and silicon-based layers arranged alternately, and a magnetic material channel formed through the stack. The channel has a first diameter at which it extends through the silicon-based layer and a second diameter at which it extends through the dielectric layer. Pinning sites defined by layers are formed in the channel, each pinning site configured to store one magnetic potential. A first metal layer is disposed on the first end of the channel and the stack. A magnetic tunnel junction (MTJ) and a first electrode are arranged on the first metal layer at a distance from each other. The first metal layer is configured as a spin-orbit torque (SOT) orbit, or the second metal layer is configured as a SOT orbit, where the second end of the channel and the stack are disposed on the second metal layer.

Description

Technical Field

[0001] This disclosure relates to magnetic memory devices. In particular, this disclosure proposes a novel magnetic memory device that can achieve high memory density (bit density). The magnetic memory device of this disclosure is based on a spin orbit torque (SOT) magnetic random access memory (MRAM) device architecture. Background Technology

[0002] In today's complex microelectronics landscape, various memory technologies are employed to meet system-level speed and density requirements. For example, fast on-chip static random access memory (SRAM) is typically placed near the central processing unit (CPU) due to its high operating speed, even with very limited areal density. Dynamic random access memory (DRAM) serves as a denser but slower volatile working memory. Further down the hierarchy, 3D-NAND memory finds application in solid-state drives (SSDs) and similar media, providing affordable high-capacity storage, but with slower read and write speeds.

[0003] Over the past decade, several new memory technologies have competed for positions at various levels of the memory pyramid. Spin transfer torque (STT) MRAM is one such technology. STT-MRAM is a resistive memory that utilizes a magnetic tunnel junction (MTJ) to encode data in the magnetic orientation of the free layer relative to a reference layer with a fixed orientation. The tunnel magnetoresistance (TMR) effect provides different resistance states depending on whether the magnetization of the free layer and the reference layer is parallel or antiparallel aligned.

[0004] STT-MRAM is considered an embedded memory (built on the same die as the logic circuitry) due to its relatively fast operating speed (as low as a few nanoseconds), robust endurance, and compatibility with advanced complementary metal-oxide-semiconductor (CMOS) voltages. It also provides non-volatility by storing bits in a magnetic state, thus offering improved leakage power compared to alternatives in SRAM and DRAM.

[0005] Various styles of magnetic memories exist, with STT-MRAM being the most advanced, but SOT-MRAM and voltage-controlled MRAM are potential next-generation candidates with the potential for faster speed and / or lower power operation. However, all of these magnetic memories are based on MTJ technology. Since the MRAM stack itself is a complex collection of more than 20 individual ultrathin layers, physical vapor deposition (PVD) is required, which necessitates planar implementation.

[0006] While the aforementioned MRAM technology makes a good candidate for SRAM replacement or on-chip memory, the planar configuration ultimately limits the achievable memory density, thus restricting its application to embedded memory technologies with limited current density. For the other parts of the memory pyramid, MRAM would have to utilize a third dimension to potentially increase memory density by approximately 100 times, while ideally retaining and controlling the known advantages of MRAM regarding speed and endurance. Summary of the Invention

[0007] In view of the above, this disclosure aims to provide a novel magnetic memory device based on MRAM. The objective is particularly to utilize all three dimensions, namely, to deviate from the planar configuration. Therefore, the ultimate goal is to significantly increase the achievable memory density for storing more information in the magnetic memory device.

[0008] A first aspect of this disclosure provides a 3D magnetic memory device comprising: a stack including a plurality of dielectric layers and a silicon substrate arranged alternately to each other; a magnetic material channel formed through the stack, wherein the magnetic material channel extends through each layer of the stack, wherein the magnetic material channel has a first diameter where it extends through the silicon substrate and a second diameter where it extends through the dielectric layers of the stack, and wherein a plurality of pinning sites defined by the plurality of layers of the stack are formed in the magnetic material channel, each pinning site being configured to store a magnetic potential; a first metal layer disposed on a first end of the magnetic material channel and on the last layer of the stack; a magnetic tunnel junction (MTJ) disposed on the first metal layer; and a first electrode disposed on the first metal layer at a distance from the MTJ; wherein the first metal layer is configured as a spin-orbit torque (SOT) orbital, or the magnetic memory device includes a second metal layer configured as an SOT orbital, and a second end of the magnetic material channel and the first layer of the stack are disposed on the second metal layer.

[0009] Magnetic material channels can be memory cells of the magnetic memory device of the first aspect. The magnetic memory device can include multiple such magnetic material channels formed in multiple stacks in the same manner as described above, to realize multiple memory cells of the magnetic memory device. Thus, the multiple magnetic material channels can be arranged parallel to each other and / or can be arranged as an array of magnetic material channels, for example, an array comprising multiple rows and columns. That is, the channels can be arranged as a 2D array and can extend along a third dimension. Therefore, the 3D magnetic memory device of the first aspect can utilize all three dimensions and deviate from the usual planar configuration. Therefore, the magnetic memory device of the first aspect can have a significantly increased memory density and can store more information than conventional planar magnetic memory devices.

[0010] Furthermore, the magnetic memory device of the first aspect can employ SOT to write information into the magnetic material channel of the memory cell, and can employ TMR using MTJ to read information from the magnetic material channel of the memory cell. Additionally, information can be moved in the magnetic material channel by a push current, thereby moving the magnetic potential stored in the magnetic material channel from one pinning point to the next pinning point.

[0011] Pinning sites are achieved through the periodicity of the stacked layers and can stabilize magnetic domains within a single layer height. Therefore, the height of the magnetic potential can be defined periodically.

[0012] In implementation, the 3D magnetic memory device also includes a second electrode disposed on or directly below the second end of the magnetic material channel.

[0013] The second electrode facilitates the transmission of injection current toward the first electrode through a magnetic material channel.

[0014] In the implementation of 3D magnetic storage devices, the first diameter is larger than the second diameter.

[0015] This allows for adjustment of the pinning strength at the corresponding pinning sites within the magnetic material channel. Consequently, the performance of the magnetic memory device can also be customized, for example, regarding its retention and delay.

[0016] In the implementation of 3D magnetic memory devices, the ratio between the first diameter and the second diameter is in the range of 1.1:1 to 2:1.

[0017] A smaller ratio can be used to improve latency, while a larger ratio can be used to improve the retention time of magnetic memory devices.

[0018] In the realization of 3D magnetic memory devices, the thickness of the silicon substrate and dielectric layer are in the range of 5-150nm.

[0019] In the implementation of 3D magnetic memory devices, the interface between the transition region between the first diameter and the second diameter is aligned with the interface between the alternating stacked layers.

[0020] In the implementation of 3D magnetic memory devices: the dielectric layer is a silicon oxide layer and the silicon substrate is a silicon nitride layer; or the dielectric layer is a silicon layer and the silicon substrate is a silicon germanium layer.

[0021] In the realization of 3D magnetic memory devices, the magnetic material channel is made of ferromagnetic or ferrimagnetic and / or conductive materials, such as cobalt, iron, nickel or their alloys, or any of the aforementioned materials except boron.

[0022] In the realization of 3D magnetic memory devices, at least one of the first metal layer and the second metal layer is made of tantalum nitride, tungsten nitride, tungsten, tantalum, platinum, hafnium, molybdenum nitride, or an alloy thereof, or is made of a topological insulator.

[0023] These materials allow the use of a first or second metal layer as a SOT track, through which SOT current is sent to write magnetic bits into the magnetic material channels of the memory cell.

[0024] In the implementation of 3D magnetic memory devices, the MTJ is arranged directly above the first end of the magnetic material channel on the first metal layer, or is arranged off-center from the first end of the magnetic material channel.

[0025] In the realization of 3D magnetic memory devices, MTJ includes a magnetic free layer having a coercivity equal to or less than 20-40 mT or a coercivity in the range of 2-3 mT.

[0026] In this way, the stray magnetic field at the pinning site closest to the MTJ can determine the orientation of the free layer.

[0027] A second aspect of this disclosure provides a method for operating a 3D magnetic memory device of the first aspect or any implementation thereof, wherein the method includes at least one of the following operations: writing a magnetic bit into a magnetic material channel by passing a current through a SOT track, wherein the magnetic bit is written into a pinning site in the magnetic material channel closest to the SOT track; pushing the magnetic bit along the magnetic material channel from one pinning site to the next pinning site by passing a current through a first electrode; and determining tunneling magnetoresistance by reading the magnetic bit from the magnetic material channel by passing a current through an MTJ, wherein the magnetic bit stored in the pinning site in the magnetic material channel closest to the MTJ is read.

[0028] The second aspect of the method allows for the performance of write, read, or push operations using the magnetic memory device of the first aspect, particularly within the memory cells of a magnetic memory device that includes channels of magnetic material. Similar operations can then be performed on different memory cells of the magnetic memory device, either subsequently or in parallel.

[0029] In an implementation of the method, the magnetic memory device includes a second electrode, and driving the magnetic bit includes sending current from the second electrode to the first electrode; or the magnetic memory device does not include a second electrode but includes a second metal layer, and driving the magnetic bit includes sending current from the second metal layer to the first electrode; or the magnetic memory device includes a second electrode and the first metal layer is configured as an SOT track, and driving the magnetic bit includes sending bipolar current from the second metal layer to the first electrode.

[0030] The above implementation provides different ways to perform drive operations using the magnetic memory device of the first aspect.

[0031] In the implementation of this method, when a magnetic bit stored in the magnetic material channel is pushed, the magnetic bit stored in the pinning point closest to the first metal layer in the magnetic material channel is destroyed, and the method further includes: rewriting the destroyed magnetic bit into the magnetic material channel or storing information corresponding to the destroyed magnetic bit in a memory.

[0032] A third aspect of this disclosure provides a method for manufacturing a 3D magnetic memory device, the method comprising: forming a stack of a plurality of dielectric layers and a silicon substrate arranged alternately to each other; forming a via through the stack, wherein the via extends through the layers of the stack; selectively etching from within the via to recess the dielectric layer or the silicon substrate, thereby partially widening the via; filling the etched via with a magnetic material to form a magnetic material channel having a first diameter at its extension through the silicon substrate of the stack and a second diameter at its extension through the dielectric layer of the stack, wherein the magnetic material channel is formed by the plurality of layers of the stack. A plurality of defined stacked pinning sites are formed in the magnetic material channel, each pinning site being configured to store a magnetic potential; a first metal layer is formed on a first end of the magnetic material channel and on the last layer of the stack; a magnetic tunnel junction (MTJ) is formed on the first metal layer; and a first electrode is formed on the first metal layer at a distance from the MTJ; wherein the first metal layer is configured as a spin-orbit torque (SOT) orbital, or the method further includes forming a second metal layer configured as an SOT orbital and arranging the second end of the magnetic material channel and the first layer of the stack on the second metal layer.

[0033] In one implementation, the method further includes depositing a liner of SOT orbital material on the walls of the hole before filling the hole with magnetic material.

[0034] The third approach achieves the same advantages as the magnetic storage device of the first approach described above. The third approach can be extended by corresponding implementations as described above for the magnetic storage device of the first approach. Attached Figure Description

[0035] The above aspects and implementations are explained in the following description of embodiments with reference to the accompanying drawings: Figure 1 An example of a magnetic memory device with a top SOT track according to this disclosure is shown.

[0036] Figure 2 Another example of a magnetic memory device with a bottom SOT track according to this disclosure is shown.

[0037] Figure 3 Another example of a magnetic memory device with an out-of-plane MTJ according to the present disclosure is shown.

[0038] Figure 4 Another example of a magnetic memory device with a bottom electrode according to the present disclosure is shown.

[0039] Figure 5 Another example of a magnetic memory device according to this disclosure is shown, which has no bottom electrode but has another top electrode.

[0040] Figure 6 An example of writing magnetic bits into a magnetic memory device according to the present disclosure is shown.

[0041] Figure 7 An example of driving a magnetic bit in a magnetic memory device according to the present disclosure is shown.

[0042] Figure 8 A method for operating a magnetic storage device according to the present disclosure is shown.

[0043] Figure 9 A method for manufacturing a magnetic memory device according to the present disclosure is shown.

[0044] Figure 10 Examples of recessed channels and layer stack heights are shown to control retention and latency for different performance specifications.

[0045] Figure 11 Another example of a magnetic memory device with an SOT pad according to this disclosure. Detailed Implementation

[0046] Figure 1 An example of a 3D magnetic memory device 10 according to the present disclosure is shown.

[0047] Similar to all examples of the memory device 10 presented in this disclosure, Figure 1 The magnetic memory device 10 includes a stack 11 comprising a plurality of dielectric layers 11a and silicon substrates 11b arranged alternately to each other. Magnetic material channels 12 are formed through this stack 11. The magnetic material channels 12 extend through each layer 11a, 11b of the stack 11. The magnetic material channels 12 may extend along a first direction, the first direction corresponding to the stacking direction of the layers 11a, 11b of the stack 11. This first direction may be referred to as the "vertical direction," such as... Figure 1 The orientation of the magnetic material channel 12 is such that it can extend perpendicularly to the surface of the layers 11. However, the magnetic material channel 12 can also extend at a small angle to the surfaces of layers 11a and 11b.

[0048] As in Figure 1 As can be further seen and common to all examples of the magnetic memory device 10 presented in this disclosure, the magnetic material channel 12 has a first diameter d1 where it extends through the silicon substrate 11b and a second diameter d2 where it extends through the dielectric layer 11a of the stack 11. That is, at least one magnetic material channel 12 has a varying diameter. This can be caused by partially recessing the silicon substrate 11b or dielectric layer 11a of the stack 11 during the fabrication of the memory device 10 before forming the magnetic material channel 12. For example, as... Figure 1 As shown, the first diameter can be larger than the second diameter, but it can also be the other way around.

[0049] Due to the alternation of layers 11a and 11b in the stack 11, and further enhanced by the varying diameter of the magnetic material channel 12, a plurality of pinning sites defined by the multiple layers 11a and 11b of the stack are formed in the magnetic material channel 12. Each of these pinning sites is configured to store a magnetic potential. For the pinning sites, it may be advantageous to align the interface between the transition region between the first diameter d1 and the second diameter d2 and between the alternating layers 11a and 11b of the stack 11.

[0050] like Figure 1As shown, each example of the magnetic memory device 10 in this disclosure further includes a first metal layer 13 disposed on a first end of the magnetic material channel 12 and on the last layer of the stack 11. "Last layer" refers to the arrangement of layers from the first layer of the stack to the last layer of the stack 11 along the stacking direction of layers 11a, 11b during the fabrication of the stack 11. An MTJ 14 is disposed on the first metal layer 13. Furthermore, a first electrode 15 (also referred to as a "top electrode") is disposed on the first metal layer 13 at a distance from the MTJ 14. The MTJ 14 includes at least a free layer, a reference layer, and a tunnel barrier layer, enabling it to measure TMR, as known from conventional MRAMs. Advantageously, the MTJ 14 may include a magnetic free layer having a coercivity equal to or less than 20-40 mT or in the range of 2-3 mT.

[0051] like Figure 1 As shown in the example, the MTJ 14 can be arranged on the first metal layer 13 directly above the first end of the magnetic material channel 12.

[0052] For example Figure 1 As illustrated in the example, the magnetic memory device 10 may include a second metal layer 16 configured as an SOT track. In this case, the second end of the magnetic material channel 12 and the first layer of the stack 11 are disposed on the second metal layer 16. Being configured as an SOT track means that the second metal layer 16 may be made of a certain material, have a certain thickness, and be connected to suitable electrodes to allow an SOT current (ISOT) to pass through the second metal layer 16. This allows magnetic potentials to be SOT-written at pinning sites defined by the layer of the stack 11 closest to the second metal layer 16, as will be explained later.

[0053] Figure 2 Another example of a 3D magnetic memory device 10 according to this disclosure is shown. Figure 1 and Figure 2 The same elements of the memory device 10 in the figure share the same reference numerals.

[0054] like Figure 2 As shown in the example, the first metal layer 13 can be configured as an SOT track, rather than like Figure 1 Like a magnetic memory device, it includes a second metal layer 16. That is, the first metal layer 13 may be made of a certain material, have a certain thickness, and may be connected to suitable electrodes to allow the SOT current ISOT to pass through the layer 13, which causes the magnetic potential to be SOT-written into the pinning site defined by the layer of the stack 11 closest to the first metal layer 13.

[0055] At least one of the first metal layer 13 and the second metal layer 16 (particularly the metal layers 13, 16 configured as at least SOT orbitals) may be made of tantalum nitride, tungsten nitride, tungsten, tantalum, platinum, hafnium, molybdenum, molybdenum nitride or alloys thereof, or an alloy thereof, or a topological insulator.

[0056] Figure 3 Another example of a 3D magnetic memory device 10 according to this disclosure is shown. Figure 3 The same reference numerals are shared with the same elements as those in the memory device 10 in the previous figures.

[0057] like Figure 3 As shown in the example, MTJ 14 can also be arranged offset from the first end of the magnetic material channel, i.e., not directly above the first end of channel 12 in this case. Therefore, MTJ 14 can be closer to or further away from the first electrode 15, as in... Figure 1 and Figure 2 The first and second examples are shown. In this case, the MTJ 14 is also referred to as being arranged out of plane.

[0058] Figure 4 Another example of a 3D magnetic memory device 10 according to this disclosure is shown. Figure 4 The same reference numerals are shared with the same elements as those in the memory device 10 shown in the previous figures. Figure 4 The example is specifically based on Figure 1 On the example, but the following features also apply. Figure 2 and Figure 3 Example of a magnetic storage device 10.

[0059] like Figure 4 As shown in the example, the magnetic memory device 10 may include a second electrode 41 (also referred to as a "bottom electrode") disposed on or directly below the second end of the magnetic material channel 12. As shown, the second electrode 41 may be placed on the second metal layer 16. However, without the second metal layer 16, similar to... Figure 2 For example, the second electrode 41 can be positioned at the second end of the magnetic material channel 12 and directly above the first layer of the stack 11. The second electrode 41 can allow the injected current I to be delivered. Push It is sent into the magnetic material channel 12 and toward the first electrode 15.

[0060] Figure 5 Another example of a 3D magnetic memory device 10 according to this disclosure is shown. Figure 5 The same reference numerals are shared with the same elements as those in the memory device 10 shown in the previous figures. Figure 4 The examples are especially based on Figure 1 On the example.

[0061] like Figure 5 As shown in the example, the magnetic memory device 10 may include another first electrode 51 (also referred to as "another top electrode"). Furthermore, the magnetic memory device 10 may not include a second electrode 41 at the bottom, as... Figure 4 As shown. Without the second electrode 41, a more compact memory cell can be obtained in the memory device 10, which may result in a smaller footprint for the memory device 10 including multiple such memory cells. Figure 5 In the example, the injected current I can be provided by sending current through both sides of the SOT rail provided by the second metal layer 16. Push In particular, current is pushed from both sides to limit the current density in the second metal layer 16 and increase its durability and reliability.

[0062] Figure 6 An example of writing magnetic bits into a magnetic memory device 10 according to the present disclosure is shown. Figure 6 A special illustration is shown for demonstrating write operations. Figure 4 Examples. Figure 6 (a) shows the magnetic memory device 10 before / during a write operation, while Figure 6 (b) shows the magnetic memory device 10 after a write operation.

[0063] A magnetic potential is written into the magnetic material channel 12 by passing a current ISOT through a second metal layer 16 configured as an SOT orbital. The magnetic potential is written into pinning sites within the magnetic material channel 12, which are closest to the SOT orbitals, i.e., corresponding to pinning sites in the first layer of channel 12. Positive or negative current ISOT determines the writing of the magnetic potential as "up" or "down" (for vertical magnetization) or "left" or "right" (for in-plane magnetization). For example, in… Figure 6 In (b), the writing of the magnetic bit has already caused a bit switching, that is, a switching of magnetization in the corresponding pinning site.

[0064] Figure 7 An example of driving a magnetic bit in a magnetic memory device 10 according to the present disclosure is shown. Figure 7 Specially shown Figure 4 Examples are used to demonstrate in Figure 6 The push operation following the write operation is shown. The push of the magnetic bit moves the magnetic bit along the magnetic material channel 12 from one pinning point to the next. When using... Figure 4 In the example, the magnetic potential is Figure 7 The magnetic material in the channel 12 is pushed upward, i.e., toward MTJ 14.

[0065] By making the current I PushThe magnetic position is driven by the first electrode 15. Figure 7 In this process, current is sent from the first electrode 15 to the second electrode 41. If the second electrode 41 were not present, then current I could be sent from the first electrode 15. Push ,like Figure 5 As shown, a second metal layer 16 is used. During the push operation, the pulse timing can advantageously be synchronized with the domain wall movement of one cycle (one pinning site). Injected current I Push This will shift all magnetic domains (pinned domains) upwards by one pinning point. Figure 7 At the top of the magnetic channel 12, the surface of the first end of the magnetic material channel 12 is advantageously flat, for example, it can be planarized by chemical mechanical polishing (CMP). In this case, the first metal layer 13 can be used as a thin metal spacer layer (wherein it can be made of TaN) to provide a path for current to the first electrode 15.

[0066] To read the magnetic bit, it can be done according to Figure 4 The magnetic state of the highest magnetic potential is sensed in the example magnetic memory device 10. This can be accomplished using a top-pinned MTJ 14. The free layer of the MTJ 14 can be deposited in direct contact with the first metal layer 13. The free layer can have the aforementioned low coercivity of 40 mT or less, such that the stray magnetic field of the top magnetic potential (e.g., "up" or "down" above the coercivity of the free layer) can determine the orientation of the free layer. Actual sensing can then be accomplished by reading the resistance and TMR effect of the MTJ 14.

[0067] In this example, since the magnetic bit that reaches the top of the magnetic channel 12 (which can be read using MTJ 14) will disappear on the next push, the read operation of the magnetic memory device 10 can be a destructive read. The magnetic bit can then be rewritten at the bottom of the magnetic material channel 12 (i.e., at the SOT track) or can be stored in a buffer memory, for example, for a later burst write.

[0068] The magnetic memory device 10 can operate, for example, in a “full string” write and / or read mode. This means that the minimum addressable bit length can be equal to the number of double layers 11a / 11b in the stack 11. However, the operating mode of the magnetic memory device 10 can also be determined by the architecture selection at the array and system levels.

[0069] Figure 8A method 80 for operating a 3D magnetic memory device 10 is shown, which generally summarizes the above. The method includes at least one of the following operations: operation 81, writing a magnetic bit into a magnetic material channel 12 by passing a current through a SOT track, wherein the magnetic bit is written into the pinning site closest to the SOT track in the magnetic material channel; operation 82, pushing the magnetic bit along the magnetic material channel 12 from one pinning site to the next pinning site by passing a current through a first electrode 15; operation 83, determining the TMR by reading the magnetic bit from the magnetic material channel 12 by passing a current through an MTJ 14, wherein the magnetic bit stored in the pinning site closest to the MTJ 14 in the magnetic material channel 12 is read.

[0070] If the magnetic storage device 10 includes a second electrode 41 (e.g.) Figure 4 As shown), driving the magnetic position can include transferring current I Push From the second electrode 41, the signal is transmitted to the first electrode 15. If the magnetic memory device 10 does not include the second electrode 41, but instead includes a second metal layer 16 as an SOT track (e.g., ... Figure 5 As shown), driving the magnetic position can include transferring current I Push From the second metal layer 16, the energy is transmitted to the first electrode 15. If the magnetic memory device 10 includes the second electrode 41 and the first metal layer 13 is configured as an SOT track (similar to...), then... Figure 2 However, if the second electrode 41 is arranged below the second end of the magnetic material channel 12, then pushing the magnetic position may include sending a bipolar current from the second metal layer 16 to the first electrode 15.

[0071] Figure 9 A method 90 for manufacturing a 3D magnetic memory device 10 according to this disclosure is illustrated. Method 90 includes step 91 of forming a stack 11 of a plurality of dielectric layers 11a and silicon substrates 11b, the dielectric layers and silicon substrates being arranged alternately. Method 90 further includes step 92 of forming holes through the stack 11, wherein the holes extend through the layers 11a, 11b of the stack 11. Method 90 then includes step 93 of selectively etching from within the holes to recess either the dielectric layer 11a or the silicon substrate 11b, thereby partially widening the holes. Method 90 then includes step 94 of filling the etched holes with a magnetic material to form a magnetic material channel 12, the magnetic material channel having a first diameter d1 at its extension through the silicon substrate 11b of the stack and a second diameter d2 at its extension through the dielectric layer 11a of the stack 11.

[0072] Method 90 further includes steps 95 of forming a first metal layer 13 at the first end of the magnetic material channel 12 and the last layer of the stack 11, and step 96 of forming an MTJ 14 on the first metal layer 13. Then, the method further includes step 97 of forming a first electrode 15 on the first metal layer 13 at a distance from the MTJ 14.

[0073] If the magnetic storage device 10 includes a first metal layer 13 as an SOT track (e.g.) Figure 2 (as shown), then method 90 can be completed at this time. Alternatively, method 90 may also include forming a second metal layer 16 configured as an SOT track (as shown). Figure 1 (as shown) and step 97, which involves arranging the second end of the magnetic material channel 12 and the first layer of the stack 11 on the second metal layer 16.

[0074] Figure 10 Examples of different recessed magnetic material channels 12 and stack heights are shown, which can be applied to any example of the magnetic memory device 10 of this disclosure. Various configurations can allow control over the retention time and delay of the magnetic memory device 10, which can be useful for meeting different performance specifications. Figure 10 In the example, the first diameter d1 is greater than the second diameter d2.

[0075] Typically, the ratio between the first diameter d1 and the second diameter d2 can be in the range of 1.1:1 to 2:1. The transition region between the first diameter d1 and the second diameter d2 is advantageously aligned with the interface between the alternating layers 11a and 11b of the stack 11. Furthermore, the thickness t1 of the silicon substrate 11b and the thickness t2 of the dielectric layer 11a can each be in the range of 5-150 nm. Identical layers 11a or 11b can all have the same thickness t1 or t2.

[0076] Specifically, Figure 10 (a) shows an example of a magnetic material channel recess, which reduces retention but is advantageous for delay. The number of layers 11a, 11b of the stack 11 can be relatively small, for example, only about 2-10 each. Furthermore, the recess can be relatively small, for example, the ratio between the first diameter d1 and the second diameter d2 can be in the range of 1.1:1 to 4:3.

[0077] Figure 10 (b) shows an example of a magnetic material channel recess, which reduces delay but improves retention, i.e., increases retention. The number of layers 11a, 11b in the stack 11 can be relatively large, especially compared to Figure 10 The number in (b) is large, for example, approximately 10-50 for each. Furthermore, the recesses can be relatively small, especially compared to... Figure 10In (b), the ratio can be larger, for example, the ratio between the first diameter d1 and the second diameter d2 can be in the range of 3:2 to 2:1.

[0078] For example, after creating vias in stack 11, selective etching can be applied to recess either layer of material. This allows control or adjustment of the diameter of the magnetic material channels 12. This can drastically improve domain wall movement, placement, and sizing. Tuning the recesses (and thus the magnetic channel diameter variation) enables the adjustment of domain pinning strength to achieve a good operating window or adjust retention requirements. This also opens the way for customized performance. For example, one can imagine finite-height bit stacks with low pinning strength to more closely approximate the latency and endurance operation of DRAM, or very high stacks with high pinning strength to cover 3D-NAND and long-term archiving specifications.

[0079] Figure 11 Another example of the magnetic storage device 10 according to this disclosure is shown. Figure 11 The same reference numerals are shared with the same elements as those in the memory device 10 in the previous figures. Figure 11 Examples, especially those based on Figure 4 and Figure 5 Examples, where, Figure 11 The magnetic storage device 10 includes Figure 5 The other first electrode 51 and Figure 4 The second electrode 41 of both.

[0080] like Figure 11 As illustrated in the example, the magnetic memory device 10 may include a pad (e.g., a sheet) of SOT orbital material at the interface between the magnetic material channel 12 and layers 11a, 11b, i.e., an SOT material pad. For example, the SOT orbital material pad may be deposited on the walls of the holes through the stack 11 before the magnetic material is filled into the holes to form the magnetic material channel 12. The pad can increase domain wall mobility efficiency, thus reducing the injection current I. Push Ideally, for compatibility reasons (but this is not mandatory), the padding material should be the same as or at least similar to that of the SOT track.

[0081] In all examples of this disclosure, dielectric layer 11a may be a silicon oxide layer, and silicon substrate 11b may be a silicon nitride layer. Alternatively, T-shaped dielectric layer 11a may be a silicon layer, and silicon substrate may be a silicon-germanium layer.

[0082] In all examples of this disclosure, the magnetic material channel may be made of ferromagnetic or ferrimagnetic and / or conductive materials, such as cobalt, iron, nickel or alloys thereof, or any of the aforementioned materials except boron.

[0083] In summary, this disclosure presents a magnetic memory device 10 that stores magnetic bits based on the vertical arrangement of magnetic domains in a magnetic material channel 12 (e.g., a magnetic material wire). Domain pinning (for high retention) can be achieved using a stack 11, for example, by providing a Sin / SiO matrix whose morphology can be tuned to enhance or reduce pinning. Write bits occur at one end of the stack via SOT. Domain wall transport can be achieved by applying a current to the magnetic material channel 12 itself, and readout can occur at the location of the stray magnetic field of the nearest domain in the MTJ 14.

[0084] In the claims and the description of this disclosure, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude multiple. A single element can perform the function of several entities or items set forth in the claims. The fact that certain measures are set forth in mutually different dependent claims does not mean that a combination of these measures cannot be used for beneficial implementation.

Claims

1. A three-dimensional, 3D, magnetic memory device (10), the magnetic memory device (10) comprising: a stack (11) comprising a plurality of dielectric layers (11a) and silicon-based layers (lib), the plurality of dielectric layers and the silicon-based layers being arranged alternately to each other; a magnetic material channel (12) formed through the stack (11), wherein the magnetic material channel (12) extends through each layer (11a, lib) of the stack (11), wherein the magnetic material channel (12) has a first diameter (dl) at its extension through a silicon-based layer (lib) and a second diameter (d2) at its extension through a dielectric layer (11a) of the stack (11), and wherein a plurality of pinning sites, each configured to store one magnetic bit, is formed in the magnetic material channel (12) by the plurality of layers (11a, lib) of the stack; a first metal layer (13) arranged on a first end portion of the magnetic material channel (12) and on a last layer of the stack (11); a magnetic tunnel junction, MTJ, (14) arranged on the first metal layer (13); and a first electrode (15) arranged on the first metal layer (13) at a distance from the MTJ; wherein the first metal layer (13) is configured as a spin-orbit torque, SOT, track, or the magnetic memory device (10) comprises a second metal layer (16) configured as a SOT track, and a second end portion of the magnetic material channel (12) and the first layer of the stack (11) are arranged on the second metal layer (16).

2. The 3D magnetic memory device (10) according to claim 1, further comprising a second electrode (41) arranged on or directly below a second end portion of the magnetic material channel (12).

3. The 3D magnetic memory device (10) according to claim 1 or 2, wherein, The first diameter (dl) is larger than the second diameter (d2).

4. The 3D magnetic memory device (10) according to one of claims 1 to 3, wherein, A ratio between the first diameter (dl) and the second diameter (d2) is in a range of 1.1:1 to 2:

1.

5. The 3D magnetic memory device (10) according to one of claims 1 to 4, wherein, A thickness of the silicon-based layers (lib) and of the dielectric layers (11a) is in a range of 5-150 nm, respectively.

6. The 3D magnetic memory device (10) according to one of claims 1 to 5, wherein, A transition zone between the first diameter (dl) and the second diameter (d2) is aligned with an interface between alternately arranged layers of the stack (11).

7. The 3D magnetic memory device (10) according to one of claims 1 to 6, wherein: The dielectric layers (11a) are silicon oxide layers and the silicon-based layers (lib) are silicon nitride layers; or The dielectric layers (11a) are silicon layers and the silicon-based layers (lib) are silicon germanium layers.

8. The 3D magnetic memory device (10) according to one of claims 1 to 7, wherein, The magnetic material channel (12) is made of a ferromagnetic or ferrimagnetic material and / or an electrically conductive material, for example, of cobalt, iron, nickel or alloys thereof, or of any of the aforementioned materials except boron.

9. The 3D magnetic memory device (10) according to one of claims 1 to 8, wherein, At least one of the first metal layer (13) and the second metal layer (16) is made of tantalum nitride, tungsten nitride, tungsten, tantalum, platinum, hafnium, molybdenum, molybdenum nitride, or alloys thereof, or is made of a topological insulator.

10. The 3D magnetic memory device (10) according to one of claims 1 to 9, wherein, The MTJ (14) is arranged directly above the first end of the magnetic material channel (12) on the first metal layer (13), or is arranged offset from the first end of the magnetic material channel (12).

11. The 3D magnetic memory device (10) according to one of claims 1 to 10, wherein, The MTJ (14) comprises a magnetic free layer having a coercivity equal to or less than 20-40 mT or in the range of 2-3 mT.

12. A method (80) of operating a 3D magnetic memory device (10) according to any one of claims 1 to 10, wherein, The method (80) comprises at least one of the following operations: writing (81) a magnetic bit into the magnetic material channel (12) by passing a current through the SOT track, wherein the magnetic bit is written into the magnetic material channel (12) in the pinning site closest to the SOT track; pushing (82) a magnetic bit along the magnetic material channel (12) from one pinning site to the next pinning site by passing a current through the first electrode (15); reading (83) a magnetic bit from the magnetic material channel (12) by passing a current through the MTJ (14), thereby determining tunneling magnetoresistance, wherein the magnetic bit stored in the pinning site of the magnetic material channel (12) closest to the MTJ (14) is read.

13. The method (80) of claim 12, wherein: the magnetic memory device (10) comprises the second electrode (41), and pushing the magnetic bit comprises sending the current from the second electrode (41) to the first electrode (15); or the magnetic memory device (10) does not comprise the second electrode (41) but comprises the second metal layer (16), and pushing (82) the magnetic bit comprises sending the current from the second metal layer (16) to the first electrode (15); or the magnetic memory device (10) comprises the second electrode (41), and the first metal layer (13) is configured as the SOT track, and pushing (82) the magnetic bit comprises sending a bipolar current from the second metal layer (16) to the first electrode (15).

14. The method (80) of claim 12 or 13, wherein when pushing (82) the magnetic bit stored in the magnetic material channel (12), the magnetic bit stored in the pinning site of the magnetic material channel (12) closest to the first metal layer (13) is destroyed, and the method (80) further comprises: overwriting the destroyed magnetic bit into the magnetic material channel (12) or storing the information corresponding to the destroyed magnetic bit in a memory.

15. A method (90) of manufacturing a 3D magnetic memory device (10), the method (90) comprising: forming (91) a stack (11) of a plurality of dielectric layers (11a) and silicon-based layers (11b) arranged alternately to each other; forming (92) a hole through the stack (11), wherein the hole extends through the layers (11a, 11b) of the stack (11); selectively etching (93) from within the hole to recess the dielectric layer (11a) or the silicon-based layer (11b) to partially widen the hole; filling (94) the etched hole with a magnetic material to form a magnetic material channel (12) having a first diameter (d1) where it extends through the silicon-based layer (11b) of the stack (11) and a second diameter (d2) where it extends through the dielectric layer (11a) of the stack (11), wherein a plurality of stacked pinning sites defined by the plurality of layers (11a, 11b) of the stack (11) are formed in the magnetic material channel (12), each pinning site configured to store one magnetic bit; forming (95) a first metal layer (13) on a first end of the magnetic material channel (12) and on a last layer of the stack (11); forming (96) a magnetic tunnel junction, MTJ, (14) on the first metal layer (13); and forming (97) a first electrode (15) on the first metal layer (13) at a distance from the MTJ (14); wherein the first metal layer (3) is configured as a spin-orbit torque, SOT, track, or the method (90) further comprises forming (98) a second metal layer (16) configured as a SOT track and arranging a second end of the magnetic material channel (12) and a first layer of the stack (11) on the second metal layer (16).

16. The method (90) of claim 15, further comprising depositing a liner (110) of SOT track material on the walls of the hole prior to filling the hole with the magnetic material.

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