Three-dimensional phase change storage device and control method thereof

Abstract

A memory device and an operating method thereof are provided. A memory device includes a memory cell array and control logic. The memory cell array includes word lines, bit lines, and memory cells connected between the word lines and the bit lines. The control logic is coupled to the memory cell array and configured to receive a zero refresh command, perform a first read operation on the memory cell array, and in response to determining that data of a first memory cell of the memory cell array is' 0 ', reprogram the first memory cell of the memory cell array with' 0 '.

Description

Background Art

[0001] The present disclosure relates to a three-dimensional (3D) phase-change memory (PCM) storage device and an operation method thereof.

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit.

[0003] 3D memory architecture can solve the density limitations in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals in and out of the memory array. For example, PCM can be based on electrothermal heating and quenching of phase change materials, using the difference between the resistivity of the amorphous and crystalline phases in the phase change material. PCM array cells can be stacked vertically in 3D to form 3D PCM. Summary of the invention

[0004] In one aspect, a memory device includes a memory cell array and control logic. The memory cell array includes word lines, bit lines, and memory cells connected between the word lines and the bit lines. The control logic is coupled to the memory cell array and is configured to: receive a zero refresh command; perform a first read operation on the memory cell array; and in response to determining that data of a first memory cell of the memory cell array is "0", reprogram the first memory cell of the memory cell array with "0".

[0005] In some embodiments, the control logic is further configured to: in response to determining that the data of the first memory cell of the memory cell array is not "0", perform a first write operation to write to a memory cell of the memory cell array.

[0006] In some implementations, the first read operation is performed in response to a clock, a timer, a counter, or a combination thereof reaching a predetermined condition.

[0007] In some embodiments, the predetermined condition includes a clock pulse number, a voltage pulse number, or a time interval.

[0008] In some implementations, during the first read operation, first read data is stored in a cache memory of the storage device.

[0009] In some embodiments, the memory device further comprises: a page buffer coupled to the memory cell array; and an address register coupled to the control logic. The cache memory is located in the page buffer, the address register or the control logic.

[0010] In some implementations, the first read data is sampled and output to the cache memory at time intervals.

[0011] In some embodiments, each of the memory cells comprises a phase change memory (PCM) cell.

[0012] In another aspect, a system includes a memory device and a memory controller, the memory controller being coupled to the memory device and configured to control the memory device. The memory device includes a memory cell array and control logic. The memory cell array includes word lines, bit lines, and memory cells connected between the word lines and the bit lines. The control logic is coupled to the memory cell array and configured to: receive a zero refresh command; perform a first read operation on the memory cell array; and in response to determining that data of a first memory cell of the memory cell array is "0", reprogram the first memory cell of the memory cell array with "0".

[0013] In some embodiments, the control logic is further configured to: in response to determining that the data of the first memory cell of the memory cell array is not "0", perform a first write operation to write to a memory cell of the memory cell array.

[0014] In some embodiments, the first read operation is performed in response to a clock, a timer, a counter, or a combination thereof reaching a predetermined condition.

[0015] In some embodiments, the predetermined condition includes a number of clock pulses, a number of voltage pulses, or a time interval.

[0016] In some implementations, the first read data is stored in a cache memory of the storage device during the first read operation.

[0017] In some embodiments, the memory device further comprises: a page buffer coupled to the memory cell array; and an address register coupled to the control logic. The cache memory is located in the page buffer, the address register or the control logic.

[0018] In some implementations, the first read data is sampled and output to the cache memory at time intervals.

[0019] In some embodiments, each of the memory cells comprises a phase change memory (PCM) cell.

[0020] In yet another aspect, a method for operating a memory device is provided. The memory device includes a memory cell array. The memory cell array includes word lines, bit lines, and memory cells connected between the word lines and the bit lines. The method includes: receiving a zero refresh command; performing a first read operation on the memory cell array; and in response to determining that data of a first memory cell of the memory cell array is "0", reprogramming the first memory cell of the memory cell array with "0".

[0021] In some embodiments, the method further includes: in response to determining that the data of the first memory cell of the memory cell array is not "0", performing a first write operation to write into the memory cell of the memory cell array.

[0022] In some embodiments, the method further includes: storing first read data in a cache memory of the storage device during the first read operation; and outputting the first read data samples to the cache memory at time intervals.

[0023] In some embodiments, the method further includes transmitting the first read data to a memory controller or a host. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0025] Figure 1 A perspective view of a 3D storage device according to some aspects of the present disclosure is shown.

[0026] Figure 2 A schematic diagram of an exemplary memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0027] Figure 3 A block diagram of an exemplary memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0028] Figure 4A A block diagram of an exemplary storage system including a storage device, a memory controller, and a host and data transfer flow thereof according to some aspects of the present disclosure is shown.

[0029] Figure 4B A block diagram of an exemplary storage system including a storage device, a memory controller, and a host and data transfer flow thereof according to some aspects of the present disclosure is shown.

[0030] Figure 5AA flowchart illustrating an exemplary method for operating a 3D storage device according to some aspects of the present disclosure is shown.

[0031] Figure 5B A flowchart of an exemplary method for operating a 3D storage device according to some aspects of the present disclosure is shown.

[0032] Figure 6 A block diagram of an exemplary system having a 3D storage device according to some aspects of the present disclosure is shown.

[0033] Fig. 7A A diagram showing an exemplary memory card with 3D storage according to some aspects of the present disclosure.

[0034] Figure 7B A diagram of an exemplary solid-state drive (SSD) having 3D storage devices according to some aspects of the present disclosure is shown.

[0035] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0036] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the present disclosure may be used for various other applications. The functions and structural features described in the present disclosure may be combined, adjusted and modified with each other in a manner not specifically depicted in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the present disclosure.

[0037] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms (such as "one", "an" or "the") can be understood to convey singular usage or to convey plural usage, which depends at least in part on the context. In addition, the term "based on" can be understood as not necessarily intended to convey a set of exclusive factors, but can allow the presence of additional factors that are not necessarily explicitly described, again, at least in part depending on the context. In addition, the term "coupled", "coupled to" or "coupled between..." can be understood as not necessarily intended to be "physically connected or attached", i.e., directly attached, but can be interpreted as indirectly connected through an intermediate component.

[0038] A phase-change memory (PCM) cell is a non-volatile storage device that uses phase-change materials to store data. Based on electrothermal heating and quenching of a phase-change material (e.g., a chalcogenide alloy), PCM can utilize the difference between the resistivity of the amorphous phase and the crystalline phase in the phase-change material. The phase-change material in the PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the material between the two phases (or at least a portion of it that blocks the current path) to store data. The "set" state is a low-resistance state of the PCM cell, which can be obtained by creating a crystalline region in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficiently long duration. In contrast, the "reset" state is a high-resistance state of the PCM cell, which can be obtained by creating an amorphous region in the chalcogenide material. The amorphous state can be produced when the chalcogenide material is heated to above its melting temperature and then rapidly quenched to produce an amorphous morphology. The "set" state may be referred to as the "on" state, and the "reset" state may be referred to as the "off" state.

[0039] The characteristics of a PCM cell will change slowly with retention over time, or with read / write disturbances after the PCM cell has been written and read multiple times. After multiple reads and writes, the threshold voltage Vt of the PCM cell may gradually derive and switch from the reset state to the set state, resulting in a read "0" failure (i.e., retention failure). In contrast, the threshold voltage Vt of a PCM cell may drift high over time, thereby expanding the Vt distribution and thus reducing the read window. In addition, read / write disturbances may also increase the Vt of the set PCM cell, resulting in a read "1" failure.

[0040] One method to solve the above problem is to refresh the data stored in the PCM cells at regular time intervals. Therefore, the storage system may need to periodically read out the data stored in the PCM cells and rewrite the data back to the PCM cells in order to prevent retention errors or read / write interference. However, periodically reading out the data stored in the PCM cells and rewriting the data back to the PCM cells may generate additional time and energy costs in order to retain the data in the PCM cells. The entire refresh operation may take longer to read out each data and rewrite it to the PCM cells. If there are more data to be stored in the PCM cells in the PCM cell array, the system resources used for data transmission may become higher. In addition, the storage system may require additional circuit design to create a data path to refresh the data. This may also increase the complexity of the circuit design in the storage system. The data transmitted from the PCM cells to the memory controller or the host may also bring additional unwanted errors during the transmission process.

[0041] In order to solve one or more of the above-mentioned problems, the present disclosure provides a solution in which a zero refresh operation is introduced to receive a zero refresh command from a memory controller or a host, and automatically and internally refresh data with "0" in a storage device (for example, a reset operation of writing a storage cell with "0") without reading data from and reading data into the storage device.

[0042] Figure 1 A perspective view of a 3D memory device 100 is shown. According to some embodiments, the 3D memory device 100 may include a 3D cross-point (XPoint) memory device, which is a transistor-free, cross-point architecture that positions memory cells at the intersections of vertical conductors. The 3D memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above the lower bit lines 102. The 3D memory device 100 also includes a plurality of parallel word lines 106 in the same plane located between the lower bit lines 102 and the upper bit lines 104 in a vertical direction. Figure 1 As shown, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction (parallel to the wafer plane) in the plan, and each word line 106 extends laterally along the word line direction in the plan. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

[0043] Note that the x-axis and y-axis are included Figure 1 is used to illustrate two orthogonal directions in the wafer plane. The x direction is the word line direction, and the y direction is the bit line direction. Note that the z axis is also included Figure 1 1 is used to further illustrate the spatial relationship of components in the 3D storage device 100. The substrate (not shown) of the 3D storage device 100 includes two side surfaces extending laterally in the xy plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite to the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate is located in the lowest plane of the semiconductor device in the z-direction, whether one component (e.g., a layer or a device) is "above", "above" or "below" another component (e.g., a layer or a device) of the semiconductor device (e.g., the 3D storage device 100) is determined relative to the substrate of the semiconductor device in the z-direction (a vertical direction perpendicular to the xy plane). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0044] like Figure 1As shown, the 3D memory device 100 includes a plurality of memory cells 108, each memory cell 108 being arranged at the intersection of a lower bit line or an upper bit line 102 or 104 and a corresponding word line 106. Each memory cell 108 has a vertical square column shape. Each memory cell 108 includes at least a vertically stacked PCM element 110 and a selector 112. Each memory cell 108 stores a single data bit and can be written or read by changing the voltage applied to the corresponding selector 112, which replaces the need for a transistor. Each memory cell 108 is individually accessed by a current applied through the top and bottom conductors (e.g., the corresponding word line 106 and the lower bit line or upper bit line 102 or 104) in contact with each memory cell 108. The memory cells 108 in the 3D memory device 100 are arranged in a memory array.

[0045] To form the 3D memory device 100 , the bottom memory cell 108 in the bottom cell stack between the lower bit line 102 and the word line 106 is first formed by patterning both the lower bit line 102 and the word line 106 to define the bottom pillar memory cell 108 , followed by top cell stack deposition and patterning of the upper bit line 104 to define the top pillar memory cell 108 .

[0046] Figure 2 1 is a schematic circuit diagram of an exemplary 3D memory device 200 including peripheral circuits according to some aspects of the present disclosure. The 3D memory device 200 may include or correspond to Figure 1 3D memory device 100 in. 3D memory device 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to memory cell array 201. Memory cell array 201 may include word lines (e.g., selected word lines 214), bit lines (e.g., selected bit lines 216 and unselected bit lines 218), and memory cells (e.g., selected memory cells 208 and unselected memory cells 210) formed between the word lines and the bit lines. In some embodiments, each memory cell (e.g., selected memory cell 208 and unselected memory cell 210) may include a PCM element (not shown) connected in series with a selector (not shown). The PCM element connected in series with the selector may be, for example, Figure 110 and a selector 112 are vertically stacked in the PCM element 110. In some embodiments, the memory cell (e.g., 208 or 210) may also be a DRAM cell including a paired transistor and a capacitor. In order to read the selected memory cell (e.g., the selected memory cell 208), a selected word line voltage (e.g., a selected word line voltage Vwl1) may be applied to the selected word line (e.g., the selected word line 214), and a selected bit line voltage (e.g., a selected bit line voltage Vbl1) may be applied to the selected bit line (e.g., the selected bit line 216). The other unselected word lines will remain at the unselected word line voltage (e.g., Vwl0), and the other unselected bit lines will remain at the unselected bit line voltage (e.g., Vbl0). In some implementations, the unselected bit line voltage (e.g., Vbl0) of the unselected bit line (e.g., unselected bit line 218) is configured to be set as a reference voltage by a series of voltages during the precharge sharing, charge sharing, and discharge process before the selected word line voltage (e.g., selected word line voltage Vwl1) is applied to the selected word line (e.g., selected word line 214). In some implementations, the selected bit line voltage (e.g., Vbl1) of the selected bit line (e.g., selected bit line 216) is configured to be set as a series of voltages during the precharge sharing, charge sharing, and discharge process before the selected word line voltage (e.g., selected word line voltage Vwl1) is applied to the selected word line (e.g., selected word line 214).

[0047] Figure 3 An exemplary 3D memory device 200 (eg, corresponding to a 3D memory device 200 ) including a memory cell array 201 and peripheral circuits according to some aspects of the present disclosure is shown. Figure 1 In some embodiments, the memory cells of the memory cell array 201 include memory cells 108, such as Figure 1 middle.

[0048] like Figure 3 As shown, the page buffer / sense amplifier 304 can be coupled to the memory cell array 201 and configured to read data from the memory cell array 201 and program (write) data to the memory cell array 201 according to the control signal from the control logic 312. In one example, the page buffer / sense amplifier 304 can store a page of programming data (write data) to be programmed into a page of the memory cell array 201. In another example, the page buffer / sense amplifier 304 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 208 coupled to the selected word line 214, as shown in FIG. Figure 2 In yet another example, the page buffer / sense amplifier 304 can also sense a low power signal from the selected bit line 216 representing a data bit stored in the memory cell 208 and amplify the small voltage swing to a recognizable logic level in a read operation.

[0049] The column decoder / bit line driver 306 can be coupled to the memory cell array 201 and the control logic 312 and configured to be controlled by the control logic 312 and select one or more memory cells (e.g., the selected memory cell 208) and bit lines (e.g., the selected bit line 216). The column decoder / bit line driver 306 can be further configured to drive the selected bit line 216 using the bit line voltage generated from the voltage generator 310.

[0050] The data input / output (I / O) 316 can be coupled to the page buffer / sense amplifier 304 and / or the column decoder / bit line driver 306 and is configured to direct (route) data input from the data bus 323 to the selected memory cell 208 of the memory cell array 201, and to direct (route) data output from the selected memory cell to the data bus 323.

[0051] The row decoder / word line driver 308 may be coupled to the control logic 312 and the memory cell array 301 and configured to be controlled by the control logic 312 and select one or more memory cells (e.g., the selected memory cell 208) and a selected word line (e.g., the selected word line 214) of the memory cell array 201. The row decoder / word line driver 308 may be further configured to drive the selected word line 214 using a word line voltage generated from the voltage generator 310.

[0052] The voltage generator 310 can be coupled to the control logic 312 and configured to be controlled by the control logic 312 according to a control signal from the control logic 312 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verification voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0053] The control logic 312 may be coupled to each of the above-described peripheral circuits and configured to control the operation of each peripheral circuit. The control logic 312 is configured to receive a clock signal, a command signal, an address signal, and a data signal from a host. The command signal is received via a command bus 321. The data signal is received via a data bus 323. In some embodiments, the control logic 312 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (digital signal processor, DSP), an application-specific integrated circuit (application-specific integrated circuit, ASIC), a field-programmable gate array (field-programmable gate array, FPGA), a programmable logic device (programmable logic device, PLD), a state machine, a gating logic, a discrete hardware circuit, and other suitable hardware, firmware, and / or software configured to perform the various functions described. In some embodiments, the control logic 312 is coupled to the word line driver 308 and configured to direct the read voltage into the selected storage cell via the word line driver 308.

[0054] The address register 314 may be coupled to or included in the control logic 312. The address register 314 may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0055] Figure 4A 1 is a block diagram of an exemplary memory system 400 including a 3D memory device 200, a memory controller 350, and a host 360 and a data transmission flow thereof according to some aspects of the present disclosure. The 3D memory device 200 may include a memory cell array 201 and a core 300 coupled to the memory cell array 201. The core 300 may correspond to a peripheral circuit 202, such as Figure 2 In some embodiments, core 300 may include control logic 312, address registers 314, voltage generators 310, row decoders / word line drivers 308, page buffers / sense amplifiers 304, column decoders / bit line drivers 306, data I / O 316, etc. Figure 3 As shown. Figure 4AAs shown, the core 300 includes a write control unit 331, which is configured to write data input data 333 into the memory cell array 201. The data input data 333 and the write command can be received from the host 360 and through the memory controller 350 and the data path 339 between the memory controller and the core 300. The data input data 333 and the write command can be stored in, for example, the control logic 312 and / or the address register 314 via the command bus 321 and the data bus 323, as shown in FIG. Figure 3 In some embodiments, the control logic 312 and / or the address register 314 may include a cache memory in which the data input data 333 and the write command may be temporarily stored. Figure 4A As shown, the core 300 may further include a read control unit 335, which is configured to read data output data 337 from the memory cell array 201. A read command may be received from the host 360 and through the memory controller 350 and the data path 339 to read the data output data 337 from the memory cell array 201. The read command may be stored in, for example, the control logic 312 and / or the address register 314 via the command bus 321 and the data bus 323, as shown in FIG. Figure 3 Data output data 337 may also be stored in, for example, control logic 312 and / or address register 314, such as Figure 3 In some embodiments, control logic 312 and / or address register 314 may include a cache memory in which data output data 337 and write commands may be temporarily stored.

[0056] As described above, the characteristics of the PCM cells may gradually change due to multiple issues and cause several read errors. Therefore, a refresh operation may be required to refresh the data stored in the PCM cells at regular time intervals, thereby generating additional system resources for data transfer into and out of the 3D memory device 200. In order to solve one or more of the above problems, the present disclosure provides a solution in which a zero refresh operation is introduced to receive a zero refresh command from a memory controller or a host, and automatically and internally refresh the data with "0" in the memory device (e.g., a reset operation that writes a memory cell with "0") without reading out and reading in data to the memory device. It should be noted that the zero refresh operation can be used to indicate that one or more memory cells (e.g., the first memory cell of the 3D memory device 200) are reprogrammed with data "0" to overwrite existing or original data stored in the one or more memory cells. This includes instructing the page buffer / sense amplifier 304 to program (write) data "0" to the memory cell array 201 by the control logic 312.

[0057] Figure 4BFIG. 4 is a block diagram showing an exemplary memory system 410 including a 3D memory device 200, a memory controller 350, and a host 360 and a data transfer flow thereof according to some aspects of the present disclosure. Figure 4A In some embodiments, the 3D memory device 200 of the memory system 410 may further include a backward control unit 341, which is configured to: in response to receiving a zero refresh command (e.g., a zero refresh write command) of the core 300 from the host 360 via the memory controller 350, rewrite the data output data 337 back to the memory cell array 201 at time intervals. In some embodiments, the backward control unit 341 may include a clock, a timer, a counter, or a combination thereof for counting, for example, clock pulses, time intervals, voltage pulses, etc. In some embodiments, the backward control unit 341 may be configured to perform the functions of the control logic 312, the address register 314, the voltage generator 310, the row decoder / word line driver 308, the page buffer / sense amplifier 304, the column decoder / bit line driver 306, the data I / O 316, or other components in the 3D memory device 200. Note that the backward control unit 341 according to some embodiments of the present disclosure is only an example of implementing a desired function or mechanism; any other control logic gate combination that implements the same or similar function is possible according to the above teachings. In some embodiments, the backward control unit 341 can be a combination or part of a combination of control logic 312, address register 314, voltage generator 310, row decoder / word line driver 308, page buffer / sense amplifier 304, column decoder / bit line driver 306, data I / O 316, or other components in the 3D memory device 200.

[0058] In some embodiments, a zero refresh command may be received from the host 360 via the command bus 321, input data (e.g., first data) may be received from the host 360 via the data bus 323, the control logic 312 may be configured to receive the zero refresh command and the input data, and the input data may be temporarily stored in the address register 314. In response to a clock, a timer, a counter, or a combination thereof reaching a predetermined condition, for example, within a specific time interval, it may trigger a zero refresh operation, wherein a read operation is performed. And, in response to determining that the data of the first memory cell of the memory cell array is "0", the first memory cell of the memory cell array is reprogrammed with "0", for example, within a certain time interval. In some embodiments, before the predetermined condition is triggered, the read operation may not be performed to reduce power consumption. In some embodiments, the read operation may be performed, for example, within a certain time interval. Therefore, refreshing the data stored in the PCM cell of the memory cell array 201 with "0" under predetermined conditions, for example, at a time interval, can prevent read errors caused by read / write interference, set / reset failure, threshold voltage Vt drift problems, etc. Further, by using the backward control unit 341 (the backward control unit 341 may be implemented by a combination or part of a combination of components in the 3D memory device 200 (e.g., the control logic 312, the address register 314, the voltage generator 310, the row decoder / word line driver 308, the page buffer / sense amplifier 304, the column decoder / bit line driver 306, and / or the data I / O 316)), it avoids the complication of the data transmission sequence control in the memory controller 350 and / or the host 360, thereby reducing the complexity of the system control. In addition, since the zero refresh operation is performed inside the 3D memory device 200, it avoids an additional data transmission path to and from the memory controller 350 and / or the host 360, thereby reducing the system bus occupancy rate and improving the system bus utilization efficiency. Finally, compared with refreshing the data with "1" (e.g., a set operation), refreshing the data stored in the PCM cell of the memory cell array 201 with "0" (e.g., a reset operation) is a much lower power consumption operation. Therefore, periodically refreshing the memory cells with data "0" may not be burdensome to the entire device and degrade overall device performance.

[0059] Figure 5A A flow chart of an exemplary method 500 for operating a 3D storage device according to some aspects of the present disclosure is shown. Figure 5B 1 is a flowchart showing a more detailed process of an exemplary method 500 for operating a 3D storage device according to some aspects of the present disclosure. The 3D storage device may be any suitable storage device disclosed herein, such as the 3D storage device 100 or 200. The method 500 may be partially or entirely performed by Figure 3 The control logic 312 in Figure 4BIt should be understood that the operations shown in method 500 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 5A or Figure 5B The different orders are shown.

[0060] refer to Figure 5A , method 500 begins at operation 502 where a zero refresh command is received. Figure 3 and Figure 4B As shown, the zero refresh command can be transmitted from the host 360 or the memory controller 350 to the control logic 312 and / or the address register 314 via the command bus 321. In some embodiments, the zero refresh command is received by the control logic 312 and stored in the address register 314. A piece of input data can also be received by the control logic 312 and temporarily stored in the address register 314. The input data is used to program the memory cells of the memory cell array in a write operation (e.g., a programming operation).

[0061] Method 500 proceeds to operation 504, such as Figure 5A As shown, a read operation is performed to determine whether any memory cell of the memory cell array has data "0". Figure 5B As shown, in some embodiments, a read operation is performed to determine whether any memory cell of the memory cell array has data "0". For example, a read operation is performed to determine whether the first memory cell of the memory cell array has data "0". If the data "0" is determined, it will trigger the next operation. In some embodiments, the read operation can be a conventional read operation of the storage device or an additional read operation in response to a zero refresh command. In some embodiments, the read operation can be performed in response to a clock, a timer, a counter, or a combination thereof, for example, reaching a predetermined condition within a certain time interval. In some embodiments, the read data received during the read operation can be sampled and output, for example, within a specific time interval to be stored in the cache memory, the control logic 312, or the address register 314 of the page buffer 304.

[0062] Method 500 proceeds to operation 506, such as Figure 5A As shown, in response to determining that the data of the first memory cell of the memory cell array is "0", a reprogramming operation (e.g., a reset operation) with data "0" is performed (e.g., triggered) on the first memory cell of the memory cell array. Figure 3 and Figure 4B As shown, in some embodiments, in response to determining that the data of the first memory cell of the memory cell array is "0", a reprogramming operation (eg, Figure 5BIn the embodiment of the present invention, a reprogramming operation (shown as a write "0" operation) is triggered so that data "0" is written back to the first memory cell of the memory cell array 201 to update and refresh the data "0" stored in the first memory cell of the memory cell array 201. After the reprogramming operation with data "0" is completed, the conventional read operation and / or write operation can be resumed to read and write the memory cells of the memory cell array 201. And the read operation and / or write operation can be suspended, and the next reprogramming operation with "0" is performed in response to determining that the data of the second memory cell of the memory cell array is "0". This process can be repeated until the refresh command is suspended, canceled, or removed from the control sequence.

[0063] In some embodiments, such as Figure 5B As shown, in response to determining that the data of the first memory cell of the memory cell array is not “0”, no operation is performed and a conventional read operation and / or write operation may be restored to read and write memory cells of the memory cell array 201 .

[0064] Figure 6 A block diagram of an exemplary system 600 with a 3D storage device according to some aspects of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6 As shown, system 600 may include a host 608 (eg, corresponding to Figure 4A and Figure 4B 3D storage device 604 (e.g., corresponding to Figure 1 The 3D storage device 100 or Figure 3 3D storage device 200 in FIG. 1 ) and memory controller 606 (eg, corresponding to Figure 4A and Figure 4B The host 608 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 608 may be configured to send data to the 3D storage device 604 or receive data from the 3D storage device 604.

[0065] According to some embodiments, the memory controller 606 (also referred to as a controller circuit) is coupled to the 3D memory device 604 and the host 608 and is configured to control the 3D memory device 604. For example, the memory controller 606 can be configured to communicate with the 3D memory device 604 via word lines (e.g., Figure 2 214), a bit line (eg, Figure 26 and the host 608. The memory controller 606 can manage the data stored in the 3D storage device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 606 is designed to operate in a high duty cycle environment SSD or embedded multi-media-card (eMMC), SSD or embedded multi-media card is used as data storage for mobile devices (such as smart phones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 606 can be configured to control the operation of the 3D storage device 604, such as read operations, erase operations, and programming operations. The memory controller 606 may also be configured to manage various functions regarding data stored or to be stored in the 3D storage device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction code (ECC) regarding data read from or written to the 3D storage device 604. The memory controller 606 may perform any other suitable functions, such as formatting the 3D storage device 604. The memory controller 606 may communicate with an external device (e.g., a host 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0066] The memory controller 606 and the one or more 3D storage devices 604 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 602 can be implemented and packaged into different types of terminal electronic products. In one example, Fig. 7A As shown, the memory controller 606 and the single 3D storage device 604 can be integrated into the memory card 702. The memory card 702 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 702 may also include a memory card connector 704, which connects the memory card 702 to a host (e.g., Figure 6 The host 608 in the embodiment is electrically coupled. Figure 7B In another example shown, the memory controller 606 and the plurality of 3D storage devices 604 may be integrated into an SSD 706. The SSD 706 may also include a processor that interfaces the SSD 706 with a host (e.g., Figure 6 In some embodiments, the storage capacity and / or operating speed of SSD 706 is greater than the storage capacity and / or operating speed of memory card 702.

[0067] The foregoing description of the specific embodiments will reveal the general nature of the present disclosure so that others can easily modify and / or adapt the various applications of such specific embodiments by applying knowledge within the technical scope of the art without excessive experimentation and without departing from the general concept of the present disclosure. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the terms or terms herein are for the purpose of description rather than limitation, so that the terms or terms of this specification will be interpreted by those skilled in the art according to teachings and guidance.

[0068] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A storage device, comprising: A memory cell array, the memory cell array comprising word lines, bit lines, and memory cells connected between the word lines and the bit lines; as well as a control logic coupled to the memory cell array and configured to: Receive zero refresh command; performing a first read operation on the memory cell array; as well as In response to determining that the data of the first memory cell of the memory cell array is “0”, the first memory cell of the memory cell array is reprogrammed with “0”.

2. The storage device according to claim 1, wherein: The control logic is further configured to: In response to determining that data of a first memory cell of the memory cell array is not “0”, a first write operation is performed to write to the memory cell of the memory cell array.

3. The storage device according to claim 1, wherein: In response to a clock, a timer, a counter, or a combination thereof reaching a predetermined condition, the first reading operation is performed.

4. The storage device according to claim 3, wherein: The predetermined condition includes the number of clock pulses, the number of voltage pulses or the time interval.

5. The storage device according to claim 1, wherein: During the first read operation, first read data is stored in a cache memory of the storage device.

6. The storage device according to claim 5, further comprising: a page buffer coupled to the memory cell array; as well as An address register is coupled to the control logic, wherein the cache memory is located in the page buffer, the address register, or the control logic.

7. The storage device according to claim 5, wherein: The first read data is sampled and output to the cache memory at time intervals.

8. The storage device according to claim 1, wherein: Each of the memory cells comprises a phase change memory (PCM) cell.

9. A system comprising: A storage device, the storage device comprising: A memory cell array, the memory cell array comprising word lines, bit lines, and memory cells connected between the word lines and the bit lines; and a control logic coupled to the memory cell array and configured to: Receive zero refresh command; performing a first read operation on the memory cell array; and In response to determining that the data of the first memory cell of the memory cell array is "0", reprogramming the first memory cell of the memory cell array with "0"; and A memory controller is coupled to the memory device and is configured to control the memory device.

10. The system of claim 9, wherein: The control logic is further configured to: In response to determining that data of a first memory cell of the memory cell array is not “0”, a first write operation is performed to write to the memory cell of the memory cell array.

11. The system of claim 9, wherein: In response to a clock, a timer, a counter, or a combination thereof reaching a predetermined condition, the first reading operation is performed.

12. The system of claim 11, wherein: The predetermined condition includes the number of clock pulses, the number of voltage pulses or the time interval.

13. The system of claim 9, wherein: During the first read operation, first read data is stored in a cache memory of the storage device.

14. The system of claim 13, wherein: The storage device also includes: A page buffer coupled to the memory cell array; and An address register is coupled to the control logic, wherein the cache memory is located in the page buffer, the address register, or the control logic.

15. The system of claim 13, wherein: The first read data is sampled and output to the cache memory at time intervals.

16. The system of claim 9, wherein: Each of the memory cells comprises a phase change memory (PCM) cell.

17. A method for operating a storage device, wherein: The memory device comprises a memory cell array, the memory cell array comprises word lines, bit lines, and memory cells connected between the word lines and the bit lines, and the method comprises: Receive zero refresh command; performing a first read operation on the memory cell array; and In response to determining that the data of the first memory cell of the memory cell array is “0”, the first memory cell of the memory cell array is reprogrammed with “0”.

18. The method of claim 17, further comprising: In response to determining that data of a first memory cell of the memory cell array is not “0”, a first write operation is performed to write to the memory cell of the memory cell array.

19. The method of claim 17, further comprising: storing first read data in a cache memory of the storage device during the first read operation; as well as The first read data samples are output to the cache memory at time intervals.

20. The method of claim 19, further comprising: The first read data is transmitted to a memory controller or a host.

Images