Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor (1) capable of achieving both the contact between an internal electrode layer (5) and an external electrode (3) and the adhesion between the internal electrode layer (5) and a dielectric layer (7). A laminated ceramic capacitor (1) is provided with: a laminated body (2) including a plurality of laminated dielectric layers (7) and a plurality of internal electrode layers (5), the first main surface (M1) and the second main surface (M2) face each other in the lamination direction (T), the first side surface (S1) and the second side surface (S2) face each other in the width direction (W) orthogonal to the lamination direction (T), and the first end surface (E1) and the second end surface (E2) face each other in the length direction (L) orthogonal to the lamination direction (T) and the width direction (W); and an external electrode (3) disposed on the first end surface (E1) and the second end surface (E2) and connected to the internal electrode layer (5), the internal electrode layer (5) having a first region (A1) and a second region (A2) having different coverage rates, the coverage rate of the first region (A1) being larger than that of the second region (A2), and the first region (A1) being connected to the external electrode (3).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] There are known technologies for improving the coverage of internal electrode layers in laminated ceramic capacitors. For example, Patent Document 1 describes that by setting the average crystal grain size of the internal electrode layer to 0.1 μm or less, structural defects of the internal electrode layer can be suppressed. As a result of suppressing the structural defects of the internal electrode layer, the coverage of the internal electrode layer can be improved. If the coverage of the internal electrode layer is improved, the area connected to the external electrode increases, and ESR (Equivalent Series Resistance) can be suppressed.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-7187 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] In a multilayer ceramic capacitor, there are areas where the internal electrode layer and the dielectric layer are bonded together, and areas where the dielectric layer and the dielectric layer are bonded together. The areas where the internal electrode layer and the dielectric layer are bonded together tend to be more susceptible to peeling than the areas where the dielectric layer and the dielectric layer are bonded together.

[0008] Here, if the coverage of the internal electrode layer increases, generally, the interlayer adhesion between the internal electrode layer and the dielectric layer decreases.

[0009] Therefore, if the coverage of the internal electrode layer is improved to increase the coverage, the reliability of the multilayer ceramic capacitor may decrease.

[0010] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor capable of achieving both contact between internal electrode layers and external electrodes and adhesion between internal electrode layers and dielectric layers.

[0011] Technical solutions to solve problems

[0012] A stacked ceramic capacitor comprises: a stacked body including a plurality of stacked dielectric layers and a plurality of internal electrode layers, and having a first main surface and a second main surface opposite to each other in a stacking direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the stacking direction and the width direction; and external electrodes arranged on the first end surface and the second end surface and connected to the internal electrode layers, the internal electrode layers having a first region and a second region with different coverages, the first region having a larger coverage than the second region, and the first region being connected to the external electrodes.

[0013] Effects of the Invention

[0014] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of achieving both contact between internal electrode layers and external electrodes and adhesion between internal electrode layers and dielectric layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a perspective view of a multilayer ceramic capacitor of the present invention.

[0016] Figure 2 yes Figure 1 I-I line cross-sectional view.

[0017] Figure 3 yes Figure 1 Sectional view along line II-II.

[0018] Figure 4 yes Figure 1 Sectional view along line III-III.

[0019] Figure 5 It is a diagram showing a LT cross section of an internal electrode layer.

[0020] Figure 6 It is a diagram showing a state where an internal electrode layer is formed on a dielectric layer.

[0021] Figure 7 It is a figure which shows the sheet|seat after cutting.

[0022] Figure 8 It is a diagram showing a LT cross section of a multilayer ceramic capacitor.

[0023] Fig. 9 It is a diagram showing a LT cross section of a multilayer ceramic capacitor. DETAILED DESCRIPTION

[0024] Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are attached to the same or corresponding parts in each figure.

[0025] <Outline of Multilayer Ceramic Capacitor>

[0026] based on Figure 1 , an outline of the appearance of the multilayer ceramic capacitor 1 will be described. Figure 1 1 is a perspective view showing a multilayer ceramic capacitor 1 according to the present embodiment.

[0027] like Figure 1 As shown, a multilayer ceramic capacitor 1 includes a multilayer body 2 and external electrodes 3 .

[0028] <Definition of direction>

[0029] exist Figures 1 to 9 The L direction, W direction, and T direction are shown. The L direction is the length direction L of the multilayer ceramic capacitor 1 . The W direction is the width direction W of the multilayer ceramic capacitor 1 . The T direction is the stacking direction T of the multilayer ceramic capacitor 1 .

[0030] thus, Figure 2 The section shown is called the LT section. Figure 3 The section shown is called the WT section. Figure 4 The section shown is called LW section.

[0031] The length direction L, the width direction W, and the stacking direction T are not necessarily necessarily orthogonal to each other. The length direction L, the width direction W, and the stacking direction T may be intersecting to each other.

[0032] <Laminate appearance>

[0033] like Figure 1 As shown, the stacked body 2 has a substantially rectangular parallelepiped shape.

[0034] The laminate has two main surfaces, two end surfaces, and two side surfaces. The main surfaces are surfaces facing each other in the stacking direction T. The end surfaces are surfaces facing each other in the length direction L. The side surfaces are surfaces facing each other in the width direction W.

[0035] The two main surfaces are referred to as the first main surface M1 and the second main surface M2. The two end surfaces are referred to as the first end surface E1 and the second end surface E2. The two side surfaces are referred to as the first side surface S1 and the second side surface S2.

[0036] It is preferable that the ridges and corners of the laminate 2 are rounded. The ridges are the portions where two surfaces of the laminate 2 intersect. The corners are the portions where three surfaces of the laminate 2 intersect.

[0037] <Size of laminate>

[0038] The size of the laminated body 2 can be set as follows, for example.

[0039] That is, the length of the laminate 2 in the longitudinal direction L can be 200 μm to 3500 μm. The length of the laminate 2 in the stacking direction T can be 100 μm to 2800 μm. The length of the laminate 2 in the width direction W can be 100 μm to 2800 μm.

[0040] The length of each portion of the laminate 2 can be measured using a micrometer or an optical microscope.

[0041] <Internal structure of the laminate (LT cross section)>

[0042] based on Figure 2 , the internal structure of the stacked body 2 is described. Figure 2 yes Figure 1 A cross-sectional view taken along line II of the multilayer ceramic capacitor shown.

[0043] like Figure 2 As shown, the laminated body 2 includes a plurality of dielectric layers 7 and a plurality of internal electrode layers 5. The plurality of dielectric layers 7 and the plurality of internal electrode layers 5 are laminated in a lamination direction T with respect to each other.

[0044] <Inner layer and outer layer>

[0045] The laminated body 2 includes, in the lamination direction T, an inner layer portion IL and two outer layer portions OL, namely, a first outer layer portion OL1 and a second outer layer portion OL2 which are arranged to sandwich the inner layer portion IL.

[0046] The inner layer portion IL includes a part of the plurality of dielectric layers 7 and the plurality of internal electrode layers 5. In the inner layer portion IL, the plurality of internal electrode layers 5 are arranged to face each other with the dielectric layers 7 interposed therebetween.

[0047] The inner layer portion IL is a portion that forms electrostatic capacitance and thus substantially functions as a capacitor. Therefore, it can be said that the inner layer portion IL is an effective region in the stacking direction T.

[0048] The first outer layer portion OL1 is arranged on the first main surface M1 side of the laminate 2 , and the second outer layer portion OL2 is arranged on the second main surface M2 side of the laminate 2 .

[0049] Specifically, the first outer layer portion OL1 is disposed between the inner electrode layer 5 closest to the first main surface M1 and the first main surface M1. The second outer layer portion OL2 is disposed between the inner electrode layer 5 closest to the second main surface M2 and the second main surface M2.

[0050] The first outer layer portion OL1 and the second outer layer portion OL2 do not include the internal electrode layer 5 , and include the remaining dielectric layers 7 among the plurality of dielectric layers 7 excluding the dielectric layers 7 for the inner layer portion IL.

[0051] The first outer layer portion OL1 and the second outer layer portion OL2 are portions that function as protective layers for the inner layer portion IL.

[0052] <Dielectric layer>

[0053] The dielectric layer 7 includes an outer dielectric layer 7a and an inner dielectric layer 7b.

[0054] <Outer dielectric layer>

[0055] The outer dielectric layer 7 a is a dielectric layer 7 constituting the first outer layer portion OL1 and the second outer layer portion OL2 among the dielectric layers 7 .

[0056] The outer dielectric layer 7 a is located between the first main surface M1 and the internal electrode layer 5 closest to the first main surface M1 , and between the second main surface M2 and the internal electrode layer 5 closest to the second main surface M2 .

[0057] <Inner dielectric layer>

[0058] The inner dielectric layer 7 b is a dielectric layer 7 that is located between the internal electrode layers 5 and constitutes the inner layer portion IL together with the internal electrode layers 5 .

[0059] The inner dielectric layer 7b is located between a first inner electrode layer 5a and a second inner electrode layer 5b described below.

[0060] <Number of dielectric layers>

[0061] The number of dielectric layers 7 stacked in the stacked body 2 can be, for example, 10 or more and 1800 or less. The number of dielectric layers 7 includes the number of outer dielectric layers 7a and the number of inner dielectric layers 7b.

[0062] <Thickness of dielectric layer>

[0063] The thickness of the outer dielectric layer 7 a in the dielectric layer 7 can be set to, for example, 10 μm or more and 200 μm or less. The thickness of the inner dielectric layer 7 b can be set to, for example, 0.3 μm or more and 5.0 μm or less.

[0064] <Material of dielectric layer>

[0065] The material of the dielectric layer 7 can be made of, for example, BaTiO 3 , CaTiO 3 , SrTiO 3、 Dielectric ceramics such as CaZrO3 or TiO2.

[0066] The material of the dielectric layer 7 may be a material obtained by adding a Mn compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, or the like to the above-mentioned dielectric ceramic.

[0067] <Internal electrode layer>

[0068] The internal electrode layer 5 includes a first internal electrode layer 5a and a second internal electrode layer 5b. The first internal electrode layer 5a is the internal electrode layer 5 connected to the first external electrode 3a. The second internal electrode layer 5b is the internal electrode layer 5 connected to the second external electrode 3b.

[0069] The first internal electrode layer 5a extends from the first end surface E1 toward the second end surface E2. The second internal electrode layer 5b extends from the second end surface E2 toward the first end surface E1.

[0070] <Opposing part and lead-out part>

[0071] The first internal electrode layer 5 a and the second internal electrode layer 5 b each have a counter electrode portion and a lead electrode portion.

[0072] The opposing electrode portion is a portion of the internal electrode layer 5 where the first internal electrode layer 5 a and the second internal electrode layer 5 b face each other in the stacking direction T. The lead electrode portion is a portion of the internal electrode layer 5 that is led out from the opposing electrode portion to the end surface E1 or the end surface E2 of the stacked body 2 .

[0073] The counter electrode portion of the first internal electrode layer 5a is referred to as the first counter electrode portion 5af, and the lead electrode portion of the first internal electrode layer 5a is referred to as the first lead electrode portion 5ad. The first lead electrode portion 5ad is a portion led out from the first counter electrode portion 5af to the first end surface E1 of the laminate 2.

[0074] Similarly, the opposing electrode portion of the second internal electrode layer 5b is referred to as the second opposing electrode portion 5bf, and the extraction electrode portion of the second internal electrode layer 5b is referred to as the second extraction electrode portion 5bd. The second extraction electrode portion 5bd is a portion extracted from the second opposing electrode portion 5bf to the second end surface E2 of the stacked body 2.

[0075] <Number of internal electrode layers>

[0076] The number of the internal electrode layers 5 can be, for example, not less than 10 and not more than 1800. The number of the internal electrode layers 5 includes the number of the first internal electrode layers 5a and the number of the second internal electrode layers 5b.

[0077] <Thickness of internal electrode layer>

[0078] The thickness of the internal electrode layer 5 can be set to, for example, 0.3 μm or more and 5.0 μm or less.

[0079] <Material of internal electrode layer>

[0080] The material of the internal electrode layer 5 can be, for example, a metal such as Ni, Cu, Ag, Pd, or Au, an alloy of Ni and Cu, an alloy of Ag and Pd, etc. In addition, the material of the internal electrode layer 5 may further include dielectric particles of the same composition system as the ceramic included in the dielectric layer 7.

[0081] <Electrode facing part>

[0082] The division of the laminate 2 in the longitudinal direction L will be described.

[0083] The laminated body 2 has, in the longitudinal direction L, an electrode facing portion LF and two end spacers EG, namely, a first end spacer EG1 and a second end spacer EG2 .

[0084] The electrode facing portion LF is a portion where the first internal electrode layer 5a and the second internal electrode layer 5b face each other in the stacking direction T. That is, a portion where the first opposing electrode portion 5af and the second opposing electrode portion 5bf face each other in the stacking direction T is the electrode facing portion LF.

[0085] The electrode facing portion LF is located at the center portion in the longitudinal direction L of the stacked body 2 .

[0086] The first opposed electrode portion 5af and the second opposed electrode portion 5bf are opposed to each other via the inner dielectric layer 7b, thereby forming a capacitor. Therefore, it can be said that the electrode opposed portion LF is an effective region in the longitudinal direction L.

[0087] <End spacer>

[0088] The end portion spacing portion is a portion where the first internal electrode layer 5 a and the second internal electrode layer 5 b do not face each other in the stacking direction T.

[0089] Specifically, a portion where the first internal electrode layer 5a is arranged but the second internal electrode layer 5b is not arranged in the stacking direction T is a first end spacer EG1. Similarly, a portion where the second internal electrode layer 5b is arranged but the first internal electrode layer 5a is not arranged is a second end spacer EG2.

[0090] The first end gap portion EG1 corresponds to a portion where the first lead electrode portion 5ad is arranged, and the second end gap portion EG2 corresponds to a portion where the second lead electrode portion 5bd is arranged.

[0091] The first end gap portion EG1 functions as an extraction electrode of the first internal electrode layer 5a to the first end surface E1, and the second end gap portion EG2 functions as an extraction electrode of the second internal electrode layer 5b to the second end surface E2.

[0092] The end interval EG is a division in the length direction L, and therefore is also referred to as an L interval.

[0093] The length of the end spacer portion EG in the longitudinal direction L can be set to, for example, 5 μm or more and 30 μm or less.

[0094] <External electrodes>

[0095] The external electrodes include a first external electrode 3 a and a second external electrode 3 b .

[0096] The first external electrode 3a is an external electrode disposed on the first end surface E1 of the stacked body 2. The first external electrode 3a is electrically connected to the first internal electrode layer 5a.

[0097] The first external electrode 3 a extends from the first end surface E1 to a part of both main surfaces and a part of both side surfaces.

[0098] The portion of the first external electrode 3a disposed on the first end surface E1 of the stacked body 2 is referred to as the end surface external electrode 3aE. The portion of the first external electrode 3a disposed on a portion of the first principal surface M1 or a portion of the second principal surface M2 is referred to as the principal surface external electrode 3aM. The portion of the first external electrode 3a disposed on a portion of the first side surface S1 or a portion of the second side surface S2 is referred to as the side surface external electrode 3aS.

[0099] The second external electrode 3b is an external electrode disposed on the second end surface E2 of the stacked body 2. The second external electrode 3b is electrically connected to the second internal electrode layer 5b.

[0100] The second external electrode 3 b has the same structure as the first external electrode 3 a .

[0101] That is, the second outer electrode 3 b extends from the second end surface E2 to a part of both main surfaces and a part of both side surfaces.

[0102] The portion of the second external electrode 3b disposed on the second end surface E2 of the stacked body 2 is referred to as the end surface external electrode 3bE. The portion of the second external electrode 3b disposed on a portion of the first principal surface M1 or a portion of the second principal surface M2 is referred to as the principal surface external electrode 3bM. The portion of the second external electrode 3b disposed on a portion of the first side surface S1 or a portion of the second side surface S2 is referred to as the side surface external electrode 3bS.

[0103] <Layer structure of external electrodes>

[0104] based on Figure 2 The layer structure of the external electrode 3 will be described.

[0105] The first external electrode 3a includes a first base electrode layer 3a1, a first inner plating layer 3a2, and a first surface plating layer 3a3. Similarly, the second external electrode 3b includes a second base electrode layer 3b1, a second inner plating layer 3b2, and a second surface plating layer 3b3.

[0106] Hereinafter, the layer structure of the external electrode 3 will be described based on the first external electrode 3a. The description based on the first external electrode 3a is also applicable to the second external electrode 3b. This is because the first external electrode 3a and the second external electrode 3b have the same structure although they are provided on different surfaces.

[0107] The first base electrode layer 3a1 is arranged on the first end face E1 of the stacked body 2 and covers the first end face E1 of the stacked body 2. The first base electrode layer 3a1 may extend from the first end face E1 to a portion of the first principal face M1, a portion of the second principal face M2, a portion of the first side face S1, and a portion of the second side face S2.

[0108] The first base electrode layer 3a1 may also be a fired layer containing metal and glass. As glass, a glass component containing at least one selected from B, Si, Ba, Mg, Al or Li can be cited. As a specific example, borosilicate glass can be used. As a metal, Cu is included as a main component. In addition, as a metal, for example, at least one selected from metals such as Ni, Ag, Pd or Au, or alloys such as Ag-Pd alloys can be included as a main component, and components other than the main component can also be included.

[0109] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate by an impregnation method and firing it. In addition, the fired layer may be fired after the internal electrode layer is fired, or may be fired simultaneously with the internal electrode layer. In addition, the fired layer may also be a plurality of layers.

[0110] In addition, the first base electrode layer 3a1 may be a resin layer containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-mentioned fired layer, or may be formed directly on the laminate without forming a fired layer.

[0111] The resin layer is a layer obtained by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing it. In addition, the resin layer may be fired after the internal electrode layer is fired, or may be fired simultaneously with the internal electrode layer. In addition, the resin layer may also be a plurality of layers.

[0112] The thickness of each of the first foundation electrode layer 3 a 1 and the second foundation electrode layer 425 , which are fired layers or resin layers, is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0113] Alternatively, the first base electrode layer 3 a 1 may be a thin film layer having a thickness of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition and in which metal particles are deposited.

[0114] The first inner plating layer 3a2 is disposed on the first base electrode layer 3a1 and covers at least a portion of the first base electrode layer 3a1. The first inner plating layer 3a2 includes, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0115] The first surface plating layer 3a3 is disposed on the first inner plating layer 3a2 and covers at least a portion of the first inner plating layer 3a2. The first surface plating layer 3a3 includes, for example, a metal such as Sn.

[0116] Preferably, the first inner plating layer 3a2 is a Ni plating layer, and the first surface plating layer 3a3 is a Sn plating layer. The Ni plating layer can prevent the base electrode layer from being corroded by the solder when mounting the ceramic electronic component, and the Sn plating layer can improve the wettability of the solder when mounting the ceramic electronic component, making the mounting easier. In other words, the first inner plating layer 3a2 has a characteristic of lower solder wettability than the first surface plating layer 3a3.

[0117] <Internal structure of the laminate (WT cross section)>

[0118] based on Figure 3 , and the internal structure of the stacked body 2 is described based on the appearance viewed from the second end surface E2. Figure 3 yes Figure 1 A cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown.

[0119] like Figure 3 As shown, the laminate 2 includes, in the width direction W, an electrode facing portion WF where the internal electrode layers 5 face each other, and two side spacers SG, namely, a first side spacer SG1 and a second side spacer SG2 , which are arranged to sandwich the electrode facing portion WF.

[0120] The first side spacer SG1 is located between the electrode facing portion WF and the first side surface S1 , and the second side spacer SG2 is located between the electrode facing portion WF and the second side surface S2 .

[0121] Specifically, the first lateral spacer SG1 is located between the end of the internal electrode layer 5 on the first side face S1 and the first side face S1 , and the second lateral spacer SG2 is located between the end of the internal electrode layer 5 on the second side face S2 and the second side face S2 .

[0122] The first side spacer SG1 and the second side spacer SG2 do not include the internal electrode layer 5 but include only the dielectric layer 7 .

[0123] The first side spacers SG1 and the second side spacers SG2 function as protective layers for the internal electrode layers 5 .

[0124] The side spacer SG is a partition in the width direction W, and therefore is also called a W space.

[0125] The length of the side spacer SG in the width direction W can be set to, for example, 5 μm or more and 30 μm or less.

[0126] <Size of Multilayer Ceramic Capacitors>

[0127] The length of the entire multilayer ceramic capacitor 1 including the laminate 2 and the external electrode 3 in the longitudinal direction L can be set, for example, to be greater than 0.2 mm and less than 3.5 mm. The length of the entire multilayer ceramic capacitor 1 in the stacking direction T can be set, for example, to be greater than 0.1 mm and less than 2.8 mm. The length of the entire multilayer ceramic capacitor 1 in the width direction W can be set, for example, to be greater than 0.1 mm and less than 2.8 mm.

[0128] In addition, in the present embodiment, the multilayer ceramic capacitor 1 is a two-terminal capacitor. However, the multilayer ceramic capacitor 1 is not limited to a two-terminal capacitor, and can be a multi-terminal capacitor of three or more terminals.

[0129] <Internal electrode layer coverage>

[0130] The multilayer ceramic capacitor 1 of the present embodiment is characterized by the coverage of the internal electrode layer 5. Figure 4 , the distribution of coverage within the surface of the internal electrode layer 5 is described. Figure 4 is with Figure 1 The cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 corresponds to the cross-sectional view of the multilayer body 2 along the line III-III. In other words, Figure 4 The LW cross section of the laminated body 2 at the position where the first internal electrode layer 5 a exists is shown. Figure 4 is a cross-sectional view of the laminate 2, so Figure 1 The external electrodes 3 are not shown.

[0131] Hereinafter, the first internal electrode layer 5 a will be described as the internal electrode layer 5 .

[0132] The first internal electrode layer 5a extends from the first end surface E1 toward the second end surface E2 and is located in the first end gap portion EG1 and the electrode facing portion LF in the longitudinal direction L of the laminate 2 .

[0133] The first internal electrode layer 5a has a plurality of regions having different coverage ratios within its surface.

[0134] Specifically, the first internal electrode layer 5a has four regions, namely, the first region A1 to the fourth region A4, and the coverage of these four regions is different.

[0135] <Coverage rate>

[0136] The internal electrode layer 5 is formed of the aforementioned metal material. However, the internal electrode layer 5 is not completely filled with the metal material. The internal electrode layer 5 includes a hollow portion where no metal material exists.

[0137] Therefore, the ratio of the metal material in the internal electrode layer 5 is referred to as the coverage ratio. The coverage ratio is also referred to as the coverage ratio. The method for measuring the coverage ratio will be described later.

[0138] <Area 1 to Area 4>

[0139] As described above, the first internal electrode layer 5a has four regions having different coverage ratios, namely the first region A1 to the fourth region A4.

[0140] The order of the coverage rates of the first area A1 to the fourth area A4 is: the first area A1 > the second area A2 > the third area A3 > the fourth area A4.

[0141] The arrangement of the respective regions in the first internal electrode layer 5a is as follows.

[0142] The first region A1, the third region A3, the second region A2 and the fourth region A4 are arranged in this order from the first end face E1 toward the second end face E2. Specifically, the first region A1 and the third region A3 are arranged in the first end spacer EG1, and the second region A2 and the fourth region are arranged in the electrode facing portion LF.

[0143] In other words, the first region A1 and the third region A3 occupy the first end gap portion EG1, and the second region A2 and the fourth region occupy the electrode facing portion LF.

[0144] In the multilayer ceramic capacitor 1 of the present embodiment, the internal electrode layer 5 has a plurality of regions with different coverages, thereby achieving both connectivity between the internal electrode layer 5 and the external electrode 3 and suppression of separation between the internal electrode layer 5 and the dielectric layer 7 .

[0145] The following describes the features of the area configuration in sequence.

[0146] <Feature 1>

[0147] The internal electrode layer 5 has a plurality of regions with different coverages, and the first region A1 with a large coverage is arranged at a position facing the first end surface E1, while the regions with a small coverage are arranged at other positions.

[0148] <Connectivity>

[0149] A first region A1 having a large coverage is arranged at a position in the first internal electrode layer 5a that is connected to the first external electrode 3a.

[0150] Therefore, the connectivity between the first internal electrode layer 5a and the first external electrode 3a can be improved.

[0151] <Peeling suppression>

[0152] The first internal electrode layer 5a has a second region and a third region as regions with a small coverage. The regions with a small coverage can improve the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b. As a result, interlayer delamination between the first internal electrode layer 5a and the inner dielectric layer 7b can be suppressed.

[0153] The reason for the improved adhesion is as follows. In the first internal electrode layer 5a in the area with a small coverage, there are many cavities, through holes, depressions, etc. in the first internal electrode layer 5a compared with the first internal electrode layer 5a in the area with a large coverage. The dielectric of the inner dielectric layer 7b easily enters the cavities, through holes, and depressions. Since the dielectric of the inner dielectric layer 7b enters the interior of the first internal electrode layer 5a, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b is improved.

[0154] As described above, a region with a large coverage is arranged at a position in the first internal electrode layer 5 a connected to the first external electrode 3 a , and a region with a small coverage is arranged at a position not directly involved in the connection with the first external electrode 3 a .

[0155] Therefore, it is possible to achieve both improvement in connectivity between the first external electrodes 3 a and suppression of delamination between the first internal electrode layer 5 a and the internal dielectric layer 7 b .

[0156] <Feature 2>

[0157] The first internal electrode layer 5a includes a second region A2 and a third region A3 as regions having a coverage lower than that of the first region A1. The third region A3 is disposed between the first region A1 and the second region A2 and disposed at the end spacer EG1. The coverage of the third region A3 is lower than that of the second region A2.

[0158] By arranging the first to third regions A1 to A3 as described above, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved without sacrificing either the connectivity between the first internal electrode layer 5a and the first external electrode 3a or the formation of capacitance.

[0159] The third region A3 having the smallest coverage among the first region A1 to the third region A3 is not arranged in the electrode facing portion LF but is arranged in the first end portion interval portion EG1.

[0160] Therefore, even if the coverage of the third area A3 is small, it does not hinder the formation of capacitance.

[0161] Furthermore, the third region A3 is not arranged on the first end face E1 side in the first end gap EG1 but is arranged on the electrode facing portion LF side. Therefore, the third region A3 is arranged in the first end gap EG1 but does not face the first end face E1.

[0162] As described above, even if the coverage of the third area A3 is small, the connectivity with the external electrode 3 is not reduced.

[0163] On the other hand, since the coverage of the third region A3 is small, as described above, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved.

[0164] As described above, the third region A3 with a small coverage is arranged on the side of the electrode opposing portion LF in the first end spacer portion EG, so that the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved without sacrificing either the capacitance formation or the connectivity between the first internal electrode layer 5a and the first external electrode 3a.

[0165] <Feature 3>

[0166] The fourth region A4 is disposed at the end of the second region A2 on the opposite side to the first end spacer EG1. The fourth region A4 is the region with the smallest coverage among the first region A1 to the fourth region A4. In addition, as described later, the length of the fourth region A4 in the longitudinal direction L is much shorter than the length of the second region A2 in the longitudinal direction.

[0167] By arranging the fourth region A4 as described above, it is possible to improve the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b without sacrificing the formation of capacitance.

[0168] As described later, the fourth region A4 is disposed at a portion corresponding to an end portion when the internal electrode layer 5 is formed on the dielectric layer 7 by coating or the like. Therefore, the thickness of the first internal electrode layer 5a in the fourth region A4 gradually decreases toward the end portion. That is, the cross section is inclined obliquely.

[0169] Therefore, it can be said that the end portion of the first internal electrode layer 5a where the fourth region A4 is arranged is a region that is unlikely to contribute to the formation of capacitance. Therefore, even if the coverage of the fourth region A4 is small, the influence on the formation of capacitance is not significant.

[0170] On the other hand, the end of the internal electrode layer 5 is a portion that is easily separated from the dielectric layer 7. Therefore, by arranging the fourth region A4 at the end of the first internal electrode layer 5a, separation between the first internal electrode layer 5a and the inner dielectric layer 7b can be effectively suppressed.

[0171] As described above, by arranging the fourth region A4 having the smallest coverage at the end of the first internal electrode layer 5a on the second end face E2 side, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved without sacrificing capacitance formation.

[0172] The above description is based on the first internal electrode layer 5a, and the configuration of each region is described. The above description is also the same for the second internal electrode layer 5b. In addition, the configuration of each region in the second internal electrode layer 5b will be described later based on the first internal electrode layer 5a. Figure 7 Provide explanation.

[0173] <Length of each area>

[0174] A preferred length of each region in the longitudinal direction L and a preferred ratio of each region to the length of the end interval portion EG1 (ie, L interval) in the longitudinal direction L will be described.

[0175] First, the first area A1 and the third area A3 arranged in the end interval portion EG1 are as follows.

[0176] Preferably, the length of the first region A1 is not less than 5 μm and not more than 15 μm, and the ratio of the first region A1 to the L interval is not less than 8% and not more than 25%.

[0177] Preferably, the length of the third region A3 is not less than 16 μm and not more than 45 μm, and the ratio of the length to the L interval is not less than 26% and not more than 75%.

[0178] Next, the second region A2 and the fourth region A4 arranged in the electrode opposing portion LF are as follows.

[0179] Preferably, the length of the second region A2 is greater than or equal to 1840 μm and less than or equal to 1880 μm, and the ratio of the length to the L interval is greater than or equal to 3067% and less than or equal to 3133%.

[0180] Preferably, the length of the fourth region A4 is not less than 1 μm and not more than 30 μm, and the ratio of the length to the L interval is not less than 2% and not more than 50%.

[0181] The above numerical values ​​are merely examples and can be appropriately changed according to the size of the multilayer ceramic capacitor 1 and the like.

[0182] Next, a method for measuring the coverage ratio and determining the area will be described.

[0183] <Method for measuring coverage>

[0184] The coverage ratio was measured as follows.

[0185] As described above, the internal electrode layer 5 includes a hollow portion where no metal exists. Therefore, the ratio of metal in the internal electrode layer 5 is defined as the coverage.

[0186] However, when the internal electrode layer 5 and the dielectric layer 7 are stacked, the dielectric material may fill part of the cavity of the internal electrode layer 5 .

[0187] Therefore, the coverage is defined as: metal / (metal+(void or dielectric)).

[0188] That is, the entire internal electrode layer 5 is defined as the sum of (i) metal, (ii) a portion that is not filled with dielectric and exists as a cavity, and (iii) a portion filled with dielectric in the cavity. The ratio of (i) metal to the entire internal electrode layer 5 is defined as coverage.

[0189] Specifically, the coverage can be obtained through the following steps 1 and 2.

[0190] Step 1: The surface of the laminate 2 including the longitudinal direction L and the lamination direction T (ie, the LT surface) is polished to the center portion in the width direction W to expose the LT cross section of the internal electrode layer 5 .

[0191] Step 2: Divide the exposed LT section of the internal electrode layer 5 into regions of a given length in the length direction L, and find the ratio of the metal in the divided region to the whole. The found ratio is the coverage. The given length is set to be, for example, 2% or more and 3% or less of the total length in the length direction L of the internal electrode layer 5. In addition, this length is only an example, and can be appropriately changed according to the size of the multilayer ceramic capacitor 1, the size of the end spacer, etc. For example, the given length can also be 50 μm.

[0192] The following is based on Figure 5 An example of measuring coverage will be described. Figure 5 LT is a diagram showing a cross section of the internal electrode layer 5. Specifically, Figure 5 It is shown Figure 4 FIG. 2 is a diagram showing a cross section of the first internal electrode layer 5 a taken along the line LT.

[0193] exist Figure 5 In FIG. 1 , four frames R1 to R4 are shown as outer frames of the portion where the coverage is measured. In these frames, the ratio of the metal to the whole is obtained.

[0194] In addition, Figure 5 In FIG. 1 , the dielectric (ie, dielectric material) of the dielectric layer 7 that has entered the cavity of the internal electrode layer 5 is shown as intra-cavity dielectric 7 c .

[0195] <Procedure for measuring coverage>

[0196] The order for determining coverage is as follows.

[0197] First, an optical microscope is used to observe the region within a frame within its field of view.

[0198] Then, the length L2 of the entire internal electrode layer within the field of view of the optical microscope in the longitudinal direction L is calculated. The length L1 in the longitudinal direction L where the metal is substantially observed within the range within the field of view of the optical microscope is calculated. The remaining length after subtracting the length of the "area where the metal is not observed" of the internal electrode layer from the entirety is referred to as L1.

[0199] The ratio is obtained by dividing the length L1 by the length L2, and the obtained ratio becomes the coverage rate.

[0200] <Determining the area based on coverage>

[0201] Determination of a region based on the coverage ratio value obtained as described above will be described.

[0202] The area with a coverage rate of 95% or more is determined to be the first area A1 with a large coverage rate.

[0203] An area with a coverage rate of 80% or more and less than 95% is determined to be a second area A2 in terms of coverage rate.

[0204] The region with a coverage ratio of 70% or more and less than 80% is determined to be a third region A3 with a small coverage ratio.

[0205] The area with a coverage ratio of 50% or more and less than 70% is determined to be the fourth area A4 with the smallest coverage ratio.

[0206] <First internal electrode layer and second internal electrode layer>

[0207] based on Figure 6 as well as Figure 7 , the relationship between the first internal electrode layer 5a and the second internal electrode layer 5b will be described.

[0208] Figure 6 The figure shows a state where the first internal electrode layer 5 a and the second internal electrode layer 5 b are formed on the upper surface of the dielectric layer 7 .

[0209] Figure 6 Part 601 shows a LW cross section in the laminate 2 , and part 602 shows a LT cross section corresponding to part 601 .

[0210] As shown in a portion 601 , the first internal electrode layer 5 a and the second internal electrode layer 5 b are formed on the dielectric layer 7 . This is referred to as the sheet 10 before cutting.

[0211] The pre-cut sheet 10 is cut into two at the cutting line CL. One of the two sheets produced by the cutting is referred to as the first post-cut sheet 10a, and the other is referred to as the second post-cut sheet 10b.

[0212] exist Figure 7 The first cut sheet 10a and the second cut sheet 10b are shown. Figure 7 The diagram shows the first cut sheet 10a and the second cut sheet 10b. Figure 7 The portion 701 shows the LW cross section of the first cut sheet 10 a , and the portion 702 shows the LW cross section of the second cut sheet 10 b .

[0213] The inner layer portion IL in the laminate 2 can be formed by sequentially laminating a plurality of first cut sheets 10 a shown in the portion 701 and second cut sheets 10 b shown in the portion 702 .

[0214] <Sheet before cutting>

[0215] based on Figure 6 , the sheet material 10 before cutting will be described in detail.

[0216] As described above, the internal electrode layer 5 corresponding to the first internal electrode layer 5a and the internal electrode layer 5 corresponding to the second internal electrode layer 5b are provided on the dielectric layer 7. Then, the internal electrode layer 5 is cut along the cutting line CL to separate the internal electrode layer 5 into the first internal electrode layer 5a and the second internal electrode layer 5b.

[0217] In addition, portions where the internal electrode layer 5 is not formed are provided at both ends of the dielectric layer 7 in the longitudinal direction L. These portions are portions that serve as the end gap portions EG in the laminate 2 .

[0218] According to the positional relationship between the dielectric layer 7 and the internal electrode layer 5 in the sheet material 10 before cutting, the portion of the internal electrode layer 5 facing the cutting line CL in the sheet material 10 before cutting is connected to the external electrode 3. Therefore, the portion facing the cutting line CL is preferably the first region A1 with a large coverage.

[0219] In addition, if Figure 7 As shown in the figure, in the state where the first cut sheet 10a and the second cut sheet 10b are stacked, the portion where the first internal electrode layer 5a and the second internal electrode layer 5b overlap becomes the electrode facing portion LF. The electrode facing portion LF is a portion where a capacitor is formed. Therefore, as a region subsequent to the first region A1 located on both sides of the cutting line CL, a second region A2 having a coverage ratio second only to that of the first region A1 can also be provided.

[0220] However, in the end gap portion EG, it is not necessary to make the portion of the internal electrode layer 5 subsequent to the first region A1 a region with a large coverage rate. This is because no capacitance is formed in the end gap portion EG.

[0221] Therefore, if Figure 6 As shown in FIG. 1 , the third region A3 having a smaller coverage than the first region A1 and the second region A2 is arranged in the end interval portion EG following the first region A1 .

[0222] Therefore, if Figure 7 As shown, while maintaining the connectivity between the internal electrode layer 5 and the external electrode 3 , it is possible to suppress the separation between the internal electrode layer 5 and the dielectric layer 7 using a portion that contributes little to the formation of capacitance.

[0223] Furthermore, the second region A2 having a larger coverage than the third region A3 is arranged at a position corresponding to the electrode facing portion LF as a region subsequent to the third region A3 of the internal electrode layer 5. Thus, the capacitance formed in the electrode facing portion LF can be ensured.

[0224] (Region 4)

[0225] Next, the fourth area A4 will be described.

[0226] like Figure 6 As shown, the fourth region A4 is arranged at both end portions in the longitudinal direction L of the internal electrode layer 5 in the sheet material 10 before cutting.

[0227] As shown as region LE in portion 602, the end surface is inclined obliquely at both ends of the internal electrode layer 5 in the longitudinal direction L. That is, the LT cross section of the internal electrode layer 5 has a trapezoidal shape.

[0228] In the case where the internal electrode layer 5 is formed on the dielectric layer 7 by screen printing or the like, the end surface of the internal electrode layer 5 inevitably becomes inclined.

[0229] When the internal electrode layer 5 is formed by printing, the electrode material paste is wetted and spread on the dielectric layer 7 to form a coating film. The aforementioned end face of the internal electrode layer 5 corresponds to the front end of the printed coating film. Therefore, the end face of the internal electrode layer 5 is inclined.

[0230] The film thickness of the internal electrode layer 5 is reduced in the inclined portion, so that the internal electrode layer 5 becomes a portion that is unlikely to contribute to the formation of capacitance.

[0231] Furthermore, the end faces of the internal electrode layers 5 are portions where separation from the dielectric layer 7 is likely to occur.

[0232] Therefore, the fourth region A4 having a small coverage is arranged in the region LE of the internal electrode layer 5 .

[0233] This makes it possible to improve the adhesion between the internal electrode layer 5 and the dielectric layer 7 without impairing the formation of capacitance.

[0234] <Adjustment of coverage ratio>

[0235] An example of a method for adjusting the coverage will be described. In this example, the auxiliary dielectric layer 7d is used to adjust the coverage. Therefore, first, the auxiliary dielectric layer 7d will be described.

[0236] Preferably, the difference in length in the stacking direction T of the stacked body 2 is small between the electrode facing portion LF and the end portion spacing portion EG.

[0237] However, in the inner layer portion IL, the lengths in the stacking direction T tend to be different between the electrode facing portion LF and the end spacer portion EG. This is because, in the electrode facing portion LF, a plurality of dielectric layers 7 and internal electrode layers 5 are stacked, whereas in the end spacer portion EG, only dielectric layers 7 are stacked and internal electrode layers 5 are not stacked.

[0238] Therefore, in order to reduce the difference in length between the end gap portion EG and the electrode opposing portion LF in the stacking direction T, an auxiliary dielectric layer 7 d as an additional dielectric layer 7 may be arranged in the end gap portion EG.

[0239] <Auxiliary dielectric layer>

[0240] based on Figure 8 as well as Fig. 9 , the auxiliary dielectric layer 7d is described.

[0241] Figure 8 as well as Fig. 9 LT is a diagram showing a cross section of the multilayer ceramic capacitor 1 . Figure 8 as well as Fig. 9 The simulation shows Figure 2 In addition, in the Figure 8 as well as Fig. 9 In FIG. 1 , an example in which the structure is different in the vicinity of the auxiliary dielectric layer 7 d is shown.

[0242] like Figure 8 As shown, in the first end gap EG1, an auxiliary dielectric layer 7d is disposed between two inner dielectric layers 7b. Since the auxiliary dielectric layer 7d compensates for the thickness of the second inner electrode layer 5b, the difference in length in the stacking direction T between the end gap EG and the electrode facing portion LF is reduced.

[0243] In addition, Figure 8 The structure shown and Fig. 9In the structure shown in FIG. 1 , the structure of the portion where the auxiliary dielectric layer 7d and the second internal electrode layer 5b are in contact is different. Figure 8 In the structure shown in FIG. 1 , the auxiliary dielectric layer 7d overlaps the second internal electrode layer 5b. Fig. 9 In the structure shown, the second internal electrode layer 5b overlaps the auxiliary dielectric layer 7d.

[0244] Here, overlapping means covering from the upper side in the stacking direction T. In addition, the second main surface M2 side is set as the upper side with respect to the first main surface M1. Overlapping means covering from the second main surface M side.

[0245] The auxiliary dielectric layer 7d and the internal electrode layer 5 may overlap as described above, or may not overlap. That is, the end surfaces of the layers may be in contact with each other instead of one covering the other.

[0246] The coverage can be adjusted by changing the composition of the auxiliary dielectric layer 7 d to thereby change the degree of shrinkage of the auxiliary dielectric layer 7 d that occurs during firing.

[0247] In the internal electrode layer 5 , metal discontinuities occur when following the contraction of the auxiliary dielectric layer 7 d . Therefore, the coverage of the internal electrode layer 5 can be adjusted by changing the degree of contraction of the auxiliary dielectric layer 7 d .

[0248] <Other methods of adjusting coverage ratio>

[0249] Other methods of adjusting the coverage ratio are described.

[0250] When the internal electrode layer 5 is formed on the dielectric layer 7 by screen printing, the coverage can be adjusted by adjusting the depth of the opening of the mesh used in the screen printing.

[0251] Specifically, the opening of the mesh is adjusted as follows.

[0252] Opening corresponding to the first area A1: large depth (deepest)

[0253] Opening corresponding to the second area A2: Medium depth (depth between the deepest and shallowest)

[0254] Opening corresponding to the third area A3: small depth (shallowest)

[0255] In addition, regarding the fourth area A4, the viscosity of the printed conductive paste can be adjusted to form an inclined area ( Figure 6 Area LE shown in the figure), thereby setting the 4th area A4.

[0256] The internal electrode layer 5 can also be formed using gravure printing.

[0257] When the internal electrode layer 5 is formed by gravure printing, the coverage of each region can be adjusted by adjusting the area and volume of the opening of the gravure corresponding to each region.

[0258] The area and volume of the opening can be adjusted by, for example, drawing with a laser.

[0259] In addition, whether or not to provide the aforementioned auxiliary dielectric layer 7d can be arbitrarily selected.

[0260] When providing the auxiliary dielectric layer 7d, the printing may be performed in the order of printing the Ni paste and then the paste for the auxiliary dielectric layer 7d, or vice versa.

[0261] The composition of the auxiliary dielectric layer 7d may be the same as or different from the composition of the other parts of the dielectric layer 7. Here, the composition means the elements constituting the dielectric layer 7 and the amount of the elements.

[0262] In addition, the auxiliary dielectric layer 7d and the other parts of the dielectric layer 7 may have different grains. The grains in the auxiliary dielectric layer 7d may be smaller than the grains in the other parts of the dielectric layer 7, or vice versa.

[0263] Sn may exist at the interface between the internal electrode layer 5 and the dielectric layer 7 .

[0264] Furthermore, as a method for forming the laminated body 2 , a so-called method of adding the first side spacers SG1 and the second side spacers SG2 to the counter electrode portion WF can also be used.

[0265] As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, Various changes and deformation|transformation are possible.

[0266] <1>

[0267] A multilayer ceramic capacitor comprising:

[0268] A laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; and

[0269] an external electrode, disposed on the first end surface and the second end surface and connected to the internal electrode layer;

[0270] The internal electrode layer has a first region and a second region having different coverages from each other,

[0271] The coverage of the first area is greater than that of the second area,

[0272] The first region is connected to the external electrode.

[0273] <2>

[0274] The multilayer ceramic capacitor according to <1>,

[0275] A third region is provided between the first region and the second region,

[0276] The coverage rate of the third region is smaller than any one of the coverage rate of the first region and the coverage rate of the second region.

[0277] <3>

[0278] The multilayer ceramic capacitor according to <1> or <2>, wherein:

[0279] When the region where the internal electrode layers face each other is defined as the effective region, the second region includes at least a portion of the effective region where the internal electrode layers face each other.

[0280] <4>

[0281] The multilayer ceramic capacitor according to any one of <1> to <3>,

[0282] The coverage rate of the first area is more than 95%,

[0283] The coverage rate of the second region is greater than or equal to 80% and less than 95%.

[0284] <5>

[0285] The multilayer ceramic capacitor according to <2>,

[0286] The coverage rate of the third region is greater than 70% and less than 80%.

[0287] <6>

[0288] The multilayer ceramic capacitor according to <3>,

[0289] A fourth region is provided at an end portion of the second region on the opposite side to the first region,

[0290] The coverage of the fourth region is smaller than that of any of the first region, the second region, and the third region.

[0291] <7>

[0292] The multilayer ceramic capacitor according to <6>,

[0293] The coverage rate of the fourth region is greater than 50% and less than 70%.

[0294] Description of Reference Numerals

[0295] 1: Multilayer ceramic capacitor;

[0296] 2: laminate;

[0297] 3: External electrode;

[0298] 3a: 1st external electrode;

[0299] 3b: second external electrode;

[0300] 5: Internal electrode layer;

[0301] 5a: 1st internal electrode layer;

[0302] 5ad: 1st lead electrode portion;

[0303] 5af: 1st counter electrode portion;

[0304] 5b: second internal electrode layer;

[0305] 5bd: 1st lead electrode portion;

[0306] 5bf: second opposing electrode portion;

[0307] 7: dielectric layer;

[0308] 7a: outer dielectric layer;

[0309] 7b: inner dielectric layer;

[0310] 7c: dielectric inside the cavity;

[0311] 7d: auxiliary dielectric layer;

[0312] 10: Cut off the front sheet;

[0313] 10a: Sheet after the first cut;

[0314] 10b: Sheet after the second cut;

[0315] IL: inner layer;

[0316] OL1: Outer layer 1;

[0317] OL2: Outer layer 2;

[0318] LF: electrode facing part;

[0319] EG1: 1st end spacer;

[0320] EG2: 2nd end spacer;

[0321] WF: electrode facing part;

[0322] SG1: 1st lateral septum;

[0323] SG2: lateral septum 2;

[0324] M1: 1st main surface;

[0325] M2: second main surface;

[0326] E1: 1st end face;

[0327] E2: 2nd end face;

[0328] S1: side 1;

[0329] S2: side 2;

[0330] T: stacking direction;

[0331] L: length direction;

[0332] W: width direction;

[0333] A1: Area 1;

[0334] A2: Area 2;

[0335] A3: Area 3;

[0336] A4: Area 4;

[0337] CL: Cut the line.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; and an external electrode, disposed on the first end surface and the second end surface and connected to the internal electrode layer; The internal electrode layer has a first region and a second region having different coverages from each other, The coverage of the first area is greater than that of the second area, The first region is connected to the external electrode.

2. The multilayer ceramic capacitor according to claim 1, wherein A third region is provided between the first region and the second region, The coverage rate of the third region is smaller than any one of the coverage rate of the first region and the coverage rate of the second region.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: When the region where the internal electrode layers face each other is defined as the effective region, the second region includes at least a portion of the effective region where the internal electrode layers face each other.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The coverage rate of the first area is more than 95%, The coverage rate of the second region is greater than or equal to 80% and less than 95%.

5. The multilayer ceramic capacitor according to claim 2, wherein: The coverage rate of the third region is greater than 70% and less than 80%.

6. The multilayer ceramic capacitor according to claim 2, wherein: A fourth region is provided at an end portion of the second region on the opposite side to the first region, The coverage of the fourth region is smaller than that of any of the first region, the second region, and the third region.

7. The multilayer ceramic capacitor according to claim 6, wherein: The coverage rate of the fourth region is greater than 50% and less than 70%.

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