Method and apparatus for facilitating access control in memory

Abstract

Embodiments of the invention relate to a method and apparatus for facilitating access control in a memory. Methods, apparatus, systems, and articles of manufacture are described for facilitating access control in memory. An example method includes accessing a state value stored in a non-volatile memory (304), the state value corresponding to a state of the non-volatile memory; in response to obtaining a request to enter a diagnostic mode (308), authenticating a certificate corresponding to the request (312); determining the state of the non-volatile memory based on the state value (316); and determining whether to grant or inhibit access to the non-volatile memory based on the determined state (318).

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 532,702, filed on August 15, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present description relates generally to circuits and, more particularly, to methods and apparatus for facilitating access control in memory. Background Art

[0004] Devices that include electronic components are produced by manufacturers. Such devices may include processing circuitry, memory, etc. After the device is deployed, customers may install sensitive data (including proprietary code, encrypted data, keys, and other data) into the device memory that the customer does not want others to access. If a device fails, the customer may send the device to the manufacturer or another entity for debugging to determine the cause of the failure. Summary of the invention

[0005] Examples of the present specification include an apparatus comprising: a nonvolatile memory configured to store a set of state values; a processor circuit system coupled to the nonvolatile memory and configured to store data to the nonvolatile memory; and a security manager circuit system coupled to the nonvolatile memory and configured to: access the set of state values; in response to obtaining a request to enter a diagnostic mode, authenticate a certificate corresponding to the request; based on the set of state values, determine the state of the nonvolatile memory; and based on the determined state, determine whether to grant or prohibit access to the nonvolatile memory. Other examples are described.

[0006] An example method includes: accessing a state value stored in a non-volatile memory, the state value corresponding to a state of the non-volatile memory; in response to obtaining a request to enter a diagnostic mode, authenticating a credential corresponding to the request; based on the state value, determining the state of the non-volatile memory; and based on the determined state, determining whether to grant or prohibit access to the non-volatile memory. Other examples are described.

[0007] An apparatus includes: a nonvolatile memory including a memory bank configured to store a set of state values ​​corresponding to a state of the nonvolatile memory; and a memory controller coupled to the nonvolatile memory and configured to write the set of state values ​​to the memory bank based on the state of the nonvolatile memory. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is an example state diagram illustrating different states of memory in a computing device.

[0009] Figure 2 is a block diagram of an example of a device implementing a memory.

[0010] Figure 3 The illustrated representations may be executed, instantiated, or performed by an example programmable circuit system to implement Figure 2 A flow chart of example machine-readable instructions or operations for a device circuit system to facilitate access control in a memory.

[0011] Figure 4 shows the state of the memory corresponding to Figure 2 memory in the device.

[0012] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (either functionally or structurally) features. DETAILED DESCRIPTION

[0013] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and the specification represent the same or similar parts. Although the drawings show regions with clean lines and borders, some or all of these lines or borders may be idealized. In practice, borders or lines may not be observable, blended, or irregular.

[0014] A computing device is any device that includes processing circuitry to perform one or more operations. Most computing devices include non-volatile memory that retains stored values ​​even after the computing device is powered off. Non-volatile memory includes flash memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), phase change memory (PCM), resistive random access memory (RRAM), etc. During device manufacturing, the manufacturer can initialize, prepare, and test the computing device for customer use. After the customer receives the computing device, the customer can initialize the non-volatile memory by storing sensitive data such as keys (e.g., encryption keys, authentication keys, etc.), proprietary code, or other information in the non-volatile memory.

[0015] If a device fails, the customer may send the computing device back to the manufacturer or another entity for failure analysis (e.g., debugging). However, the customer may wish to limit the ability of the manufacturer or another untrusted party to access information stored in the device. A device failure may occur in non-volatile memory or in another component of the computing device. Before sending the computing device back to the manufacturer for debugging, the customer determines whether the error occurred in the non-volatile memory or in another component of the computing device. If the error occurred in the non-volatile memory, the customer deletes data outside the location where the error occurred to avoid providing sensitive data to the entity that will debug the computing device. The customer may retain some information stored in the non-volatile memory at or near the location where the failure occurred for debugging purposes. However, the customer typically deletes any data that is not needed for debugging to avoid providing sensitive data to the manufacturer.

[0016] Traditionally, if the failure occurred outside of the non-volatile memory, then the customer would delete all data in the non-volatile memory because the deleted data is not needed for debugging. In this way, all sensitive data can be removed and therefore cannot be accessed by a third party (e.g., the manufacturer or any other entity). However, verifying that the non-volatile memory has been properly erased may be difficult because the external boot option may have been disabled due to the failure. When the failure did not occur in the non-volatile memory, the examples described herein eliminate the actions traditionally required of the customer before returning the computing device for failure analysis.

[0017] To provide a seamless failure analysis process for customers, the examples described herein utilize security manager circuitry to disable access to non-volatile memory when a failure occurs outside of the non-volatile memory. In this way, data stored in the non-volatile memory is inaccessible to the manufacturer or other entities and is protected without requiring the user to delete the data before sending the computing device to be debugged. The state of the non-volatile memory identifies whether keys have been provided in the non-volatile memory, whether code has been stored in the non-volatile memory, and whether a failure has occurred in the non-volatile memory. The user and / or computing device tracks the state and stores one or more state values ​​corresponding to the current state of the non-volatile memory in the non-volatile memory.

[0018] When the state changes, one or more state values ​​corresponding to the current state of the non-volatile memory are provided to the security manager circuit system. In this way, when the security manager circuit system obtains a request to operate the computing device in a diagnostic mode for debugging purposes, the security manager circuit system can enable or disable access to the non-volatile memory based on the one or more state values. For example, if the one or more state values ​​correspond to a state associated with a fault in the non-volatile memory, the security manager circuit system enables access to the non-volatile memory so that the fault can be debugged. However, if the one or more state values ​​correspond to a state not associated with a fault in the non-volatile memory, the security manager circuit system disables access to the non-volatile memory to protect the data stored in the non-volatile memory. Therefore, when a fault other than the non-volatile memory occurs, the customer does not need to delete the non-volatile memory to protect the information stored in the non-volatile memory when returning the device for debugging, because the security manager circuit system prevents anyone from accessing the data in the non-volatile memory. Therefore, the examples described herein provide a seamless and secure return of a computing device containing a non-volatile memory.

[0019] Figure 1 1 is an example state diagram 100 showing different states of memory within a device. State diagram 100 includes a test state 102, a high security - field security state (HS-FS) 104, a high security - key provisioned state (HS-KP) 106, a high security - security enabled state (HS-SE) 108, a high security - fault analysis state (HS-FA) 110, a diagnostic - no memory state (DGN-NOM) 112, and a diagnostic memory state (DGN-M) 114.

[0020] exist Figure 1 In the test state 102 of the non-volatile memory, the device may be tested by the manufacturer before being sent to the customer. In the test state 102, the manufacturer may perform various tests to ensure that the device operates correctly according to any standards or requirements. After the testing is completed, the device is provided to the customer and the non-volatile memory is initialized to the HS-FS state 104. The HS-FS state 104 of the non-volatile memory can be considered an initial state. In the HS-FS state 104, the customer has not yet provided / stored a key and has not yet stored / provided code into the non-volatile memory.

[0021] After the customer provides or stores the key in non-volatile memory, the device enters Figure 1 HS-KP state 106. Because the key contains sensitive data (e.g., authentication keys, encryption keys, etc.), HS-KP state 106 is the first state in which an override device for debugging may cause the non-volatile memory to be decoupled or otherwise unavailable to anyone.

[0022] In some examples, after the customer provides the key to the non-volatile memory, the customer may store one or more state values ​​in one or more memory cells of the non-volatile memory to indicate that the key has been provided. In some examples, the processing device may automatically store the one or more state values ​​in the one or more memory cells of the non-volatile memory to indicate that the key has been provided after the user provides the key to the non-volatile memory. Therefore, the one or more state values ​​in the one or more memory cells indicate the state of the non-volatile memory. As further described below, the security manager circuit system may access the one or more state values ​​after obtaining a request to operate the device in a diagnostic mode to determine the state of the non-volatile memory. In this way, the security manager circuit system can enable or disable access to the non-volatile memory based on the state of the non-volatile memory. For example, if a diagnostic mode request is obtained when the one or more state values ​​indicate that the device is in the HS-KP state 106, the security manager circuit system will disable access to the non-volatile memory to cause the device to enter the diagnostic mode no memory state 112, as further described below.

[0023] After the customer provides or stores the code in non-volatile memory, the device enters Figure 1 HS-SE state 108. Because the code may contain proprietary and / or sensitive information, HS-SE state 108 (also referred to as code provided state) is a second state in which an override device for debugging may cause the non-volatile memory to be decoupled or unavailable to anyone. In some examples, after the customer provides the code to the non-volatile memory, the customer may store one or more state values ​​in one or more memory cells of the non-volatile memory to indicate that the code has been provided. In some examples, the processing device may automatically store the one or more state values ​​in the one or more memory cells of the non-volatile memory to indicate that the code has been provided after the user provides the code to the non-volatile memory. Therefore, the one or more state values ​​in the one or more memory cells indicate the state of the non-volatile memory. As further described below, the security manager circuit system may access the one or more state values ​​after obtaining a request to cause the device to operate in a diagnostic mode to determine the state of the non-volatile memory. In this way, the security manager circuit system can enable or disable access to the non-volatile memory based on the state of the non-volatile memory. For example, if a diagnostic mode request is obtained when the one or more state values ​​indicate that the device is in the HS-SE state 108, the security manager circuitry may disable access to non-volatile memory to cause the device to enter the diagnostic no memory state 112, as further described below.

[0024] If a failure occurs at the nonvolatile memory (e.g., a nonvolatile memory failure) while the device is operating in the HS-KP state 106 or the HS-SE state 108, the device enters Figure 1 HS-FA state 110 (e.g., non-volatile memory failure state). In order to transform to HS-FA state 110, a user can perform an action to delete sensitive information (e.g., a return mechanism authorization (RMA) protocol) while maintaining data at or near a location associated with the failure. For example, if a failure occurs when accessing or storing information at a specific location of the non-volatile memory, the user can maintain the information at the location. In addition, the user can maintain information at several locations near the location where the failure occurred and delete the remaining data. In this way, during debugging, the manufacturer can access data at or near the location where the failure occurred and run a debugging protocol based on the accessed data. In some examples, after the customer executes the RMA protocol, the customer can store one or more status values ​​in one or more memory cells of the non-volatile memory to indicate that the RMA protocol is complete (e.g., corresponding to HS-FA state 110). In some examples, the processing device can automatically store the one or more status values ​​in the one or more memory cells of the non-volatile memory after the customer executes the RMA protocol to indicate the HS-FA state 110 of the non-volatile memory. Thus, the one or more state values ​​in the one or more memory cells indicate a state of the non-volatile memory. As further described below, the security manager circuitry may access the one or more state values ​​after obtaining a request to cause the device to enter a diagnostic mode to determine the state of the non-volatile memory. In this way, the security manager circuitry may enable or disable access to the non-volatile memory based on the state of the non-volatile memory. For example, if a diagnostic mode request is obtained when the one or more state values ​​indicate that the device is in the HS-FA state 110, the security manager circuitry will enable access to the non-volatile memory to cause the device to enter the diagnostic memory state 114, as further described below.

[0025] Figure 1The DGN-NOM state 112 occurs after the manufacturer obtains access to the device for debugging and requests a diagnostic mode, while the non-volatile memory is in the HS-KP state 106 or the HS-SE state 108. As described above, if the fault does not occur in the non-volatile memory and sensitive data is already stored in the non-volatile memory, then the security controller will disable access to the non-volatile memory because the information is not relevant to debugging the fault. Therefore, after the security manager circuitry obtains a request to put the device into diagnostic mode, the security manager circuitry can determine the state of the non-volatile memory and enter the DGN-NOM state 112 if the current state of the non-volatile memory is the HS-KP state 106 or the HS-SE state 108. The DGN-NOM state 112 protects customer data without requiring additional action by the customer.

[0026] Figure 1 The DGN-M state 114 occurs after the manufacturer obtains access to the device for debugging purposes and requests a diagnostic mode, while the non-volatile memory is in the HS-FS state 104 or the HS-FA state 110. As described above, in the HS-FS state 104, no sensitive data is stored in the non-volatile memory. Therefore, there is no need to disable access to the non-volatile memory. Therefore, if the manufacturer requests that the device enter diagnostic mode, the security manager circuit system enables access to the non-volatile memory while the non-volatile memory is in the HS-FS state 104. In the HS-FA state 110, the customer has executed an RMA protocol to delete sensitive data stored in the non-volatile memory while maintaining sufficient information to debug the fault. Therefore, if the manufacturer requests that the device enter diagnostic mode, the security manager circuit system enables access to the non-volatile memory based on the non-volatile memory being in the HS-FA state 110.

[0027] Figure 2 2 is a block diagram of an example device 200 described in conjunction with the examples described herein. Device 200 includes non-volatile memory 202, memory bank 203, memory unit 204, memory controller 205, direct memory access (DMA) controller 206, security manager 207, interface 208, processor circuitry 210, and machine-readable instructions 212a-c.

[0028] Figure 2 The device 200 may be any device including non-volatile memory and processing circuitry. For example, the device 200 may be a computer, a mobile phone, a tablet, a server, a cloud-based or edge-based device, a television, a video game device, an automotive computing device, and / or any other device including or otherwise connected to non-volatile memory and processing circuitry.

[0029] Figure 2 The non-volatile memory 202 is a memory that can store data and maintain the stored data even if power is off. The non-volatile memory 202 can be a flash memory, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), a phase change memory (PCM), a resistive random access memory (RRAM), etc. The non-volatile memory 202 includes an example memory storage body 203 and a memory controller 205, and the memory storage body includes memory cells for storing data. The memory controller 205 reads (e.g., accesses) or writes (e.g., stores) data to the memory storage body 203 based on instructions from the DMA controller 206 or the processor circuit system 210. After the customer obtains the device 200, the customer can store key information, codes, etc. in the memory storage body 203 of the non-volatile memory 202. The memory storage body 203 of the non-volatile memory 202 includes a memory cell 204 reserved for storing state information. Therefore, after the user performs a specific action to cause the non-volatile memory 202 to change state (e.g., provide a key, provide a code, perform an RMA), the user directly or indirectly changes the value of the one or more memory cells 204 to indicate that the action has occurred. In some examples, after the user performs a specific action, the non-volatile memory controller (e.g., memory controller 205) or processor circuit system 210 automatically adjusts the state value in the one or more memory cells 204 to indicate that the action has occurred. Therefore, the state value in the one or more memory cells 204 corresponds to the state of the non-volatile memory 202. The state value stored in the one or more memory cells 204 is protected. For example, the entire sector storing state information can be programmed only on the device 200 (e.g., each bit can be changed from 1 to 0, but cannot be changed from 0 to 1). In such an example, the sector is not erasable after leaving the test mode. Therefore, after the user programming, the state cannot be erased. Therefore, an attacker needs a device-specific certificate to override any state value of the one or more memory cells 204. Examples of correlations between the state value of memory cell 204 and the state of non-volatile memory 202 are described below in conjunction with Figure 4 Further description.

[0030] Figure 2The DMA controller 206 of the non-volatile memory 202 performs direct memory access to read, write, or otherwise access a state value in the non-volatile memory 202, such as the memory unit 204. As described above, the state value stored in the memory unit 204 corresponds to the state of the non-volatile memory 202. The DMA controller 206 stores the accessed state value in a storage device (e.g., one or more registers, flip-flops, other storage devices, etc.) in the security manager 207. In some examples, the DMA controller 206 cooperates with the memory controller 205 of the non-volatile memory 202 to access data from the memory unit 204. For example, in response to a direct memory access instruction from the DMA controller 206, the memory controller 205 may output data corresponding to the direct memory access instruction. In some examples, the DMA controller 206 may use any combination of hard-coded logic and / or programmable logic to execute or instantiate machine-readable instructions 212a (also referred to as one or more computer-readable instructions) to operate.

[0031] Figure 2 The security manager 207 (also referred to as the security manager circuit system) is a circuit system that controls access to the non-volatile memory 202 when entering the diagnostic mode. The security manager 207 includes any combination of one or more registers, flip-flops, or other storage devices for storing state values ​​accessed from the memory unit 204. After the security manager 207 obtains a request to enter the diagnostic mode (e.g., via the interface 208), the security manager 207 first authenticates the request by sending information corresponding to the request to the processor circuit system 210 for authentication. For example, the request contains information that can authenticate that the entity requesting the diagnostic mode is real. In some examples, the request may include a manufacturer's certificate and a certificate associated with the device 200 itself. For example, after a customer returns the device 200 for debugging, the customer may provide the manufacturer with a device-specific or customer-specific certificate (also referred to as a device certificate or a customer certificate). In addition, the manufacturer may have a manufacturer-specific certificate provided with the diagnostic mode request. As further described below, the processor circuit system 210 may authenticate the diagnostic mode request based on the manufacturer-specific certificate and the device / customer-specific certificate. After the processor circuit system 210 authenticates the manufacturer to put the device 200 into the diagnostic mode, the security manager 207 processes the stored state value to determine the state of the non-volatile memory 202. The security manager 207 controls access to the non-volatile memory 202 in the diagnostic mode based on the determined state. For example, if the security manager 207 determines that the state of the device 200 is Figure 1If the security manager 207 determines that the state of the device 200 is in the HS-FS state 104 or the HS-FA state 110, the security manager 207 sets the state of the device 200 to the diagnostic memory state 114 and enables access to the non-volatile memory 202. Figure 1 If the HS-KP state 106 or HS-SE state 108 of the device 200 is set to the diagnostic no memory state 112 and access to the non-volatile memory 202 is disabled. The memory state 112 may be gated or decoupled from the non-volatile memory 202 using switches, logic circuits, or any other circuit system. In some examples, the security manager 207 may use any combination of hard-coded logic and / or programmable logic to execute or instantiate machine-readable instructions 212b (also referred to as one or more computer-readable instructions) to perform operations.

[0032] Figure 2 Interface 208 of the device 200 obtains a request from the manufacturer to put the device 200 into diagnostic mode. After the device is returned to the manufacturer for debugging, the manufacturer submits a request to put the device 200 into diagnostic mode to execute the debugging protocol. In order to ensure that the manufacturer is authentic and that they are executing the correct protocol on the correct device, the diagnostic mode request can include manufacturer credentials (e.g., unique identifier, password, username, etc.) and customer credentials (e.g., customer-provided password, customer-provided username, unique identifier of the device 200, etc.) via interface 208. Interface 208 forwards the request and credentials to security manager 207. If the credentials are not authenticated, then interface 208 can output a signal indicating an authentication error back to the entity that transmitted the diagnostic mode request.

[0033] Figure 2The processor circuit system 210 obtains a certificate from the manufacturer via the interface 208 and the security manager 207. The processor circuit system 210 authenticates the manufacturer certificate. For example, the processor circuit system 210 can compare the manufacturer certificate with the stored certificate to verify that the certificate matches. In addition, the processor circuit system 210 authenticates the customer certificate to ensure that the entity requesting the diagnostic mode is operating the expected device. The processor circuit system 210 can compare the customer certificate with the stored certificate to verify that the certificate matches. If the processor circuit system 210 determines that the certificate is authentic, the processor circuit system 210 outputs a signal to the security manager 207 to continue to enter the diagnostic mode and allow access to the device 200. If the processor circuit system 210 determines that the certificate is invalid or unauthentic, the processor circuit system 210 outputs a signal to the security manager 207 to prevent entry into the diagnostic mode. In some examples, the processor circuit system 210 can use any combination of hard-coded logic and / or programmable logic to execute or instantiate machine-readable instructions 212c (also referred to as one or more computer-readable instructions) to operate.

[0034] Figure 3 It is shown that the Figure 2 Flowchart of a method or operation 300 performed or instantiated by the memory controller 205, DMA controller 206, security manager 207, processor circuitry 210, or any other component of the device 200 to facilitate fault analysis of the device 200. Figure 3 The machine readable instructions or operations 300 of begin at block 302: the DMA controller 206 determines whether the non-volatile memory 202 is booting up, initializing, or resetting. The non-volatile memory 202 boots up / initializes / resets during power-up and / or after a user changes the state of the non-volatile memory 202.

[0035] If the DMA controller 206 has not obtained information corresponding to a state change of the non-volatile memory 202 (block 302: No), control returns to block 302 until the state change information is obtained. If the DMA controller 206 obtains information corresponding to a state change from the non-volatile memory 202 (block 302: Yes), the DMA controller 206 accesses a state value from the memory unit 204 of the non-volatile memory 202 (block 304). For example, the DMA controller 206 may perform DMA to obtain the state value stored in the memory unit 204. At block 306, the example DMA controller 206 stores the accessed state value in any combination of a register, a flip-flop, or other storage device of the security manager 207.

[0036] At block 308, the example security manager 207 determines whether a diagnostic mode certificate has been obtained. Figure 2As described, after the device 200 is returned to the manufacturer for debugging, the manufacturer connects to the interface 208 of the device to provide a diagnostic mode request with one or more certificates for the diagnostic mode. Therefore, after the interface 208 obtains the diagnostic mode request, the interface 208 provides the request and the corresponding certificate to the security manager 207. If the security manager 207 determines that the diagnostic mode certificate has been obtained by the interface 208 (block 308: yes), then control continues to 312. If the security manager 207 determines that the diagnostic mode certificate has not been obtained (block 308: no), then the DMA controller 206 determines whether the information corresponding to the state change has been obtained from the non-volatile memory 202 (block 310). If the DMA controller 206 determines that the information corresponding to the state change has not been obtained from the non-volatile memory 202 (block 310: no), then control returns to block 308. If the DMA controller 206 determines that the information corresponding to the state change has been obtained from the non-volatile memory 202 (block 310: yes), then control returns to block 302.

[0037] At block 312, processor circuitry 210 determines whether the diagnostic mode certificate is authentic. For example, processor circuitry 210 compares the one or more certificates to stored certificates to determine whether the obtained certificate matches the stored certificate. If processor circuitry 210 determines that the diagnostic mode certificate is not authentic (block 312: No), processor circuitry 210 outputs a signal to security manager 207 to prevent entry into the diagnostic mode (block 314). If processor circuitry 210 determines that the diagnostic mode certificate is authentic (block 312: Yes), security manager 207 determines the state of non-volatile memory 202 based on the stored state value accessed from memory unit 204 (block 316). As described above, the stored state value corresponds to the state of non-volatile memory 202 and can be used to determine whether fault analysis requires access to the non-volatile memory.

[0038] At block 318, the security manager 207 determines whether the state of the non-volatile memory 202 corresponds to a memory failure analysis. For example, if the security manager 207 can determine, based on the stored state value, that the state of the non-volatile memory 202 corresponds to a memory failure analysis, Figure 1 The memory fault analysis of the state value of the HS-FS state 104 or the HS-FA state 110, or the state of the nonvolatile memory 202 does not correspond to the state value of the HS-FS state 104 or the HS-FA state 110 based on the state value corresponding to Figure 1 If the security manager 207 determines that the state corresponds to a memory failure analysis (block 318: yes), the security manager 207 enters a diagnostic mode while being able to access non-volatile memory (e.g., Figure 1If the security manager 207 determines that the state does not correspond to a memory failure analysis (block 318: No), the security manager 207 enters a diagnostic mode but is unable to access non-volatile memory (e.g., Figure 1 DGN-NOM status 112) (box 322).

[0039] Figure 4 An example table 400 is shown of state values ​​that may be stored in memory cells 204 of non-volatile memory 202 and corresponding non-volatile memory states. Figure 4 Contains four memory cells each holding a value (e.g., '0' or '1'). The key provided (KP) memory cell holds a value indicating that a key has been provided. After the customer provides the key in the non-volatile memory 202, the user or processing circuit changes the value of the non-volatile memory 202, causing the DMA controller 206 to set the value of the KP register to '1'. The code provided (CP) memory cell holds a value indicating that the code has been provided in the non-volatile memory 202. After the customer provides the code to the non-volatile memory 202, the user or processing circuit changes the value of the non-volatile memory 202, causing the DMA controller 206 to set the value of the CP register to '1'. The FA memory cell holds a value indicating that the RMA protocol is being executed to cause the non-volatile memory 202 to enter FA analysis. After the customer executes the RMA protocol, the user or processing circuit changes the value of the non-volatile memory 202, causing the DMA controller 206 to set the value of the FA register to '1'.

[0040] As shown in the example table 400, if the state values ​​of the KP, CP, and FA memory cells are '0', then the state of the non-volatile memory 202 is the same as Figure 1 If the state values ​​of the CP and FA memory cells are '0' and the value of the KP memory cell is '1', then the state of the non-volatile memory 202 is associated with the HS-FS state 104. Figure 1 If the value of the CP memory cell is '0' and the state values ​​of the KP and FA memory cells are '1', then the state of the non-volatile memory 202 is associated with the HS-FS state 104. Figure 1 If the value of the FA memory cell is '0' and the state values ​​of the KP and CP memory cells are '1', then the state of the non-volatile memory 202 is associated with the HS-FA state 110. Figure 1 If the state values ​​of the KP, CP and FA memory cells are '1', then the state of the non-volatile memory 202 is associated with the HS-SE state 108. Figure 14. In some examples, a state value corresponding to an unused state may be associated with the HS-FA state 110. In this example, other combinations of state values ​​are not used. In some examples, a customer or device is prohibited from entering a state value corresponding to an unused state in a memory cell. For example, a memory controller of the non-volatile memory 220 may prevent a state value corresponding to an unused state from being written (e.g., stored) into the memory cell 204. In some examples, if a state value corresponding to an invalid state is input, an error message or alarm may be triggered. Although the state values ​​in table 400 reflect specific state values, the state values ​​may be reversed. For example, '0' in the table may be replaced with '1', and '1' may be replaced with '0'.

[0041] exist Figure 2 An example method of implementing the apparatus 200 is shown in FIG. Figure 2 One or more of the elements, processes, and / or devices shown may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0042] In addition, non-volatile memory 202, memory controller 205, DMA controller 206, security manager 207, interface 208 and / or processor circuit system 210 can be implemented by hardware, software, firmware and / or any combination of hardware, software and / or firmware. Thus, for example, any of non-volatile memory 202, DMA controller 206, security manager 207, interface 208 and / or processor circuit system 210 can be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable logic devices (PLDs) and / or field programmable logic devices (FPLDs).

[0043] When any apparatus or system claim of this patent is read to cover pure software and / or firmware implementations, at least one of non-volatile memory 202, memory controller 205, DMA controller 206, security manager 207, interface 208, and / or processor circuit system 210 is expressly defined herein as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., comprising software and / or firmware. Still further, non-volatile memory 202, memory controller 205, DMA controller 206, security manager 207, interface 208, and / or processor circuit system 210 may include one or more elements, processes, and / or devices as Figure 2In addition to or in place of those shown, and / or may include any or all of more than one of the elements, processes and devices shown. As used herein, the phrase "communication", including variations thereof, covers direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-time events.

[0044] Figure 3 The diagram shows a method for implementing Figure 2 The flowchart of example hardware logic, machine readable instructions, hardware implemented state machine and / or any combination thereof of the apparatus 200 of the present invention is shown. The machine readable instructions may be one or more executable programs or portions of executable programs for execution by a computer processor. The programs may be embodied as software stored on a non-transitory computer readable storage medium, such as a CD-ROM, floppy disk, hard drive, DVD, Blu-ray disk, or memory associated with a processor, but the entire program and / or portions thereof may alternatively be executed by a device other than a processor and / or embodied as firmware or dedicated hardware.

[0045] Furthermore, although the sample programs are reference Figure 3 The flowchart shown in the figure is described, but many other methods of implementing the device 200 may be used instead. For example, the execution order of the blocks can be changed, and / or some of the blocks described can be changed, eliminated, or combined. In addition or alternatively, any or all of the blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without the need to execute software or firmware.

[0046] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, and the like, and the machine-readable instructions described herein may be stored as data (e.g., portions of instructions, code, code representations, and the like) that may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, reassigned, compiled, and the like in order to enable them to be directly read, interpreted, and / or executed by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and stored on separate computing devices, where the portions, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program (e.g., the program described herein).

[0047] In another example, the machine-readable instructions may be stored in a state in which they can be read by a computer, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the instructions on a particular computing device or another device. In another example, the machine-readable instructions may be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before the machine-readable instructions and / or corresponding programs can be executed in whole or in part. Thus, the machine-readable instructions and / or corresponding programs encompass such machine-readable instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs when stored or otherwise at rest or in transmission.

[0048] The machine-readable instructions described herein may be represented by any past, present or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0049] As mentioned above, Figure 3The example processes of can be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on a non-transitory computer and / or machine readable medium, such as a hard drive, flash memory, read-only memory, compact disk, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, temporarily, for temporary buffering, and / or for information caching). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media.

[0050] Although certain example methods, apparatus, and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture that fully fall within the scope of the claims of this patent.

[0051] When identifying multiple elements or components that can be mentioned separately, the descriptors "first", "second", "third", etc. are used herein. Unless otherwise specified or understood from the context of their use, such descriptors do not confer any meaning of priority, physical order or arrangement in a list, or time ordering, but are merely used as labels to refer to multiple elements or components separately to facilitate understanding of the described examples. In some examples, the descriptor "first" can be used to refer to an element in the detailed description, while the same element can be referred to by different descriptors in the claims, such as "second" or "third". In such cases, such descriptors are used simply for convenience in referring to multiple elements or components.

[0052] In the specification and claims, unless otherwise indicated, the terms "including" and "having" and their variations are similar to the term "comprising" and should be inclusive. Unless otherwise indicated, the "about", "roughly" or "substantially" in front of a value refers to + / -10% of the value. In another example, the "about", "roughly" or "substantially" in front of a value refers to + / -5% of the value. In another example, the "about", "roughly" or "substantially" in front of a value refers to + / -1% of the value.

[0053] As used herein, the terms "couple", "coupled", "couples" and variations thereof may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, if a first example device A is coupled to device B, or if a second example device A is coupled to device A through an intermediate component C (provided that the intermediate component C does not substantially change the functional relationship between device A and device B), such that device B is controlled by device A via the control signal generated by device A. In addition, the terms "couple", "coupled", "couples" or variations thereof include indirect or direct electrical or mechanical connections.

[0054] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by the manufacturer to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through construction and / or arrangement of hardware components and interconnection of the device, or through a combination of these operations.

[0055] although Figure 2 Although not all are individually labeled, the components or elements of the systems and circuits shown therein have one or more conductors or terminals that allow signals to enter and / or leave the components or elements. Conductors or terminals (or portions thereof) may be referred to herein as pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0056] As used herein, the "end" of a component, device, system, circuit, integrated circuit or other electronic or semiconductor component is generally a conductor, such as a wire, trace, pin, pad or other connector or interconnect, which enables the component, device and system, etc. to be electrically connected and / or mechanically connected to another component, device or system, etc. For example, an end can be used to receive or provide an analog or digital electrical signal (or simply, a signal), or to be electrically connected to a common or ground reference. Therefore, an input end or input is used to receive a signal from another component, device, system, etc. An output end or output is used to provide a signal to another component, device, system, etc. Other ends can be used to connect to a common, ground or voltage reference, such as a reference end or ground terminal. The end of an IC or PCB may also be referred to as a pin (vertical conductor) or a pad (planar conductor). A node refers to a connection or interconnection point of two or more ends. An example number of ends and nodes may be shown. However, depending on a specific circuit or system topology, there may be more or fewer ends and nodes. However, in some cases, "ends", "nodes", "interconnects", "pads" and "pins" may be used interchangeably.

[0057] The term "or" or "and / or" when used in the form of, for example, A, B and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A, B and C.

[0058] Example methods, devices, systems, and articles of manufacture for facilitating access control in memory are described herein. Other examples and combinations thereof include the following: Example 1 includes a device comprising: a non-volatile memory configured to store a set of state values; a processor circuit system coupled to the non-volatile memory and configured to store data to the non-volatile memory; and a security manager circuit system coupled to the non-volatile memory and configured to: access the set of state values; in response to obtaining a request to enter a diagnostic mode, authenticate a certificate corresponding to the request; based on the set of state values, determine a state of the non-volatile memory; and based on the determined state, determine whether to allow or prohibit access to the non-volatile memory.

[0059] Example 2 includes the apparatus of example 1, wherein the certificate includes a manufacturer certificate and a device certificate.

[0060] Example 3 includes the apparatus of Example 1, wherein the processor circuitry is configured to store the set of state values ​​based on storing the data to the non-volatile memory.

[0061] Example 4 includes the apparatus of Example 1, wherein the security manager circuitry is configured to permit access to the nonvolatile memory based on determining that the state corresponds to a nonvolatile memory failure.

[0062] Example 5 includes the apparatus of example 1, wherein the state of the nonvolatile memory corresponds to a key provisioned state, a code provisioned state, or a nonvolatile memory failure state.

[0063] Example 6 includes the apparatus of Example 5, wherein the security manager circuitry is configured to disable access to the non-volatile memory based on determining that the state corresponds to the key-provided state or the code-provided state.

[0064] Example 7 includes the apparatus of Example 1, wherein the security manager circuitry is configured to transition to the diagnostic mode based on authenticating the credential.

[0065] Example 8 includes a method comprising: accessing a status value stored in a non-volatile memory, the status value corresponding to a status of the non-volatile memory; in response to obtaining a request to enter a diagnostic mode, authenticating a certificate corresponding to the request; based on the status value, determining the status of the non-volatile memory; and based on the determined status, determining whether to permit or prohibit access to the non-volatile memory.

[0066] Example 9 includes the method of example 8, wherein the certificate includes a manufacturer certificate and a device certificate.

[0067] Example 10 includes the method of example 8, wherein the state is user defined.

[0068] Example 11 includes the method of Example 8, wherein granting the access to the nonvolatile memory is based on determining that the state corresponds to a nonvolatile memory failure.

[0069] Example 12 includes the method of Example 8, wherein the state of the nonvolatile memory corresponds to a key provisioned state, a code provisioned state, or a nonvolatile memory failure state.

[0070] Example 13 includes the method of example 12, wherein disabling the access to the non-volatile memory is based on determining that the state corresponds to the key-provided state or the code-provided state.

[0071] Example 14 includes the method of Example 8, further comprising causing the state to enter the diagnostic mode based on authenticating the certificate.

[0072] Example 15 includes a device comprising: a non-volatile memory, which includes a memory storage body configured to store a set of state values ​​corresponding to the state of the non-volatile memory; and a memory controller, which is coupled to the non-volatile memory and configured to write the set of state values ​​to the memory storage body based on the state of the non-volatile memory.

[0073] Example 16 includes the nonvolatile memory of Example 15, wherein the memory bank includes three memory cells for storing data corresponding to the state of the nonvolatile memory.

[0074] Example 17 includes the nonvolatile memory of Example 15, wherein the state of the nonvolatile memory corresponds to a key provided state, a code provided state, or a nonvolatile memory failure state.

[0075] Example 18 includes the nonvolatile memory of Example 15, further comprising a direct memory access controller to cause the set of state values ​​to be stored in registers of the security manager circuitry.

[0076] Example 19 includes the nonvolatile memory of Example 15, wherein the memory controller is to prevent the set of state values ​​from being written to the memory bank when the set of state values ​​corresponds to an unused state.

[0077] Example 20 includes the nonvolatile memory of Example 15, wherein in response to a direct memory access instruction, the memory controller is to output the set of status values.

[0078] The described examples can be modified, and other examples are possible, within the scope of the claims.

Claims

1. A device comprising: a non-volatile memory configured to store a set of state values; processor circuitry coupled to the non-volatile memory and configured to store data to the non-volatile memory; as well as a security manager circuit system coupled to the non-volatile memory and configured to: accessing the set of state values; In response to obtaining a request to enter a diagnostic mode, authenticating a credential corresponding to the request; determining a state of the non-volatile memory based on the set of state values; as well as Based on the determined status, a determination is made whether to grant or prohibit access to the non-volatile memory.

2. The apparatus of claim 1, wherein the certificate comprises a manufacturer certificate and a device certificate. 3 . The apparatus of claim 1 , wherein the processor circuitry is configured to store the set of state values ​​based on storing the data to the non-volatile memory.

4. The apparatus of claim 1, wherein the security manager circuitry is configured to permit access to the non-volatile memory based on a determination that the status corresponds to a non-volatile memory failure.

5. The apparatus of claim 1, wherein the state of the non-volatile memory corresponds to a key provisioned state, a code provisioned state, or a non-volatile memory failure state.

6. The apparatus of claim 5, wherein the security manager circuitry is configured to disable access to the non-volatile memory based on determining that the state corresponds to the key-provided state or the code-provided state.

7. The apparatus of claim 1, wherein the security manager circuitry is configured to transition to the diagnostic mode based on authenticating the credential.

8. A method comprising: accessing a state value stored in a non-volatile memory, the state value corresponding to a state of the non-volatile memory; In response to obtaining a request to enter a diagnostic mode, authenticating a credential corresponding to the request; Based on the state value, determining the state of the non-volatile memory; as well as Based on the determined status, a determination is made whether to grant or prohibit access to the non-volatile memory.

9. The method of claim 8, wherein the certificates include a manufacturer certificate and a device certificate.

10. The method of claim 8, wherein the status is user defined.

11. The method of claim 8, wherein granting the access to the nonvolatile memory is based on determining that the state corresponds to a nonvolatile memory failure.

12. The method of claim 8, wherein the state of the non-volatile memory corresponds to a key provisioned state, a code provisioned state, or a non-volatile memory failure state.

13. The method of claim 12, wherein disabling the access to the non-volatile memory is based on determining that the state corresponds to the key-provided state or the code-provided state.

14. The method of claim 8, further comprising causing the state to enter the diagnostic mode based on authenticating the certificate.

15. An apparatus comprising: a non-volatile memory comprising a memory bank configured to store a set of state values ​​corresponding to a state of the non-volatile memory; as well as A memory controller is coupled to the non-volatile memory and is configured to write the set of state values ​​to the memory bank based on the state of the non-volatile memory.

16. The apparatus of claim 15, wherein the memory bank comprises three memory cells for storing data corresponding to the state of the non-volatile memory.

17. The apparatus of claim 15, wherein the state of the non-volatile memory corresponds to a key provisioned state, a code provisioned state, or a non-volatile memory failure state.

18. The device of claim 15, further comprising a direct memory access controller to cause the set of state values ​​to be stored in registers of security manager circuitry.

19. The apparatus of claim 15, wherein the memory controller is to prevent the set of state values ​​from being written to the memory bank when the set of state values ​​corresponds to an unused state.

20. The apparatus of claim 15, wherein in response to a direct memory access instruction, the memory controller is to output the set of status values.

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