A hybrid cache architecture and cache data management method and system

Abstract

The present application relates to the field of storage, specifically to a hybrid cache architecture and a cache data management method and system. The hybrid cache architecture includes multiple cache groups, each cache group includes M SRAM storage spaces and N STT‑RAM storage spaces, SRAM is used for cache data writing, and STT‑RAM is used to maintain the data content in the cache; each storage space of the STT‑RAM has two states: activated and deactivated. The cache data management method sets a counting register and a threshold T1 based on the hybrid cache architecture, and performs adaptive tag comparison when reading data. The adaptive tag comparison greatly compresses the exploration space, and only the cache paths of the STT‑RAM in the activated state participate in the tag comparison, thereby improving the operation speed. The present invention can not only improve the area utilization and reduce the overall power consumption, but also reduce the tag comparison exploration space, significantly reducing the power consumption and delay of the tag comparison process while ensuring performance.

Description

Technical Field

[0001] This application relates to the field of storage technologies, for example, to a hybrid cache architecture, a cache data management method, and a system. Background Art

[0002] In a GPGPU, the cache structure usually includes two parts: the L1 cache private to the SM (Streaming Multiprocessor) or CU (Compute Unit), and the L2 cache shared by each SM. The capacity and performance of the cache structure are closely related to the performance of the entire GPGPU. Due to the high cost of increasing the L1 cache capacity, the research focus has gradually shifted to the optimization of the L2 cache structure.

[0003] The traditional L2 cache is composed of SRAM. The leakage power consumption in the case of a large-capacity design is the main problem faced by the design, and this problem will become more serious when expanding the cache size and affect data integrity. Therefore, researchers have turned their attention to non-volatile storage technologies.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] In view of the deficiencies of the prior art, the present invention provides a hybrid cache architecture, a cache data management method, and a system, which improve the area utilization rate and reduce the overall power consumption.

[0006] To solve the above technical problems, the technical solution adopted by the present invention is: a hybrid cache architecture, including a plurality of cache groups, each cache group including M SRAM storage spaces and N STT-RAM storage spaces, M + N = H, and M < N, where H is the total number of storage spaces in the cache group, SRAM is used to cache data writes, and STT-RAM is used to maintain the data content in the cache; each storage space of STT-RAM has two states: active and deactivated, active indicating the existence of valid data, and deactivated indicating that the data in the current storage space is invalid.

[0007] The present invention also discloses a cache data management method, which is implemented based on the above hybrid cache structure and includes data writing and data reading. The process of data writing is as follows:

[0008] S11. Receive a data write request, and determine whether the SRAM storage space is full. If the SRAM storage space is not full, perform a write operation to the available SRAM storage space. If the SRAM storage space is full, proceed to step S12;

[0009] S12, data migration, first determine whether there is a storage space in the STT-RAM with a disabled state, if so, migrate the data in the SRAM to the STT-RAM storage space with a disabled state, and set the state of the migrated SRAM storage space to empty, set the state of the migrated STT-RAM storage space to activated, and perform a write operation on the storage space in the SRAM with an empty state; if there is no storage space in the STT-RAM with a disabled state, proceed to step S13;

[0010] S13, perform a data pop-up operation on a certain storage space of the STT-RAM cache, after the data pop-up operation is performed, set the state of the storage space where it is located to disabled, perform data migration on the storage space set to disabled state, and perform a write operation on the SRAM storage space vacated by the data migration; there are two ways to pop out data, one is to adopt the first-in-first-out FIFO data mode, the first data stored is first popped out after the STT-RAM space is full, the second is to adopt the least recently used principle, set a memory access counter to monitor the access frequency of the STT-RAM and adjust the state of the storage space according to the access frequency, for each clock cycle after the storage space is set to be activated, if the current storage space is not accessed, the corresponding memory access counter is increased by 1, for each SST-RAM storage space, if the count of the memory access counter exceeds the threshold T1, it is considered that the data in the current storage space is temporarily not accessed, the data is popped out and the state is changed to disabled, and the counter is reset;

[0011] The process of data reading is:

[0012] S21, receiving a data read request, comparing the tag in the data read request with the tag in the hybrid cache architecture to determine whether the cache hits, the tag comparison is performed by a tag checker and a tag comparator, the tag checker is connected to the STT-RAM, the input of the tag checker is the cache tag of each storage space of the STT-RAM and the corresponding state identifier, the cache tag is selected according to the state identifier, if the state identifier is activated, the tag comparator is enabled and the cache tag is sent to the tag comparator;

[0013] S22, the tag comparator receives the tag in the data read request and the cache tag, performs a hit comparison on the tag in the data read request and the cache tag, and then reads data from the hit cache; if the status is marked as disabled, skips the comparison operation of the current tag.

[0014] Furthermore, the threshold T1 is dynamically updated, and the updating process is as follows: when the tag comparator returns a hit signal, the status of all storage spaces in the current STT-RAM is collected and counted. If the number of storage units in the disabled state is 0, it means that the threshold T1 is too high, and the threshold T1 is reduced by 1, otherwise the threshold T1 is increased by 1; when the tag comparator returns a miss signal, the status of all storage spaces in the current STT-RAM is also collected and counted. If the number of storage spaces in the disabled state is greater than half of the total number of storage spaces in the STT-RAM, it means that the threshold T1 is too low, and the threshold T1 is increased by 1, otherwise the threshold T1 is reduced by 1.

[0015] Furthermore, the least recently used principle takes precedence over the first-in-first-out FIFO data mode.

[0016] Furthermore, the tag checker is also connected to the SRAM. When connected to the SRAM, the input of the tag checker is the cache tag of each storage space of the SRAM and the corresponding status identifier. The cache tag is selected according to the status identifier. If the status identifier is full, the tag comparator is enabled and the cache tag is sent to the tag comparator. The input of the tag comparator is the tag and the cache tag in the data read request. The tag in the data read request and the cache tag are compared, and then the data is read from the hit cache; if the status identifier is empty, the comparison operation of the current tag is skipped.

[0017] Furthermore, when reading data, STT-RAM has a higher priority than SRAM.

[0018] Furthermore, the bit width of the memory access counter is configurable.

[0019] The present invention also discloses a cache data management system, comprising a hybrid cache architecture, a data writing module and a data reading module. The hybrid cache architecture is the above-mentioned hybrid cache architecture. The data writing module comprises an SRAM state judgment module, an STT-RAM state judgment module, a data migration module and a data pop-up module. The SRAM state judgment module is connected to the hybrid cache architecture and is used to judge whether the SRAM storage space is full. If the SRAM storage space is not full, a write operation is performed to the available storage space of the SRAM. If the SRAM storage space is full, a SRAM storage space full signal is sent to the STT-RAM module. After receiving the SRAM storage space full signal, the STT-RAM state judgment module judges whether there is a storage space in the STT-RAM with a disabled state. If so, a data migration signal is sent to the data migration module. The data migration module migrates the data in the SRAM to the STT-RAM storage space with a disabled state, and sets the state of the migrated SRAM storage space to empty. The state of the migrated STT-RAM storage space is set to activated, and the state of the SRAM is empty. The storage space is written; if there is no storage space in the STT-RAM whose status is disabled, a data pop-up signal is sent to the data pop-up module, and the data pop-up module performs a data pop-up operation on a storage space in the STT-RAM cache. There are two ways to pop out data. One is to adopt the first-in-first-out FIFO data mode. The first data stored is first popped out after the STT-RAM space is full. The second is to adopt the least recently used principle and set a memory access counter to monitor the access frequency of the STT-RAM and adjust the state of the storage space according to the access frequency. For each clock cycle after the storage space is set to be activated, if the current storage space is not accessed, the corresponding memory access counter is increased by 1. For each SST-RAM storage space, if the count of the memory access counter exceeds the threshold T1, it is considered that the data in the current storage space is not accessed temporarily, and the data is popped out and the status is changed to disabled, and the counter is reset; after the data pop-up operation is performed, the status of the storage space where it is located is set to disabled, data migration is performed on the storage space whose status is set to disabled, and a write operation is performed on the SRAM storage space vacated by the data migration;

[0020] The data reading module includes a tag checker and a tag comparator. The tag checker is connected to the STT-RAM. The input of the tag checker is the cache tag of each storage space of the STT-RAM and the corresponding status flag. The cache tag is selected according to the status flag. If the status flag is activated, the tag comparator is enabled and the cache tag is sent to the tag comparator; the tag comparator receives the tag and cache tag in the data reading request, performs a hit comparison on the tag in the data reading request and the cache tag, and then reads data from the hit cache; if the status flag is disabled, the comparison operation of the current tag is skipped.

[0021] Furthermore, the threshold T1 is dynamically updated, and the updating process is as follows: when the tag comparator returns a hit signal, the status of all storage spaces in the current STT-RAM is collected and counted. If the number of storage units in the disabled state is 0, it means that the threshold T1 is too high, and the threshold T1 is reduced by 1, otherwise the threshold T1 is increased by 1; when the tag comparator returns a miss signal, the status of all storage spaces in the current STT-RAM is also collected and counted. If the number of storage spaces in the disabled state is greater than half of the total number of storage spaces in the STT-RAM, it means that the threshold T1 is too low, and the threshold T1 is increased by 1, otherwise the threshold T1 is reduced by 1.

[0022] Furthermore, the tag checker is also connected to SRAM. When connected to SRAM, the input of the tag checker is the cache tag of each storage space of SRAM and the corresponding status flag. The cache tag is selected according to the status flag. If the status flag is full, the tag comparator is enabled and the cache tag is sent to the tag comparator. The input of the tag comparator is the tag and cache tag in the data read request. The tag in the data read request and the cache tag are compared, and then the data is read from the hit cache; if the status flag is empty, the comparison operation of the current tag is skipped; when reading data, STT-RAM has a higher priority than SRAM.

[0023] Beneficial effects of the present invention: The present invention proposes a hybrid cache architecture of RAM and STT-RAM. STT-RAM is a non-volatile storage with better performance and durability. The hybrid architecture of STT-RAM & SRAM reduces power consumption and improves area utilization. However, the hybrid architecture of STT-RAM & SRAM also expands the cache search area, and the increase in memory access time also brings additional overhead. Therefore, a data management method based on adaptive tag comparison is proposed, which reduces the tag comparison exploration space, significantly reduces the power consumption and delay of the tag comparison process while ensuring performance.

[0024] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0026] Figure 1 is a principle block diagram of the hybrid cache architecture described in the embodiment;

[0027] Figure 2 It is a flowchart of data writing;

[0028] Figure 3 It is a flowchart of data reading;

[0029] Figure 4 It is the schematic diagram of data writing, data migration, and data pop-up;

[0030] Figure 5 This is the principle block diagram of the data writing module;

[0031] Figure 6 This is the principle block diagram of the data reading module. DETAILED DESCRIPTION

[0032] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0033] Unless otherwise stated, the term "plurality" means two or more.

[0034] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0035] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0036] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0037] Example 1

[0038] This embodiment discloses a hybrid cache architecture, which is applied to the L2 cache of a GPGPU, such as Figure 1As shown, it includes multiple cache groups. Each cache group is composed of M SRAM storage units and N STT-RAM storage units, where M + N = H, M < N, and H is the total number of storage units in the cache group. The SRAM part uses its low-power writing feature to write cached data, while the STT-RAM part uses its stability to maintain the main data content in the cache. In this embodiment, each storage space of SRAM and STT-RAM has a status flag bit. The status flag bit of SRAM has two states: full and empty. Full means that the current storage space has data or the stored data is in a valid state, and empty means that the current storage unit has no data or the stored data is in an invalid state. Each storage space of STT-RAM has two states: active and deactivated. Active means that valid data exists, and deactivated means that the data in the current storage space is invalid.

[0039] Embodiment 2

[0040] The present invention also discloses a cache data management method, which is implemented based on the hybrid cache structure described in Embodiment 1 and includes data writing and data reading, as Figure 2 shown, the process of data writing is as follows:

[0041] S11. Receive a data writing request, and determine whether the SRAM storage space is full. If the SRAM storage space is not full, perform a writing operation to the available SRAM storage space. If the SRAM storage space is full, proceed to step S12;

[0042] S12. Data migration. First, determine whether there is a deactivated storage space in the STT-RAM. If there is, migrate the data in the SRAM to the deactivated STT-RAM storage space, set the status of the migrated SRAM storage space to empty, set the status of the migrated STT-RAM storage space to active, and perform a writing operation to the SRAM storage space with an empty status. If there is no deactivated storage space in the STT-RAM, proceed to step S13;

[0043] S13, perform a data pop-up operation on a storage space of the STT-RAM cache. After the data pop-up operation is performed, the state of the storage space is set to disabled, data migration is performed on the storage space set to disabled, and a write operation is performed on the SRAM storage space vacated by the data migration. There are two ways to pop out data. One is to adopt the first-in-first-out FIFO data mode. The first data stored is popped out first after the STT-RAM space is full. The second is to adopt the least recently used principle and set a memory access counter to monitor the access frequency of the STT-RAM and adjust the state of the storage space according to the access frequency. For each clock cycle after the storage space is set to be activated, if the current storage space is not accessed, the corresponding memory access counter is increased by 1. For each SST-RAM storage space, if the count of the memory access counter exceeds the threshold T1, it is considered that the data in the current storage space is temporarily not accessed, the data is popped out and the state is changed to disabled, and the counter is reset.

[0044] like Figure 4 As shown, it is the principle diagram of data writing, data migration and data pop-up. Figure 4 The first line is a schematic diagram of regular data writing. When there is data to be written, the data will be written to the available storage space in SRAM. Regular cache writes cannot directly write to the STT-RAM area. Data writing to STT-RAM is performed through data migration inside the cache, such as Figure 4 As shown in the second row. Each storage space of STT-RAM has two states: activated (ACT) and deactivated (DEA), and the current state is identified by a flag bit. ACT indicates that valid data exists, while DEA indicates that the data in the current cache line is invalid. When data is available in SRAM or the SRAM storage space is full, and there is a storage space in SST-RAM with a state of DEA, data migration is performed. Remove the data in SRAM and set the corresponding storage space state to empty, then store the data in the storage space of SST-RAM, and change the flag bit of the current way to ACT.

[0045] When trying to write data, if the SRAM is full, it will first try to migrate the data. If the STT-RAM is also full, that is, the status of each channel is ACT, the data will be ejected. There are two ways to eject data. One is Figure 4 As shown in the third row, STT-RAM adopts the FIFO data mode of first-in first-out. The first data stored will be popped out first when the storage space is full, the data will be cleared and the flag bit will be flipped, and then data migration will be performed.

[0046] However, there are exceptions to the first-in, first-out data mode. For each way in the STT-RAM, this scheme additionally designs a memory access counter with a configurable bit width to monitor the access frequency and dynamically adjust the state of the current way accordingly. For each clock cycle after the storage space state is set to ACT, if the current storage space is not accessed, the memory access counter is incremented by 1. For each SST-RAM storage space, if its memory access count exceeds the predetermined threshold T1, it is considered that the data in the current storage space will not be accessed temporarily. Then the state is changed to DEA, the counter is reset and the data is cleared for data migration, such as Figure 4 As shown in the fourth row. In this embodiment, the priority of popping data from the memory access counter is higher than that of LRU. That is, when the memory access counter count does not reach the predetermined threshold value T1, the FIFO data mode is adopted. When the memory access counter count reaches the predetermined threshold value T1, the FIFO data mode is adopted. Figure 4 The method shown in the fourth row.

[0047] The purpose of introducing the access counter is to compress the tag comparison exploration space to reduce the delay, power consumption and bit error rate of tag comparison. Tag comparison is mainly used in the data reading process, such as Figure 3 As shown, the process of data reading is:

[0048] S21, receiving a data read request, comparing the tag in the data read request with the tag in the hybrid cache architecture to determine whether the cache hits, the tag comparison is performed by a tag checker and a tag comparator, the tag checker is connected to the STT-RAM, the input of the tag checker is the cache tag of each storage space of the STT-RAM and the corresponding state identifier, the cache tag is selected according to the state identifier, if the state identifier is activated, the tag comparator is enabled and the cache tag is sent to the tag comparator;

[0049] S22, the tag comparator receives the tag and cache tag in the data read request, performs a hit comparison on the tag and cache tag in the data read request, and then reads data from the hit cache; if the status is marked as disabled, the comparison operation of the current tag is skipped. In this process, the exploration space of the tag comparison is compressed, and only the cache way of the STT-RAM in the ACT state participates in the tag comparison, which improves the operation speed.

[0050] It can be seen from the data reading process that the compression degree of the exploration space is closely related to the value of the threshold T1. In this embodiment, the threshold T1 is dynamically updated. When the value increases, the data life of the corresponding cache path will be extended. When the value decreases, the data life will be shortened and the compression rate of the exploration space will be improved. The update process is: when the tag comparator returns a hit signal, the status of all storage spaces in the current STT-RAM is collected and counted. If the number of storage units in the disabled state is 0, it means that the threshold T1 is too high, and the threshold T1 is reduced by 1, otherwise the threshold T1 is increased by 1; when the tag comparator returns a miss signal, the status of all storage spaces in the current STT-RAM is also collected and counted. If the number of storage spaces in the disabled state is greater than half of the total number of storage spaces in the STT-RAM, it means that the threshold T1 is too low, and the threshold T1 is increased by 1, otherwise the threshold T1 is reduced by 1.

[0051] In this embodiment, the tag checker is also connected to the SRAM. When connected to the SRAM, the input of the tag checker is the cache tag of each storage space of the SRAM and the corresponding status identifier. The cache tag is selected according to the status identifier. If the status identifier is full, the tag comparator is enabled and the cache tag is sent to the tag comparator. The input of the tag comparator is the tag and the cache tag in the data read request. The tag in the data read request and the cache tag are compared, and then the data is read from the hit cache; if the status identifier is empty, the comparison operation of the current tag is skipped.

[0052] When reading data, STT-RAM has a higher priority than SRAM.

[0053] Example 2

[0054] This embodiment discloses a cache data management system, including a hybrid cache architecture, a data writing module and a data reading module, wherein the hybrid cache architecture is the hybrid cache architecture described in Embodiment 1. Figure 5As shown, the data writing module includes an SRAM status judgment module, an STT-RAM status judgment module, a data migration module and a data pop-up module. The SRAM status judgment module is connected to the hybrid cache architecture and is used to judge whether the SRAM storage space is full. If the SRAM storage space is not full, a write operation is performed to the available storage space of the SRAM. If the SRAM storage space is full, a SRAM storage space full signal is sent to the STT-RAM module. After receiving the SRAM storage space full signal, the STT-RAM status judgment module judges whether there is a storage space in the STT-RAM with a disabled state. If so, a data migration signal is sent to the data migration module. The data migration module migrates the data in the SRAM to the STT-RAM storage space with a disabled state, and sets the state of the migrated SRAM storage space to empty. The state of the migrated STT-RAM storage space is set to activated, and a write operation is performed to the storage space with an empty state of the SRAM. If there is no storage space in the STT-RAM with a disabled state, the STT-RAM storage space is activated after migration. If the storage space is disabled, a data pop-up signal is sent to the data pop-up module, and the data pop-up module performs a data pop-up operation on a storage space of the STT-RAM cache. There are two ways to pop out data. One is to adopt the first-in-first-out FIFO data mode. The first data stored in the STT-RAM space is popped out first after the STT-RAM space is full. The second is to adopt the least recently used principle and set a memory access counter to monitor the access frequency of the STT-RAM and adjust the state of the storage space according to the access frequency. For each clock cycle after the storage space is set to be activated, if the current storage space is not accessed, the corresponding memory access counter is increased by 1. For each SST-RAM storage space, if the count of the memory access counter exceeds the threshold T1, it is considered that the data in the current storage space is not accessed temporarily, and the data is popped out and the state is changed to disabled, and the counter is reset; after the data pop-up operation is executed, the state of the storage space where it is located is set to disabled, data migration is performed on the storage space set to disabled, and a write operation is performed on the SRAM storage space vacated by the data migration.

[0055] like Figure 6 As shown, the data reading module includes a tag checker and a tag comparator. The tag checker is connected to the STT-RAM. The input of the tag checker is the cache tag of each storage space of the STT-RAM and the corresponding state flag. The cache tag is selected according to the state flag. If the state flag is activated, the tag comparator is enabled and the cache tag is sent to the tag comparator; the tag comparator receives the tag and cache tag in the data read request, performs a hit comparison on the tag and cache tag in the data read request, and then reads the data from the hit cache; if the state flag is disabled, the comparison operation of the current tag is skipped. In this process, the exploration space of the tag comparison is compressed, and only the cache way of the STT-RAM with the state of ACT participates in the tag comparison, which improves the operation speed.

[0056] In this embodiment, the threshold T1 is dynamically updated, and the updating process is as follows: when the tag comparator returns a hit signal, the status of all storage spaces in the current STT-RAM is collected and counted. If the number of storage units in the disabled state is 0, it means that the threshold T1 is too high, and the threshold T1 is reduced by 1, otherwise the threshold T1 is increased by 1; when the tag comparator returns a miss signal, the status of all storage spaces in the current STT-RAM is also collected and counted. If the number of storage spaces in the disabled state is greater than half of the total number of storage spaces in the STT-RAM, it means that the threshold T1 is too low, and the threshold T1 is increased by 1, otherwise the threshold T1 is reduced by 1.

[0057] The tag checker is also connected to SRAM. When connected to SRAM, the input of the tag checker is the cache tag and the corresponding status flag of each storage space of SRAM. The cache tag is selected according to the status flag. If the status flag is full, the tag comparator is enabled and the cache tag is sent to the tag comparator. The input of the tag comparator is the tag and cache tag in the data read request. The tag in the data read request and the cache tag are compared, and then the data is read from the hit cache; if the status flag is empty, the comparison operation of the current tag is skipped; when reading data, STT-RAM has a higher priority than SRAM.

[0058] In summary, the present invention proposes a hybrid L2 cache structure of SRAM and STT-RAM, and designs a data management method adapted to the hybrid cache structure. It can solve the data integrity problem of the traditional SRAM cache, improve area utilization and reduce overall power consumption. At the same time, for a larger cache structure, the tag comparison exploration space is reduced, and the power consumption and delay of the tag comparison process are significantly reduced while ensuring performance.

[0059] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or including (comprising) refer to the existence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or these groups. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same or similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0060] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0061] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically separately, or two or more units may be integrated in one unit.

Claims

1. A cache data management method, characterized in that: This method is implemented based on a hybrid cache architecture. The hybrid cache architecture includes multiple cache groups. Each cache group includes M SRAM storage spaces and N STT-RAM storage spaces, where M + N = H and M < N. Here, H is the total number of storage spaces in the cache group. SRAM is used to cache data writes, and STT-RAM is used to maintain the data content in the cache. Each storage space in STT-RAM has two states: active and inactive. Active means valid data exists, and inactive means the data in the current storage space is invalid. The cache data management method includes data write and data read. The process of data write is as follows: S11. Receive a data write request, and determine whether the SRAM storage space is full. If the SRAM storage space is not full, perform a write operation to the available SRAM storage space. If the SRAM storage space is full, proceed to step S12; S12. Data migration. First, determine whether there is an inactive storage space in STT-RAM. If there is, migrate the data in SRAM to the inactive STT-RAM storage space, set the state of the migrated SRAM storage space to empty, set the state of the migrated STT-RAM storage space to active, and perform a write operation to the SRAM storage space with an empty state. If there is no inactive storage space in STT-RAM, proceed to step S13; S13. Perform a data pop operation on a certain storage space in the STT-RAM cache. After the data pop operation, set the state of the storage space where it is located to inactive, perform data migration on the storage space with the state set to inactive, and perform a write operation on the SRAM storage space vacated by the data migration. There are two ways of data pop. One is to use the FIFO (First In First Out) data mode. The data that is stored first is popped first after the STT-RAM space is full. The other is to use the least recently used principle. Set a memory access counter to monitor the access frequency of STT-RAM and adjust the state of the storage space according to the access frequency. For each clock cycle after the storage space is set to active, if the current storage space is not accessed, the corresponding memory access counter is incremented. For each STT-RAM storage space, if the count of the memory access counter exceeds the threshold T1, it is considered that the data in the current storage space is not accessed temporarily, pop the data and change the state to inactive, and reset the counter; The process of data read is as follows: S21. Receive a data read request. Compare the tag in the data read request with the tags in the hybrid cache architecture to determine whether the cache is hit. The tag comparison is performed through a tag checker and a tag comparator. The tag checker is connected to STT-RAM. The input of the tag checker is the cache tag and the corresponding status flag of each storage space in STT-RAM. Discard the cache tag according to the status flag. If the status flag is active, enable the tag comparator and send the cache tag to the tag comparator; S22, the tag comparator receives the tag in the data read request and the cache tag, performs a hit comparison on the tag in the data read request and the cache tag, and then reads data from the hit cache; if the status is marked as disabled, skips the comparison operation of the current tag.

2. The cache data management method according to claim 1, characterized in that: Threshold T1 is dynamically updated, and the updating process is as follows: when the tag comparator returns a hit signal, the status of all storage spaces in the current STT-RAM is collected and counted. If the number of storage units in the disabled state is 0, it means that threshold T1 is too high, and threshold T1 is reduced by 1, otherwise threshold T1 is increased by 1; when the tag comparator returns a miss signal, the status of all storage spaces in the current STT-RAM is also collected and counted. If the number of storage spaces in the disabled state is greater than half of the total number of storage spaces in the STT-RAM, it means that threshold T1 is too low, and threshold T1 is increased by 1, otherwise threshold T1 is reduced by 1.

3. The cache data management method according to claim 1, characterized in that: The least recently used principle takes precedence over the first-in-first-out FIFO data mode.

4. The cache data management method according to claim 1, characterized in that: The tag checker is also connected to the SRAM. When connected to the SRAM, the input of the tag checker is the cache tag of each storage space of the SRAM and the corresponding status flag. The cache tag is selected according to the status flag. If the status flag is full, the tag comparator is enabled and the cache tag is sent to the tag comparator. The input of the tag comparator is the tag and the cache tag in the data read request. The tag in the data read request and the cache tag are compared, and then the data is read from the hit cache. If the status flag is empty, skip the comparison operation of the current tag.

5. The cache data management method according to claim 4, characterized in that: When reading data, STT-RAM has a higher priority than SRAM.

6. The cache data management method according to claim 1, characterized in that: The bit width of the memory access counter is configurable.

7. A cache data management system, characterized in that: It includes a hybrid cache architecture, a data writing module, and a data reading module. The hybrid cache architecture includes multiple cache groups. Each cache group includes M SRAM storage spaces and N STT-RAM storage spaces, where M + N = H and M < N. Here, H is the total number of storage spaces in the cache group. SRAM is used to cache data writing, and STT-RAM is used to maintain the data content in the cache. Each storage space in STT-RAM has two states: active and deactivated. Active means valid data exists, and deactivated means the data in the current storage space is invalid. The data writing module includes an SRAM status judgment module, an STT-RAM status judgment module, a data migration module, and a data pop module. The SRAM status judgment module is connected to the hybrid cache architecture and is used to judge whether the SRAM storage space is full. If the SRAM storage space is not full, a write operation is performed on the available SRAM storage space. If the SRAM storage space is full, a signal indicating that the SRAM storage space is full is sent to the STT-RAM module. After receiving the signal that the SRAM storage space is full, the STT-RAM status judgment module judges whether there is a deactivated storage space in STT-RAM. If there is, a data migration signal is sent to the data migration module. The data migration module migrates the data in SRAM to the deactivated STT-RAM storage space, sets the status of the migrated SRAM storage space to empty, sets the status of the migrated STT-RAM storage space to active, and performs a write operation on the SRAM storage space with an empty status. If there is no deactivated storage space in STT-RAM, a data pop signal is sent to the data pop module. The data pop module performs a data pop operation on a certain storage space cached in STT-RAM. There are two ways of data pop. One is to adopt the FIFO (First In First Out) data mode. The data that is stored first is popped first after the STT-RAM space is full. The other is to adopt the least recently used principle. A memory access counter is set to monitor the access frequency of STT-RAM and adjust the status of the storage space according to the access frequency. For each clock cycle after the storage space is set to active, if the current storage space is not accessed, the corresponding memory access counter is incremented. For each STT-RAM storage space, if the count of the memory access counter exceeds the threshold T1, it is considered that the data in the current storage space is not accessed temporarily, the data is popped and the status is changed to deactivated, and the counter is reset. After the data pop operation is performed, the status of the storage space where it is located is set to deactivated, a data migration is performed on the storage space with a deactivated status, and a write operation is performed on the SRAM storage space emptied by the data migration. The data reading module includes a tag checker and a tag comparator. The tag checker is connected to the STT-RAM. The input of the tag checker is the cache tag of each storage space of the STT-RAM and the corresponding status flag. The cache tag is selected according to the status flag. If the status flag is activated, the tag comparator is enabled and the cache tag is sent to the tag comparator; the tag comparator receives the tag and cache tag in the data reading request, performs a hit comparison on the tag in the data reading request and the cache tag, and then reads data from the hit cache; if the status flag is disabled, the comparison operation of the current tag is skipped.

8. The cache data management system according to claim 7, characterized in that: Threshold T1 is dynamically updated, and the updating process is as follows: when the tag comparator returns a hit signal, the status of all storage spaces in the current STT-RAM is collected and counted. If the number of storage units in the disabled state is 0, it means that threshold T1 is too high, and threshold T1 is reduced by 1, otherwise threshold T1 is increased by 1; when the tag comparator returns a miss signal, the status of all storage spaces in the current STT-RAM is also collected and counted. If the number of storage spaces in the disabled state is greater than half of the total number of storage spaces in the STT-RAM, it means that threshold T1 is too low, and threshold T1 is increased by 1, otherwise threshold T1 is reduced by 1.

9. The cache data management system according to claim 7, characterized in that: The tag checker is also connected to the SRAM. When connected to the SRAM, the input of the tag checker is the cache tag of each storage space of the SRAM and the corresponding status flag. The cache tag is selected according to the status flag. If the status flag is full, the tag comparator is enabled and the cache tag is sent to the tag comparator. The input of the tag comparator is the tag and the cache tag in the data read request. The tag in the data read request and the cache tag are compared, and then the data is read from the hit cache. If the status flag is empty, the comparison operation of the current tag is skipped; when reading data, STT-RAM has a higher priority than SRAM.

Images