Power-on control method and device of server, medium and program product

Abstract

The invention discloses a power-on control method and device of a server, a medium and a program product, and relates to the technical field of servers, a control system of the server negotiates and defines an out-of-band response identifier used for indicating whether a substrate management controller responds to an out-of-band command or not in advance, and the out-of-band response identifier is used for indicating whether the substrate management controller responds to the out-of-band command when power-on of the server starts. The processor firstly configures the out-of-band response identifier to be in a first state, and at the moment, the substrate management controller executes a power-on time sequence of the server and does not respond to an out-of-band command; after the power-on time sequence of the server is executed, the processor and the basic input / output system adjust the out-of-band response identifier to the second state, and the baseboard management controller normally responds to the peripheral power supply control command; the external power supply command is suppressed by additionally configuring the out-of-band response identifier, so that the condition that the power-on time sequence of the server is interfered can be fundamentally avoided, and the whole time sequence startup and shutdown process is independently carried out and is not interfered by the outside.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a power-on control method, equipment, medium and program product of a server. Background Art

[0002] With the continuous development of computer service technology, the CPU (Central Processing Unit) system in the server system has become more and more complex. How to ensure the stability of system services in various scenarios has become more and more important. In particular, when the service cluster needs to be restarted as a whole, it is necessary to ensure the smooth control of the power-on / off timing of the server system as a whole to ensure the normal power on and off of the machine. Taking the server power-on as an example, the default power-on timing is generally executed in sequence. However, during the power-on process, there may be power-on commands issued out of band, and the BMC (Baseboard Management Controller) will still respond to out-of-band commands to notify the CPLD (Complex Programming logic device) to perform some timing operations. However, these out-of-band timing operations will impact the power-on timing of the server's own CPU; especially at certain key timing points, if some peripheral signals are pulled low, the power-on timing of the server system itself may be disrupted, causing the machine to be in a downtime state.

[0003] It can be seen that how to prevent the out-of-band command from affecting the normal power on and off of the server is a problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a server power-on control method, device, medium and program product, which can solve the problem that the normal power-on sequence of the server is disrupted by out-of-band commands, causing the server to crash.

[0005] To solve the above technical problems, an embodiment of the present invention provides a power-on control method for a server, which is applied to a control system of the server. The control system of the server includes a processor, a baseboard management controller, and a basic input and output system. The power-on control method for the server includes: The processor configures the out-of-band response flag to a first state in response to a power-on trigger signal of the server; The processor controls the power module of the server to power on the hardware devices in the server according to the power-on sequence; When the hardware device in the server is powered on, the basic input and output system is started, and the out-of-band response identifier is configured to the second state; The baseboard management controller detects the status of the out-of-band response identifier; If the out-of-band response flag is in the first state, the baseboard management controller disables its function of responding to out-of-band commands; If the out-of-band response flag is in the second state, the baseboard management controller enables its own function of responding to out-of-band commands.

[0006] Optionally, the process of determining whether the power-on of the hardware device in the server is completed includes: The processor detects the reset pin of the central processor of the server; If the reset pin of the central processing unit is activated, it is determined that the power-on of the hardware device in the server is completed; If the reset pin of the central processing unit is not activated, it is determined that the power-on of the hardware device in the server is not completed, and the process jumps again to the step of the processor detecting the reset pin of the central processing unit of the server.

[0007] Optionally, before configuring the out-of-band response identifier to the second state, the method further includes: The basic input and output system determines whether the power supply of the central processing unit of the server has reached a stable state; If the power supply of the CPU reaches a stable state, the basic input and output system adjusts the out-of-band response flag to a second state; If the power supply of the CPU has not reached a stable state, the BIOS configures the out-of-band response flag to the first state and jumps back to the step where the BIOS determines whether the power supply of the CPU of the server has reached a stable state.

[0008] Optionally, the basic input and output system determines whether the power supply of the central processing unit of the server reaches a stable state, including: The basic input and output system determines whether the interconnection topology between the central processors has been initialized; If so, it is determined that the power supply of the central processing unit of the server has reached a stable state; If not, it is determined that the power supply of the CPU of the server has not reached a stable state.

[0009] Optionally, the basic input / output system adjusts the out-of-band response identifier to a second state, including: Power functions associated with the interconnection topology between the basic input and output system configuration and the central processor; If the interconnection topology between the CPUs is initialized, the basic input / output system executes a power function to adjust the out-of-band response flag to a second state.

[0010] Optionally, also include: When the server is powered on, the baseboard management controller determines whether a reset completion instruction of the server is received; If yes, the baseboard management controller starts a first preset timer, and the timing time of the first preset timer is positively correlated with the time required for the central processing unit to start to the specified position; When the first preset timer expires, the baseboard management controller determines a current state of the out-of-band response identifier; If the out-of-band response identifier is still in the first state, the process directly jumps to the step in which the basic input / output system adjusts the out-of-band response identifier to the second state.

[0011] Optionally, the baseboard management controller determines whether a reset completion instruction of the server is received, including: The baseboard management controller detects a reset signal of a communication interface between itself and the central processing unit of the server; Whether a reset completion instruction from the server is received is determined based on the level conversion state of the communication interface reset signal.

[0012] Optionally, the baseboard management controller determines whether a reset completion instruction of the server is received based on a level conversion state of a reset signal of the communication interface, including: If the communication interface reset signal changes from a low level to a high level, the baseboard management controller configures the preset flag bit to a preset state; If the preset flag is in a preset state, the baseboard management controller determines that a reset completion instruction of the server is received.

[0013] Optionally, also include: The baseboard management controller obtains the set number of the central processing unit of the server, the model information of the central processing unit and the in-place status of the central processing unit; The timing time of the first preset timer is set based on the number of currently located central processing units and the model information of the corresponding central processing units.

[0014] Optionally, before the basic input and output system executes the power function, it also includes: The basic input and output system determines whether a restart instruction from the server is currently received; If yes, jump to the step of configuring the out-of-band response identifier to the first state in the basic input and output system; If not, jump to the step of executing the power function.

[0015] Optionally, also include: If no restart instruction of the server is currently received, the baseboard management controller starts a second preset timer, and the timing time of the second preset timer is positively correlated with the time required for the central processing unit to start to the specified position; When the second preset timer expires, the baseboard management controller determines a current state of the out-of-band response identifier; If the out-of-band response identifier is still in the first state, the process directly jumps to the step in which the basic input / output system adjusts the out-of-band response identifier to the second state.

[0016] Optionally, also include: The baseboard management controller obtains the set number of the central processing unit of the server, the model information of the central processing unit and the in-place status of the central processing unit; The timing time of the second preset timer is set based on the number of currently located central processing units and the model information of the corresponding central processing units.

[0017] To solve the above technical problems, an embodiment of the present invention further provides an electronic device, including: Memory for storing computer programs; The processor is used to execute a computer program to implement the steps of the aforementioned server power-on control method.

[0018] To solve the above technical problems, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the power-on control method of the server as described above are implemented.

[0019] To solve the above technical problem, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the aforementioned server power-on control method when executed by a processor.

[0020] It can be seen from the above technical solution that the control system of the server pre-negotiates and defines an out-of-band response flag used to indicate whether the baseboard management controller responds to out-of-band commands. When the server is powered on, the processor first configures the out-of-band response flag to the first state. At this time, the baseboard management controller executes the power-on sequence of the server itself and will not respond to the out-of-band command; after the power-on sequence of the server itself is completed, the processor and the basic input and output system will adjust the out-of-band response flag to the second state, and the baseboard management controller will respond to the out-of-band command and respond normally to the peripheral power control command. The beneficial effect of the present invention is that by additionally configuring the out-of-band response flag to suppress the external power command, the situation of interference with the server power-on sequence can be fundamentally eliminated, so that the entire power on and off sequence process is carried out independently without external interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic flow chart of a method for controlling power-on of a server provided in an embodiment of the present invention; Figure 2 A schematic flow chart of another method for controlling power-on of a server provided in an embodiment of the present invention; Figure 3 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0025] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0026] Next, a server power-on control method provided by an embodiment of the present invention is described in detail, which is applied to a server control system. The server control system includes a processor, a baseboard management controller, and a basic input and output system. The processor can be implemented by CPLD or MCU. The following description mainly takes the processor using CPLD as an example. Figure 1 As shown, Figure 1 A schematic diagram of a flow chart of a power-on control method for a server provided in an embodiment of the present invention; see Figure 2 As shown, Figure 2 A flow chart of another method for controlling power-on of a server provided in an embodiment of the present invention; the method for controlling power-on of the server includes:

[0027] In order to avoid the influence of out-of-band response on the power-on timing of the server, the present invention predefines an out-of-band response identifier VGPIO2, and uses the defined out-of-band response identifier VGPIO2 as the function execution condition for limiting the control system of the server to respond to out-of-band commands. When the out-of-band response identifier VGPIO2 is in the first state, the control system cannot execute the function of responding to the out-of-band command. When the out-of-band response identifier VGPIO2 is in the second state, the control system can execute the function of responding to the out-of-band command and effectively respond to the out-of-band command. The specific types and implementation methods of the first state and the second state are not particularly limited in this application, and can be implemented by means of level signals, etc. The specific types and implementation methods of the out-of-band response identifiers are not particularly limited in this application. Out-of-band commands are out-of-band power control commands. The specific types and implementation methods are not particularly limited in this application, including power cycle (power cycle, indicating that the server system must go through a power-off and power-on process), power reset and other power control operations.

[0028] It is not difficult to understand that the execution subject of the power-on control method of the server provided by the present invention is the control system of the server. Considering that the power-on timing of the server is completed by the cooperation of CPLD, BMC and BIOS, CPLD is responsible for generating a power-on enable signal to control the components on the server motherboard to power on in a certain order; BMC is responsible for monitoring and managing the status of the server hardware, including temperature, voltage, etc., and adjusting the fan speed according to this information to control the server temperature and power consumption; BIOS is the firmware program that runs first when the computer starts, responsible for initializing the hardware device and starting the operating system. In the server power-on timing, BIOS starts working after the central processing unit is powered on, performs hardware initialization and loads and starts the operating system, thereby completing the entire power-on timing of the server. Therefore, the control system of the server includes CPLD, BMC and BIOS (Basic Input Output System), so an out-of-band response identifier VGPIO2 defined by negotiation among CPLD, BIOS and BMC is required. One end of the BIOS establishes a communication connection with one end of the BMC through a communication link, and the other end of the BMC establishes a communication connection with one end of the CPLD through a communication link, thereby realizing data communication among the three parties. The present application does not specifically limit the specific type and implementation method of the communication link in the control system, and it can be implemented using an ESPI (Enhanced Serial Peripheral Interface) bus or the like.

[0029] It can be understood that during the entire power-on control process, since a three-party communication link is established in the control system, the CPLD, BIOS, and BMC can adjust the state of the out-of-band response identifier VGPIO2 according to their own operating status and the detected real-time status of the server. The BMC detects the state of the out-of-band response identifier VGPIO2 in real time. If the out-of-band response identifier is in the first state, the out-of-band command response function of the BMC is restricted and cannot respond to the out-of-band command. If the out-of-band response identifier is in the second state, the restriction on the out-of-band command response function of the BMC is lifted, and the out-of-band command can be responded to normally. A specific embodiment is that when the out-of-band response identifier VGPIO2 is at a low level, the function of the BMC responding to the out-of-band command is restricted and cannot be used; when the out-of-band response identifier VGPIO2 is at a high level, the BMC is allowed to respond to the out-of-band command, and the function of the BMC responding to the out-of-band command can be used normally.

[0030] S11: The processor configures the out-of-band response flag to a first state in response to a power-on trigger signal of the server.

[0031] It is not difficult to understand that in order to prevent the server's power-on sequence from being affected by out-of-band commands, the out-of-band response flag needs to be configured to the first state when the server starts to power on. The out-of-band response flag in the first state will limit the BMC's function of responding to out-of-band commands, making it impossible for the BMC to respond to out-of-band commands, thereby ensuring the accuracy of the server's power-on sequence and avoiding interference from out-of-band commands. The power-on of the server refers to the process of powering the server. The power-on trigger signal represents the start of the server's power-on. When the power switch of the server's power system is turned on, the power system starts to supply power to the server's mainboard and all connected hardware devices, and the server generates a power-on trigger signal. When the server generates a power-on trigger signal, the processor will immediately respond to the server's power-on trigger signal and configure the out-of-band response flag to the first state.

[0032] It should be noted that, in order to ensure that the BMC can remain in a state where it cannot respond to out-of-band commands when the server is powered on, the first state of the out-of-band response identifier can be configured as the default state value of the out-of-band response identifier. When the control system does not control it to adjust to the second state, the out-of-band response identifier remains in the first state by default, so that when the server system is powered on, the out-of-band response identifier can be directly set to the default first state. For example, when the server system is powered on, the default level of the out-of-band response identifier VGPIO2 will be directly set to a low level. The out-of-band response identifier VGPIO2 can be a physical GPIO (General Purpose Input Output) or a virtual GPIO transmitted through a communication link, that is, a communication signal. When the out-of-band response identifier VGPIO2 is a physical GPIO, the out-of-band response identifier can be directly implemented using the pin of the CPLD itself, and its default state value is controlled by the CPLD; and when the out-of-band response identifier VGPIO2 is a virtual GPIO, considering that the BMC will be powered on at the same time when the server is powered on, its power-on default state value is controlled by the BMC.

[0033] As a specific embodiment, taking the out-of-band response identifier VGPIO2 in the form of a virtual GPIO as an example, a virtual general purpose input and output pin is defined as the out-of-band response identifier VGPIO2 through negotiation among CPLD, BIOS and BMC. Taking the low level as the first state as an example, when the server system is powered on, the BMC sets the default level of the out-of-band response identifier VGPIO2 to low. The specific code for the BMC to set the default level is: void on_power_on() { VGPIO2 = LOW; / / Set VGPIO2 to low level };

[0034] S12: The processor controls the power module of the server to power on the hardware devices in the server according to the power-on sequence.

[0035] S13: When the hardware devices in the server are powered on, the basic input and output system is started, and the out-of-band response flag is configured to the second state.

[0036] It is understandable that it is only necessary to ensure that the power-on sequence of the server will not be interfered by the out-of-band command. In other cases, the BMC still needs to maintain the response to the out-of-band command to perform the corresponding operation. Therefore, after the out-of-band response flag is configured to the first state, the server's own sequence can be started to execute, and the power-on of the hardware devices in the server can be detected in real time to determine whether the power-on sequence of the server is completed. The specific detection method of whether the power-on of the hardware devices in the server is completed is not specifically limited in this application.

[0037] S14: The baseboard management controller detects the state of the out-of-band response identifier; S15: If the out-of-band response flag is in the first state, the baseboard management controller disables its function of responding to the out-of-band command; S16: If the out-of-band response flag is in the second state, the baseboard management controller enables its own function of responding to out-of-band commands.

[0038] It should be noted that the baseboard management controller detects the status of the out-of-band response identifier in real time after the server is powered on, which is independent of the operation of the processor and basic input and output system adjusting the out-of-band response identifier, and there is no specific execution order.

[0039] It is not difficult to understand that when the power-on sequence of the server is executed, the server is powered on. At this time, the response to the out-of-band command will no longer affect the power-on sequence that has been executed. The BMC can start to respond to the out-of-band command. Therefore, the out-of-band response flag can be adjusted to the second state at this time to release the BMC's inhibition of the out-of-band power control operation. Considering that the BIOS starts running after the server is powered on, the operation of adjusting the out-of-band response flag to the second state is generally completed by the BIOS. The specific implementation method of the BMC restoring the response to the out-of-band command and the like is not particularly limited in this application. Specifically, the notify instruction can be used to lift the restriction on the out-of-band command response. A specific embodiment is that after the BMC reads the out-of-band response flag VGPIO2 as a high level, it restores the corresponding response to the power control operation of the server system out-of-band. The specific code for the BMC to restore the out-of-band command response is: / / BMC code example void on_vgpio2_high() { disable_out_of_band_commands(); / / Remove restrictions on out-of-band power control operations };

[0040] Furthermore, based on the out-of-band response identifier VGPIO2, the influence of responding to out-of-band commands on the power-off sequence of the server can also be avoided. The specific operation is to configure the out-of-band response identifier VGPIO2 to the first state at the moment of powering off the server. The power-off of the server also needs to be carried out according to the power-off sequence, and it takes a period of time to complete the complete power-off of the server. When the server just starts to execute the power-off sequence, the BMC and CPLD are still in normal working state, so the working state of the out-of-band response identifier VGPIO2 can be adjusted, thereby avoiding the influence of the BMC responding to the out-of-band command when the server executes the power-off sequence, ensuring that the server can execute the power-off sequence normally and realize the normal power-off and shutdown operation.

[0041] It is understandable that the power on and off of the server may be caused by the server system needing to perform an overall DC power off (Direct Current), REBOOT (restarting the operating system), or AC (Alternating Current) power off, and the server power on and off method provided by the present invention can be effectively applied to the power on and off of the server caused by any situation, thereby avoiding the influence of the BMC response to out-of-band commands on the power on and off timing of the server.

[0042] The present invention provides a power-on control method for a server. An out-of-band response identifier VGPIO2 and its state are negotiated by CPLD, BMC and BIOS. According to the state of the out-of-band response identifier VGPIO2, the BMC is controlled to enable or disable the function of responding to an out-of-band power control command. The state of the out-of-band response identifier VGPIO2 is controlled by CPLD and BIOS. The power-on timing disorder caused by the out-of-band command and the problems of boot memory loss and server downtime caused by the out-of-band command are avoided. In the execution process of the server power-on timing and power-off timing, the external power supply command is suppressed, which can fundamentally prevent the power-on timing between CPLD and CPU from being interfered, so that the entire power on / off timing process is an independent process and is not interfered by the outside world.

[0043] As an optional embodiment, the process of determining whether the power-on of the hardware device in the server is completed includes: The processor detects the reset pin of the central processor of the server; If the reset pin of the central processing unit is activated, it is determined that the power-on of the hardware device in the server is completed; If the reset pin of the central processing unit is not activated, it is determined that the power-on of the hardware device in the server is not completed, and the process jumps again to the step of the processor detecting the reset pin of the central processing unit of the server.

[0044] It is not difficult to understand that the power-on sequence of the server includes the complete process from the complete power-off state of the entire server system to the complete startup and running of the operating system. When the CPU (Central Processing Unit) of the server is powered on, the BIOS will start to run and start the operating system. Therefore, when the CPU is powered on, it can be said that the power-on sequence of the server has been executed and the server is powered on. When the CPU is powered on, the CPU will actively set its own reset pin CPU RESET to a high level state. When the reset pin CPU RESET is in a high level state, it means that the reset pin CPU RESET is activated and the server is powered on. Therefore, it is possible to determine whether the server has completed power-on by directly detecting the reset pin of the CPU. This application does not make any special restrictions on the activation method of the reset pin, etc., and is not limited to the method of setting it to a high level proposed in this implementation. Considering that the BIOS will start running synchronously after the CPU is powered on, if it is determined that the server is powered on, the BIOS can be used to adjust the state of the out-of-band response identifier VGPIO2.

[0045] Specifically, as the power-on sequence continues, the CPU, a key component of the server, will also begin to receive power supply. When the CPU is powered on, the BIOS can start running and load and start the operating system. Therefore, the power-on of the CPU can be used as a sign that the power-on sequence is completed. The state of the CPU's reset pin is directly used to determine whether the server power-on is completed. This is simple, effective and easy to implement.

[0046] As an optional embodiment, before configuring the out-of-band response identifier to the second state, the method further includes: The basic input and output system determines whether the power supply of the central processing unit of the server has reached a stable state; If the power supply of the CPU reaches a stable state, the basic input and output system adjusts the out-of-band response flag to a second state; If the power supply of the CPU has not reached a stable state, the BIOS configures the out-of-band response flag to the first state and jumps back to the step where the BIOS determines whether the power supply of the CPU of the server has reached a stable state.

[0047] It is understandable that out-of-band commands will not only affect the power-on sequence of the server when the server executes the power-on sequence, but also affect the physical links and parameter settings of the server system during the power-on and power-off process. Out-of-band commands mainly affect the communication links between CPUs in the server. The power-on of the server will also trigger the initialization and training process of the UPI (Ultra Path Interconnect) link in the server. The UPI link is used to realize the connection between CPUs and the connection between CPUs and other components. During the server power-on process, since the UPI link needs to link, speed up, and train, it takes a certain amount of time for the physical link between CPUs to form a stable topology. If at this time, an unexpected power failure occurs due to the BMC responding to the out-of-band command, the server system will fail to form a stable UPI topology, causing communication failure between CPUs in the server system, or speed reduction. In the current existing technology, when the BIOS detects that the UPI topology of this startup is inconsistent with the previous startup, a cold restart of the machine is performed to solve the problem of UPI topology loss, but due to the execution of an additional cold restart, the server startup time will be greatly increased. At the same time, in the early stage of BIOS operation, the power status of the CPU and the related parameters involved in the soft strap will be set. If the BMC responds to out-of-band commands and unexpected warm reset occurs during the parameter setting, the memory will not be powered on and the PCIE (Peripheral Component Interconnect Express) device will not work properly. Therefore, how to ensure that the abnormal operation caused by responding to out-of-band commands during the power-on or power-off of the server will not affect the physical link construction of the server system, and how to avoid the impact of out-of-band commands on the BIOS parameter setting process are also important aspects that need to be considered during the server power-on process.

[0048] Considering the impact of out-of-band commands on the physical link of the server system and the BIOS parameter setting process, after the server is powered on, a certain amount of time will be reserved for the construction of the UPI topology between CPUs and the BIOS parameter setting. Therefore, after the server is powered on, that is, when the power-on sequence of the server host is completed, the CPU reset pin CPU RESET is set high, and BIOS starts running; at this time, the BIOS that starts running will re-initialize the out-band response identifier VGPIO2, and control the out-band response identifier VGPIO2 to remain in the first state. In order to facilitate BMC to read the out-band response identifier VGPIO2, BIOS will set the attribute of the out-band response identifier VGPIO2 to output; then BIOS starts running, and after the parameters of UPI and CPU are initialized by BIOS, the power supply of CPU reaches a stable state, and BIOS adjusts the defined out-band response identifier VGPIO2 to the second state, and notifies BMC of the state of the out-band response identifier VGPIO2 in the form of signal output. The out-band response identifier VGPIO2 is output from BIOS and input to BMC. When BMC learns that this out-band response identifier VGPIO2 is in the second state, it releases the suppression of the out-band power command, and the server system responds to the peripheral power control command normally.

[0049] It should be noted that in order to ensure that out-of-band commands do not affect the physical link of the server system and the BIOS parameter setting process, after the server is powered on, the running BIOS will repeat the initialization process of the out-of-band response identifier VGPIO2, and set the out-of-band response identifier VGPIO2 to the first state to ensure that the BMC cannot respond to out-of-band commands at this time. After that, after determining that the power supply of the CPU has reached a stable state, it means that the UPI topology between the CPUs has been completed and the BIOS parameter setting has been completed. At this time, the out-of-band response identifier VGPIO2 is adjusted to the second state, and the BMC will start to respond to out-of-band commands. By adjusting the control conditions for controlling the state change of the out-of-band response identifier VGPIO2, the BMC is prevented from responding to out-of-band commands when the UPI topology is constructed and the BIOS is setting parameters. This application does not make any special restrictions on the specific implementation method of whether the power supply of the central processing unit reaches a stable state. The power supply of the central processing unit reaches a stable state means that the power supply of the CPU can maintain a stable voltage and current level to ensure that the CPU can reliably execute instructions and process data.

[0050] As a specific embodiment, after the power sequence of the server host is completed, the CPU RESET is set high and the BIOS starts to run; the BIOS initializes the out-of-band response flag VGPIO2 and sets its attribute to output, and the output level is low. The specific code for setting the out-of-band response flag VGPIO2 is: / / BIOS code example void on_cpu_reset_high() { initialize_vgpio2(); set_vgpio2_output(); set_vgpio2_low(); };

[0051] Furthermore, the judgment of whether the power supply of the central processing unit has reached a stable state can be realized by using the CPL1 in the CPU. CPL1 is the maximum power consumption that the CPU or GPU can maintain under long-term continuous load. Therefore, the actual power consumption of the CPU can be detected in real time through BMC or hardware sensors, and the actual power consumption is compared with the CPL1 of the CPU. If the actual power consumption is continuously lower than or equal to the PL1 value, then the CPU power state can be considered stable. If the actual power consumption exceeds the PL1 value, it is necessary to analyze whether this excess occurs occasionally or persists. Occasional excesses may be due to momentary high loads, while continuous excesses may indicate unstable or insufficient power supply.

[0052] Specifically, after the server is powered on, it will further determine whether the power supply of the server's central processing unit has reached a stable state. When the power supply of the server's central processing unit has reached a stable state, the out-of-band response flag VGPIO2 will be adjusted to the second state, so that the BMC will not respond to out-of-band commands when the UPI topology is constructed and the BIOS is setting parameters, thereby ensuring the stability of the UPI link connecting the CPUs, thereby ensuring the normal function of the server system as a whole, and ensuring that each component of the host can obtain a stable and safe power supply when it starts.

[0053] As an optional embodiment, the basic input and output system determines whether the power supply of the central processing unit of the server reaches a stable state, including: The basic input and output system determines whether the interconnection topology between the central processors has been initialized; If so, it is determined that the power supply of the central processing unit of the server has reached a stable state; If not, it is determined that the power supply of the CPU of the server has not reached a stable state.

[0054] It is not difficult to understand that the BIOS will set the power state related to the CPU and the related parameters involved in the soft strap in the early stage of BIOS operation, and the construction of the UPI link also requires link training and other processes. Therefore, the parameter setting is generally completed before the UPI link initialization, and the UPI link can only work normally when the CPU has a stable power supply. Therefore, whether the interconnection topology of the UPI link between the CPUs is initialized can be used as a specific implementation method to determine whether the power supply of the central processing unit has reached a stable state. After the UPI link training and construction are completed, the CPU can work normally. There are many options for the specific judgment method of whether the UPI link is initialized. The establishment of the communication link can be detected by data transmission and other methods. When the communication link is established, normal data transmission and communication can be carried out between each CPU and the CPU and its corresponding external components.

[0055] Specifically, the stable operation of the UPI link requires the CPU power supply to reach a steady state to ensure that the high-speed interconnection between processors is not affected by power supply fluctuations. Therefore, it is possible to determine whether the power supply of the central processor has reached a stable state by judging whether the interconnection topology has been initialized. After ensuring the correct connection of the link and the normal operation of the device, the state of the out-of-band response identifier VGPIO2 is adjusted to avoid the impact of out-of-band commands on the construction of the UPI link topology.

[0056] As an optional embodiment, the basic input / output system adjusts the out-of-band response flag to a second state, including: Power functions associated with the interconnection topology between the basic input and output system configuration and the central processor; If the interconnection topology between the CPUs is initialized, the basic input / output system executes a power function to adjust the out-of-band response flag to a second state.

[0057] It can be understood that the overload for determining whether the interconnection topology between the central processing units has been initialized can be implemented by means of a constructor. When the BIOS runs in the PEI (Pre-EFI Initialization) stage, a power function InhabitPowerControl is constructed and registered to associate it with the UPI initialization in the PEI stage. The condition for the execution of the power function is that the UPI link in the PEI stage has been initialized. The power function is used to perform the action of adjusting the out-of-band response identifier to the second state. When the interconnection topology between the central processing units has been initialized, the power function will be automatically executed to adjust the out-of-band response identifier to the second state. This application does not make any special restrictions on the specific type and construction method of this power function.

[0058] As a specific embodiment, BIOS constructs a function InhabitPower Control in the PEI (pre-execution environment) stage, registers the function, and associates it with the initialization of the UPI link in the PEI stage. The condition for the execution of the function is that the UPI in the PEI stage is initialized. The construction, registration and execution code of the power function are as follows: / / BIOS PEI stage code example void pei_initialize() { register_function(InhabitPowerControl, UPI_INITIALIZED); }; void InhabitPowerControl() { if (is_system_reset_required()) { return; } set_vgpio2_high(); };

[0059] Construct the InhabitPowerControl function and register it to UPI. After initialization is completed, when PeiServicesInstallPpi (mAfterKtircPpi), the function is executed. At this time, the CPU power is in a stable state, and the UPI bus between the CPUs has established a stable topological relationship. The executed power function sets the state of the out-of-band response identifier VGPIO2 signal at this time. At the same time, the out-of-band response identifier VGPIO2 signal after adjusting the state can be captured by the BMC through the communication link based on the ESPI signal protocol built between the BMC and the CPU, and the BMC removes the suppression of the out-of-band power command.

[0060] Specifically, the constructor can be used to implement the BIOS's judgment on whether the power supply of the central processing unit has reached a stable state and the state adjustment operation of the out-of-band response identifier VGPIO2 when the power supply of the central processing unit has reached a stable state. The entire process of BIOS adjusting the state of the out-of-band response identifier VGPIO2 is modularized for easy maintenance and calling.

[0061] As an optional embodiment, it also includes: When the server is powered on, the baseboard management controller determines whether a reset completion instruction of the server is received; If yes, the baseboard management controller starts a first preset timer, and the timing time of the first preset timer is positively correlated with the time required for the central processing unit to start to the specified position; When the first preset timer expires, the baseboard management controller determines a current state of the out-of-band response identifier; If the out-of-band response identifier is still in the first state, the process directly jumps to the step in which the basic input / output system adjusts the out-of-band response identifier to the second state.

[0062] It is not difficult to understand that the judgment of whether the power supply of the server's central processing unit has reached a stable state and the adjustment of the state of the out-of-band response identifier VGPIO2 after the power supply of the server's central processing unit has reached a stable state both require the BIOS to be run to implement. However, during the operation of the BIOS and its adjustment of the state of the out-of-band response identifier VGPIO2, the BIOS may not operate normally due to abnormal conditions such as firmware failure. Once the BIOS does not operate normally or does not adjust the state of the out-of-band response identifier VGPIO2 normally, the state of the out-of-band response identifier VGPIO2 will always remain in the first state, resulting in a situation where the BMC still cannot respond to out-of-band commands normally after the server system has completed power-on and the CPU has stable power supply. In order to avoid this situation, a process for detecting the reset completion instruction of the server and a first preset timer are also set in the BMC. The BMC will power on when the server is powered on, and detect whether the server has completed the power-on reset. If the server has completed the power-on reset, it means that the server has started to initialize the CPU at this time. At this time, the BMC starts the first preset timer. The timing time of the first preset timer is positively correlated with the time required for the central processing unit to start to the specified position, which is generally slightly longer than the time required for the central processing unit to start to the specified position. When the first preset timer stops, theoretically, the CPU has started to the specified position. Under normal circumstances, the BIOS has been running for a period of time and has completed the parameter configuration and the UPI link construction process. The state of the out-of-band response identifier VGPIO2 should have been adjusted to the second state by the BIOS control. At this time, if the state of the out-of-band response identifier VGPIO2 is still the first state, it means that the BIOS is not running normally and has not normally executed the operation of adjusting the state of the out-of-band response identifier VGPIO2. At this time, you can directly jump to the step of adjusting the out-of-band response identifier to the second state to forcibly release the suppression of the BMC response to the out-of-band command.

[0063] As a specific embodiment, when the BMC starts running, it can determine whether the server reset is completed by judging whether the ESPI_RESET pin changes from low to high. If this action occurs, a FLAG is set. When the FLAG is set, it does not affect the IPMITOOL POWER CYCLE, POWER RESET action initiated out of band; and set a time out event of n seconds on the node where the FLAG is set. When the time expires, the BMC resumes responding to the out-of-band power command.

[0064] It should be noted that the present application does not specifically limit the specific type and implementation of the first preset timer. The timing of the first preset timer needs to be set according to the current number of CPUs and model parameters of the server system. For server systems with different models and different numbers of CPUs, logical judgment can be made in advance from the BMC end to set the time out mechanism of the first preset timer, so as to effectively be compatible with the power suppression strategy between different CPUs. The CPU starts to the specified position, which means that the CPU starts to execute a specific code in the startup process. This code is responsible for initializing the hardware, configuring the system environment, and finally guiding the loading of the operating system; therefore, when the CPU starts to the specified position, the CPU has received a stable power supply and starts to execute the code. Within the timeout range of the first preset timer, if the out-of-band response flag VGPIO2 given by the BIOS is judged to be high, the suppression of the out-of-band power command is released in advance. If the timeout of the first preset timer is reached, the out-of-band response flag VGPIO2 is still not set high, and the suppression of the out-of-band power command is still forced to be released; this can solve the problem that when the contact suppression operation in the power suppression strategy is not introduced due to BIOS abnormality, the power control behavior of the BMC can still work normally.

[0065] Specifically, when the server is powered on, the BMC can indirectly determine the startup status of the CPU through the change of the ESPI_RESET signal between the CPU and the BMC, thereby forcibly lifting the restriction on suppressing the out-of-band power command response when the BIOS fails to normally adjust the state of the out-of-band response identifier VGPIO2, and determining whether the BIOS is running normally by setting a first preset timer, ensuring that the BMC can normally respond to the out-of-band command after the CPU is started and complete the power instructions issued out-of-band.

[0066] As an optional embodiment, the baseboard management controller determines whether a reset completion instruction of the server is received, including: The baseboard management controller detects a reset signal of a communication interface between itself and the central processing unit of the server; Whether a reset completion instruction from the server is received is determined based on the level conversion state of the communication interface reset signal.

[0067] It can be understood that the ESPI_RESET signal is used for the POR (Power-On Reset) of the ESPI bus power domain, which can ensure that the ESPI bus and its related devices can start working from a known initial state when the server is powered on. In the control system of the server, the ESPI bus is used to realize the communication connection between the BMC and the CPU. At this time, the communication interface reset signal is the ESPI_RESET signal. Therefore, the level conversion state of the ESPI_RESET signal can directly represent the power-on reset state of the server, especially can directly reflect whether the power-on reset of the CPU is completed. Therefore, the BMC can further determine the power-on status of the server through the ESPI_RESET signal, and further judge the startup status of the CPU, so as to realize the state adjustment of the out-of-band response identifier VGPIO2 when the BIOS is not operating normally.

[0068] Specifically, considering that the BMC and the CPU will form a communication connection through the ESPI bus, the BMC can directly detect the power-on reset of the server through the ESPI_RESET signal, a communication interface reset signal, so as to determine the power state of the CPU while the BIOS is running, so as to adjust the state of the out-of-band response flag VGPIO2 by itself when the BIOS is abnormal, and realize the forced recovery of the response out-of-band command function.

[0069] As an optional embodiment, the baseboard management controller determines whether a reset completion instruction of the server is received based on the level conversion state of the communication interface reset signal, including: If the communication interface reset signal changes from a low level to a high level, the baseboard management controller configures the preset flag bit to a preset state; If the preset flag is in a preset state, the baseboard management controller determines that a reset completion instruction of the server is received.

[0070] It is not difficult to understand that the ESPI_RESET signal is valid at a low level. When the ESPI_RESET signal is converted from a high level signal to a low level signal, the reset action of the ESPI bus will be triggered, and the ESPI bus and the corresponding connected CPU will perform a reset operation. When the ESPI_RESET signal is restored from a low level to a high level signal, it indicates that the ESPI bus and the corresponding connected CPU have completed the reset. Therefore, when the communication interface reset signal changes from a low level to a high level, a FLAG can be set to indicate that the server reset is complete. The specific types and implementation methods of the preset flag bits and preset states are not particularly limited in this application.

[0071] As a specific embodiment, when the BMC starts running, it determines whether the ESPI_RESET pin changes from low to high. If this action occurs, a FLAG is set, and a 7-second timeout event is set on the node. After the time expires, the BMC is restored to respond to the out-of-band power command. The specific code of the BMC reset judgment and timing process is as follows: / / BMC code example void on_bmc_start() { if (ESPI_RESET == HIGH) { set_flag(FLAG); start_timer(7000); / / Start the 7 second timer } }; void on_timer_expired() { clear_flag(FLAG); enable_out_of_band_commands(); / / Restore BMC's response to out-of-band power commands };

[0072] Specifically, in order to facilitate the start of the first preset timer, when the BMC detects that the communication interface reset signal changes from a low level to a high level, it will further indicate the completion of the server reset by configuring a preset flag bit. The first preset timer can start itself directly by detecting the preset flag bit to achieve timing. The start control of the first preset timer is achieved by setting the preset flag bit, which is simple, effective and easy to implement.

[0073] As an optional embodiment, it also includes: The baseboard management controller obtains the set number of the central processing unit of the server, the model information of the central processing unit and the in-place status of the central processing unit; The timing time of the first preset timer is set based on the number of currently located central processing units and the model information of the corresponding central processing units.

[0074] It is understandable that due to the difference in the time required to start to the specified position for different numbers of CPUs, the setting value of the timing time of the first preset timer will also be different for different CPU configurations. Therefore, when setting the timing time of the first preset timer, the BMC needs to read the model information transmitted by the CPLD and the CPU in-place status to set the timing time of the first preset timer. For example, when the number of CPUs is 1, the timing time of the first preset timer is set to 7 seconds; when the number of CPUs is 2, the timing time of the first preset timer is 14 seconds; when the number of CPUs is 4, the timing time of the first preset timer is 28 seconds, etc.; so as to flexibly adapt to the suppression of out-of-band power command time under different CPU configurations.

[0075] As a specific embodiment, the BMC obtains the server model information and the CPU status information provided by the CPLD, so as to determine the number of CPUs in the current server system. When it is determined that the number of CPUs is 1, the time-out time is set to n. When the number of CPUs is m, the time-out time is set to mxn. After obtaining the time-out time, the BMC thus designs a forced release procedure: void on_bmc_start() { if (ESPI_RESET == HIGH) { set_flag(FLAG); start_timer(mxn); / / Start the timer } }; / / BMC code example void on_vgpio2_high() { disable_out_of_band_commands(); / / Disable out-of-band power control operations };

[0076] Specifically, for server systems with different CPU configurations, the setting value of the timing time of the first preset timer in the BMC is also different, so that the BMC's forced release of the out-of-band power command operation can adapt to server systems with various configurations, thereby improving the flexibility of the entire control method and expanding the scope of application of the entire control method.

[0077] As an optional embodiment, before the basic input and output system executes the power function, it also includes: The basic input and output system determines whether a restart instruction from the server is currently received; If yes, jump to the step of configuring the out-of-band response identifier to the first state in the basic input and output system; If not, jump to the step of executing the power function.

[0078] It is not difficult to understand that when the server restarts again within a short period of time after the current power-on sequence ends, in order to avoid the BMC responding to out-of-band commands during this continuous restart process, after the interconnection topology between the central processors is initialized, it will further determine whether the current server system needs to continue to restart. If the server needs to restart, although the interconnection topology between the central processors is initialized, the power function will not be executed, and it will directly return to the step of setting the out-of-band response flag to the first state, and directly start the next restart of the server; if the server does not need to restart, the power function will be executed, the out-of-band response flag will be adjusted to the second state, and the BMC's response to the out-of-band power command will be restored.

[0079] It should be noted that the reception judgment of the server restart instruction can also be added to the execution condition of the InhabitPowerControl function. The InhabitPowerControl function reads whether the current server system needs to be restarted. If it needs to be restarted, it returns directly; if there is no restart requirement, the InhabitPowerControl function is executed to set VGPIO2 to a high level; the code of this part in the InhabitPowerControl function is: bool is_system_reset_required() { / / Determine whether the system needs to be reset return system_reset_flag; }; void set_vgpio2_high() { VGPIO2 = HIGH; / / Set VGPIO2 to high level };

[0080] Specifically, when the server system does not need to be restarted or reset, after the BMC reads VGPIO2 as a high level, the suppression of power control operations such as power cycle and power reset performed on the system out of band is released. When the BIOS uses the power function to set the out-of-band response identifier VGPIO2 signal, the BIOS further determines whether the current server system needs to be restarted. If a restart is required, there is no need to set the out-of-band response identifier VGPIO2, thereby avoiding the situation where the out-of-band response identifier VGPIO2 is cleared by the restart behavior actively initiated by the BIOS after it is set; at the same time, it avoids the reset of the out-of-band response identifier VGPIO2 caused by the server restart, resulting in the disorder of the state of the out-of-band response identifier VGPIO2; and avoids the risk of BMC misjudgment.

[0081] As an optional embodiment, it also includes: If no restart instruction of the server is currently received, the baseboard management controller starts a second preset timer, and the timing time of the second preset timer is positively correlated with the time required for the central processing unit to start to the specified position; When the second preset timer expires, the baseboard management controller determines a current state of the out-of-band response identifier; If the out-of-band response identifier is still in the first state, the process directly jumps to the step in which the basic input / output system adjusts the out-of-band response identifier to the second state.

[0082] It is understandable that if the restart instruction of the server is not received at present, the power function needs to be executed normally to adjust the state of the out-of-band response identifier VGPIO2. At this time, in order to avoid abnormal situations when the power function is executed, a second preset timer is set similar to the first preset timer to time the execution process of the power function. When the power function is executed normally, the BMC can receive the out-of-band response identifier VGPIO2 adjusted to the second state; however, if the execution of the power function is abnormal, the out-of-band response identifier VGPIO2 is not adjusted to the second state under the action of the power function, then when the second preset timer stops, the out-of-band response identifier VGPIO2 will still remain in the first state. At this time, you can directly jump to the step of adjusting the out-of-band response identifier to the second state, and forcibly lift the restriction on the BMC response to the out-of-band command. The specific type of the second preset timer, the value of the timing time, and other implementation methods are not specifically limited in this application. Its timing time can be consistent with the timing time of the first preset timer, so that the first preset timer can be directly called to implement the second preset timer.

[0083] Specifically, when executing the power function, a second preset timer is also set to determine whether the power function is executed normally. If the power function is not executed normally, the restriction on suppressing the out-of-band power command response is forcibly lifted to ensure that the BMC can respond to the out-of-band command normally after the CPU is started and complete the power instructions issued out-of-band.

[0084] As an optional embodiment, it also includes: The baseboard management controller obtains the set number of the central processing unit of the server, the model information of the central processing unit and the in-place status of the central processing unit; The timing time of the second preset timer is set based on the number of currently located central processing units and the model information of the corresponding central processing units.

[0085] It is not difficult to understand that, similar to the first preset timer, when setting the timing of the second preset timer, the BMC also needs to read the model information transmitted by the CPLD and the CPU in-position status to set the timing of the second preset timer, thereby flexibly adapting the suppression time of the out-of-band power command under different CPU configurations.

[0086] As a specific embodiment, Figure 2As shown, the control system first defines VGPIO2 as an out-of-band response identifier. When the out-of-band response identifier is a physical GPIO, the CPLD sets its default value and sets its default value to a low level; when the out-of-band response identifier is a virtual GPIO, the BMC can set it to a low level when powered on. After the server is powered on, the BMC detects the low-level VGPIO2 and suppresses the response to the out-of-band command, that is, suppresses the power supply operations such as power on and off performed by the out-of-band command on the server; as the power-on sequence proceeds, the server that has completed the power-on reset will trigger the ESPI_RESET signal to a high level; when the BMC is powered on, after detecting that the ESPI_RESET signal changes from a low level to a high level, it starts the first preset timer and executes a 7-second timeout mechanism; when the server is powered on, the CPU RESET is set high, and the BIOS starts running. The running BIOS will initialize VGPIO2 to a low level and configure its attributes as output. At the same time, BIOS constructs the InhabitPowerControl function in the PEI stage. After registering the function, the function will further determine whether the current server system needs to be restarted when the UPI link initialization is completed. If the server does not need to be restarted, BIOS executes the function, BMC starts the second preset timer, and executes the 7-second timeout mechanism again. If the 7 seconds of the second preset timer are not reached, BIOS executes the function normally to set VGPIO2 to a high level. After detecting that VGPIO2 is at a high level, BMC cancels the inhibition of the out-of-band power control command; if the 7 seconds of the second preset timer are reached, BIOS does not execute the function normally, BMC will also directly cancel the inhibition of the out-of-band power control command.

[0087] Specifically, both BIOS and CPLD can specify corresponding signals as out-of-band response identifiers for interacting with BMC. When specifying physical GPIO, CPLD can set it to a low level when the server is powered on according to the pre-defined default state value. When BIOS starts working, the out-of-band response identifier is initialized again, and after the UPI initialization is completed, the out-of-band response identifier signal is set high through the registration function. BMC then releases the suppressed power command based on this signal, so that the system can respond normally to the out-of-band power control command; BMC reads the reset state of the ESPI_RESET signal to judge the power cycle, power reset or hot or cold restart initiated in the band, accurately covering various timing startup scenarios, and suppressing the out-of-band power command during the server power-on timing, ensuring the entire timing process is not interfered by the outside world.

[0088] See also Figure 3 As shown, Figure 3A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. To solve the above technical problems, an embodiment of the present invention further provides an electronic device, the electronic device comprising: A memory 60, for storing computer programs; The processor 61 is used to implement the steps of the server power-on control method as described in the above embodiment when executing a computer program.

[0089] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0090] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0091] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601, wherein, after the computer program is loaded and executed by the processor 61, the relevant steps of the power-on control method of the server disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data in the power-on control method of the server, etc.

[0092] In some embodiments, the electronic device may further include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0093] Those skilled in the art will understand that Figure 3 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure.

[0094] For the description of the features in the electronic device provided by the embodiment of the present invention, reference may be made to the relevant description of the embodiment of the power-on control method of the above-mentioned server, which will not be described in detail here.

[0095] It is understandable that if the power-on control method of the server in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program codes.

[0096] Based on this, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the server power-on control method described in the above embodiment are implemented.

[0097] For the description of the features in the computer-readable storage medium provided in the embodiment of the present invention, reference can be made to the relevant description of the embodiment of the power-on control method of the above-mentioned server, which will not be described in detail here.

[0098] To solve the above technical problem, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the server power-on control method as described in the above embodiment.

[0099] For descriptions of features in the computer program product provided by the embodiments of the present invention, reference may be made to the relevant descriptions of the embodiments of the power-on control method of the server described above, which will not be described in detail here.

[0100] The above is a detailed introduction to a power-on control method, device, medium and program product of a server provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0101] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0102] The above is a detailed introduction to the power-on control method, device, medium and program product of a server provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A method for controlling power-on of a server, characterized in that: A control system applied to a server, the control system of the server comprising a processor, a baseboard management controller and a basic input and output system; The power-on control method of the server includes: The processor configures the out-of-band response flag to a first state in response to a power-on trigger signal of the server; The processor controls the power module of the server to power on the hardware devices in the server according to the power-on sequence; When the hardware device in the server is powered on, the basic input and output system is started, and the out-of-band response identifier is configured to a second state; The baseboard management controller detects the state of the out-of-band response identifier; If the out-of-band response flag is in the first state, the baseboard management controller disables its function of responding to out-of-band commands; If the out-of-band response flag is in the second state, the baseboard management controller enables its own function of responding to out-of-band commands.

2. The server power-on control method according to claim 1, characterized in that: The process of determining whether the power-on of the hardware device in the server is completed includes: The processor detects a reset pin of a central processing unit of the server; If the reset pin of the central processing unit is activated, it is determined that the power-on of the hardware device in the server is completed; If the reset pin of the central processing unit is not activated, it is determined that the power-on of the hardware device in the server is not completed, and the process jumps again to the step of the processor detecting the reset pin of the central processing unit of the server.

3. The server power-on control method according to claim 1, characterized in that: Before configuring the out-of-band response identifier to the second state, the method further includes: The basic input and output system determines whether the power supply of the central processing unit of the server reaches a stable state; If the power supply of the central processing unit reaches a stable state, the basic input and output system adjusts the out-of-band response flag to a second state; If the power supply of the CPU has not reached a stable state, the BIOS configures the out-of-band response flag to a first state and jumps back to the step in which the BIOS determines whether the power supply of the CPU of the server has reached a stable state.

4. The server power-on control method according to claim 3, characterized in that: The basic input and output system determines whether the power supply of the central processing unit of the server reaches a stable state, including: The basic input and output system determines whether the interconnection topology between the central processing units has been initialized; If yes, it is determined that the power supply of the central processing unit of the server has reached a stable state; If not, it is determined that the power supply of the central processing unit of the server has not reached a stable state.

5. The server power-on control method according to claim 4, characterized in that: The basic input / output system adjusts the out-of-band response identifier to a second state, including: A power function associated with the interconnection topology between the basic input and output system structure and the central processing unit; If the interconnection topology between the central processors is initialized, the basic input and output system executes the power function to adjust the out-of-band response flag to a second state.

6. The method for controlling the power-on of a server according to claim 3, characterized in that: Also includes: When the server is powered on, the baseboard management controller determines whether a reset completion instruction of the server is received; If yes, the baseboard management controller starts a first preset timer, and the timing time of the first preset timer is positively correlated with the time required for the central processing unit to start to the specified position; When the first preset timer stops, the baseboard management controller determines a current state of the out-of-band response identifier; If the out-of-band response identifier is still in the first state, the process directly jumps to the step in which the basic input / output system adjusts the out-of-band response identifier to the second state.

7. The server power-on control method according to claim 6, characterized in that: The baseboard management controller determines whether a reset completion instruction of the server is received, including: The baseboard management controller detects a communication interface reset signal between itself and the central processing unit of the server; Whether a reset completion instruction of the server is received is determined based on the level conversion state of the communication interface reset signal.

8. The method for controlling the power-on of a server according to claim 7, characterized in that: The baseboard management controller determines whether a reset completion instruction of the server is received based on the level conversion state of the communication interface reset signal, including: If the communication interface reset signal changes from a low level to a high level, the baseboard management controller configures the preset flag bit to a preset state; If the preset flag is in a preset state, the baseboard management controller determines that a reset completion instruction of the server is received.

9. The server power-on control method according to claim 6, characterized in that: Also includes: The baseboard management controller obtains the set number of the central processing unit of the server, the model information of the central processing unit and the in-place status of the central processing unit; The timing time of the first preset timer is set based on the number of currently in-place central processing units and the model information of the corresponding central processing units.

10. The server power-on control method according to claim 5, characterized in that: Before the basic input and output system executes the power function, it also includes: The basic input and output system determines whether a restart instruction of the server is currently received; If yes, jump to the step of configuring the basic input / output system to configure the out-of-band response identifier to the first state; If not, jump to the step of executing the power function.

11. The server power-on control method according to claim 10, characterized in that: Also includes: If no restart instruction of the server is currently received, the baseboard management controller starts a second preset timer, and the timing time of the second preset timer is positively correlated with the time required for the central processing unit to start to the specified position; When the second preset timer stops, the baseboard management controller determines a current state of the out-of-band response identifier; If the out-of-band response identifier is still in the first state, the process directly jumps to the step in which the basic input / output system adjusts the out-of-band response identifier to the second state.

12. The server power-on control method according to claim 11, characterized in that: Also includes: The baseboard management controller obtains the set number of the central processing unit of the server, the model information of the central processing unit and the in-place status of the central processing unit; The timing time of the second preset timer is set based on the number of currently in-place central processing units and the model information of the corresponding central processing units.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program to implement the steps of the power-on control method of the server as described in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the power-on control method of the server according to any one of claims 1 to 12 are implemented.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the power-on control method of the server as described in any one of claims 1 to 12 are implemented.

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