A data processing device, method and related equipment

Abstract

The present application proposes a data processing device, method and related equipment. The device includes a storage control module, a PCIe module, a page table entry buffer, and a physical address buffer; the storage control module is configured to determine the starting page table entry and the starting physical address based on the DMA read and write request and send them to the PCIe module; the PCIe module is configured to store the page table entry and the physical address in the page table entry buffer and the physical address buffer; the target data is read and written based on the starting physical address, and when the number of packets available for the remaining space in each memory block drops to a preset number, a query request is sent to the storage control module; the storage control module is configured to: determine the next page table entry of the currently read and written page table entry and the physical address corresponding to the next page table entry and send them to the PCIe module. The PCIe module is used to send a query request to the storage control module according to the preset number of times. Before the preset number of times is not reached, the storage control module can process other read and write requests, thereby improving the processing capacity of the storage control module.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a data processing device, method and related equipment. Background Art

[0002] In a computer system, when processing a direct memory access (DMA) read or write request, it is necessary to search the page table (a mapping table of virtual addresses and physical addresses) through the storage control module to determine the physical address corresponding to the virtual address of the data requested to be read or written by the DMA read or write request, and then send a processing instruction containing the physical address to the high-speed serial computer expansion bus (Peripheral Component Interconnect express, PCIe) module, and the PCIe module processes the data based on the physical address.

[0003] In addition, in the prior art, the memory modules to which the physical addresses belong are mostly arranged in the form of memory blocks of a fixed size (such as 2 megabytes (MegaByte, M)), and each memory block corresponds to a page table entry in the page table. When the PCIe module processes data based on the physical address, it can only process it mechanically according to the physical address and the size of the data. However, the memory blocks of the data to be read and written in the memory module are often discontinuous. For example, the data to be read are discontinuous in the various memory blocks of the memory module, or the write addresses of the data to be written in the various memory blocks on the memory module are discontinuous. This results in that if the PCIe module reads and writes data in the order of the various memory blocks in the memory module, the data will be processed on the wrong memory block.

[0004] In the prior art, when the data of a DMA read or write request is large (spanning at least one memory block), in order to prevent the PCIe module from processing the data on the wrong memory block, the storage control module needs to send multiple processing instructions to the PCIe module according to the distribution of the data in each memory block in the memory module. Each processing instruction is only for one memory block, which seriously reduces the task processing capability of the storage control module. Summary of the invention

[0005] The main purpose of the present application is to propose a data processing device, method and related equipment, aiming to solve the problem in the prior art that when the data of a DMA read or write request is large, the storage control module needs to send multiple processing instructions to the PCIe module according to the distribution of the data in each memory block in the memory module, which seriously reduces the task processing capability of the storage control module.

[0006] To achieve the above-mentioned purpose, the present application proposes a data processing device, comprising: a storage control module, a PCIe module, a page table entry buffer, and a physical address buffer;

[0007] The storage control module is configured to: in response to receiving a DMA read / write request, determine a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry based on the DMA read / write request, and send the starting page table entry and the starting physical address to the PCIe module;

[0008] The PCIe module is configured to: in response to receiving the page table entry and the corresponding physical address sent by the storage control module, store the page table entry and the physical address in the page table entry buffer and the physical address buffer respectively;

[0009] And, based on the starting physical address, the target data is read and written in the memory module, and when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module; the query request is used to request to query the next page table entry in the page table corresponding to the memory block currently read and written and the physical address corresponding to the next page table entry;

[0010] The storage control module is also configured to: in response to receiving the query request, determine the next page table entry in the page table of the currently read and written page table entry and the physical address corresponding to the next page table entry, and send the next page table entry and the physical address corresponding to the next page table entry to the PCIe module.

[0011] In an embodiment of the present application, the storage control module is further configured to: in response to receiving a DMA read / write request, determine, based on the DMA read / write request, a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, as well as a next page table entry of the starting page table entry in a page table and a physical address corresponding to the next page table entry;

[0012] The starting page table entry and the starting physical address corresponding to the starting page table entry, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry of the starting page table entry are sent to the PCIe module.

[0013] In the embodiment of the present application, the PCIe module is further configured to: based on the starting physical address and the physical address corresponding to the next page table entry of the starting page table entry, continuously read and write the target data corresponding to the starting page table entry and the next page table entry of the starting page table entry; and

[0014] Starting from the memory block corresponding to the next page table entry of the starting page table entry, when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module.

[0015] In an embodiment of the present application, the storage control module is further configured to determine the total number of times the target data crosses the boundary in the memory module based on the DMA read and write request, the size of each memory block in the memory module, and the starting physical address.

[0016] In the embodiment of the present application, the data processing device further includes a cross-border count buffer;

[0017] The storage control module is further configured to: send the total number of times the target data crosses the boundary in the memory module to the PCIe module;

[0018] The PCIe module is further configured to: store the total number of times the target data crosses the boundary in the memory module in the cross-boundary count buffer; and

[0019] Every time a portion of target data corresponding to a page table entry is read and written, the number of cross-border times in the cross-border times counting buffer is updated once.

[0020] In an embodiment of the present application, the data processing device further includes a descriptor buffer, and the storage control module is further configured to: in response to receiving multiple DMA read / write requests, generate a descriptor for each of the DMA read / write requests, and send each of the descriptors to the PCIe module;

[0021] The PCIe module is further configured to store each of the descriptors in the descriptor buffer respectively;

[0022] The descriptor buffer, the page table entry buffer, the physical address buffer and the cross-border count buffer store the descriptor, page table entry, physical address and cross-border count of the same DMA read / write request in the same storage depth.

[0023] The present application also proposes a data processing method, which is applied to the data processing device described in any of the above embodiments. The data processing method includes:

[0024] In response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, determining a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, and sending the starting page table entry and the starting physical address to the PCIe module;

[0025] Based on the PCIe module, the page table entry and the corresponding physical address sent by the storage control module are stored in the page table entry buffer and the physical address buffer respectively;

[0026] And, based on the starting physical address, the target data is read and written in the memory module, and when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module; the query request is used to request to query the next page table entry in the page table corresponding to the memory block currently read and written and the physical address corresponding to the next page table entry;

[0027] In response to receiving the query request, based on the storage control module, determine the next page table entry in the page table of the currently read and written page table entry and the physical address corresponding to the next page table entry, and send the next page table entry and the physical address corresponding to the next page table entry to the PCIe module.

[0028] In the embodiment of the present application, the data processing method further includes:

[0029] In response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, determining a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, as well as a next page table entry of the starting page table entry in a page table and a physical address corresponding to the next page table entry;

[0030] The starting page table entry and the starting physical address corresponding to the starting page table entry, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry of the starting page table entry are sent to the PCIe module.

[0031] In the embodiment of the present application, the data processing method further includes:

[0032] Based on the starting physical address and the physical address corresponding to the next page table entry of the starting page table entry, continuously read and write the target data corresponding to the starting page table entry and the next page table entry of the starting page table entry; and

[0033] Starting from the memory block corresponding to the next page table entry of the starting page table entry, when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module.

[0034] In an embodiment of the present application, the data processing method also includes: determining the total number of times the target data crosses the boundary in the memory module based on the storage control module, the DMA read and write request, the size of each memory block in the memory module, and the starting physical address.

[0035] In the embodiment of the present application, the data processing method further includes:

[0036] Based on the storage control module, the total number of times the target data crosses the boundary in the memory module is sent to the PCIe module;

[0037] Based on the PCIe module, storing the total number of times the target data crosses the boundary in the memory module in the cross-boundary count buffer; and

[0038] Every time a portion of target data corresponding to a page table entry is read and written, the number of cross-border times in the cross-border times counting buffer is updated once.

[0039] In the embodiment of the present application, the data processing method further includes:

[0040] In response to receiving multiple DMA read / write requests, generating a descriptor for each of the DMA read / write requests based on the storage control module, and sending each of the descriptors to the PCIe module;

[0041] Based on the PCIe module, each descriptor is stored in the descriptor buffer respectively; wherein, the descriptor, page table entry, physical address and cross-boundary count of the same DMA read / write request are stored in the same storage depth of the descriptor buffer, the page table entry buffer, the physical address buffer and the cross-boundary count buffer.

[0042] The present application also proposes a computer-readable storage medium, which includes instructions. When the computer-readable storage medium is executed on a computer, the computer executes the method described in any one of the above embodiments.

[0043] The present application also proposes a computing device, which includes a processor, and the processor is used to implement the method described in any of the above embodiments when executing a computer program stored in a memory.

[0044] In the embodiment of the present application, by setting a page table entry buffer and a physical address buffer, when processing a DMA read and write request, the storage control module only needs to send the starting page table entry and the corresponding starting physical address when sending a processing instruction to the PCIe module. The PCIe module stores the starting page table entry and the corresponding starting physical address in the page table entry buffer and the physical address buffer, and can read the target data in the page table entry corresponding to the physical address according to the physical address in the physical address buffer; in addition, by counting the number of TLP packets available for the remaining space of the memory block currently read and written, when it drops to a preset number, a query request is sent to the storage control module based on the PCIe module to query the next page table entry and the corresponding physical address, and the next page table entry and the corresponding physical address of the reflux are stored in the page table entry buffer and the physical address buffer, so that when the target data corresponding to the previous page table entry is read and written, the target data corresponding to the next page table entry can be read and written, thereby improving data processing efficiency. Moreover, the present application utilizes the PCIe module to send query requests to the storage control module in reverse according to a preset number of times. Compared with the PCIe module in the prior art that mechanically executes the processing instructions of the storage control module, when the PCIe module in the present application reads and writes each memory block, the storage control module only needs to send the starting page table entry and the corresponding starting physical address to the PCIe module, and then it can process other read and write requests, thereby also improving the processing capability of the storage control module. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0046] Figure 1 This is a schematic diagram of a page in an embodiment of the present application;

[0047] Figure 2 A block diagram of a data processing device in an embodiment of the application;

[0048] Figure 3 This is a schematic diagram of a page in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of storage of each buffer in an embodiment of the present application;

[0050] Figure 5 A step diagram of a data processing method in an embodiment of the present application;

[0051] Figure 6 A module diagram of a computer-readable storage medium in an embodiment of the present application;

[0052] Figure 7 A module diagram of a computing device in one embodiment of the present application.

[0053] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0054] The terms "including" and "having" in the specification and claims of the embodiments of the present application and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The division of modules appearing in the embodiments of the present application is only a logical division. There may be other division methods when implemented in actual applications. For example, multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling between modules, and the communication connection can be electrical or other similar forms, which are not limited in the embodiments of the present application. In addition, the modules or submodules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0055] The principles and spirit of the present application are explained in detail below with reference to several representative implementations of the present application.

[0056] Exemplary Devices

[0057] like Figure 1 As shown, Figure 1 The figure is a schematic diagram of a page table (used to represent the mapping relationship between virtual addresses and physical addresses), where #0-#7 are 8 page table entries in a page of the page table. The memory module to which the physical address belongs is divided according to the size of each memory block of 2 megabytes (Mega Byte, M), 0-2M is a memory block, 2-4M is a memory block, 4-6M is a memory block, and so on. In addition, the connection between the page table entry and the memory block represents the mapping relationship. For example, the physical address corresponding to the page table entry #0 is the memory block of 0-2M, the physical address corresponding to the page table entry #1 is the memory block of 2-4M, and so on.

[0058] In addition, for any DMA read / write request, the DMA read / write request includes the virtual address of the requested data, which includes the page table page number value, page table entry and offset. Therefore, the physical address of the requested data can be determined based on the page table page number value, page table entry and offset.

[0059] Generally speaking, the virtual addresses of the data requested by a DMA read / write request are continuous in the page table. For example, for a DMA read / write request, the requested data size is 12M, and the page table entry corresponding to the requested data is Figure 1 #0-#5 in the page table, that is, 6 consecutive page table entries. However, the memory blocks of data in the memory module are often discontinuous. For example, the 12M data requested by the DMA read and write request is distributed in 5 consecutive memory blocks of 0-10M and 12-14M. Then, if the starting physical address can be determined to be located in the memory block of 0-2M in the memory module according to page table entry #0, the specific position of the starting physical address in the memory block of 0-2M can be determined according to the offset. Assuming that the starting physical address starts from 0M, if 12M of data is read and written continuously starting from the memory block where 0-2M is located, and the data is read and written after the memory block of 10-12M is read and written, this is obviously different from the 12M data that actually needs to be processed, that is, it is easy to read and write incorrectly.

[0060] Based on this, in order to avoid errors in reading and writing data, the prior art, for the DMA read and write request of the above-mentioned 12M data, after receiving the DMA read and write request, when the storage control module sends a processing instruction to the PCIe module, each instruction only contains the physical address of a memory block. For example, the processing instruction of reading and writing 0-2M is first sent to the PCIe module. After the processing is completed, the storage control module sends the processing instruction of reading and writing 2-4M to the PCIe module again, until the data in each memory block corresponding to the page table entries #0-#5 is processed.

[0061] In summary, in the prior art, the PCIe module can only mechanically execute the processing instructions issued by the storage control module. In order to avoid data reading and writing errors, the storage control module mostly issues processing instructions to the PCIe module one by one according to each memory block corresponding to each page table entry. When the data requested by a DMA read or write request is large, that is, it contains multiple memory blocks, a corresponding number of multiple processing instructions must be issued to the PCIe module, thereby seriously reducing the task processing capability of the storage control module.

[0062] Based on this, the present application proposes a data processing device, which sets a page table cache and a physical address cache on the basis of an existing PCIe module, so as to solve the problem that when the prior art faces a DMA read and write request with large data, it adopts the method of sending processing instructions to the PCIe module one by one, resulting in low task processing efficiency of the storage control module.

[0063] like Figure 2 As shown, in the embodiment of the present application, the data processing device 400 includes:

[0064] Storage control module 100, PCIe module 200, page table entry buffer 220, physical address buffer 230;

[0065] The storage control module 100 is configured to: in response to receiving a DMA read / write request, determine a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry based on the DMA read / write request, and send the starting page table entry and the starting physical address to the PCIe module 200;

[0066] The PCIe module 200 is configured to: in response to receiving the page table entry and the corresponding physical address sent by the storage control module 100, store the page table entry and the physical address in the page table entry buffer 220 and the physical address buffer 230 respectively;

[0067] And, based on the starting physical address, the target data is read and written in the memory module 300, and when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module 300 drops to a preset number, a query request is sent to the storage control module 100; the query request is used to request to query the next page table entry in the page table corresponding to the memory block currently read and written and the physical address corresponding to the next page table entry;

[0068] The storage control module 100 is also configured to: in response to receiving the query request, determine the next page table entry in the page table of the currently read and written page table entry and the physical address corresponding to the next page table entry, and send the next page table entry and the physical address corresponding to the next page table entry to the PCIe module 200.

[0069] In an embodiment of the present application, a DMA read / write request may be a DMA read request or a DMA write request, a write request may be a request to write data to each memory block of the memory module 300, and a read request may be a request to read data from each memory block of the memory module 300.

[0070] Continue to refer to Figure 2 After receiving the DMA read / write request, the storage control module 100 can find the starting page table entry and the starting physical address corresponding to the starting page table entry in the page table according to the virtual address contained therein.

[0071] by Figure 3Taking the page table shown as an example, the target data size is 12M, the target data is discontinuous in the memory module, and the target data is distributed in each memory block of 0-10M and each memory block of 12-16M, that is, each memory block of 0-10M and 12-16M has a part of the target data. The starting page table entry corresponding to the virtual address in the DMA read and write request of the target data is #0. The storage control module 100 determines based on the DMA read and write request that the starting page table entry corresponds to the memory block of 0-2M, and the starting physical address is located at the 1M position in the memory block of 0-2M, that is, the starting physical address is 1M. At this time, the storage control module 100 sends the starting page table entry #1 and the starting physical address 1M to the PCIe module 200.

[0072] When the PCIe module 200 receives the starting page table entry #0 and the starting physical address 1M, the starting page table entry #0 is stored in the page table entry buffer 220, and the starting physical address 1M is stored in the physical address buffer 230. It should be noted that the same storage depth in the page table entry buffer 220 and the physical address buffer 230 stores the page table entry of the same DMA read / write request and the physical address corresponding to the page table entry. Figure 4 As shown, Figure 4 The schematic diagram of the storage depth of the page table entry buffer 220 and the physical address buffer 230 in an embodiment of the present application is shown. The storage depth of each buffer is 16, that is, it contains storage locations with storage depths of 0-15. The page table entries and physical addresses stored in the storage locations at the same depth correspond to the same DMA request, and the page table entries and physical addresses at the same storage depth correspond to each other. For example, Figure 4 The page table entry buffer 220 and the physical address buffer 230 in the storage depth 0 store page table entries #0 and 1M respectively, which means that the physical address corresponding to the page table entry #0 starts from 1M.

[0073] After the PCIe module 200 stores the starting page table entry and the starting physical address sent by the storage control module 100 in the page table entry buffer 220 and the physical address buffer 230 respectively, the target data can be read and written according to the information cached in the page table buffer and the physical address buffer 230. For example, the page table entry #0 is stored in the storage position of the storage depth 0 of the page table entry buffer 220, that is, the sending port of the PCIe module 200 can be used to read and write the data corresponding to the page table entry #0 starting from the position 1M of the memory module 300 according to the physical address 1M at the storage position of the storage depth 0 of the physical address buffer 230, and the content read and written is the part of the target data corresponding to the page table entry #0.

[0074] In addition, in an embodiment of the present application, the PCIe module 200 is also configured to send a query request to the storage control module 100 when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module 300 drops to a preset number.

[0075] Among them, when the sending port in the PCIe module 200 reads and writes the target data corresponding to the page table entry in the memory module 300 based on the physical address in the physical address buffer 230, it is processed according to the preset transaction layer packet (Transaction Layer Packet, TLP), and the size of the TLP is preset and fixed, for example, the TLP size is generally 256 bytes (Byte, B) or 512B. In addition, the size of each memory block in the memory module 300 is also preset, for example, the size of each memory block is 2M. Then for each memory block, the total number of packets that can be sent by the sending port of the PCIe module from the starting address (starting boundary) of the memory block to the ending address (ending boundary) of the memory block is determined. For example, if the size of each memory block is 2M and the size of the TLP is 512B, then the number of times a memory block can be sent is 4096. Therefore, in the embodiment of the present application, the PCIe module 200 is used to record the number of packets sent by the sending port when reading and writing the target data corresponding to each page table entry, so as to determine the number of packets available for sending in the remaining space of the memory block corresponding to the current page table entry.

[0076] It should be noted that, for the memory block corresponding to the start page table entry, the start physical address may be the middle position of the memory block corresponding to the start page table entry, that is, it is not the start boundary of the memory block. Therefore, when calculating the number of times that the memory block corresponding to the start page table entry can be sent, it is necessary to calculate according to the available read and write space of the memory block corresponding to the start page table entry. For example, the start page table entry is #0, and the corresponding memory block is a memory block of 0-2M, but the start physical address is 1M, that is, the available read and write space of the memory block of 0-2M is 1M, so the number of times that the sending port of the PCIe module 200 can send packets is 2048 times. For other memory blocks after the memory block corresponding to the start page table entry, all read and write start from the start boundary of each memory block, so the number of times that the sending port of the PCIe module 200 can send packets is 4096 times.

[0077] In the embodiment of the present application, the preset number of times can be set to 10 times, 20 times, or 30 times, and the embodiment of the present application does not limit the specific number of times set for the preset number of times. Taking the preset number of times as 10 times as an example, when the remaining space of each memory block is reduced to 10 times according to the preset TLP packet sending number, the PCIe module 200 sends a query request to the storage control module 100.

[0078] For example, when the PCIe module 200 reads and writes the page table entry #0 in the page table entry buffer 220, it starts to send packets according to the preset TLP size from the starting physical address 1M of the memory block of 0-2M. After 2038 packets are sent, the number of times the remaining space can be used for sending packets is reduced to 10. At this time, the PCIe module 200 can send a query request to the storage control module 100 to request the physical address corresponding to the next page table entry #1 in the page table of the current page table entry #0. After receiving the query request sent by the PCIe module 200, the storage control module 100 can determine that the next page table entry of the page table entry #0 is #1. Based on the page table, it can be found that the physical address corresponding to the next page table entry #1 is the starting boundary address of the 2-4M memory block, that is, the physical address is 2M. At this time, the storage control module 100 sends the page table entry #1 and its corresponding physical address 2M to the PCIe module 200. After receiving the page table entry #1 and its corresponding physical address 2M, the PCIe module 200 stores the page table entry 1# in the page table entry buffer 220, and stores the physical address 2M in the physical address buffer 230 at a storage location with the same storage depth as the page table entry #1 in the page table entry buffer 220, so as to be read and written by the PCIe module 200. After the PCIe module 200 has finished reading and writing the partial target data corresponding to the page table entry #0, it can immediately read and write the partial target data corresponding to the page table entry #1 according to the physical address corresponding to the page table entry #1.

[0079] In addition, it should be noted that the size set by the preset number of times satisfies that before the preset number of TLP packets are sent, the next page table entry and physical address requested by the query request sent by the PCIe module 200 to the storage control module 100 have been returned to the PCIe module 200 and stored in the page table entry buffer 220 and the physical address buffer 230, so as to ensure that the PCIe module 200 can immediately start reading and writing the part of the target data corresponding to the next page table entry after completing the reading and writing of the target data corresponding to a page table entry, thereby improving the data processing efficiency. For example, if the preset number of times is 10 times, then within 10 TLP packet sending cycles, the next page table entry corresponding to the query request and the physical address corresponding to the next page table entry have been stored in the page table entry buffer 220 and the physical address buffer 230.

[0080] In the embodiment of the present application, by setting the page table entry buffer 220 and the physical address buffer 230, when processing a DMA read / write request, the storage control module 100 only needs to send the starting page table entry and the corresponding starting physical address when sending a processing instruction to the PCIe module 200. The PCIe module 200 stores the starting page table entry and the corresponding starting physical address in the page table entry buffer 220 and the physical address buffer 230, and can read the target data in the page table entry corresponding to the physical address according to the physical address in the physical address buffer 230; in addition, By counting the number of TLP packets available for sending in the remaining space of the memory block currently being read or written, when it drops to a preset number, the PCIe module 200 actively sends a query request to the storage control module 100 to query the next page table entry and the corresponding physical address, and stores the next page table entry and the corresponding physical address returned in the page table entry buffer 220 and the physical address buffer 230, so that when the target data corresponding to the previous page table entry is read and written, the target data corresponding to the next page table entry can be read and written, thereby improving data processing efficiency. Moreover, the present application utilizes the PCIe module 200 to actively send a query request to the storage control module 100 in reverse according to a preset number of times. Compared with the PCIe module 200 in the prior art that mechanically executes the processing instructions of the storage control module 100, when the PCIe module 200 in the present application reads and writes each memory block, the storage control module 100 only needs to send the starting page table entry and the corresponding starting physical address to the PCIe module, and then it can process other read and write requests, thereby also improving the processing capability of the storage control module 100.

[0081] Continue to refer to Figure 3 ,exist Figure 3In the illustrated embodiment, the starting page table entry of the target data is #0, and the starting physical address is 1M. Therefore, when reading and writing the target data corresponding to the starting page table entry, according to the TLP size of 512B, it takes 2048 packets to drop to the boundary of the 0-2M memory block, that is, from the beginning of reading and writing the target data corresponding to the starting page table entry from the starting physical address, until the remaining space is available for the number of TLP packets to drop to the preset number and the query request is sent to the storage control module 100, a large number of packet cycles must be passed during this period, and there are sufficient clock cycles to send the query request. However, in other embodiments, when processing the target data corresponding to the starting page table entry from the starting physical address, it may only take a small number of packet cycles to reach the preset number, or, starting from the starting physical address in the memory block corresponding to the starting physical address, the remaining storage space is less than the space required for the preset number of packets. For example, the starting physical address of the target data in the 0-2M memory block is 2094592B, that is, the remaining space of the 0-2M memory block starting from the starting physical address is only 5120B, which can be packetized 5 times according to the 512B TLP, which is less than the preset number of 10. At this time, a query request is sent to the storage control module 100 from the beginning of reading and writing. It is very likely that after the reading and writing of the target data corresponding to the page table entry #0 is completed, that is, after 5 TLP packet sending cycles, the next page table entry corresponding to the query request and the corresponding physical address may not have flowed back to the PCIe module 200. Therefore, it is necessary to wait for the flow back before starting to read and write the next page table entry, which will waste clock cycles.

[0082] Therefore, in the embodiment of the present application, the storage control module 100 is further configured to: in response to receiving a DMA read / write request, determine the starting page table entry of the virtual address of the target data in the page table and the starting physical address corresponding to the starting page table entry, as well as the next page table entry of the starting page table entry in the page table and the physical address corresponding to the next page table entry based on the DMA read / write request;

[0083] The starting page table entry and the starting physical address corresponding to the starting page table entry, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry of the starting page table entry are sent to the PCIe module 200 .

[0084] That is, after receiving a DMA read / write request, the starting page table entry and the starting physical address, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry are directly sent to the PCIe module 200. The PCIe module 200 stores the two pairs of page table entries and physical addresses in the page table entry buffer 220 and the physical address buffer 230, respectively. After the target data corresponding to the starting page table entry is read and written, the target data corresponding to the next page table entry can be continuously read and written directly according to the physical address corresponding to the next page table entry in the physical address buffer 230, thereby avoiding the waste of clock cycles caused by the failure of the next page table entry and physical address corresponding to the query request to flow back in time when the remaining space of the memory block corresponding to the starting page table entry starting from the starting physical address is less than the preset number of TLP packets.

[0085] In the embodiment of the present application, the storage control module 100 is configured to initially send the starting page table entry and the starting physical address, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry to the PCIe module 200. Therefore, when the PCIe module 200 reads and writes the memory block corresponding to the starting page table entry, when the number of TLP packets available for the remaining space in the memory block corresponding to the starting page table entry drops to a preset number or is less than the preset number, it is not necessary to send a query request to the storage control module 100, but it starts from the memory block corresponding to the next page table entry of the starting page table entry, and starts to send query requests to the storage control module 100 when the number of TLP packets available for the remaining space in the memory block drops to a preset number. For example, Figure 3 In the embodiment shown, the storage control module 100 initially directly sends #0 and #1 and their corresponding physical addresses to the PCIe module 200, and the PCIe module 200 starts with the 2-4M memory block corresponding to #1, and when the number of times that the remaining space of the 2-4M memory block and other subsequent memory blocks can be used to send packets drops to a preset number, the PCIe module 200 sends a query request to the storage control module 100. That is, in the embodiment of the present application, the PCIe module 200 is further configured as follows:

[0086] Based on the starting physical address and the physical address corresponding to the next page table entry of the starting page table entry, continuously read and write the target data corresponding to the starting page table entry and the next page table entry of the starting page table entry; and

[0087] Starting from the memory block corresponding to the next page table entry of the starting page table entry, when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module 300 drops to a preset number, a query request is sent to the storage control module 100.

[0088] In an embodiment of the present application, the storage control module 100 is also configured to determine the total number of times the target data crosses the boundary in the memory module 300 based on the DMA read and write request, the size of each memory block in the memory module 300, and the starting physical address.

[0089] by Figure 3 For example, based on the DMA read / write request, it can be determined that the size of the target data is 12M, the starting physical address is 1M, and the size of each memory block is 2M. Then it can be known that the target data must occupy at least 7 memory blocks in the memory module 300, that is, it must cross 6 memory blocks, that is, the total number of cross-borders is 6. It should be noted that the cross-border in this application refers to the target data crossing from one memory block to another memory block, such as from 0-2M memory block to 2-4M memory block, which is a cross-border once, and similarly, from 8-10M memory block to 12-14M memory block, which is also a cross-border once.

[0090] In the embodiment of the present application, the data processing device further includes a cross-border times counting buffer 240;

[0091] The storage control module 100 is further configured to: send the total number of times the target data crosses the boundary in the memory module 300 to the PCIe module 200;

[0092] The PCIe module 200 is further configured to: store the total number of times the target data crosses the boundary in the memory module 300 in the cross-boundary count buffer 240; and

[0093] Each time a portion of target data corresponding to a page table entry is read and written, the number of cross-border counts in the cross-border count buffer 240 is updated.

[0094] Continue to refer to Figure 3 , the target data size is 12M, the starting physical address is 1M, 7 memory blocks are occupied, and the total number of cross-borders is 6 times. When the storage control module 100 sends the starting page table entry and the starting physical address to the PCIe module 200, the total number of cross-borders is also sent to the PCIe module 200, and the PCIe module 200 stores the total number of cross-borders in the cross-border count buffer 240. Since each page table entry corresponds to a memory block, the number of times the memory blocks are crossed is the same as the number of times the page table entry is updated. For example, Figure 3 In the 12M target data shown, there are 7 page table entries #0-#6 corresponding to the target data and 7 memory blocks corresponding to the 7 page table entries. Starting from the starting page table entry #0, 6 page table entries need to be updated, spanning 6 memory blocks.

[0095] Each time the PCIe module 200 finishes reading and writing a portion of the target data corresponding to a page table entry, the page table entry is updated once, and the number of cross-border counts in the cross-border count buffer 240 is updated once. Therefore, it can be determined whether the target data has been read out based on the number of cross-border counts in the cross-border count buffer 240. When the number of cross-border counts is 0, it means that the reading and writing of the current read and write memory block is completed, and the processing of the DMA read and write request is completed.

[0096] For example, Figure 3 , Figure 4 For example, when reading and writing the target data corresponding to page table entry #0, the number of out-of-bounds counts in the out-of-bounds count buffer 240 is 6. When starting to read and write the target data corresponding to page table entry #1, the number of out-of-bounds counts in the out-of-bounds count buffer 240 is updated to 5. Similarly, when starting to read and write page table entry #6, the number of out-of-bounds counts in the out-of-bounds count buffer 240 is updated to 0, which means that after the target data corresponding to page table entry #6 is read and written, the DMA read and write request has been processed.

[0097] like Figure 4 As shown, in the embodiment of the present application, the data processing device further includes a descriptor buffer 210; the storage control module 100 is further configured to: in response to receiving multiple DMA read / write requests, generate a descriptor for each of the DMA read / write requests, and send each of the descriptors to the PCIe module 200;

[0098] The PCIe module 200 is further configured to store each of the descriptors in the descriptor buffer 210;

[0099] The descriptor buffer 210, the page table entry buffer 220, the physical address buffer 230 and the cross-border count buffer 240 store the descriptor, page table entry, physical address and cross-border count of the same DMA read / write request in the same storage depth.

[0100] The storage control module 100 often has to process multiple DMA read and write requests. In the embodiment of the present application, the storage control module 100 is configured to generate different descriptors for different DMA read and write requests. The descriptors are used to identify each DMA read and write request. For example, different identifiers DMA0, DMA1, DMA2, DMA3, etc. can be assigned to each DMA read and write request according to the order in which the DMA read and write requests are received. When the storage control module 100 sends the start page table entry, the start physical address and the total number of cross-border operations to the PCIe module 200, the descriptor of the DMA read and write request is sent to the PCIe module 200. The PCIe module 200 stores the descriptor of the DMA read and write request, the start page table entry, the start physical address and the total number of cross-border operations in the same storage depth of the descriptor buffer 210, the page table entry buffer 220, the physical address buffer 230 and the cross-border operation count buffer 240. Figure 3 Take the target data shown in the figure as an example. Figure 4 Each position of the memory depth 0 of each buffer stores DMA0, #0, 1M, and 6, which represent Figure 3 The descriptor of the DMA read / write request in is DMA0, the starting page table entry of the target data is #0, the starting physical address is 1M, and the current number of out-of-bounds times is 6. When the number of packets available for sending in the remaining space of the memory block corresponding to the page table entry #0 drops to a preset number, a query request is sent to the storage control module 100. When sending the query request, it indicates to the storage control module 100 that the query request is used to request to query the next page table entry and physical address of the DMA read / write request corresponding to DMA0. When the PICe module receives the next page table entry #1 and the corresponding physical address 2M, the page table entry #0 in the storage depth 0 of the page table buffer 220 is updated to page table entry #1, the physical address 1M in the storage depth 0 of the physical address buffer 230 is updated to 2M, and the number of out-of-bounds times 6 in the storage depth 0 of the out-of-bounds times buffer 240 is updated to 5. Similarly, for other DMA read and write requests, when updating their page table entries, physical addresses, and out-of-bounds counts, they can be updated at the storage location with the same storage depth as the descriptor of the corresponding DMA read and write request in the page table entry cache 220, the physical address cache 230, and the out-of-bounds count cache 240.

[0101] The embodiment of the present application can process multiple DMA read and write requests simultaneously by setting the descriptor buffer 210, and can also ensure that no error occurs when processing multiple DMA read and write requests simultaneously.

[0102] In the embodiment of the present application, by setting the page table entry buffer 220 and the physical address buffer 230, when processing a DMA read / write request, the storage control module 100 only needs to send the starting page table entry and the corresponding starting physical address when sending a processing instruction to the PCIe module 200. The PCIe module 200 stores the starting page table entry and the corresponding starting physical address in the page table entry buffer 220 and the physical address buffer 230, and can read the target data in the page table entry corresponding to the physical address according to the physical address in the physical address buffer 230; in addition, By counting the number of TLP packets available for sending in the remaining space of the memory block currently being read or written, when it drops to a preset number, the PCIe module 200 actively sends a query request to the storage control module 100 to query the next page table entry and the corresponding physical address, and stores the next page table entry and the corresponding physical address returned in the page table entry buffer 220 and the physical address buffer 230, so that when the target data corresponding to the previous page table entry is read and written, the target data corresponding to the next page table entry can be read and written, thereby improving data processing efficiency. Moreover, the present application utilizes the PCIe module 200 to actively send a query request to the storage control module 100 in reverse according to a preset number of times. Compared with the PCIe module 200 in the prior art that mechanically executes the processing instructions of the storage control module 100, when the PCIe module 200 in the present application reads and writes each memory block, the storage control module 100 only needs to send the starting page table entry and the corresponding starting physical address to the PCIe module 200, and then it can process other read and write requests, thereby also improving the processing capability of the storage control module 100.

[0103] Exemplary Methods

[0104] like Figure 5 As shown, the present application also proposes a data processing method, which is applied to the data processing device in each embodiment of the above exemplary device, and the data processing method includes the following steps:

[0105] Step S100: In response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, determining a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, and sending the starting page table entry and the starting physical address to the PCIe module;

[0106] Step S200: Based on the PCIe module, the page table entry and the corresponding physical address sent by the storage control module are stored in the page table entry buffer and the physical address buffer respectively;

[0107] And, based on the starting physical address, the target data is read and written in the memory module, and when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module; the query request is used to request to query the next page table entry in the page table corresponding to the memory block currently read and written and the physical address corresponding to the next page table entry;

[0108] Step S300: In response to receiving the query request, based on the storage control module, determine the next page table entry in the page table of the currently read and written page table entry and the physical address corresponding to the next page table entry, and send the next page table entry and the physical address corresponding to the next page table entry to the PCIe module.

[0109] The specific implementation methods of steps S100 - S300 refer to the various embodiments of the above-mentioned data processing device, which will not be described in detail here.

[0110] In the embodiment of the present application, the data processing method further includes:

[0111] In response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, determining a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, as well as a next page table entry of the starting page table entry in a page table and a physical address corresponding to the next page table entry;

[0112] The starting page table entry and the starting physical address corresponding to the starting page table entry, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry of the starting page table entry are sent to the PCIe module.

[0113] In the embodiment of the present application, the data processing method further includes:

[0114] Based on the starting physical address and the physical address corresponding to the next page table entry of the starting page table entry, continuously read and write the target data corresponding to the starting page table entry and the next page table entry of the starting page table entry; and

[0115] Starting from the memory block corresponding to the next page table entry of the starting page table entry, when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module.

[0116] In an embodiment of the present application, the data processing method also includes: determining the total number of times the target data crosses the boundary in the memory module based on the storage control module, the DMA read and write request, the size of each memory block in the memory module, and the starting physical address.

[0117] In the embodiment of the present application, the processing method further includes:

[0118] Based on the PCIe module, storing the total number of times the target data crosses the boundary in the memory module in the cross-boundary count buffer; and

[0119] Every time a portion of target data corresponding to a page table entry is read and written, the number of cross-border times in the cross-border times counting buffer is updated once.

[0120] In the embodiment of the present application, the data processing method further includes:

[0121] In response to receiving multiple DMA read / write requests, generating a descriptor for each of the DMA read / write requests based on the storage control module, and sending each of the descriptors to the PCIe module;

[0122] Based on the PCIe module, each descriptor is stored in the descriptor buffer respectively; wherein, the descriptor, page table entry, physical address and cross-boundary count of the same DMA read / write request are stored in the same storage depth of the descriptor buffer, the page table entry buffer, the physical address buffer and the cross-boundary count buffer.

[0123] The data processing method of the embodiment of the present application is applied to the data processing device of any of the above embodiments, and therefore includes all the beneficial effects of the data processing device described in any of the above embodiments, which will not be elaborated here one by one.

[0124] Exemplary Media

[0125] After introducing the method and device of the exemplary embodiment of the present application, next, refer to Figure 6 For a description of the computer-readable storage medium of the exemplary embodiment of the present application, please refer to Figure 6, the computer-readable storage medium shown is a CD-ROM 70, on which a computer program (i.e., a program product) is stored. When the computer program is executed by the processor, the steps described in the above method implementation are implemented, for example, in response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, determining the starting page table entry of the virtual address of the target data in the page table and the starting physical address corresponding to the starting page table entry, and sending the starting page table entry and the starting physical address to the PCIe module; based on the PCIe module, storing the page table entry and the corresponding physical address sent by the storage control module in the page table entry buffer and the physical address buffer respectively; and based on the starting physical The target data is read and written in the memory module at the address, and when the number of packets available for sending in the remaining space of each memory block of the memory module according to the preset TLP size drops to the preset number, a query request is sent to the storage control module; the query request is used to request to query the next page table item in the page table corresponding to the memory block currently read and written and the physical address corresponding to the next page table item; in response to receiving the query request, the storage control module determines the next page table item in the page table of the page table currently read and written and the physical address corresponding to the next page table item, and sends the next page table item and the physical address corresponding to the next page table item to the PCIe module. The specific implementation method of each step will not be repeated here. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0126] Exemplary Computing Devices

[0127] refer to Figure 7 , the present application also provides a computing device.

[0128] Figure 7 A block diagram of an exemplary computing device 80 suitable for implementing embodiments of the present application is shown. The computing device 80 may be a computer system or a server. Figure 7 The computing device 80 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0129] like Figure 7As shown, the components of the computing device 80 may include, but are not limited to: one or more processors or processing units 801 , a system memory 802 , and a bus 803 connecting various system components (including the system memory 802 and the processing unit 801 ).

[0130] The computing device 80 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 80, including volatile and non-volatile media, removable and non-removable media.

[0131] The system storage 802 may include computer system readable media in the form of volatile storage, such as random access memory (RAM) 8021 and / or cache memory 8022. The computing device 80 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the ROM 8023 may be used to read and write non-removable, non-volatile magnetic media ( Figure 7 is not shown in the Figure 7 As shown in FIG. 8 , a disk drive for reading and writing a removable non-volatile disk (e.g., a “floppy disk”) and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) can be provided. In these cases, each drive can be connected to the bus 803 via one or more data medium interfaces. The system storage 802 may include at least one program product, which has a set (e.g., at least one) of program modules, which are configured to perform the functions of each embodiment of the present application.

[0132] A program / utility 8025 having a set (at least one) of program modules 8024 may be stored, for example, in system memory 802, and such program modules 8024 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. Program modules 8024 generally perform the functions and / or methods of the embodiments described herein.

[0133] The computing device 80 may also communicate with one or more external devices 804 (e.g., a keyboard, a pointing device, a display, etc.). Such communication may be performed via an input / output (I / O) interface. In addition, the computing device 80 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 806. Figure 7 As shown, the network adapter 806 communicates with other modules (such as the processing unit 801, etc.) of the computing device 80 via the bus 803. It should be understood that although Figure 7Not shown, other hardware and / or software modules may be used in conjunction with computing device 80 .

[0134] The processing unit 801 executes various functional applications and data processing by running the program stored in the system memory 802. For example, in response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, the processing unit 801 determines the starting page table entry of the virtual address of the target data in the page table and the starting physical address corresponding to the starting page table entry, and sends the starting page table entry and the starting physical address to the PCIe module; based on the PCIe module, the page table entry and the corresponding physical address sent by the storage control module are stored in the page table entry buffer and the physical address buffer respectively; and based on the starting physical address, the target data is accessed in the memory module. Read and write, and when the number of packets available for sending in the remaining space of each memory block of the memory module according to the preset TLP size drops to the preset number, send a query request to the storage control module; the query request is used to request to query the next page table item in the page table corresponding to the memory block currently read and written and the physical address corresponding to the next page table item; in response to receiving the query request, based on the storage control module, determine the next page table item in the page table of the page table currently read and written and the physical address corresponding to the next page table item, and send the next page table item and the physical address corresponding to the next page table item to the PCIe module. The specific implementation of each step is not repeated here. It should be noted that although several units / modules or sub-units / sub-modules of the computing device are mentioned in the above detailed description, this division is only exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units / modules described above can be concretized in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be concretized.

[0135] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0136] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A data processing device, comprising: Storage control module, PCIe module, page table entry buffer, physical address buffer; The storage control module is configured to: in response to receiving a DMA read / write request, determine a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry based on the DMA read / write request, and send the starting page table entry and the starting physical address to the PCIe module; The PCIe module is configured to: in response to receiving the page table entry and the corresponding physical address sent by the storage control module, store the page table entry and the physical address in the page table entry buffer and the physical address buffer respectively; and, reading and writing the target data in the memory module based on the starting physical address, and sending a query request to the storage control module when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number; The query request is used to request to query the next page table entry in the page table corresponding to the memory block currently read or written and the physical address corresponding to the next page table entry; The storage control module is also configured to: in response to receiving the query request, determine the next page table entry in the page table of the currently read and written page table entry and the physical address corresponding to the next page table entry, and send the next page table entry and the physical address corresponding to the next page table entry to the PCIe module.

2. The data processing device according to claim 1, wherein the storage control module is further configured to: in response to receiving a DMA read / write request, determine, based on the DMA read / write request, a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, as well as a next page table entry of the starting page table entry in a page table and a physical address corresponding to the next page table entry; The starting page table entry and the starting physical address corresponding to the starting page table entry, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry of the starting page table entry are sent to the PCIe module.

3. The data processing device according to claim 2, wherein the PCIe module is further configured to: continuously read and write target data corresponding to the starting page table entry and the next page table entry of the starting page table entry based on the starting physical address and the physical address corresponding to the next page table entry of the starting page table entry; and Starting from the memory block corresponding to the next page table entry of the starting page table entry, when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module.

4. According to the data processing device as described in claim 1, the storage control module is also configured to: determine the total number of times the target data crosses the boundary in the memory module based on the DMA read and write request, the size of each memory block in the memory module, and the starting physical address.

5. The data processing device according to claim 4, further comprising a buffer for counting the number of times the boundary is crossed; The storage control module is further configured to: send the total number of times the target data crosses the boundary in the memory module to the PCIe module; The PCIe module is further configured to: store the total number of times the target data crosses the boundary in the memory module in the cross-boundary count buffer; and Every time a portion of target data corresponding to a page table entry is read and written, the number of cross-border times in the cross-border times counting buffer is updated once.

6. The data processing device according to claim 5, wherein the data processing device further comprises a descriptor buffer, and the storage control module is further configured to: in response to receiving a plurality of DMA read / write requests, generate a descriptor for each of the DMA read / write requests, and send each of the descriptors to the PCIe module; The PCIe module is further configured to store each of the descriptors in the descriptor buffer respectively; in, The descriptor buffer, the page table entry buffer, the physical address buffer and the cross-border count buffer store the descriptor, page table entry, physical address and cross-border count of the same DMA read / write request in the same storage depth.

7. A data processing method, applied to the data processing device according to any one of claims 1 to 6, the data processing method comprising: In response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, determining a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, and sending the starting page table entry and the starting physical address to the PCIe module; Based on the PCIe module, the page table entry and the corresponding physical address sent by the storage control module are stored in the page table entry buffer and the physical address buffer respectively; and, reading and writing the target data in the memory module based on the starting physical address, and sending a query request to the storage control module when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number; The query request is used to request to query the next page table entry in the page table corresponding to the memory block currently read or written and the physical address corresponding to the next page table entry; In response to receiving the query request, based on the storage control module, determine the next page table entry in the page table of the currently read and written page table entry and the physical address corresponding to the next page table entry, and send the next page table entry and the physical address corresponding to the next page table entry to the PCIe module.

8. The data processing method according to claim 7, further comprising: In response to receiving a DMA read / write request, based on the storage control module and the DMA read / write request, determining a starting page table entry of a virtual address of target data in a page table and a starting physical address corresponding to the starting page table entry, as well as a next page table entry of the starting page table entry in a page table and a physical address corresponding to the next page table entry; The starting page table entry and the starting physical address corresponding to the starting page table entry, as well as the next page table entry of the starting page table entry and the physical address corresponding to the next page table entry of the starting page table entry are sent to the PCIe module.

9. The data processing method according to claim 8, further comprising: Based on the starting physical address and the physical address corresponding to the next page table entry of the starting page table entry, continuously read and write the target data corresponding to the starting page table entry and the next page table entry of the starting page table entry; and Starting from the memory block corresponding to the next page table entry of the starting page table entry, when the number of packets available for sending according to the preset TLP size in the remaining space of each memory block of the memory module drops to a preset number, a query request is sent to the storage control module.

10. The data processing method according to claim 7, further comprising: Based on the storage control module, the DMA read / write request, the size of each memory block in the memory module, and the starting physical address, the total number of times the target data crosses the boundary in the memory module is determined.

11. The data processing method according to claim 10, further comprising: Based on the storage control module, the total number of times the target data crosses the boundary in the memory module is sent to the PCIe module; Based on the PCIe module, storing the total number of times the target data crosses the boundary in the memory module in a cross-boundary count buffer; as well as Every time a portion of target data corresponding to a page table entry is read and written, the number of cross-border times in the cross-border times counting buffer is updated once.

12. The data processing method according to claim 10, further comprising: In response to receiving a plurality of DMA read / write requests, generating a descriptor for each of the DMA read / write requests based on the storage control module, and sending each of the descriptors to the PCIe module; Based on the PCIe module, each descriptor is stored in the descriptor buffer respectively; wherein, the descriptor, page table entry, physical address and out-of-bounds count of the same DMA read / write request are stored in the same storage depth of the descriptor buffer, the page table entry buffer, the physical address buffer and the out-of-bounds count buffer.

13. A computer-readable storage medium comprising instructions, which, when executed on a computer, causes the computer to execute the method according to any one of claims 7 to 12.

14. A computing device, comprising a processor, wherein the processor is configured to implement the method according to any one of claims 7 to 12 when executing a computer program stored in a memory.

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