Satellite-borne image data simulation source system

Abstract

The invention belongs to the field of aviation and aerospace payload testing, and relates to a satellite-borne image data simulation source system, which is used for providing image data for testing for a satellite-borne image processing system and comprises a storage register module realized based on an FPGA (Field Programmable Gate Array) and a simulation image processing module deployed on an upper computer, the storage register module is used for receiving and storing the image frame data generated by the image processing module and providing the image frame data to a satellite-borne image processing system; the feedback module is also used for feeding back the return data of the satellite-borne image processing system to the analog image processing module; the image processing module is used for providing a graphical user interface, receiving a user instruction to manage the image source database, framing to generate image frame data, and transmitting the image frame data to the FPGA; and the receiving module is also used for receiving return data which is transmitted by the FPGA and comes from the satellite-borne image processing system. The system has the advantages of multiple adaptive interfaces, rich configuration options, high flexibility and high reliability.

Description

Technical Field

[0001] The invention belongs to the field of aviation and aerospace payload testing, and in particular relates to a satellite-borne image data simulation source system. Background Art

[0002] The design and development of various satellites is an important way to achieve space science exploration and space application development. The payload, as a direct tool to achieve the above-mentioned means, must undergo rigorous testing and evaluation before being installed on the satellite. Image processing, as an important part of the onboard data processing function, plays a vital role. In order to ensure the performance and reliability of the onboard image acquisition and processing system, comprehensive ground testing, verification and evaluation have become an indispensable part.

[0003] Traditional image data analog sources mainly rely on CCD cameras to generate image data, but their inherent limitations make it difficult to meet the growing and diverse needs. Specifically, these analog sources are unable to output image content in flexible and changeable scenes, realize multiple transmission formats, and provide rich configuration options.

[0004] In addition, the existing general ground detection system cannot fully simulate the complex environment and abnormal conditions that may be encountered in satellite image processing, and it is difficult to deeply optimize and adapt specific satellite image processing algorithms, which may lead to problems such as low matching degree and unstable performance in actual applications. And it is usually composed of an industrial computer and an FPGA board with an external payload interface adapter board. Although such an architecture can meet basic image processing requirements, it still has shortcomings in processing speed and flexibility, and the chassis will be bulky and inconvenient to carry. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and propose a satellite-borne image data simulation source system.

[0006] In order to achieve the above-mentioned object, the present invention provides a satellite-borne image data simulation source system for providing test image data for a satellite-borne image processing system, comprising: a storage register module implemented based on FPGA and a simulation image processing module deployed on a host computer; wherein,

[0007] The storage module is used to receive and store the image frame data generated by the image processing module and provide it to the onboard image processing system; it is also used to feed back the return data of the onboard image processing system to the analog image processing module;

[0008] The image processing module is used to provide a graphical user interface, receive user instructions to manage the image source database, assemble frames to generate image frame data and transmit them to the FPGA; and is also used to receive return data from the satellite-borne image processing system transmitted via the FPGA.

[0009] Preferably, the FPGA and the host computer communicate via a PCIe high-speed channel, using a PCIe to Thunderbolt 4 adapter board.

[0010] Preferably, the storage register module includes: a configuration control register group, a check unit, an external memory management unit, a transmission clock control unit, a parallel-to-serial conversion unit and a serial-to-parallel conversion unit; wherein,

[0011] The configuration control register group is used to realize the control of the FPGA by the host computer and the function of the FPGA returning the working status to the host computer, including control registers, address registers, size registers, peripheral registers, load and send status registers and receive status registers;

[0012] The verification unit is used to verify the data integrity and correctness of the loading process, start the work through the specific field of the control register, perform synchronization header verification, instruction verification and data verification on the input data, and store the verification result in the specific field of the receiving status register;

[0013] The external memory management unit is used to realize efficient reading and writing of the external SDRAM memory, provide an SRAM memory read and write interface to other modules, and realize writing of specified size data from the logical area to the specified address of the memory and reading of specified size data from the specified address of the memory to the logical area through the control of the control register, the address register and the size register;

[0014] The sending clock control unit is used to generate and select a clock of a corresponding frequency as a sending clock according to a specific field of the control register;

[0015] The parallel-to-serial conversion unit is used to receive data from the external memory management unit, and use the transmission clock selected by the transmission clock control unit to convert the parallel data into serial data and output it to the external interface of the FPGA board;

[0016] The serial-to-parallel conversion unit is used to convert serial data received by the external interface of the FPGA board into parallel data according to the enable flag of the control register, and transmit it to the external storage management unit in bytes.

[0017] Preferably, the control register, address register, size register and peripheral register support read and write operations, and the load send status register and receive status register only support read operations.

[0018] Preferably, the image processing module includes: a system control function unit, an image source database management unit, a loading function unit, a sending function unit and a receiving function unit, wherein:

[0019] The system control functional unit is used to monitor the system status by acquiring the system status field of the control register of the FPGA, to monitor the link status by acquiring the link status information of the PCIe high-speed channel, and to uniformly reset and initialize the image processing module and the FPGA;

[0020] The image source database management unit is used to index and call the local image set, to implement image preview according to image size information and bit depth information, and to perform image enhancement;

[0021] The loading function unit is used to implement image data framing, memory management, and frame loading verification according to user loading instructions, and send the processed image frames to the FPGA;

[0022] The sending function unit is used to configure the sending instruction and the sending parameters to the FPGA according to the user sending instruction;

[0023] The receiving function unit is used to receive the data returned by the FPGA according to the user's receiving instruction, store and display it.

[0024] Preferably, the processing of loading the functional unit includes:

[0025] Step 1) Start the loading thread;

[0026] Step 2) Parse the user loading instruction and open the image to be loaded;

[0027] Step 3) Allocate frame space according to image information and frame format, add frame header, image data and frame footer in sequence, frame the image data to be loaded, and use memory management to allocate memory addresses, and transfer the image frame data to the external SDRAM memory of FPGA through DMA of h2c channel;

[0028] Step 4) configure the control register, size register and address register of the FPGA;

[0029] Step 5) verifying the image frame and synchronously feeding back the verification result to the graphical user interface;

[0030] Go to step 2) until all the images to be loaded are transferred and the loading thread ends.

[0031] Preferably, the frame header in the frame format includes: an 8-byte synchronization header, a 2-byte image width, a 2-byte image height, a 2-byte image bit depth, a 4-byte image occupied byte and a 2-byte frame header check;

[0032] The number of bytes occupied by image data is determined by the actual amount of image data;

[0033] The end of the frame is a 2-byte data check, which is calculated by adding up each byte of the image data to obtain the cumulative sum.

[0034] Preferably, the processing process of the receiving functional unit includes:

[0035] Step 1) Start the receiving thread;

[0036] Step 2) configure the control register;

[0037] Step 3) detects whether the end flag is set, if it is set, go to step 5); if it is not set, read the receive status register; determine whether the receive block is full, if it is not, go to step 3), otherwise, go to step 4);

[0038] Step 4) initiate a DMA request for the c2h channel to read the data of the corresponding block. After the reading is completed, set the corresponding bit of the control register, write the block data into the file, and go to step 3);

[0039] Step 5) Read the receiving status register, obtain the amount of data stored in the last block, initiate a DMA request for the c2h channel, write the data of the last block to the file, close the receiving thread, and complete a reception.

[0040] Preferably, the graphical user interface comprises:

[0041] The system control area is used to start, stop and monitor the status of the system, provide a debugging function entry, and realize direct reading and writing of the configuration control register group;

[0042] The image source database tab is used to configure and manage various image source data, provide real-time image preview and parameter adjustment, provide an image loading function configuration parameter interface, and provide an image loading function interface;

[0043] The sending and receiving function tab is used to browse the loaded image list, provide a sending parameter configuration interface, a sending function entry, and a sending status display, as well as provide a receiving function entry, a receiving status display, and a quick view of received files; and

[0044] The log area is used to display detailed log information during system operation and implement the log file saving and recording function.

[0045] Compared with the prior art, the advantages of the present invention are:

[0046] 1. This invention is specially designed for satellite-borne image processing systems, providing comprehensive image data set management, convenient image preview function, and flexible working condition configuration sending capabilities. It is characterized by powerful functions, rich configuration options, and a user-friendly graphical interface, which ensures intuitive and easy operation, can fully meet diverse test needs, and greatly improves user experience;

[0047] 2. The external interface of the present invention adopts a modular design, which can be loaded with different on-board equipment interfaces and match different transmission rates, and has the advantages of strong compatibility and high adaptability;

[0048] 3. The present invention uses a PCIe to Thunderbolt 4 adapter board. Compared with the traditional chassis-type PCIe card insertion, a mini host with a USB4 interface can be used as the host computer, which not only supports hot plugging of cards, but also greatly reduces the weight of the system, improving the portability and practicality of the system;

[0049] 4. The design of the present invention adopts a modular concept, and the units work together efficiently, so that the system maintains a high degree of flexibility and scalability while ensuring high performance, and is also convenient for later maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0051] Figure 2 It is a typical workflow diagram of the present invention;

[0052] Figure 3 It is a flowchart of the loading function of the host computer of the present invention;

[0053] Figure 4 It is a flowchart of the sending function of the host computer of the present invention;

[0054] Figure 5 It is a flowchart of the receiving function of the host computer of the present invention;

[0055] Figure 6 It is a design block diagram of a verification unit designed by FPGA of the present invention;

[0056] Figure 7 It is a design block diagram of a parallel-to-serial conversion unit designed by FPGA of the present invention;

[0057] Figure 8 It is a design block diagram of the serial-to-parallel conversion unit designed by FPGA of the present invention. DETAILED DESCRIPTION

[0058] The system of the present invention is used to test the functional correctness of different satellite-borne image processing systems, and the system comprises: host computer software, PCIe high-speed channel, FPGA implementation, and external interface.

[0059] The host computer software includes a graphical user interface and multiple functional unit modules. The graphical user interface provides a user interaction interface, and the functional unit modules implement specific functions. The graphical user interface is divided into two areas, the system control area and the functional area. The functional area can be further divided into an image source database tab and a sending and receiving function tab.

[0060] The system control area is responsible for monitoring the operating status of the entire system and providing control instructions such as start, stop, and reset. The system control area provides status indicators for board status and link status to intuitively indicate whether the working status of the board and the link status of the PCIe link are normal. The system control area also provides advanced debugging functions, including speed measurement, sending cumulative numbers, system reset, and opening the debugging interface.

[0061] The above advanced debugging functions are used to deeply optimize and troubleshoot the system to ensure the stability and efficiency of data transmission.

[0062] The above speed test function is divided into loading speed test and reading speed test, which is used to obtain the PCIe link transmission speed through system self-test after the host computer and FPGA establish a connection. The loading speed test uses a 4MB test data packet to load into the FPGA 100 times in a loop. The time consumed is obtained by subtracting the timestamp when the loading is completed from the timestamp when the loading starts. The speed can be obtained by dividing 400MB by the time. The reading speed test is to initiate 100 4MB data read requests and calculate the transmission speed in a similar way;

[0063] The above-mentioned cumulative number sending function refers to the function of sending cumulative numbers through the external interface, which is used to detect whether the external link with the device under test is correctly connected and the data receiving capability of the device under test. It can also be used to detect whether the link of this system is unobstructed during the loopback test;

[0064] The above-mentioned system reset function refers to resetting the system, including resetting the host computer software and resetting the FPGA operating state. It is used to make the system enter the initial working state when the system is powered on, and is also used to restore the correct working state when the system is abnormal.

[0065] The above debugging interface refers to an interface that users will use in atypical usage flow situations, which is used to debug the analog source system internally. In the debugging interface, users can directly view and edit the configuration control register group, and directly monitor and control the working status of the FPGA by parsing the definitions of the register group;

[0066] The image source database tab provides a rich set of image source management functions, where users can import, export, edit and delete images, and the image loading function is also implemented in the current tab. The tab mainly provides a user interface for image data set management, image preview and image loading functions.

[0067] The above image dataset management function will automatically retrieve the legal image sets in the local image set folder when the program is running, and automatically load the detected image sets into the database. Users can use the drop-down list to select the image set. Users can also click on an image to preview it. Users can also select a single or multiple images to perform the loading function.

[0068] The preview function mentioned above means that when the user clicks on an image, a thumbnail preview and detailed content of the current image will be displayed in the preview window. You can also check the Image Brightness Enhancement checkbox to adjust the image brightness so that the details of the image can be viewed more clearly during preview.

[0069] The above-mentioned loading function means that the user selects a single image or multiple images, selects the synchronization frame header, and clicks the load button. The system will then call the loading function unit to frame the selected images and load them into the external memory of the FPGA. At the same time, the user interface will synchronously display the loading progress.

[0070] The Send and Receive tab provides the sending and receiving functions. The sending function is to convert the loaded image frame data into serial and parallel data and send it to the device under test through the external interface; while the receiving function is to receive the return data from the device under test through the external interface and save the data to a file. It is mainly divided into two areas: data sending and data receiving.

[0071] The data sending area above will display a list of all images that have been loaded into the FPGA external memory and the size of the cache space occupied. In this area, users can view the sending order, adjust the sending rate, check whether to send all, or select to send part, and click the send button to start the sending process. During sending, the system will display the current sending progress.

[0072] The above data receiving area provides start receiving and end receiving buttons, through which users can start and stop receiving data. In addition, the receiving area can also display the receiving progress in real time, and allow users to set the saving path and file name. The file name will be automatically named according to the system time as "MM-dd_HH-mm-ss.bin". A quick button to open the receiving folder is also provided, and users can perform basic data analysis directly on the interface after the data is received.

[0073] The log area records various operations and status changes during the program running process, which is convenient for users to track the execution process and troubleshoot problems. At the same time, this area also has a filtering function, and users can filter log information according to their needs and quickly locate key operation records. The entries in the log record are divided into three parts: time, prompt level and prompt information. The time is the time when this log is generated, accurate to seconds. The prompt level is divided into three types according to the importance: Error, Warning and Info, which are used to distinguish different types of information during the operation process, and are distinguished by different color fonts so that users can quickly identify and deal with various problems.

[0074] The multiple functional unit modules include a system control functional unit, an image source database management unit, a loading functional unit, a receiving functional unit and a sending functional unit, wherein:

[0075] The above system control unit is responsible for the specific implementation of system status monitoring, link status monitoring, global reset and initialization.

[0076] The above link status monitoring is to detect the PCIe link between the host computer and FPGA when the system starts running and monitor it in real time during operation. When the system starts running, the host computer will allocate a dedicated memory address for the c2h channel and call the system function to open the xdma_h2c, xdma_c2h, and xdma_user devices. If the device is opened correctly, it means that the link status is normal.

[0077] The above-mentioned system status monitoring refers to judging whether the FPGA logic is correct through the reset_n field of the control register in the configuration control register of the FPGA. If it is 1, it means that the system is in a working state, and if it is 0, it means that the system is in a reset state.

[0078] The above global reset and initialization includes a unified state reset of the devices at both ends of the host computer and FPGA, ensuring that each unit module of the system can enter the initial state synchronously. The initialization of the host computer is to perform the initial default configuration of the user graphical interface on the one hand, and to initialize each functional unit on the other hand. The initialization of the FPGA is to write 0 to the 0th bit of the control register through the xdma_user device, and then write 1 after a delay of 100us to complete the reset.

[0079] The above-mentioned image source database management unit is responsible for image data set management, and provides image preview, image information preview, and image enhancement preview functions.

[0080] The above-mentioned image data set management function means that when the system is running, it will automatically scan the image_set_dir file, find out all legal image sets in all folders, and add them all to the database index.

[0081] The definition of the above legal image set is a folder containing image files and description files, where the folder name should be consistent with the image set name. There is a JSON format description file named with the image set name under the folder, and the description file contains image-related information of all images in the image set.

[0082] The above image-related information includes image path, image file name, image name, image width, image height, image bit depth, and the name of the set to which the image belongs.

[0083] The above image preview related functions mean that when the user selects an image from the interface, the system will open the raw image, allocate a suitable memory space for caching the image according to the image related information, convert the image into a grayscale image with a color depth of 8bit or 16bit according to the bit depth, and then scale it to a suitable size and display it using the label control. At the same time, if the image enhancement preview function is enabled, the image will automatically be adaptively histogram-equalized, so that some darker images can also clearly show details.

[0084] The above loading function unit will pre-process and load the selected image according to the parameters set by the user, mainly including three functional steps: image data framing, memory address management, and frame loading verification. In order not to affect the user graphical interface, the implementation of the loading function unit will be executed in an independent thread.

[0085] The above-mentioned image data framing functional step refers to adding a frame header and a frame footer to the original raw data of the image according to the protocol regulations, and allocating memory space to store the corresponding frame data therein so that it can be directly used in the subsequent loading functional step.

[0086] The above-mentioned image frame format is defined as a frame of image consisting of three parts: frame header, image data and frame tail. In one embodiment, the frame header is set to 20 bytes, including an 8-byte synchronization header, whose value is fixed at 4954CE1F066B0000, 2-byte image width, 2-byte image height, 2-byte image bit depth, 4-byte image occupied bytes and 2-byte frame header check. The image data occupies N bytes determined by the actual image data volume. The frame tail is a 2-byte data check, which is calculated by accumulating each byte of the image data and obtaining the cumulative sum after the accumulation.

[0087] The above memory address management refers to allocating image frames to specific addresses of the external SDRAM memory of a specific FPGA to ensure the efficiency and stability of data access. In the loading buffer of the external memory, an 8-byte aligned start address is automatically allocated and the space occupied by each frame is recorded. After completing the memory address management, the system will enter the frame loading verification function step.

[0088] The above frame loading verification function steps mainly involve sending the framed frame data to the FPGA through the PCIe channel and receiving the status field returned by the FPGA to determine whether the loading process is completed correctly.

[0089] The above data is sent to the FPGA through the PCIe channel. The frame data is mainly divided into small blocks of up to 4MB. Each small block is copied to the DMA shared memory, a DMA request is initiated, and the DMA controller completes the data transmission. The address and current frame size to be stored in the current frame are written into the address register and size register respectively. During the transmission process, the load_prog field of the load and send status register is detected to monitor the data transmission progress in real time. After the transmission is completed, the check_en field of the control register is changed from 0 to 1 to generate a rising edge to enable the FPGA's check unit, and then the check_result field of the load and send status register is detected to check whether the loaded data is correct.

[0090] In one embodiment, the load_prog field and check_result field of the above-mentioned load and send status register are located in the [9:3] bit field and the [2:0] bit field of the register respectively. The load_prog field is responsible for indicating the progress of data transmission. Using 7 bits, it can represent 0 to 127. By quantizing the send size to 7 bits, the sending progress is tracked with an accuracy of 1 / 128. The check_result field is used to display the data verification result. When bit[2] is 1, it means that a verification is completed. Bit[1:0] is used to indicate the verification result: 00, the verification is correct; 01, the synchronization header is not detected; 10, the frame header verification error; 11, the frame tail verification error.

[0091] The receiving function unit above will determine whether it is in working state according to whether the user turns on the receiving enable. If it is in non-working state, no DMA read data request will be initiated, and the response field of the control register will also be set to disable. In this state, the system will maintain low power mode and only maintain the necessary register state. When the user sets the receiving enable bit, the system will be activated, and the recv_en field of the configuration control register (the [3] bit of the control register) will change from 0 to 1 to generate a rising edge. At this time, the FPGA starts to receive data. The host computer analyzes the status of the current received data in real time by continuously querying the recving field, recv_block_flag field, and recv_block_last_bytes field of the receiving status register.

[0092] The recving field (bit 30) of the receive status register is used to indicate whether the current FPGA has enabled reception. If the value is 1, it means that reception is enabled; if the value is 0, it means that reception is not enabled.

[0093] The recv_block_flag field (bits [29:22]) of the receive status register is used to indicate which receive buffer blocks have been filled. The receive buffer block is divided into 8 receive buffer blocks. Each bit of this field corresponds to a block. When this bit is 1, it means that the corresponding receive buffer block is full. The host computer needs to read the corresponding data in time to prevent data loss. At the same time, the order of reading blocks is from block 0 to block 7 and then recycles from block 0.

[0094] The recv_block_last_bytes field of the receive status register is located at the [21:0] bit of the receive status register, which is used to indicate the size of the data received by the last block buffer, indicating a range of [0,4MB). Note that its value cannot be 4MB. If a buffer is already filled, the corresponding bit of recv_block_flag will be pulled high, and the value refers to the bytes that have been filled in the next block.

[0095] The sending function unit will write a specific value to a specific field of a specific register of the configuration control register group according to the user's operation, and read a specific field of the specific register to track the sending process.

[0096] Writing a specific value to a specific field of a specific register means configuring the send_clk field of the control register to the transmission frequency selected by the user. In one embodiment, 00: 100 MHz (default), 01: 200 MHz, 10: 300 MHz, 11: 400 MHz are defined, and the send_en field is configured to change from 0 to 1 on the rising edge to enable transmission. At the same time, the address register and the size register are configured as the data address for this transmission.

[0097] Reading a specific field of a specific register to track the sending process refers to reading the send_prog field of the load send status register. This field is located at the [16:10] position of the register and uses 7 bits to represent 0 to 127. By quantizing the sending size to 7 bits, the sending progress is tracked with an accuracy of 1 / 128, thereby monitoring the data sending status in real time.

[0098] The access to the above control register, address register, size register, peripheral register, load send status register and receive status register is realized through the xdma_user device, and its address is mapped to 0x00000, 0x00008, 0x10000, 0x10008, 0x20000 and 0x20008 of the xmda_user device respectively. The configuration of the address register and size register can be realized by reading and writing the 32-bit data of the address. Among them, the control register, address register, size register and peripheral register support reading and writing, while the load send status register and receive status register only support reading.

[0099] The PCIe high-speed channel provides high-speed transmission capability for image data, ensuring that the system can maintain efficient and stable performance when processing large amounts of image data. Through this channel, images can be quickly loaded, sent and received, ensuring high efficiency and high reliability of the system when working.

[0100] The FPGA implementation includes a configuration control register group, an external memory management unit, a verification unit, a transmission clock control unit, a parallel-to-serial conversion unit, a serial-to-parallel conversion unit and an external SDRAM memory.

[0101] The configuration control register group includes 6 groups of registers, each register has a 32-bit data bit width, and is divided into 6 registers: control register, address register, size register, peripheral register, load send status register and receive status register according to different application requirements. They are connected to the XDMA core through the AXI4-Lite protocol and mapped to the 0x40000000 address through PCIeto AXI Transation address mapping. The specific implementation of this register group is implemented using AXIGPIO.

[0102] The external memory management unit is responsible for managing the external SDRAM memory and realizing efficient reading and writing of the SDRAM by the logic end. At the same time, the SDRAM space is divided into a loading buffer and a receiving buffer block area, which are respectively used to store the image data to be sent and the received return data. At the same time, the external memory management unit also has efficient data processing capabilities, and is responsible for transmitting data to the host computer, reading data from the host computer, transmitting data to the verification unit, providing the serial-to-parallel conversion unit with data to be sent, and receiving data from the parallel-to-serial conversion unit.

[0103] The verification unit includes the functions of frame synchronization header verification, cumulative sum verification and returning verification results. When a rising edge jump is detected in the check_en field of the control register, the verification will start. The internal state machine of the verification unit enters the verification mode, and then reads byte data from the data entry, matches the frame synchronization header one by one, calculates the frame header cumulative sum, calculates the data cumulative sum, and compares the preset verification value. Once any error is found during the verification process, the verification unit will immediately report the error status to the load and send status register, that is, write the corresponding verification value to the check_result field, and stop the current data transmission.

[0104] The sending clock control unit uses a PLL module to generate clocks with frequencies including but not limited to 100MHz, 200MHz, 300MHz and 400MHz, and performs clock selection according to the send_clk field of the control register, switching the clock frequency used as the working clock of the parallel-to-serial conversion module.

[0105] The parallel-to-serial conversion unit receives data sent from the external memory management unit, and converts the data in the ui_clk clock domain to the tx_clk clock domain through the cross-clock domain asynchronous FIFO, and transmits it serially by bit. When transmitting, the low byte of the data is sent first, and the high bit of each byte is sent first. The rising edge of the clock is aligned and used as the transmitting edge of the data.

[0106] The serial-to-parallel conversion unit receives serial data from the external interface, combines it into bytes in the rx_clk clock domain, sends it to the asynchronous FIFO, and uses the falling edge as the sampling edge to receive data. The data stored in the asynchronous FIFO will be synchronized to the ui_clk clock domain, and combined into a 128-bit AXIS data packet in this clock domain for processing by the external memory management unit.

[0107] The external interface refers to a level conversion board that can be connected using FMC, such as an LVDS level conversion board, a TLK2711 level conversion board, and an RS422 level conversion board, etc. By connecting level conversion boards of different interfaces, compatibility with communication interface standards of different devices under test can be achieved.

[0108] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0109] Example

[0110] like Figure 1 As shown, an embodiment of the present invention provides a satellite image data simulation source system for providing test image data for a satellite image processing system. Users can use the system to manage image data sets, and send images to the satellite image processing system through an external interface and receive return data for testing.

[0111] This system is implemented by using a host computer plus FPGA design, including: a storage register module based on FPGA and an analog image processing module deployed on the host computer;

[0112] The storage module is used to receive and store the image frame data generated by the image processing module and provide it to the onboard image processing system; it is also used to feed back the return data of the onboard image processing system to the analog image processing module;

[0113] The image processing module is used to provide a graphical user interface, receive user instructions to manage the image source database, and frame the generated image frame data to transmit to the FPGA; it is also used to receive return data from the satellite-borne image processing system transmitted via the FPGA.

[0114] The host computer and FPGA are connected through the PCIe high-speed channel, and the use of a PCIe to Thunderbolt 4 adapter board can realize hot-swapping of the FPGA board and the lightweight portability of the entire system.

[0115] The functions realized by this system include: providing a graphical user interface for convenient operation by users; supporting the management of the image source database; selecting multiple images for loading; customizing the sending conditions and sending image frame data to the onboard image processing system to be tested; receiving return data from the onboard image processing system; and displaying and parsing the received data.

[0116] A typical workflow of the present invention is as follows Figure 2As shown: the user first powers on the simulation source system, connects the FPGA and the host computer, and opens the host computer software to start the simulation source system. Then the system will perform self-test and initialization, and realize link detection and board status detection by calling the system control function unit. The image source database management unit will automatically scan the local image set, and the log function will be turned on to record the startup status. Then the user can choose to turn on the receiving enable or browse the image set at any time. After turning on the receiving enable, the system will activate the receiving thread and prepare to obtain the return data from the onboard image processing system to be tested. If the user chooses to browse the image set in the image source database tab, you can preview the image by clicking on an image, and you can select multiple images by holding down ctrl. Usually, the user will select images with different bit depths and different pixel sizes for testing as needed, and then click the load button to start loading the image frame to start the data loading process. If you need to load more images, you can continue to select images and execute the loading command. The system provides an intuitive progress bar to show the loading progress of each image. After the loading is completed, the system can configure the sending parameters, such as the sending speed, whether to send continuously, whether to send all, and the sending interval. After configuration, the user can start the sending process, at which point the FPGA will process the image frame data and achieve high-speed communication with the onboard image processing system to be tested through an external interface. In addition, the system also allows the user to monitor the data transmission status in real time during the sending process to ensure the stability and reliability of data transmission.

[0117] The flowchart of the host computer realizing the loading function of the present invention is as follows Figure 3 As shown. The graphical user interface runs in the main thread. When the user clicks the start loading button, the loading thread will be started and the loading behavior will be performed in this thread. In the loading thread, first open the image file to be loaded, calculate the space occupied by a whole frame according to the image information, and allocate space for it. In the allocated space, first add the frame header, including the synchronization frame header, image information header, and frame header check, then add the image data. If the image bit depth is greater than 8bit, it will be divided into 2 bytes for storage, and finally add the frame tail, which is the image check. Then the host computer will initiate the DMA transfer of the h2c channel and send the frame data to the external storage management unit of the FPGA. At the same time, configure the control register to indicate that a load has been initiated and the check has started. Configure the size register and address register to indicate the size and address of the check. And read the corresponding fields of the load send register to refresh the loading status and check status in real time. If there are still images to be loaded, return to the beginning to open the image file. If all images have been sent, end the loading thread.

[0118] The flow chart of the host computer realizing the sending function of the present invention is as follows Figure 4As shown. After the user configures the sending parameters through the graphical user interface of the main thread and clicks Send, the sending thread will be started. In the sending thread, the send_en field of the size register, address register, and control register will be configured, and the FPGA will start to execute the sending function. When sending, the send_prog field of the load sending register will be read to obtain the sending status, and the status refresh display of the main interface will be realized by the Qt signal and slot mechanism. When the sending is completed, the sending thread ends.

[0119] The flowchart of the host computer realizing the receiving function of the present invention is as follows Figure 5 As shown. Click the Enable Receive button on the main interface to enable reception and start the receive thread at the same time. In the receive thread, the recv_en field of the control register is first configured, and then the loop body is started to detect whether the end flag is set. If it is not set, the recv_block_flag field of the receive status register is read. If a receive block is full, a DMA request for the c2h channel will be initiated to read the data of the corresponding block. After the reading is completed, the corresponding bit of the recv_fetch_flag field of the control register is set, and then the block data is written to the file, and the loop body is returned again to determine the end flag. If the end flag is set, it means that the user clicks the End Receive button on the main interface. At this time, the recv_block_last_bytes field of the receive status register will be read to know how much data has been stored in the last block, and a DMA request for the c2h channel will be initiated, and the data of the last block will be written to the file. The receive thread is closed and a reception is completed.

[0120] The configuration control register group of the present invention is defined as shown in Table 1. It includes six 32-bit registers: control register, address register, size register, peripheral register, load transmission status register and receiving status register.

[0121] Table 1 Control register group definition

[0122]

[0123]

[0124] The block diagram of the verification unit in the FPGA design of the present invention is as follows Figure 6As shown. After receiving the check_en synchronization enable, the functional unit will enter the frame synchronization header check phase. At this time, the tready signal of the AXIS channel will be pulled high, and the frame data of the AXIS channel will be read through the handshake of the tvalid and tready signals. After the defined synchronization header is detected, the image header is detected, and each byte is accumulated to obtain the cumulative sum, and compared with the incoming header cumulative sum. If the comparison is correct, the image data is accumulated and summed, and finally compared with the frame end check. If both are correct, it means that the check is successful, and the check result returns 00. There may be a situation where the check fails. If the synchronization header is not detected, the error code is 01; if the frame header check fails, the error code is 10; if the frame end check fails, the error code is 11.

[0125] The block diagram of the parallel-to-serial conversion unit in the FPGA design of the present invention is as follows: Figure 7 As shown. After receiving the send_en synchronization enable, the unit will register size and enter the SEND state. The 128-bit frame data is first converted to the tx_clk clock domain, and then seamlessly read through the two 8-bit registers tx_buf_0 and tx_buf_1, and then converted to serial output. Among them, tx_buf_0 and tx_buf_1 implement ping-pong operation to ensure the continuity and efficiency of data transmission. When the sent byte reaches the count, it will stop sending and generate a done signal to notify the FPGA that the sending is completed.

[0126] The block diagram of the serial-to-parallel conversion unit in the FPGA design of the present invention is as follows: Figure 8 As shown in the figure. After receiving the recv_en synchronization enable, the unit starts to process the serial input data in parallel. In the rx_clk clock domain, the serial single-bit data is converted into byte data, and the AXIS data with a bit width of 128 bits is merged. The corresponding auxiliary signals such as tkeep and tlast are reasonably given to ensure the validity of the data and the integrity of the transmission.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A satellite image data simulation source system, used to provide test image data for a satellite image processing system, characterized in that: include: It includes a storage register module based on FPGA and an analog image processing module deployed on the host computer; The storage module is used to receive and store the image frame data generated by the image processing module and provide it to the onboard image processing system; it is also used to feed back the return data of the onboard image processing system to the analog image processing module; The image processing module is used to provide a graphical user interface, receive user instructions to manage the image source database, assemble frames to generate image frame data and transmit them to the FPGA; and is also used to receive return data from the satellite-borne image processing system transmitted via the FPGA.

2. The satellite-borne image data simulation source system according to claim 1, characterized in that: The FPGA and the host computer communicate through the PCIe high-speed channel, using a PCIe to Thunderbolt 4 adapter board.

3. The satellite-borne image data simulation source system according to claim 1, characterized in that: The storage register module includes: a configuration control register group, a check unit, an external memory management unit, a transmission clock control unit, a parallel-to-serial conversion unit and a serial-to-parallel conversion unit; wherein, The configuration control register group is used to realize the control of the FPGA by the host computer and the function of the FPGA returning the working status to the host computer, including control registers, address registers, size registers, peripheral registers, load and send status registers and receive status registers; The verification unit is used to verify the data integrity and correctness of the loading process, start the work through the specific field of the control register, perform synchronization header verification, instruction verification and data verification on the input data, and store the verification result in the specific field of the receiving status register; The external memory management unit is used to realize efficient reading and writing of the external SDRAM memory, provide an SRAM memory read and write interface to other modules, and realize writing of specified size data from the logical area to the specified address of the memory and reading of specified size data from the specified address of the memory to the logical area through the control of the control register, the address register and the size register; The sending clock control unit is used to generate and select a clock of a corresponding frequency as a sending clock according to a specific field of the control register; The parallel-to-serial conversion unit is used to receive data from the external memory management unit, and use the transmission clock selected by the transmission clock control unit to convert the parallel data into serial data and output it to the external interface of the FPGA board; The serial-to-parallel conversion unit is used to convert serial data received by the external interface of the FPGA board into parallel data according to the enable flag of the control register, and transmit it to the external storage management unit in bytes.

4. The satellite-borne image data simulation source system according to claim 3, characterized in that: The control register, address register, size register and peripheral register support read and write operations, and the load send status register and receive status register only support read operations.

5. The satellite-borne image data simulation source system according to claim 3, characterized in that: The image processing module includes: a system control function unit, an image source database management unit, a loading function unit, a sending function unit and a receiving function unit, wherein: The system control functional unit is used to monitor the system status by acquiring the system status field of the control register of the FPGA, to monitor the link status by acquiring the link status information of the PCIe high-speed channel, and to uniformly reset and initialize the image processing module and the FPGA; The image source database management unit is used to index and call the local image set, to implement image preview according to image size information and bit depth information, and to perform image enhancement; The loading function unit is used to implement image data framing, memory management, and frame loading verification according to user loading instructions, and send the processed image frames to the FPGA; The sending function unit is used to configure the sending instruction and the sending parameters to the FPGA according to the user sending instruction; The receiving function unit is used to receive the data returned by the FPGA according to the user's receiving instruction, store and display it.

6. The satellite-borne image data simulation source system according to claim 5, characterized in that: The processing of the loading functional unit includes: Step 1) Start the loading thread; Step 2) Parse the user loading instruction and open the image to be loaded; Step 3) Allocate frame space according to image information and frame format, add frame header, image data and frame footer in sequence, frame the image data to be loaded, and use memory management to allocate memory addresses, and transfer the image frame data to the external SDRAM memory of FPGA through DMA of h2c channel; Step 4) configure the control register, size register and address register of the FPGA; Step 5) verifying the image frame and synchronously feeding back the verification result to the graphical user interface; Go to step 2) until all the images to be loaded are transferred and the loading thread ends.

7. The satellite-borne image data simulation source system according to claim 6, characterized in that: The frame header in the frame format includes: an 8-byte synchronization header, a 2-byte image width, a 2-byte image height, a 2-byte image bit depth, a 4-byte image occupied byte and a 2-byte frame header check; The number of bytes occupied by image data is determined by the actual amount of image data; The end of the frame is a 2-byte data check, which is calculated by adding up each byte of the image data to obtain the cumulative sum.

8. The satellite-borne image data simulation source system according to claim 5, characterized in that: The processing process of the receiving functional unit includes: Step 1) Start the receiving thread; Step 2) configure the control register; Step 3) detects whether the end flag is set, if it is set, go to step 5); if it is not set, read the receive status register; determine whether the receive block is full, if it is not, go to step 3), otherwise, go to step 4); Step 4) initiate a DMA request for the c2h channel to read the data of the corresponding block. After the reading is completed, set the corresponding bit of the control register, write the block data into the file, and go to step 3); Step 5) Read the receiving status register, obtain the amount of data stored in the last block, initiate a DMA request for the c2h channel, write the data of the last block to the file, close the receiving thread, and complete a reception.

9. The satellite-borne image data simulation source system according to claim 1, characterized in that: The graphical user interface comprises: The system control area is used to start, stop and monitor the status of the system, provide a debugging function entry, and realize direct reading and writing of the configuration control register group; The image source database tab is used to configure and manage various image source data, provide real-time image preview and parameter adjustment, provide an image loading function configuration parameter interface, and provide an image loading function interface; The sending and receiving function tab is used to browse the loaded image list, provide a sending parameter configuration interface, a sending function entry, and a sending status display, as well as provide a receiving function entry, a receiving status display, and a quick view of received files; and The log area is used to display detailed log information during system operation and implement the log file saving and recording function.

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