Data processing method, device, system, equipment, medium and program product

Abstract

The invention provides a data processing method, device and system, equipment, a medium and a program product. The data processing method comprises the steps that under the condition that a trigger event occurs, a first tensor processor sends first data to a second tensor processor based on a preset rule, and the preset rule is used for indicating a destination address of the first data; and after the first data is sent, setting the value of the flag bit in the second tensor processor as a first value to indicate that the first data is sent completely. In the application, the first tensor processor and the second tensor processor directly read the value of the flag bit to obtain whether the opposite side finishes sending or receiving the data, so that the communication delay can be reduced, and the performance and the stability of the data processing system are improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data processing method, device, system, equipment, medium and program product. Background Art

[0002] In a distributed data processing system, a main control processor is connected to multiple tensor processing units (TPUs), and the main control processor controls data communication between the multiple TPUs to perform distributed communication tasks.

[0003] Usually, the master processor first sends a data communication instruction to each TPU, and the data communication instruction may include the sender and receiver of the communication data, as well as the storage address and length of the communication data. Then each TPU performs a communication task based on the data communication instruction, for example, TPU1 sends data to TPU2. When the TPU completes the communication task, it will send an interrupt signal to the master processor to allow the master processor to confirm that the communication task of the TPU has been completed, so that the next step can be performed. However, due to the heavy load of the master processor, it may control data communication between multiple TPUs at the same time, so it may also receive interrupt signals sent by multiple TPUs at the same time. Since multiple TPUs may send interrupt signals to the master processor at the same time, there will be a certain delay in the master processor receiving the interrupt signal, which will lead to poor performance and instability of the data processing system. Summary of the invention

[0004] The present application provides a data processing method, apparatus, system, device, medium and program product, which can reduce communication delay and improve the performance and stability of the data processing system.

[0005] In a first aspect, the present application provides a data processing method executed by a first tensor processor, the method comprising: when a triggering event occurs, sending first data to a second tensor processor based on preset rules, the preset rules are used to indicate the destination address of the first data; after the first data is sent, the value of a flag bit in the second tensor processor is set to a first value to indicate that the first data is sent.

[0006] In some possible implementations, when a trigger event occurs, first data is sent to a second tensor processor, including: when the trigger event occurs, obtaining the value of a flag bit; when the value of the flag bit is a second value, sending the first data to the second tensor processor, the second value being used to indicate that the second tensor processor can receive the first data sent by the first tensor processor.

[0007] In some possible implementations, sending first data to a second tensor processor includes: reading the first data from a first memory of the first tensor processor, the first memory storing data to be sent by the first tensor processor; and sending the first data to a destination address of the second tensor processor.

[0008] In some possible implementations, after the first data is sent, the value of the flag in the second tensor processor is set to the first value to indicate that the first data is sent, including: after the first data is sent, the first value is written to the first address of the first tensor processor, the first address corresponds to the second address of the flag memory storing the flag; by synchronizing the first address with the second address, the first value is written to the second address so that the value of the flag is set to the first value.

[0009] In some possible implementations, after setting the value of a flag bit in the second tensor processor to the first value, the method further includes: obtaining the value of the flag bit; and when the value of the flag bit is the second value, determining that the second tensor processor has received the first data.

[0010] In some possible implementations, when a triggering event occurs, sending first data to a second tensor processor based on preset rules includes: receiving a communication instruction sent by a master processor, the communication instruction being used to instruct the first tensor processor to perform a communication task; and sending the first data to the second tensor processor based on preset rules.

[0011] In some possible implementations, when a triggering event occurs, sending first data to a second tensor processor based on preset rules includes: receiving the first data sent by a third tensor processor, where the third tensor processor is a processor of a previous node; and sending the first data to the second tensor processor based on preset rules.

[0012] In a second aspect, the present application provides a data processing method executed by a second tensor processor, the method comprising: receiving a communication instruction sent by a main control processor, the communication instruction being used to instruct the second tensor processor to perform a communication task; receiving first data sent by a first tensor processor; after the first data is received, setting the value of a flag bit to a second value to indicate that the first data reception is completed.

[0013] In some possible implementations, after the first data is received, the value of the flag is set to a second value, including: after the first data is received, the first value of the flag is set to the second value, the first value is set by the first tensor processor, and the first value is used to indicate that the first data has been sent.

[0014] In some possible implementations, before receiving the first data sent by the first tensor processor, the method also includes: after receiving the communication instruction, setting the value of the flag bit to a second value, the second value being used to indicate that the second tensor processor can receive the first data sent by the first tensor processor.

[0015] In a third aspect, the present application provides a data processing system, which includes a main control processor, a first tensor processor and a second tensor processor; the main control processor is used to send communication instructions to the first tensor processor and the second tensor processor, and the communication instructions are used to instruct the first tensor processor and the second tensor processor to perform communication tasks; the first tensor processor is used to execute the steps in the data processing method of the first aspect; the second tensor processor is used to execute the steps in the data processing method of the second aspect.

[0016] In a fourth aspect, the present application provides a data processing device, which includes: a sending module, used to send first data to a second tensor processor based on preset rules when a trigger event occurs, and the preset rules are used to indicate the destination address of the first data; a first processing module, used to set the value of a flag bit in the second tensor processor to a first value after the first data is sent, to indicate that the first data sending is completed.

[0017] In a fifth aspect, the present application provides a data processing device, which includes: a first receiving module, used to receive a communication instruction sent by a main control processor, the communication instruction is used to instruct a second tensor processor to perform a communication task; a second receiving module, used to receive first data sent by the first tensor processor; and a second processing module, used to set the value of a flag bit to a second value after the first data is received to indicate that the first data reception is completed.

[0018] In a sixth aspect, the present application provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, and the processor implements the steps in the above-mentioned data processing method when executing the program.

[0019] In a seventh aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps in the above-mentioned data processing method when executed.

[0020] In an eighth aspect, the present application provides a computer program product, comprising a non-transitory computer-readable storage medium storing a computer program, wherein the computer program implements the steps in the above-mentioned data processing method when executed.

[0021] Compared with the prior art, the technical solution provided by this application has the following beneficial effects:

[0022] In an embodiment of the present application, when a trigger event occurs, the first tensor processor first sends the first data to the second tensor processor based on the destination address of the first data indicated by a preset rule. After the first data is sent, the value of the flag bit in the second tensor processor is set to the first value, so that the second tensor processor determines that the first data is sent based on the first value. In this way, when the first tensor processor and the second tensor processor are communicating data, only the tensor processors of both parties need to modify the value of the flag bit in the receiver when the data is sent or received. The tensor processor of the other party can confirm that the data is sent or received based on the modified value. In this way, the completion of data sending or receiving does not need to notify the main control processor, and there is no delay caused by the main control processor receiving the interrupt task. This can reduce communication delays and improve system performance and stability.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] Figure 1 It is a schematic diagram of the architecture of a data processing system provided in an embodiment of the present application;

[0026] Figure 2 This is a schematic diagram of an implementation flow of the data processing method provided in an embodiment of the present application;

[0027] Figure 3 This is a schematic diagram of data transmission provided by an embodiment of the present application;

[0028] Figure 4 This is another implementation flow diagram of the data processing method provided in the embodiment of the present application;

[0029] Figure 5 This is another implementation flow diagram of the data processing method provided in the embodiment of the present application;

[0030] Figure 6 This is another implementation flow diagram of the data processing method provided in the embodiment of the present application;

[0031] Figure 7 This is another implementation flow diagram of the data processing method provided in the embodiment of the present application;

[0032] Figure 8 It is a schematic diagram of a structure of a data processing device provided in an embodiment of the present application;

[0033] Fig. 9 It is another schematic diagram of the composition structure of the data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples consistent with some aspects of the present application as detailed in the attached claims.

[0035] Before explaining the data processing method provided in the embodiment of the present application in detail, the application scenario of the embodiment of the present application is first introduced.

[0036] In a complex and efficient distributed data processing system, the master processor, as the central nervous system of the entire data processing system, plays a key role in coordinating and monitoring data exchange between various TPUs. However, with the expansion of the scale of data processing systems and the surge in communication needs, the challenges faced by the master processor are becoming increasingly severe. In particular, when it is necessary to manage real-time data communication between multiple TPUs at the same time, the load pressure on the master processor increases significantly, which not only tests its processing power and efficiency, but is also directly related to the response speed and stability of the entire system.

[0037] At present, although the process of the main control processor distributing data communication instructions to each TPU is highly automated and accurate, the subsequent interrupt signal management mechanism has become a potential bottleneck. After completing the communication task assigned to it, each TPU will immediately send an interrupt signal to the main control processor to report the task completion status and request the next instruction. However, when multiple TPUs complete their tasks and send interrupts almost at the same time, the interrupt processing queue of the main control processor will quickly fill up, resulting in the so-called "interrupt storm" phenomenon. This phenomenon not only causes the main control processor to delay in processing interrupt requests, but also may cause additional context switching overhead due to resource competition, thereby affecting the timely response to subsequent interrupt requests. This delay not only delays the overall operating efficiency of the system, but may also introduce data consistency problems due to the disorder of communication timing, reducing the reliability and stability of the data processing system. More seriously, long-term delay accumulation and error accumulation may cause the data processing system to enter an unstable state, or even cause service interruption, which will have a serious impact on the business that relies on the data processing system for data processing and analysis.

[0038] To solve the above problems, an embodiment of the present application provides a data processing method, which sets a flag at the receiving party. After the tensor processors of both parties complete the communication task, they modify the value of the flag to notify the other party that the communication task is completed. This can reduce the dependence on the main control processor, reduce communication delays, and improve system performance and stability.

[0039] In some embodiments, the above data processing method can be applied to a data processing system. The data processing system includes a master processor and multiple TPUs. In one example, Figure 1 Schematic diagram of a data processing system provided in an embodiment of the present application. Figure 1 The data processing system includes a main control processor 100 and TPU200-1, TPU200-2...TPU200-n, where n is an integer. The main control processor 100 is used to send communication instructions to TPU200-1, TPU200-2...TPU200-n, and the communication instructions are used to instruct each TPU to perform a communication task. TPU200-1, TPU200-2...TPU200-n are used to autonomously initiate communication instructions to complete the transmission task of communication data.

[0040] In some embodiments, when TPU200-1 and TPU200-2 perform data communication, and TPU200-1 acts as a data sender and TPU200-2 acts as a data receiver, TPU200-1 is used to send first data to TPU200-2 based on the destination address of the first data indicated by a preset rule after receiving a communication instruction to perform a communication task sent by the master processor, and after the first data is sent, the value of the flag bit in TPU200-2 is set to the first value, so that TPU200-2 determines that TPU200-1 has completed sending the first data based on the first value. TPU200-2 is used to receive the first data sent by TPU200-1 after receiving a communication instruction to perform a communication task sent by the master processor, and after the first data is received, the value of the flag bit is set to the second value, so that TPU200-1 determines that TPU200-2 has received the first data based on the second value. Among them, the process of TPU200-1 and TPU200-2 performing corresponding operations will be described in detail later, and will not be repeated here.

[0041] In some embodiments, when TPU200-1, TPU200-2 and TPU200-3 perform data communication and TPU200-1 is determined as a data sender, TPU200-2 as a data transferor and TPU200-3 as a data receiver based on preset rules, TPU200-1 is used to send first data to TPU200-2 after receiving a communication instruction to perform a communication task sent by a master processor, and after the first data is sent, the value of a flag bit in TPU200-2 is set to a first value so that TPU200-2 determines that TPU200-1 has completed sending the first data based on the first value. TPU200-2 is used to receive the first data sent by TPU200-1, and after the first data is received, the value of the flag bit is set to a second value so that TPU200-1 determines that TPU200-2 has received the first data based on the second value. Moreover, after receiving the first data, TPU200-2 sends the first data to TPU200-3, and after the first data is sent, the value of the flag bit in TPU200-3 is set to the first value, so that TPU200-3 determines that TPU200-2 has completed sending the first data based on the first value. TPU200-3 is used to receive the first data sent by TPU200-2, and after the first data is received, the value of the flag bit is set to the second value, so that TPU200-2 determines that TPU200-3 has received the first data based on the second value. Among them, the process of TPU200-1, TPU200-2 and TPU200-3 performing corresponding operations will be described in detail later, and will not be repeated here.

[0042] In some embodiments, the main control processor may be a central processing unit (CPU), a neural processing unit (NPU), or other processors.

[0043] Figure 2 This is a schematic diagram of an implementation flow of the data processing method provided by this application. Figure 2 The following description is made by taking the example that the tensor processor includes a first tensor processor (TPU200-1) and a second tensor processor (TPU200-2). Figure 2 As shown, the data processing method includes the following steps.

[0044] Step S201: The master processor sends a communication instruction to the first tensor processor and the second tensor processor.

[0045] In some embodiments, the communication instruction is used to instruct the first tensor processor and the second tensor processor to perform a communication task.

[0046] It is understandable that the data processing system includes multiple tensor processors. When executing a data processing task, data may be transmitted between two tensor processors, or between multiple tensor processors. Therefore, the first tensor processor can be the source sender of the data or the transferor of the data. The second tensor processor is the receiver of the data.

[0047] It can be understood that the distributed communication between processors is a complex communication behavior implemented by stacking together multiple communication instructions. The master processor initiates different communication instructions to each tensor processor, and the communication instruction may include the sender and receiver of the communication data, as well as the storage address and length of the communication data. After receiving the communication instruction, each tensor processor performs the corresponding task based on the communication instruction. However, this places a large load on the master processor and may cause the communication system to be unstable. Therefore, the master processor in the embodiment of the present application only sends an identical communication instruction to each tensor processor, and the communication instruction is used to instruct each tensor processor to perform a communication task.

[0048] Step S202: The first tensor processor and the second tensor processor receive a communication instruction.

[0049] It can be understood that after receiving the data processing instruction, each tensor processor can autonomously start executing the distributed communication task.

[0050] In some embodiments, a data transmission rule (preset rule) can be pre-set, and the data transmission rule may include the execution order of each tensor processor when transmitting data, that is, the transmission address of the data. Each tensor processor can generate a routing table based on the data transmission rule when running, and then each tensor processor transmits data based on the routing table. Among them, the routing table is an information library used in a network device to determine the data forwarding path, and the routing table may include information such as the destination address, next hop address, metric value, and routing source of the data. In this way, after receiving the data, a tensor processor can forward the data to the next node according to the next hop address in the locally generated routing table.

[0051] Step S203: Based on a preset rule, the first tensor processor sends the first data to the second tensor processor.

[0052] It is understandable that a tensor processor is a processor designed for deep learning and other types of tensor calculations. Tensor processors are widely used to accelerate the training and reasoning of machine learning models. Therefore, the first data communicated by the tensor processor is the data required in the training and reasoning process of the machine learning model. For example, the first data may include model parameters, gradient information, weights, activation values, control information and other data.

[0053] In some embodiments, when the first tensor processor acts as the source sender of the first data, after receiving the communication instruction, the first tensor processor can determine the recipient of the first data based on the next hop address in the local routing table generated by preset rules, thereby sending the first data to the second tensor processor.

[0054] In some embodiments, after receiving the communication instruction sent by the master processor, the first tensor processor can start to perform the communication task. The first tensor processor can prepare the first data to be sent. For example, the first tensor processor can retrieve the first data from the internal storage or cache and send the first data to the second tensor processor.

[0055] In some embodiments, when the first tensor processor acts as a transit party for the first data, after receiving the communication instruction, when the first tensor processor receives the first data sent by the third tensor processor, it can determine the recipient of the first data based on the next hop address in the local routing table generated based on preset rules, thereby sending the first data to the second tensor processor, and the third tensor processor is the tensor processor of the previous node.

[0056] It can be understood that when the first tensor processor acts as an intermediate tensor processor, the source of the first data should be sent by the tensor processor located at the node above the first tensor processor. Therefore, in this case, after the first tensor processor receives the first data sent by the tensor processor of the previous node, it can send the first data to the tensor processor of the next node, that is, the second tensor processor.

[0057] In some embodiments, each tensor processor may perform preparation operations for data transmission after receiving a data processing instruction sent by the master processor. Exemplarily, the tensor processor as the data sender may prepare the data to be sent and configure the hardware unit for data transmission, and the tensor processor as the data receiver may set a flag on its end, and the value of the flag is used to indicate the state of the tensor processor. For example, a flag value of 0 (second value) indicates that the tensor processor can receive data, and a flag value of 1 (first value) indicates that the tensor processor cannot receive data. After setting the indicative meaning of different values ​​of the flag, the second tensor processor may send the indicative meaning to the first tensor processor to determine data synchronization with the first tensor processor based on the value of the flag.

[0058] In some embodiments, after receiving the communication instruction, the second tensor processor may set the value of the flag bit to a second value, and the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor, corresponding to step S2021. In this way, when the first tensor processor obtains that the value of the flag bit is the second value, the first data can be sent to the second tensor processor.

[0059] In some embodiments, when a trigger event occurs, the first tensor processor can also obtain the value of a flag bit; when the value of the flag bit is a second value, the first data is sent to the second tensor processor, and the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor. When the first tensor processor acts as the source sender of the first data, the trigger event is the event that the first tensor processor receives a communication instruction. When the first tensor processor acts as the transitor of the first data, the trigger event is the event that the first tensor processor receives the first data sent by the tensor processor of the previous node.

[0060] It is understandable that the first tensor processor can determine whether the second tensor processor can receive the first data sent by the first tensor processor by obtaining the value of the flag bit. After determining that the second tensor processor can receive the first data sent by the first tensor processor based on the value of the flag bit, the first data to be sent can be sent to the second tensor processor across the chip through the configured hardware unit.

[0061] In some embodiments, a certain address in the data sender can be pre-set to correspond to the address of the flag memory storing the flag in the data receiver, that is, different addresses on the two tensor processors correspond to each other. Exemplarily, the first address in the first tensor processor can be pre-set to correspond to the second address of the flag memory storing the flag in the second tensor processor. In this way, the first tensor processor can obtain the value of the flag by accessing its first address. If the value of the flag set by the second tensor processor is the first value, it indicates that the second tensor processor cannot receive the first data sent by the first tensor processor, and the value of the flag is the second value, it indicates that the second tensor processor can receive the first data sent by the first tensor processor. In this way, when the value of the flag is obtained as the first value, the first tensor processor can determine that the second tensor processor may be in a busy state and cannot receive new data. At this time, the first tensor processor can continue to obtain the value of the flag, and when the value of the flag is obtained as the second value, it is determined that the second tensor processor can receive the first data sent by the first tensor processor at this time, and then the first tensor processor can send the first data to the second tensor processor.

[0062] In some embodiments, the implementation process of the first tensor processor sending the first data to the second tensor processor in step S203 can be: reading the first data from the first memory of the first tensor processor, where the first memory stores the data to be sent by the first tensor processor; and sending the first data to the destination address of the second tensor processor.

[0063] It can be understood that the first tensor processor can first obtain the first data from the first memory storing the data to be sent, and then send the first data to the destination address of the second tensor processor. Exemplarily, the first tensor processor can send a data read request to the first memory, and the data read request carries information indicating the first data. After the first memory receives the data read request, it can return the first data to the first tensor processor. Then the first tensor processor sends the received first data to the memory address of the second tensor processor or a specific data receiving interface through the data processing mechanism. The data processing mechanism may include a system bus, a peripheral component interconnect express (PCIe) bus, a network interface and other mechanisms.

[0064] In some embodiments, after receiving the first data, the first tensor processor may also perform preprocessing operations on the first data before sending it to the second tensor processor to ensure the integrity and security of the first data to be sent. Exemplarily, the first tensor processor may perform formatting or encoding operations on the first data, and further, may perform operations such as compression or encryption on the first data.

[0065] In some embodiments, the first tensor processor may read the first data from the first memory through an address access unit; and send the first data to a destination address of the second tensor processor through an address forwarding unit.

[0066] In some embodiments, after receiving the data processing instruction, the first tensor processor as the data sender can configure the hardware units required for data transmission and store the hardware units in registers. Exemplarily, the first tensor processor can configure an address access unit and an address forwarding unit, the address access unit is used to access the first memory of the first tensor processor and read the first data, and the address forwarding unit is used for data forwarding. Exemplarily, the address access unit can be a chip direct memory access (CDMA) unit, and the address forwarding unit can be an address translation unit (ATU) in a PCIe bus, wherein the ATU unit is a key component in the PCIe bus and is responsible for address translation to ensure that data is correctly routed to the target device.

[0067] In one example, after receiving the data processing instruction, the main control unit in the first tensor processor can configure the CDMA unit and the ATU unit in the PCIe bus. Taking the ATU configuration as an example, the main control unit can send a configuration command to the PCIe Switch through the PCIe bus, and the configuration command includes information such as the data source address, the destination address, and the address conversion rule. The ATU unit of the PCIe Switch updates its internal table according to the configuration command to support subsequent data forwarding. After the main control unit completes the configuration of the CDMA unit and the ATU unit, it can obtain the first data from the first memory through the CDMA unit, and then encapsulate the first data according to the PCIe protocol, including adding necessary header information, such as the data destination address, the data source address, the data length, etc. Then the encapsulated first data is sent to the PCIe Switch through the PCIe bus, and the PCIe Switch routes the first data to the destination address of the second tensor processor according to the address conversion rule configured in the ATU unit. Exemplarily, the main control unit in the first tensor processor can be a scalar unit.

[0068] Figure 3 is a schematic diagram of data transmission provided by an embodiment of the present application, such as Figure 3 As shown, after the first tensor processor (TPU0) is configured with the CDMA unit and the ATU unit, the CDMA unit can read the first data from the first memory of TPU200-1, and then send the first data to a temporary storage address (bar) on the master processor, and then forward the first data to the destination address (e.g., the second memory) of the second tensor processor (TPU200-2) through the ATU unit. In some embodiments, the first data may not be sent to the bar on the master processor, but may be directly forwarded to the destination address of the second tensor processor through the ATU unit, which can reduce the participation of the master processor and improve the stability of the system.

[0069] Step S204: After the first data is sent, the first tensor processor sets the value of the flag bit in the second tensor processor to the first value to indicate that the first data is sent.

[0070] In some embodiments, the implementation process of step S204 may be: after the first data is sent, the first tensor processor writes the first value into the first address of the first tensor processor, and the first address corresponds to the second address of the flag memory that stores the flag; by synchronizing the first address with the second address, the first value is written into the second address so that the value of the flag is set to the first value.

[0071] It can be understood that the embodiment of the present application pre-sets the first address in the first tensor processor to correspond to the second address of the flag memory storing the flag in the second tensor processor, so that it can be determined that the two addresses can be logically or physically associated with each other. Therefore, when the first processor writes the first value to the first address, the system can use this address correspondence to synchronize the first value to the second address, so that the value of the flag in the second tensor processor can be updated to the first value, so that the second tensor processor determines that the first data is sent based on the first value.

[0072] Step S205: The second tensor processor receives the first data.

[0073] In some embodiments, after setting the value of the flag bit to the second value, the second tensor processor may continue to obtain the value of the flag bit, and when the value of the flag bit is updated from the second value to the first value, the second tensor processor determines that the first data has been sent. In this way, the second tensor processor can receive the first data so that the first data can be used for subsequent model training and reasoning.

[0074] Step S206: After the first data is received, the second tensor processor sets the value of the flag bit to the second value to indicate that the first data is received.

[0075] It can be understood that after receiving the first data, the second tensor processor can modify the value of the flag bit so that the first tensor processor determines that the second processor has received the first data based on the modified value, thereby achieving data synchronization between the two tensor processors.

[0076] In some embodiments, after setting the value of the flag bit in the second tensor processor to the first value, the first tensor processor obtains the value of the flag bit, corresponding to step S207.

[0077] It can be understood that after setting the value of the flag bit in the second tensor processor to the first value, the first tensor processor can continue to obtain the value of the flag bit to determine whether the second tensor processor has received the first data based on the value of the flag bit.

[0078] In some embodiments, when the value of the flag bit is the second value, the first tensor processor determines that the second tensor processor receives the first data, corresponding to step S208.

[0079] It can be understood that if the first tensor processor obtains that the value of the flag bit is updated from the first value to the second value, the first tensor processor determines that the second tensor processor receives the first data.

[0080] In an embodiment of the present application, the master processor only needs to send a communication instruction to the first tensor processor and the second tensor processor to instruct each tensor processor to start executing a communication task. The first tensor processor can send the first data to the second tensor processor. After the first data is sent, the value of the flag in the second tensor processor is set to the first value, so that the second tensor processor determines that the first data is sent based on the first value. The second tensor processor receives the first data sent by the first tensor processor, and after the first data is sent, the value of the flag is updated from the first value to the second value, so that the first tensor processor determines that the first data is received. In this way, when the first tensor processor and the second tensor processor are communicating data, only the tensor processors of both parties need to modify the value of the flag in the receiving party when the data is sent or received. The tensor processor of the other party can confirm that the data is sent or received based on the modified value. In this way, the completion of data sending or receiving does not need to notify the master processor, and there is no delay caused by the master processor receiving the interrupt task, which can reduce communication delay and improve system performance and stability.

[0081] The above is an example of the interactive operation of each processor in the data operating system to illustrate the data processing method provided by the present application. The following describes the data processing method provided by the present application by taking the first tensor processor as the execution subject.

[0082] Figure 4 is a schematic diagram of an implementation flow of a data processing method provided in an embodiment of the present application, and the data processing method is executed by a first tensor processor. Figure 4 As shown, the method includes step S401 to step S402.

[0083] Step S401: When a triggering event occurs, first data is sent to a second tensor processor based on a preset rule.

[0084] In some embodiments, the preset rule is used to indicate the destination address of the first data.

[0085] In some embodiments, when the first tensor processor is the source sender of data, the implementation process of step S401 may be: receiving a communication instruction sent by the master processor, the communication instruction is used to instruct the first tensor processor to perform a communication task; and sending the first data to the second tensor processor based on preset rules.

[0086] It can be understood that the distributed communication between processors is a complex communication behavior implemented by stacking together multiple communication instructions. The master processor initiates different communication instructions to each tensor processor, and the communication instruction may include the sender and receiver of the communication data, as well as the storage address and length of the communication data. After receiving the communication instruction, each tensor processor performs the corresponding task based on the communication instruction. However, the load of the master processor is large, which may cause the data processing system to be unstable. Therefore, the master processor in the embodiment of the present application only sends an identical communication instruction to each tensor processor, and the communication instruction is used to instruct each tensor processor to perform a communication task. After receiving the communication instruction, each tensor processor can autonomously start to execute the distributed communication task.

[0087] In some embodiments, after receiving the communication instruction sent by the master processor, the first tensor processor determines to start executing the communication task. The first tensor processor can prepare the first data to be sent. For example, the first tensor processor can retrieve the first data from the internal storage or cache, and determine the recipient of the first data based on the next hop address in the local routing table generated by the preset rule, so as to send the first data to the second tensor processor.

[0088] In some embodiments, when a trigger event occurs, the first tensor processor can also obtain the value of a flag bit; when the value of the flag bit is a second value, the first data is sent to the second tensor processor, and the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor.

[0089] In some embodiments, each tensor processor may perform a preparation operation for data transmission after receiving a data processing instruction sent by the master processor. Exemplarily, the tensor processor as the data sender may prepare the data to be sent and configure a hardware unit for data transmission, and the tensor processor as the data receiver may set a flag bit on its end, and the value of the flag bit is used to indicate the state of the tensor processor. For example, the value of the flag bit is 0 (second value) indicating that the tensor processor can receive data, and the value of the flag bit is 1 (first value) indicating that the tensor processor cannot receive data. After setting the indication meaning of different values ​​of the flag bit, the second tensor processor may send the indication meaning to the first tensor processor to determine the synchronization of data with the first tensor processor based on the value of the flag bit. In this way, the first processor may obtain the value of the flag bit to determine whether the second tensor processor can receive the first data sent by the first tensor processor. After determining that the second tensor processor can receive the first data sent by the first tensor processor based on the value of the flag bit, the first data to be sent may be sent to the second tensor processor across the chip through the configured hardware unit.

[0090] In some embodiments, a certain address in the data sender can be pre-set to correspond to the address of the flag memory storing the flag in the data receiver, that is, different addresses on the two tensor processors correspond to each other. Exemplarily, the first address in the first tensor processor can be pre-set to correspond to the second address of the flag memory storing the flag in the second tensor processor. In this way, the first tensor processor can obtain the value of the flag by accessing its first address. If the value of the flag set by the second tensor processor is the first value, it indicates that the second tensor processor cannot receive the first data sent by the first tensor processor, and the value of the flag is the second value, it indicates that the second tensor processor can receive the first data sent by the first tensor processor. In this way, when the value of the flag is obtained to be the first value, the first tensor processor determines that the second tensor processor may be in a busy state and cannot receive new data. At this time, the first tensor processor can continue to obtain the value of the flag, and when the value of the flag is obtained to be the second value, it is determined that the second tensor processor can receive the first data sent by the first tensor processor at this time, and then the first tensor processor can send the first data to the second tensor processor.

[0091] In some embodiments, the implementation process of the first tensor processor sending the first data to the second tensor processor in step S401 may be: reading the first data from the first memory of the first tensor processor, the first memory storing the data to be sent by the first tensor processor; and sending the first data to the destination address of the second tensor processor. The implementation process may refer to the above Figure 1 The relevant contents in step S203 are not repeated here.

[0092] The above is the process of the first tensor processor as the source sender of the first data to perform data transmission. When the first tensor processor performs data transmission as the transit party of the first data, the implementation process of step S401 can be: receiving the first data sent by the third tensor processor, the third tensor processor is the tensor processor of the previous node; sending the first data to the second tensor processor based on a preset rule.

[0093] It can be understood that when the first tensor processor acts as an intermediate tensor processor, the source of the first data should be sent by the tensor processor located at the node above the first tensor processor. Therefore, in this case, after the first tensor processor receives the first data sent by the tensor processor of the previous node, the recipient of the first data can be determined based on the next hop address in the local routing table generated by the preset rules, thereby sending the first data to the tensor processor of the next node, that is, the second tensor processor. Among them, the implementation process of the first tensor processor sending the first data to the second tensor processor can refer to the above-mentioned first tensor processor as the source sender of the first data, and the relevant content of sending the first data to the second tensor processor is not repeated here.

[0094] Step S402: After the first data is sent, the value of the flag bit in the second tensor processor is set to the first value to indicate that the first data is sent.

[0095] In some embodiments, the implementation process of step S402 may be: after the first data is sent, the first value is written into the first address of the first tensor processor, and the first address corresponds to the second address of the flag memory storing the flag; by synchronizing the first address with the second address, the first value is written into the second address so that the value of the flag is set to the first value.

[0096] It is understandable that the embodiment of the present application pre-sets the first address in the first tensor processor to correspond to the second address of the flag memory storing the flag in the second tensor processor, so that it can be determined that the two addresses can be logically or physically associated with each other. Therefore, when the first processor writes the first value to the first address, the system can use this address correspondence to synchronize the first value to the second address, so that the value of the flag in the second tensor processor can be updated to the first value. It is understandable that after the second tensor processor sets the value of the flag to the second value, it can continue to obtain the value of the flag, and when the value of the flag is updated from the second value to the first value, the second tensor processor determines that the first data is sent. In this way, data synchronization can be achieved between the two tensor processors.

[0097] The above is a scheme in which the data sender notifies the data receiver of the completion of data sending in a timely manner. In addition, in the embodiment of the present application, the data receiver can also promptly notify the data sender of the completion of data reception.

[0098] In some embodiments, after setting the value of the flag bit in the second tensor processor to the first value, the first tensor processor may also obtain the value of the flag bit; when the value of the flag bit is the second value, it is determined that the second tensor processor has received the first data.

[0099] It can be understood that after the first tensor processor sets the value of the flag bit in the second tensor processor to the first value, it can continue to obtain the value of the flag bit to determine whether the second tensor processor has received the first data. If the value of the flag bit is updated from the first value to the second value, the first tensor processor determines that the second tensor processor has received the first data. The operation of updating the value of the flag bit to the second value is performed by the second tensor processor.

[0100] In some embodiments, after setting the value of the flag bit to the second value, the second tensor processor may continue to obtain the value of the flag bit. When the value of the flag bit obtained is updated to the first value, the second tensor processor may determine that the first data has been sent. In this way, the second tensor processor may receive the first data, and after the first data is received, the value of the flag bit is modified to the second value to indicate that the second tensor processor has received the first data.

[0101] The above describes a method in which a first tensor processor sends first data to a second tensor processor and notifies the second tensor processor that the first data has been sent. Figure 5 As an example, the above method is further explained.

[0102] Figure 5 is another implementation flow diagram of the data processing method provided in the embodiment of the present application, the method is executed by the first tensor processor, such as Figure 5 As shown, the method includes steps S501 to S507.

[0103] Step S501: when a trigger event occurs, obtain the value of the flag bit;

[0104] Step S502: when the value of the flag bit is the second value, read the first data from the first memory.

[0105] Step S503: Send the first data to the destination address of the second tensor processor based on a preset rule.

[0106] Step S504: after the first data is sent, the first value is written into the first address, and the first address corresponds to the second address of the flag memory storing the flag.

[0107] Step S505: writing the first value into the second address by synchronizing the first address with the second address, so that the value of the flag bit is set to the first value.

[0108] Step S506: Get the value of the flag bit.

[0109] Step S507: when the value of the flag bit is the second value, determine that the second tensor processor receives the first data.

[0110] In an embodiment of the present application, when a trigger event occurs, the first tensor processor sends the first data to the second tensor processor. After the first data is sent, the flag value in the second tensor processor is set to the first value, so that the second tensor processor determines that the first data is sent based on the first value. In this way, when the first tensor processor and the second tensor processor are communicating data, they only need to modify the flag value in the receiving party when the data is sent or received. The tensor processor of the other party can confirm that the data is sent or received based on the modified value. In this way, the completion of data sending or receiving does not need to notify the main control processor, and there is no delay caused by the main control processor receiving the interrupt task. This can reduce communication delays and improve system performance and stability.

[0111] The above is a data processing method introduced with the data sender as the execution subject. The following is an introduction to the data processing method of an embodiment of the present application with the data receiver as the execution subject.

[0112] Figure 6 FIG. 1 is another implementation flow diagram of the data processing method provided in the embodiment of the present application, and the data processing method is executed by the second tensor processor. Figure 6 As shown, the method includes steps S601 to S603.

[0113] Step S601: receiving a communication instruction sent by a main control processor, where the communication instruction is used to instruct the second tensor processor to execute a communication task.

[0114] It can be understood that in a data processing system, when executing a communication task, the main control processor sends an identical communication instruction to each tensor processor, and the communication instruction is used to instruct each tensor processor to execute the communication task. After receiving the communication instruction, each tensor processor can autonomously start to execute the distributed communication task. Therefore, the second tensor processor first receives the communication instruction sent by the main control processor, and then starts to execute the communication task.

[0115] In some embodiments, after receiving the communication instruction, the second tensor processor may set a flag bit on its end, and the value of the flag bit is used to indicate the state of the second tensor processor. After setting the indication meaning of different values ​​of the flag bit, the second tensor processor may send the indication meaning to the first tensor processor to determine data synchronization with the first tensor processor based on the value of the flag bit.

[0116] In some embodiments, the second tensor processor may set the value of the flag bit to a second value, and the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor. In this way, when the first tensor processor obtains that the value of the flag bit is the second value, the first data can be sent to the second tensor processor.

[0117] Step S602: Receive first data sent by a first tensor processor.

[0118] In some embodiments, after setting the value of the flag bit to the second value, the second tensor processor may continue to obtain the value of the flag bit, and when the value of the flag bit is updated from the second value to the first value, the second tensor processor determines that the first data has been sent. In this way, the second tensor processor can receive the first data so that the first data can be used for subsequent model training and reasoning.

[0119] Step S603: After the first data is received, the value of the flag bit is set to a second value to indicate that the first data is received.

[0120] It can be understood that after receiving the first data, the second tensor processor can modify the value of the flag bit so that the first tensor processor determines that the second processor has received the first data based on the modified value, thereby achieving data synchronization between the two tensor processors.

[0121] Below Figure 7 As an example, the above method is further explained.

[0122] Figure 7 is another implementation flow diagram of the data processing method provided in the embodiment of the present application, the method is executed by the second tensor processor, such as Figure 7 As shown, the method includes steps S701 to S704.

[0123] Step S701: receiving a communication instruction sent by a main control processor;

[0124] Step S702: Set the value of the flag bit to a second value to instruct the first tensor processor to send the first data.

[0125] Step S703: Receive first data sent by the first tensor processor.

[0126] Step S704: after the first data is received, the first value of the flag is set to the second value, so that the first tensor processor determines that the first data is received.

[0127] In an embodiment of the present application, the second tensor processor receives a communication instruction sent by the master processor, sets the value of the flag to a second value to instruct the first tensor processor to send the first data, then receives the first data sent by the first tensor processor, and after the first data is sent, updates the value of the flag from the first value to the second value, so that the first tensor processor determines that the first data has been received. In this way, data synchronization can be achieved between the two tensor processors, and the master processor does not need to participate in the data synchronization operation, which can reduce communication delays and improve system performance and stability.

[0128] The present application also provides a data processing device. Figure 8 Schematic diagram of a data processing device provided in an embodiment of the present application. Figure 8 As shown, the data processing device 800 includes: a sending module 801 and a first processing module 802. The sending module 801 is used to send the first data to the second tensor processor based on a preset rule when a trigger event occurs, and the preset rule is used to indicate the destination address of the first data; the first processing module 802 is used to set the value of the flag bit in the second tensor processor to the first value after the first data is sent, so as to indicate that the first data is sent.

[0129] In some possible implementations, the sending module 801 is also used to: obtain the value of a flag bit when a trigger event occurs; and send first data to a second tensor processor when the value of the flag bit is a second value, wherein the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor.

[0130] In some possible implementations, the sending module 801 is further used to: read first data from a first memory of the first tensor processor, where the first memory stores data to be sent by the first tensor processor; and send the first data to a destination address of the second tensor processor.

[0131] In some possible implementations, the first processing module 802 is also used to: after the first data is sent, write the first value into the first address of the first tensor processor, the first address corresponds to the second address of the flag memory that stores the flag; synchronize the first address with the second address, and write the first value into the second address so that the value of the flag is set to the first value.

[0132] In some possible implementations, the device further includes: an acquisition module, configured to acquire a value of a flag bit; and a determination module, configured to determine that the second tensor processor has received the first data when the value of the flag bit is a second value.

[0133] In some possible implementations, the sending module 801 is further used to: receive a communication instruction sent by a main control processor, where the communication instruction is used to instruct the first tensor processor to perform a communication task; and send the first data to the second tensor processor based on a preset rule.

[0134] In some possible implementations, the sending module 801 is further used to: receive first data sent by a third tensor processor, where the third tensor processor is a processor of a previous node; and send the first data to the second tensor processor based on a preset rule.

[0135] The present application also provides a data processing device. Fig. 9 is another structural diagram of the data processing device provided in the embodiment of the present application. Fig. 9 As shown, the data processing device 900 includes: a first receiving module 901, a second receiving module 902, and a second processing module 903. The first receiving module 901 is used to receive a communication instruction sent by the main control processor, and the communication instruction is used to instruct the second tensor processor to perform a communication task; the second receiving module 902 is used to receive the first data sent by the first tensor processor; the second processing module 903 is used to set the value of the flag bit to the second value after the first data is received to indicate that the first data is received.

[0136] In some possible implementations, the second processing module 903 is further used to: after the first data is received, set the first value of the flag to the second value, where the first value is set by the first tensor processor and is used to indicate that the first data has been sent.

[0137] In some possible implementations, the device further includes: a third processing module, configured to set the value of the flag bit to a second value after receiving the communication instruction, wherein the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor.

[0138] The description of the above communication device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the communication device provided in the embodiments of the present disclosure can be used to execute the method described in the above method embodiment. For technical details not disclosed in the communication device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0139] The present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor implements the steps in the above-mentioned data processing method when executing the program.

[0140] The embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, some or all of the steps in the above data processing method are implemented. The computer-readable storage medium can be transient or non-transient.

[0141] The embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, some or all of the steps in the above-mentioned data processing method are implemented. The computer program product can be implemented specifically by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0142] It should be noted that those skilled in the art will readily come up with other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0143] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A data processing method, performed by a first tensor processor, characterized in that: The method comprises: When a trigger event occurs, sending first data to a second tensor processor based on a preset rule, where the preset rule is used to indicate a destination address of the first data; After the first data is sent, the value of the flag bit in the second tensor processor is set to a first value to indicate that the first data is sent.

2. The method according to claim 1, characterized in that The sending of the first data to the second tensor processor when the trigger event occurs includes: When the trigger event occurs, obtaining the value of the flag bit; When the value of the flag bit is a second value, the first data is sent to the second tensor processor, where the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor.

3. The method according to claim 1 or 2, characterized in that: The sending the first data to the second tensor processor includes: Reading the first data from a first memory of the first tensor processor, where the first memory stores data to be sent by the first tensor processor; The first data is sent to a destination address of the second tensor processor.

4. The method according to claim 1, characterized in that: After the first data is sent, setting the value of the flag bit in the second tensor processor to a first value to indicate that the first data is sent, includes: After the first data is sent, the first value is written into a first address of the first tensor processor, where the first address corresponds to a second address of a flag bit memory storing the flag bit; The first value is written into the second address by synchronizing the first address with the second address, so that the value of the flag bit is set to the first value.

5. The method according to claim 4, characterized in that After setting the value of the flag bit in the second tensor processor to the first value, the method further includes: Get the value of the flag bit; When the value of the flag bit is the second value, it is determined that the second tensor processor has received the first data.

6. The method according to claim 1, characterized in that When a trigger event occurs, sending the first data to the second tensor processor based on a preset rule includes: receiving a communication instruction sent by a main control processor, wherein the communication instruction is used to instruct the first tensor processor to perform a communication task; The first data is sent to the second tensor processor based on the preset rule.

7. The method according to claim 1, characterized in that When a trigger event occurs, sending the first data to the second tensor processor based on a preset rule includes: receiving the first data sent by a third tensor processor, where the third tensor processor is a tensor processor of a previous node; The first data is sent to the second tensor processor based on the preset rule.

8. A data processing method, executed by a second tensor processor, characterized in that: The method comprises: receiving a communication instruction sent by a main control processor, wherein the communication instruction is used to instruct the second tensor processor to perform a communication task; receiving first data sent by a first tensor processor; After the first data is received, the value of the flag bit is set to a second value to indicate that the first data is received.

9. The method according to claim 8, characterized in that After the first data is received, setting the value of the flag bit to a second value includes: After the first data is received, the first value of the flag is set to the second value, the first value is set by the first tensor processor, and the first value is used to indicate that the first data is sent.

10. The method according to claim 8, characterized in that Before receiving the first data sent by the first tensor processor, the method further includes: After receiving the communication instruction, the value of the flag bit is set to the second value, where the second value is used to indicate that the second tensor processor can receive the first data sent by the first tensor processor.

11. A data processing system, characterized in that: The data processing system includes a main control processor, a first tensor processor and a second tensor processor; The main control processor is used to send a communication instruction to the first tensor processor and the second tensor processor, and the communication instruction is used to instruct the first tensor processor and the second tensor processor to perform a communication task; The first tensor processor is used to execute the steps in the data processing method according to any one of claims 1 to 7; The second tensor processor is used to execute the steps in the data processing method according to any one of claims 8 to 10.

12. A data processing device, characterized in that: The data processing device comprises: A sending module, configured to send the first data to the second tensor processor based on a preset rule when a triggering event occurs, wherein the preset rule is used to indicate a destination address of the first data; The first processing module is used to set the value of the flag bit in the second tensor processor to a first value after the first data is sent, so as to indicate that the first data is sent.

13. A data processing device, characterized in that: The data processing device comprises: A first receiving module, used to receive a communication instruction sent by a main control processor, wherein the communication instruction is used to instruct the second tensor processor to perform a communication task; A second receiving module, used for receiving first data sent by the first tensor processor; The second processing module is used to set the value of the flag bit to a second value after the first data is received, so as to indicate that the first data is received.

14. A computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, wherein: When the processor executes the program, the steps of the data processing method according to any one of claims 1 to 7 or claims 8 to 10 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the steps in the data processing method according to any one of claims 1 to 7 or claims 8 to 10 are implemented.

16. A computer program product comprising a non-transitory computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed, the steps in the data processing method according to any one of claims 1 to 7 or claims 8 to 10 are implemented.

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