Logic device and system and method for definition and configuration of logic device

Abstract

A method of defining a logic device is provided in which the definition incorporates a definition of a special auxiliary memory cell reserved for presentation of a special code, the signature of the definition incorporated as a whole so as to constitute a watermark that protects the design and possibly other information as a whole. In some embodiments, the special code may incorporate a recursive signature from a previous version of the same device in order to constitute a watermark blockchain. According to the invention, a LUT-based FPGA architecture is proposed having special addressable memory cells reserved for this purpose, in which case the programming bitstream can form the definition according to the method of the invention.

Description

Technical Field

[0001] The present invention relates to logic devices, such as field programmable gate array devices, ASICs and other such devices. Background Art

[0002] FPGA is a type of programmable logic device. They are usually based on standard programmable logic blocks, a large number of which are arranged together to implement various functions.

[0003] Figure 1 An example of an FPGA system known in the art is schematically shown.

[0004] like Figure 1 As shown, the FPGA chip 10 includes several logic blocks 11, such as described above. The chip also includes several input / output ports 12. Connecting these logic blocks 11 and the input / output ports 12 are several tracks 14. Several programmable wiring areas 13 are provided at the junctions of these tracks. In these programmable wiring areas, switches are provided that can selectively connect any pair of intersecting tracks under the control of the logic values ​​stored in the memory cells connected to each switch. The switch memory values ​​are set from the non-volatile memory when the system starts. Accordingly, by setting the values ​​in the switch memory as needed, any connection of any logic block can be coupled to any other logic block or any connection of any input / output port 12. Therefore, by appropriately configuring the memory cells to define each logic block and configuring the switch memory 13 to establish appropriate connections between the logic blocks, any desired function can be achieved.

[0005] Figure 2 Further details of elements of an FPGA system known in the art are shown.

[0006] Figure 2 The components shown in the above description constitute Figure 1 Representative examples of partial implementations of portions of the described functionality.

[0007] As in Figure 2As shown in , a first lookup table (LUT) 21 and a second lookup table (LUT) 22 and several additional LUTs (not shown) are provided. The first LUT 21 includes seven two-input multiplexers 211, 212, 213, 214, 215, 216, 217 respectively. The second LUT and the additional LUTs are configured similarly. These multiplexers are arranged in a cascade manner to have three rows so as to constitute an 8-input multiplexer, and the output of the 8-input multiplexer constitutes the output of the LUT. The first row of multiplexers (211, 213, 215 and 217) in each cascade arrangement has a total of eight inputs. These eight inputs constitute the programming input of the first LUT 21. The selection input of each row is combined together to constitute three data inputs of the LUT. The data input and data output of the first LUT are connected to the track sets 2501, 2502. The inputs and outputs of the second LUT and the additional LUTs are correspondingly connected to the network of the additional tracks (not shown). By convention, a LUT with 3 data inputs in this manner is referred to as "LUT3". Each of the eight programming inputs of the first LUT 21 is connected to a corresponding static RAM memory device 251, 252, 253, 254, 255, 256, 257, 258. The corresponding memory device provides configuration inputs for the second LUT 22 and other LUTs provided in the system (not shown). These are schematically shown as dynamic RAM devices, but static RAM devices may also be included. In operation, these memory devices 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j, 2k, 2l, 2m, 2n, 2o, 2p, 2q, 2r, 2s, 2t, 2u, 2v, 2w, 2x, 2y, 2z provide a constant predetermined logic value to each of the eight programming inputs of each LUT. The contents of each memory cell are schematically shown as comprising a latch constructed of two inverters, each inverter receiving the output of the other inverter, wherein a transistor switch is switched by a word line 23, provided to enable the value at the output of one of the inverters in the latch to be selectively output to a bit line connected to a corresponding configuration input of the LUT 217, and also to a data line 24, by which the value of the latch can be set. The bit line of each memory device 2g, 2h, 2i, 2j, 2k, 2l, 2m, 2n, 2o, 2p, 2q, 2r, 2s, 2t, 2u, 2v, 2w, 2x, 2y, 2z is connected to a row decoder 1a, and the word line of each memory device 251, 252, 253, 254, 255, 256, 257, 258 is connected to a line decoder 1b.During the startup phase of the circuit, each memory device 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j, 2k, 2l, 2m, 2n, 2o, 2p, 2q, 2r, 2s, 2t, 2u, 2v, 2w, 2x, 2y, 2z is addressed in turn and the desired value is set to the latch in question. The logical behavior of the LUT is responsive to any binary value on its three data inputs and can therefore be defined as required. This is the underlying basic concept of FPGA technology. However, it should be understood that the functions that can be implemented by a single logic block including two LUTs 3 are limited, however, by interconnecting several appropriately configured LUTs as described above, any arbitrary combination of functions can be implemented. The interconnection is implemented by programmable interconnection of data channels 2501, 2502 and other channels (not shown) carrying data from other LUTs. As shown, although channel 2501 and channel 2502 are arranged vertically, a further channel 2503 intersecting with channel 2501 and channel 2502 is provided. A programmable switch unit 26 is provided at the intersection of the corresponding lines of channel 2501 and 2503. Considering that the intersection of two lines constitutes a total of four connections of the switch unit, the switch unit includes 6 transistor switches, which are arranged to connect or disconnect the connection between any two of the four connections. Each of these transistor switches is set to open or close by the value received from the corresponding static memory unit 2a, 2b, 2c, 2d, 2e, 2f. In addition, other such programmable switch units (not shown) with corresponding static memory devices are provided at many or all intersections of the track. As shown, these static memory devices 2a, 2b, 2c, 2d, 2e, 2f are identical to the memory devices 2g, 2h, 2i, 2j, 2k, 2l, 2m, 2n, 2o, 2p, 2q, 2r, 2s, 2t, 2u, 2v, 2w, 2x, 2y, 2z and are connected to the decoder matrix 1a, 1b so that during the start-up phase of the circuit both the LUT memory devices and the switch memory devices can be addressed in turn and the desired values ​​set to the latches in question so that the behavior of each LUT and its connection to any other LUT can be configured as required.

[0008] WO2012 / 123243A1, US7463056 Bl, US6021513A, US5432441A, US8091001 B2, US5675589A and US5027355 A describe certain aspects of the foregoing.

[0009] Section 3.22 of the article by Victor Olubunmi Aken'Ova entitled “Bridging the Gap between Soft and Hard eFPGA Design,” available at https: / / www.ece.ubc.ca / ~lemieux / publications / akenova-masc2005.pdf, provides further background information.

[0010] The defined structure is therefore highly flexible and can be reprogrammed and modified at different times and at different levels, such as hardware and software (configuration values), making it difficult to unambiguously determine which configuration version a specific device implements.

[0011] FPGAs and other digital logic devices such as those described above can be defined from the design stage based on a digital representation, known as "intellectual property" (IP), which is used as the basis for an automated manufacturing process for physical devices that implement the design. For example, given different iterations of a design, difficulties may arise in distinguishing one device from another because the devices are based on similar IP.

[0012] It would be desirable to provide a convenient integrated mechanism for distinguishing such devices. Summary of the invention

[0013] According to the content of the present invention, in a first aspect, a computer-implemented method for defining a device capable of realizing a logical function is provided, the device comprising: a memory bus having a corresponding address space; and a plurality of programming memory cells, each programming memory cell being accessible for reading and / or writing via the memory bus using a corresponding address in the address space, wherein the device also comprises a plurality of auxiliary memory cells, each auxiliary memory cell being accessible for reading via the programming memory bus using a corresponding address in the address space, and independent of the corresponding values ​​of the plurality of auxiliary memories, the selection lines and / or outputs of each lookup table are programmably interconnected with the selection lines or outputs of another lookup table.

[0014] The method includes: obtaining a digitally defined checksum value of a logic function; finding a digital value of a predefined length, which, when applied to a packaged checksum value including a digitally defined checksum value of a core function, produces a result that complies with a predefined rule according to a predefined operation; and defining an enhanced digital definition of a device, the enhanced digital definition including the digital definition of the logic function and a definition of one or more auxiliary memory cells reflecting the checksum value.

[0015] In the development of the first aspect, the step of finding a digital value of a predefined length includes: testing consecutive random digital values ​​of a predefined length against predefined rules until a digital value of a predefined length is found: when the digital value of the predefined length is applied to an encapsulated checksum value including a digitally defined checksum value of a core function, according to a predefined operation, it produces a result that complies with the predefined rules.

[0016] In a development of the first aspect, the method comprises the further step of incorporating historical checksums from previous iterations of the method of the first aspect into the encapsulated checksum by a predetermined operation before the step of finding the digital value of the predefined length.

[0017] In a development of the first aspect, the method comprises the further step of encrypting the digital definition of the enhancement to the field programmable gate array.

[0018] In a development of the first aspect, the method comprises the further step of defining a bit stream with respect to the address space such that when the bit stream is loaded into the programming memory, the field programmable gate array implements the defined logic functions.

[0019] In a development of the first aspect, the method comprises the further step of loading the bit stream into a programming memory in order to program the field programmable gate array to implement the defined logic functions.

[0020] According to the present invention, in a second aspect, a method for querying a field programmable gate array according to the first aspect is provided, the query method comprising the following steps: reading the contents of an auxiliary memory unit in a sequence defined according to a storage space.

[0021] In a development of the second aspect, some or all of the programmed memory cells are configured to output their values ​​to one or more shift registers, and wherein the step of reading the contents of the auxiliary memory cells comprises: clocking the one or more shift registers in a predefined sequence to read their contents, wherein the step of reading the contents of the auxiliary memory cells in a sequence defined according to the storage space comprises: interleaving the contents of the auxiliary memory cells with the contents read from the shift registers to achieve a predefined output structure.

[0022] According to the present disclosure, in a third aspect, there is provided a device defined according to the method of the first aspect.

[0023] According to the present invention, in a fourth aspect, there is provided a computer program comprising instructions, wherein when the program is executed by a computer, the instructions cause the computer to perform the method of the first aspect.

[0024] According to the present disclosure, in a fifth aspect, there is provided a computer readable medium storing data for defining a definition according to the method of the first aspect.

[0025] According to the content of the present invention, in a sixth aspect, a field programmable gate array capable of realizing logic functions is provided, the field programmable gate array comprising: a plurality of hardware lookup tables each comprising a plurality of selection lines and / or outputs, a programming memory bus having a corresponding address space, and a plurality of programming memory cells, each programming memory cell being accessible for reading and / or writing via the programming memory bus using a corresponding address in the address space, the selection lines and / or outputs of each lookup table being programmably interconnected with the selection lines or outputs of another lookup table according to corresponding values ​​of the plurality of programming memories.

[0026] The field programmable gate array further comprises a plurality of auxiliary memory cells, each of which is accessible for reading via a programming memory bus using a corresponding address in an address space, and independent of corresponding values ​​of the plurality of auxiliary memories, a selection line and / or output of each lookup table is programmably interconnected with a selection line or output of another lookup table.

[0027] In a development of the sixth aspect, the one or more auxiliary memory units return fixed values ​​defined in hardware.

[0028] In a development of the sixth aspect, the address space is defined by values ​​in two dimensions, and wherein addresses in the address space belong to a contiguous region including minimum values ​​in each dimension of the address space, and / or a contiguous region including maximum values ​​in each dimension of the address space, and one or more auxiliary memory units are accessible via addresses in the address space.

[0029] In a development of the sixth aspect, the one or more auxiliary memory units store the watermark value and the unique identifier or version reference. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other advantages of the present invention will now be described with reference to the accompanying drawings, in which:

[0031] Figure 1 An example of an FPGA system known in the art is schematically shown;

[0032] Figure 2 Further details of elements of an FPGA system known in the art are shown;

[0033] Figure 3 A computer-implemented method of defining a logic device is presented;

[0034] Figure 4 Logic devices suitable for definition according to certain embodiments are presented;

[0035] Figure 5 A logic device suitable for definition according to certain further embodiments is presented; and

[0036] Figure 6 A general purpose computing system suitable for implementing embodiments of the present teachings is shown. DETAILED DESCRIPTION

[0037] By way of example, certain embodiments of the present invention will be presented below in the context of an FPGA architecture. It should be remembered that unless expressly limited to the FPGA context, these embodiments are equally applicable to other types of logic devices, as will become apparent in the following discussion.

[0038] Figure 3 A computer-implemented method of defining a logic device is presented.

[0039] As reference Figure 1 and Figure 2 As described, a logic device may generally be defined with reference to a digital definition of its core functionality, for example, in terms of "IP" as described above.

[0040] In this method development, the method starts at step 3 before proceeding to step 302 of obtaining a digitally defined checksum value for the core functionality. A suitable checksum may be obtained by any suitable algorithm readily apparent to those skilled in the art, such as a parity byte or word, Sum's complement, cyclic redundancy check, or indeed a hashing algorithm such as MD5 or SHA256 hashing.

[0041] Then, the method proceeds to step 303: find a digital value of a predefined length, which, when applied to the checksum value obtained at step 302, produces a result that conforms to a predefined rule. The number can be obtained by continuously generating random numbers until a random number that satisfies the specified condition is found. For example, the predefined length can be an appropriate number of bits, which will become clear from the following discussion and can be equal to or less than the number of auxiliary memory cells provided by the logic device. The rule can be any rule that can be applied to a digital value, such as: "the number must be odd", "the number must be even", "the number must be prime", "the number must be a multiple of some other predefined number", "the digital digits at odd positions must all be odd", "the digital digits at odd positions must all be parity", "a portion of the number can be compared to a predefined string to be true", etc. The rule can include a combination of such requirements.

[0042] In some embodiments, the checksum value obtained at step 303 may be augmented with additional data. For example, the checksum value obtained at step 303 may be augmented with additional data. Figure 4 The historical checksums of previous iterations of the method are incorporated into the checksum value obtained at step 303. The previous checksum is saved on the file, which is also included in the list of encapsulated files of the current checksum being calculated. This creates a chain. In this way, the checksums can be seen to constitute a "blockchain", binding the obtained value not only to its current version, but also to each subsequent version in a series of iterations of the described method.

[0043] The step of finding a digital value of a predefined length can be selectively implemented in the following manner: testing continuous random digital values ​​of a predefined length against predefined rules until a digital value of a predefined length is found: when the digital value of the predefined length is applied to an encapsulated checksum value including a digitally defined checksum value of a core function, according to a predefined operation, produces a result that complies with the predefined rules.

[0044] While embodiments may be directed to the definition of any logic device, certain embodiments may be particularly conveniently applied to programmable devices (e.g., FPGAs as discussed above), where logic functionality is not defined (exclusively) by the device architecture, but rather primarily by a bitstream that may be loaded into the device after fabrication. Embodiments may be directed to the definition of such a bitstream.

[0045] Figure 4 Logic devices suitable for definition according to certain embodiments are presented.

[0046] like Figure 4 As shown, a field programmable gate array 400 is presented. Certain elements of the field programmable gate array 400 correspond to those of the reference Figure 2 Elements of the field programmable gate array 200 are described, and like numbered elements may be considered corresponding and may not be described further. As will be apparent to those skilled in the art, the logic function may be any set of operations consistent with the capabilities of the FPGA architecture.

[0047] As shown, the field programmable gate array 400 includes a plurality of hardware lookup tables 21 each including a plurality of select lines and / or outputs 2501, 2502, 2503, a programming memory bus 1 with a corresponding address space, and a plurality of programming memory cells 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j, 2k, 2l, 2m, 2n, 2o, 2p, 2q, 2r, 2y, each programming memory cell being accessible for reading and / or writing via the programming memory bus 1a, 1b using a corresponding address in the address space. The select lines and / or outputs 2501, 2502, 2503 of each lookup table are programmably interconnected with the select lines or outputs 2501, 2502, 2503 of other lookup tables according to the corresponding values ​​of the plurality of programming memories, for example, by the operation of the memory control of the switch 26.

[0048] At the same time, according to Figure 4 The innovative structure of the field programmable gate array also includes multiple auxiliary memory cells 4a, 4b, 4c, 4d, each of which is accessible for reading via a programming memory bus using a corresponding address in the address space. Independent of the corresponding values ​​of the multiple auxiliary memories, the selection lines and / or outputs of each lookup table are programmably interconnected with the selection lines or outputs of another lookup table, that is, the auxiliary memory cells 4a, 4b, 4c, 4d are addressable in the same address space as the programming memory cells 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j, 2k, 2l, 2m, 2n, 2o, 2p, 2k, 2l, 2m, 2n, 2o, 2p, 2q, 2r, 2y, but do not play a role in configuring the FPGA device, but can still be used for other purposes. In particular, these auxiliary memory cells can be programmed with any arbitrary value that may be needed for future reference, such as a watermark value, a unique identifier, or a version reference. Although in Figure 4 Only four auxiliary memory cells are provided in FIG. 1 , but a practical implementation may include any number of cells that may be required depending on the auxiliary data to be stored.

[0049] therefore, Figure 4 A device capable of implementing logic functions is presented, the device comprising a memory bus having a corresponding address space and a plurality of programming memory cells, each programming memory cell being accessible for reading and / or writing via the memory bus using a corresponding address in the address space, wherein the device also comprises a plurality of auxiliary memory cells, each auxiliary memory cell being accessible for reading via the programming memory bus using a corresponding address in the address space, the selection lines and / or outputs of each lookup table being programmably interconnected with the selection lines or outputs of another lookup table independently of the corresponding values ​​of the plurality of auxiliary memories.

[0050] More specifically, a field programmable gate array capable of implementing logic functions is provided, the field programmable gate array comprising: a plurality of hardware lookup tables each comprising a plurality of selection lines and / or outputs, a programming memory bus having a corresponding address space, and a plurality of programming memory cells, each programming memory cell being accessible for reading and / or writing via the programming memory bus using a corresponding address in the address space, the selection lines and / or outputs of each lookup table being programmably interconnected with the selection lines or outputs of another lookup table according to corresponding values ​​of the plurality of programming memories.

[0051] The field programmable gate array further comprises a plurality of auxiliary memory cells, each of which is accessible for reading via a programming memory bus using a corresponding address in an address space, and independent of corresponding values ​​of the plurality of auxiliary memories, a selection line and / or output of each lookup table is programmably interconnected with a selection line or output of another lookup table.

[0052] In logic devices such as Figure 4 In the case of a programmable device being present, the method may then proceed to optional step 306 of defining a bitstream with respect to an address space of the logic device such that when the bitstream is loaded into a programming memory of the field programmable gate array, the defined logic functions are implemented.

[0053] The method may then proceed to step 307, where the bit stream obtained at step 306 may be loaded into a programming memory of the logic device so as to program the logic device to implement the defined logic function and store a digital value of a predefined length in an auxiliary memory cell of the logic device.

[0054] Figure 5 Logic devices suitable for definition according to certain further embodiments are presented.

[0055] Just with Figure 2 For the same components, Figure 5 Corresponds to Figure 4 At the same time, if Figure 5 As shown, the field programmable gate array includes a plurality of auxiliary memory units 5a, 5b, 5c, 5d. Figure 5 In an embodiment of the invention, each of the auxiliary memory units is configured to return a fixed value defined in hardware. In particular, as shown, instead of including Figure 4Instead of the dynamic RAM circuit shown storing data values ​​in capacitors, the data gates of the memory access transistors of auxiliary memories 5a and 5c are simply tied to the positive voltage rail, while the data gates of the memory access transistors of auxiliary memories 5b and 5d are tied to ground. Accordingly, these particular points can no longer be programmed in the manner of conventional FPGA programming memory, but can still be addressed in the usual manner to retrieve information that was hardwired into the circuit at design time, for example. In particular, these auxiliary memory cells can be programmed with any arbitrary value that may be needed for future reference, such as a watermark value, a unique identifier, or a version reference. Although in Figure 5 Only four auxiliary memory cells are provided in FIG. 1 , but a practical implementation may include any number of cells that may be required depending on the auxiliary data to be stored.

[0056] It will be understood that although Figure 5 An FPGA is presented, but the method of defining "hard-coded" memory addresses can be applied to any type of logic device.

[0057] Figure 5 In addition, latch structures 50a, 50b are provided at the output of each lookup table. Specifically, each of these structures includes a multiplexer that receives the output from the corresponding LUT or the input from the previous latch structure and provides an input to a corresponding D flip-flop, the output of which is provided to the output bus 2501, 2502 and the input of the multiplexer in the next latch structure. Therefore, according to the selection signal sent to each multiplexer, a shift register configuration can be defined, whereby the output of the corresponding LUT can be read out.

[0058] In other types of logic devices, other mechanisms for reading the contents of an auxiliary memory address may be provided.

[0059] It will be appreciated that a combination of both programmable and hardwired auxiliary memory may be provided. Figure 4 and Figure 5 This may be convenient if, for example, the hardware version is stored in a hardwired auxiliary memory and the software configuration of the current FPGA settings is stored in a programmable auxiliary memory.

[0060] like Figure 4 and Figure 5 As shown, the address space is defined by values ​​in two dimensions, i.e. corresponding to rows and columns. It should be understood that other configurations are possible, such as based on a single linear address space. Such a linear address space can be programmable and / or accessible using shift registers, etc.

[0061] When the address space is defined by values ​​in two dimensions, the addresses in the address space can be conveniently defined as belonging to one or more continuous regions including the minimum value in each dimension of the address space and / or the continuous region including the maximum value in each dimension of the address space, and one or more auxiliary memory units are accessible via the addresses in the address space. In other words, the auxiliary memory can be conveniently defined at the edge and still at the corner of the address space matrix. Typical FPGA bitstreams usually avoid these address combinations so that these addresses can be set aside for use as auxiliary memory units, which have minimal impact on the structure of the program bitstream for a given FPGA structure and logic function.

[0062] It will be appreciated that steps 306 and 307 depend on a correct representation of the address space of the logic device to ensure that not only is the logic device actually correctly configured to implement the desired logic function, but also that the required data is loaded into the auxiliary memory unit in the desired order. Figure 4 In the case of the discussed predefined logic device structure providing the substrate for the bitstream, this can be simple. At the same time, according to certain variants, the logic device structure itself can be variable and indeed can be defined according to the data to be loaded into it. This method is particularly relevant to, for example, reference Figure 5 The method described above is consistent with the method described above, in which the auxiliary memory cells are hardwired to specific values, which can be conveniently achieved by appropriate definition of the logic device structure itself. The logic device structure can be defined, for example, in terms of semiconductor "IP", which can be converted into semiconductor masks using conventional industrial practices for manufacturing the corresponding logic device structure.

[0063] On this basis, the method implements step 304, in which an enhanced digital definition of a field programmable gate array is defined, the enhanced digital definition including the digital definition of the core function and the definition of one or more auxiliary memory cells reflecting the digital value of the predefined length. Optionally, the enhanced digital definition of the field programmable gate array obtained at step 304 can be encrypted. Encryption can protect the VHDL code, making its duplication more elusive, and the watermark can prove that the copy is not authentic in the case of a violation. Then a further step 305 of manufacturing a logic device according to the enhanced digital definition can be performed. As shown, these steps can be performed before steps 306 and 307, so that the logic device structure and the underlying address space are formally defined to support the definition and loading of the bitstream. However, it will be understood that because the alternative step 306 can be performed after step 304 or in parallel with step 304, in this case, a specific storage space can be assumed for the generation of the bitstream and then effectively integrated into the final structure, and step 305 can be performed after step 306 or in parallel with step 306.

[0064] The method then terminates at step 310 .

[0065] Therefore, there is provided a computer-implemented method of defining a device capable of implementing a logic function, the device comprising: a memory bus having a corresponding address space, and a plurality of programmed memory cells, each of which is accessible for reading and / or writing via the memory bus using a corresponding address in the address space, wherein the device also comprises a plurality of auxiliary memory cells, each of which is accessible for reading via the programmed memory bus using a corresponding address in the address space, the selection lines and / or outputs of each lookup table being programmably interconnected with the selection lines or outputs of another lookup table independently of the corresponding values ​​of the plurality of auxiliary memories, the method comprising: obtaining a digitally defined checksum value of the logic function; finding a digital value of a predefined length: the digital value of the predefined length, when applied to a packaged checksum value including a digitally defined checksum value of a core function, produces a result that complies with a predefined rule according to a predefined operation; and defining an enhanced digital definition of the device, the enhanced digital definition comprising the digital definition of the logic function and a definition of one or more auxiliary memory cells reflecting the checksum value.

[0066] The logic device so defined provides additional information retrievable from the auxiliary memory unit.Thus, a computer implemented method of querying a logic device may be defined, the method comprising the step of reading the contents of the auxiliary memory unit in a sequence defined according to the memory space.

[0067] It will be understood that although Figure 3 The method is applicable to the definition of any logic device, but it may be particularly conveniently applied to programmable devices, in which case the definition of the logic functions may be limited to the programming bitstream rather than a complete definition of the device architecture. Programmable devices themselves may be particularly suitable for implementing the present invention by providing auxiliary memory cells for the specific purpose of the present invention, or where the underlying architecture itself is defined in an enhanced digital definition, it may explicitly incorporate auxiliary memory cells for this purpose.

[0068] Thus, a method of defining a logic device is provided, wherein the definition incorporates the definition of a special auxiliary memory cell reserved for presenting a special code, a signature of the definition being incorporated as a whole so as to constitute a watermark protecting the design and possibly other information as a whole. In certain embodiments, the special code may be recursively incorporated with signatures from previous versions of the same device to constitute a watermark blockchain. A LUT-based FPGA architecture is proposed, which has special addressable memory cells reserved for this purpose, in which case the programming bitstream may constitute a definition according to the method of the invention.

[0069] In logic devices including such as reference Figure 5 In the case of an output shift register as described, such that some or all of the programmed memory cells are configured to output their values ​​to one or more shift registers, the step of reading the contents of the auxiliary memory cells may include clocking the one or more shift registers in a predefined sequence to read out their contents. In such a context, the step of reading the contents of the auxiliary memory cells in a sequence defined according to the storage space may include interleaving the contents of the auxiliary memory cells (as retrieved by sequential addressing of the storage space as described above) with the contents read from the shift registers to achieve a predefined output structure.

[0070] The disclosed implementations may take the following forms: a fully hardware embodiment (e.g., an FPGA or logic device, such as described above or as Figure 3 ) or as referenced Figure 4 or a completely software embodiment as described in 5 (e.g., implementing Figure 3 The present invention may be implemented in a manner that is consistent with the present invention (e.g., the method described in the description, or other methods presented herein), or an embodiment that includes both hardware and software elements. Software embodiments include, but are not limited to, firmware, resident software, microcode, etc. The present invention may take the form of a computer program product accessible from a computer-usable or computer-readable medium that provides program code for use by or in conjunction with a computer or instruction execution system.

[0071] A computer usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium.

[0072] In some embodiments, the methods and processes described herein may be implemented in whole or in part by a user device. These methods and processes may be implemented by computer applications or services, application programming interfaces (APIs), libraries and / or other computer program products or any combination of such entities.

[0073] The user device may be a mobile device, such as a smartphone or tablet, a computer, or any other device with processing capabilities, such as a robot or other connected device.

[0074] Figure 6 A general purpose computing system suitable for implementing embodiments of the present teachings is shown.

[0075] like Figure 6As shown, the system includes a logic device 601 and a memory device 602. The system may optionally include a display subsystem 611, input subsystems 612, 613, 614, a communication subsystem 620, and / or other components not shown.

[0076] Logic device 601 includes one or more physical devices configured to execute instructions. For example, logic device 601 can be configured to execute instructions that are part of one or more applications, services, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions can be implemented to perform tasks, implement data types, convert the state of one or more components, implement technical effects, or otherwise achieve desired results.

[0077] Logic device 601 may include one or more processors configured to execute software instructions. Additionally or alternatively, the logic device may include one or more hardware or firmware logic devices configured to execute hardware or firmware instructions. The processor of the logic device may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel and / or distributed processing. The various components of logic device 601 may optionally be distributed between two or more separate devices, which may be remotely located and / or configured for coordinated processing. Various aspects of logic device 601 may be virtualized and executed by a remotely accessible networked computing device configured in a cloud computing configuration.

[0078] The memory device 602 includes one or more physical devices configured to hold instructions executable by logic devices to implement the methods and processes described herein. When implementing such methods and processes, the state of the memory device 602 may be changed, for example, to hold different data.

[0079] The storage device 602 may include removable and / or built-in devices. The storage device 602 may include one or more types of storage devices, including optical storage (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), semiconductor storage (e.g., RAM, EPROM, EEPROM, etc.) and / or magnetic storage (e.g., hard disk drive, floppy disk drive, tape drive, MRAM, etc.), etc. The storage device may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location addressable, file addressable and / or content addressable devices.

[0080] In some arrangements, the system may include an interface 603 that is adapted to support communication between the logic device 601 and other system components. For example, additional system components may include removable and / or built-in expansion storage devices. The expansion storage device may include one or more types of storage devices, including optical storage 632 (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), semiconductor memory 433 (e.g., RAM, EPROM, EEPROM, FLASH, etc.) and / or magnetic storage 631 (e.g., hard disk drive, floppy disk drive, tape drive, MRAM, etc.), etc. Such expansion storage devices may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location addressable, file addressable and / or content addressable devices.

[0081] It will be understood that the storage device includes one or more physical devices and does not include the propagation signal itself. However, in contrast to being stored on the storage device, various aspects of the instructions described herein may alternatively be propagated through a communication medium (e.g., electromagnetic signals, optical signals, etc.).

[0082] Aspects of the logic device 601 and the memory device 402 may be integrated together into one or more hardware logic components. For example, such hardware logic components may include field programmable gate arrays (FPGAs), program and application specific integrated circuits (PASIC / ASIC), program and application specific standard products (PSSP / ASSP), systems on chips (SOCs), and complex programmable logic devices (CPLDs).

[0083] The term "program" may be used to describe aspects of a computing system that is implemented to perform a particular function. In some cases, a program may be instantiated via a logic device that executes machine-readable instructions held by a storage device. It will be understood that different modules may be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Likewise, the same program may be instantiated by different applications, services, code blocks, objects, routines, APIs, functions, etc. The term "program" may encompass single or grouped executable files, data files, libraries, drivers, scripts, database records, etc.

[0084] In particular, Figure 6 The system can be used to implement the embodiments of the present invention.

[0085] For example, implementing Figure 5The program of the steps described can be stored in the storage device 602 and executed by the logic device 601. The digital definition, checksum value, checksum supplement and / or enhanced digital definition can be stored in the storage device 602 or the extended storage device 632, 633 or 631. The logic device can determine any or all items in the digital definition, checksum value, checksum supplement and / or enhanced digital definition. When included, the display subsystem 611 can be used to present a visual representation of the data held by the storage device. The visual representation can take the form of a graphical user interface (GUI). The methods and processes described herein change the data held by the storage device 602, and thus transform the state of the storage device 602, and the state of the display subsystem 611 can also be transformed to visually represent the changes in the underlying data. The display subsystem 611 can include one or more display devices using almost any type of technology. Such a display device can be combined with a logic device and / or a storage device in a shared housing, or such a display device can be a peripheral display device. The display 611 and the user interface can be used to support CAD operations for defining digital definitions, etc.

[0086] Therefore, the present invention may be embodied in the form of a computer program.

[0087] It will be understood that a "service" as used herein is an application program executable across multiple user sessions. A service is available to one or more system components, programs, and / or other services. In some implementations, a service may run on one or more server computing devices.

[0088] When included, the input subsystem may include or interface with one or more user input devices, such as a keyboard 612, a mouse 611, a touch screen 611, or a game controller, button, foot switch, etc. (not shown). In some embodiments, the input subsystem may include or interface with selected natural user input (NUI) components. Such components may be integrated or peripheral, and the transduction and / or processing of input actions may be processed on-site or off-site. Example NUI components may include: microphones for speech and / or sound recognition; infrared, color, stereo and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers 660, accelerometers and / or gyroscopes for motion detection and / or intent recognition; and electric field sensing components for assessing brain activity.

[0089] When included, the communication subsystem 620 can be configured to communicatively couple the computing system with one or more other computing devices. For example, the communication module can communicatively couple the computing device to a remote service, for example, hosted on a remote server 676, via a network of any size (including, for example, a personal area network, a local area network, a wide area network, or the Internet). The communication subsystem may include wired and / or wireless communication devices compatible with one or more different communication protocols. As a non-limiting example, the communication subsystem may be configured to communicate via a wireless telephone network 674 or a wired or wireless local area network or a wide area network. In some embodiments, the communication subsystem may allow the computing system to send messages to other devices and / or receive messages from other devices via a network such as the Internet 675. The communication subsystem may additionally support short-range inductive communication 621 with passive devices (NFC, RFID, etc.).

[0090] Figure 6 The system is intended to reflect a wide range of different types of information processing systems. It will be understood that Figure 6 Many of the subsystems and features described are not required for implementation of the present invention, but are included to reflect possible systems in accordance with the present invention. It will be understood that system architectures vary widely, and Figure 6 The relationship between the different subsystems of the system is only schematic and may vary in layout and distribution of roles in the system. It will be appreciated that in practice the system may incorporate Figure 6 Different subsets of the various features and subsystems described.

[0091] It will be appreciated that the configuration and / or method described herein is exemplary in nature, and these specific embodiments or examples should not be considered restrictive, as many variations are possible. The specific routine or method described herein can represent one or more strategies in any number of processing strategies. Therefore, the various actions shown and / or described can be performed in the order shown and / or described, performed in other orders, performed in parallel, or omitted. Equally, the order of the above process can be changed.

[0092] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. A computer-implemented method of defining a device capable of implementing a logic function, the device comprising a memory bus having a corresponding address space and a plurality of programming memory cells, each of the programming memory cells being accessible for reading and / or writing via the memory bus using a corresponding address in the address space, wherein: The device further comprises a plurality of auxiliary memory cells, each of the auxiliary memory cells being accessible for reading via the programming memory bus using a corresponding address in the address space, a select line and / or output of each look-up table being programmably interconnected with a select line or output of another of the look-up tables independently of corresponding values ​​of the plurality of auxiliary memories, The method comprises: obtain the digitally defined checksum value of the logic function, finding a digital value of a predefined length that, when applied to a packaged checksum value of said checksum value comprising said digital definition of a core function, produces a result that complies with a predefined rule according to a predefined operation, and An enhanced digital definition of the device is defined, comprising the digital definition of the logic function and a definition of the one or more auxiliary memory cells reflecting the checksum value.

2. The method according to claim 1, wherein: The step of finding a digital value of a predefined length includes: testing continuous random digital values ​​of a predefined length against the predefined rules until a digital value of a predefined length is found as follows: when the digital value of the predefined length is applied to the encapsulated checksum value of the checksum value of the digital definition including the core function, according to a predefined operation, a result that complies with the predefined rules is produced.

3. The method according to claim 1 or 2 comprises the further step of: before the step of finding a digital value of a predefined length, by a predetermined operation, incorporating a historical checksum from a previous iteration of the method according to claim 1 or 2 into the encapsulated checksum.

4. A method according to claim 1, 2 or 3, comprising the further step of encrypting the enhanced digital definition of the field programmable gate array.

5. The method according to any one of claims 1 to 4, comprising the further step of defining a bit stream about the address space so that when the bit stream is loaded into the programming memory, the field programmable gate array implements the defined logic function.

6. The method according to claim 5, comprising the further step of: loading the bit stream into the programming memory so as to program the field programmable gate array to implement the defined logic function.

7. A method for querying a field programmable gate array according to any one of claims 1 to 6, the query method comprising the following steps: The contents of the auxiliary memory cells are read in a sequence defined according to the memory space.

8. The method for querying a field programmable gate array according to claim 7, wherein: Some or all of the programmed memory cells are configured to output the values ​​of the programmed memory cells to one or more shift registers, and wherein the step of reading the contents of the auxiliary memory cells includes: clocking the one or more shift registers in a predefined sequence to read out the contents of the one or more shift registers, wherein the step of reading the contents of the auxiliary memory cells in a sequence defined according to the storage space includes: interleaving the contents of the auxiliary memory cells with the contents read from the shift registers to achieve a predefined output structure.

9. A device defined by the method of any one of claims 1 to 6.

10. A computer program comprising instructions, wherein: When the program is executed by a computer, the computer is caused to execute the method according to any one of claims 1 to 8.

11. A computer readable medium storing data for defining a definition of a method according to any one of claims 1 to 8.

12. A field programmable gate array capable of implementing a logic function, the field programmable gate array comprising: a plurality of hardware lookup tables each including a plurality of select lines and / or outputs, a programming memory bus having a corresponding address space, and a plurality of programming memory cells, each of the programming memory cells being accessible for reading and / or writing via the programming memory bus using a corresponding address in the address space, the select lines and / or outputs of each lookup table being programmably interconnected with the select lines or outputs of another of the lookup tables according to corresponding values ​​of the plurality of programming memories, The field programmable gate array further comprises a plurality of auxiliary memory units, each of the auxiliary memory units being accessible for reading via the programming memory bus using a corresponding address in the address space, and the selection lines and / or outputs of each lookup table being programmably interconnected with the selection lines or outputs of another lookup table independent of corresponding values ​​of the plurality of auxiliary memories.

13. The field programmable gate array according to claim 12, wherein: One or more of the auxiliary memory cells return fixed values ​​defined in hardware.

14. The field programmable gate array according to claim 13, wherein: The address space is defined by values ​​in two dimensions, and wherein addresses in the address space belong to the following region: a continuous region including minimum values ​​in each dimension of the address space and / or a continuous region including maximum values ​​in each dimension of the address space, and the one or more auxiliary memory units are accessible via addresses in the address space.

15. The field programmable gate array according to any one of claims 12 to 14, wherein: One or more of the auxiliary memory units stores a watermark value and a unique identifier or version reference.

Images