A SRAF placement effect evaluation method, device, equipment and medium

Abstract

The present application discloses a SRAF placement effect evaluation method, device, equipment and medium, which relates to the field of layout correction technology, including: obtaining a SRAF placement rule file written by a user, and parsing the SRAF placement rule file to identify the position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout to obtain SRAF feature information; using preset evaluation rules to evaluate the effect of the SRAF feature information respectively to obtain the effect evaluation results of each information; outputting the current defect problems of the SRAF placement rule file according to the effect evaluation results, and prompting the user to adjust the design of the SRAF graphic. The entire evaluation cycle is shortened, and a basis can be provided for subsequent SRAF graphic design adjustments more quickly, effectively accelerating the speed of integrated circuit process development and verification.

Description

Technical Field

[0001] The present invention relates to the field of layout correction technology, and in particular to a SRAF placement effect evaluation method, device, equipment and medium. Background Art

[0002] The pre-process of OPC (Optical Proximity Correction) in EDA software is to add SRAF (Sub Resolution Assist Feature) to the layout. SRAF is used in the field of integrated circuit manufacturing. OPC process engineers use EDA software to place SRAF in the layout to improve the process window. However, in application, due to the different number, position, and shape of SRAF, it is difficult to make an expected estimate of the process window improvement, resulting in the final SRAF having to go through multiple cycles of SRAF design -> OPC verification -> ORC check (Optical Rule Check) -> process window check -> SRAF adjustment -> SRAF redesign. With the increase in transistor density on integrated circuits, the corresponding layout data has increased exponentially, which in turn causes an increase in the SRAF design-verification time cost, which in turn seriously affects the process development and verification speed of advanced processes. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide a SRAF placement effect evaluation method, device, equipment and medium, which can quickly detect the SRAF placement effect after the SRAF design is completed, and reduce the verification cycle of the SRAF design. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a method for evaluating the effect of SRAF placement, comprising:

[0005] Obtaining a SRAF placement rule file written by a user, and parsing the SRAF placement rule file to identify SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout;

[0006] Using preset evaluation rules to evaluate the effects of the SRAF feature information respectively to obtain effect evaluation results of each information;

[0007] The current defect problems of the SRAF placement rule file are output according to the effect evaluation result, and the user is prompted to make design adjustments to the SRAF graphics.

[0008] Optionally, the SRAF feature information for identifying the SRAF graphic includes:

[0009] Identify the coordinate information and layout area of ​​each SRAF graphic in the integrated circuit layout to obtain the position information of each SRAF graphic;

[0010] Identify the geometric features of each of the SRAF graphics to determine the type information of each of the SRAF graphics, and count the quantity information of the SRAF graphics;

[0011] Determining priority information of each of the SRAF graphics based on the region label of the layout region where each of the SRAF graphics is located;

[0012] SRAF feature information is acquired based on the position information, the type information, the quantity information, and the priority information.

[0013] Optionally, the identifying the coordinate information of each SRAF graphic in the integrated circuit layout and the layout area where it is located to obtain the position information of each SRAF graphic; identifying the geometric features of each SRAF graphic to determine the type information of each SRAF graphic, and counting the quantity information of the SRAF graphics; and determining the priority information of each SRAF graphic based on the area label of the layout area where each SRAF graphic is located, includes:

[0014] Dividing the integrated circuit layout according to the layout hierarchy or layout regions to obtain the integrated circuit layout carrying corresponding region labels;

[0015] Identify the coordinate information of each SRAF graphic in a preset coordinate system and the layout area of ​​the SRAF graphic in the integrated circuit layout currently carrying the corresponding area label, so as to obtain the position information of each SRAF graphic;

[0016] Identifying the geometric features of each of the SRAF graphics to obtain the geometric features to be classified, and determining the SRAF types corresponding to the geometric features to be classified according to the first mapping relationship between the geometric features of different SRAF graphics and the corresponding SRAF types to obtain the type information of each of the SRAF graphics;

[0017] Counting the number of the SRAF graphics according to a preset counting rule to obtain the total number of SRAF graphics;

[0018] Performing priority identification on the SRAF graphics according to a preset priority identification rule to obtain priority information of each SRAF graphic;

[0019] The preset coordinate system is a coordinate system constructed based on the layout information of the current integrated circuit layout.

[0020] Optionally, before performing effect evaluation on the SRAF feature information respectively by using preset evaluation rules to obtain effect evaluation results of each information, the method further includes:

[0021] Setting a first defect assessment rule for conflict signals where there is a position conflict between SRAF patterns, and a problem where a corresponding type and / or number of SRAF patterns are missing from a target position in an integrated circuit layout;

[0022] Set up for the satisfied version Figure 1 a second defect assessment rule that a difference value between SRAF patterns in an area of ​​an integrated circuit layout with a consistent position condition is greater than a preset threshold;

[0023] Setting a third defect assessment rule for a problem in which a corresponding type and / or number of SRAF patterns are missing from a non-target position in an integrated circuit layout;

[0024] Constructing a preset assessment rule based on the first defect assessment rule, the second defect assessment rule, and the third defect assessment rule;

[0025] The target position in the integrated circuit layout is the regional position of the integrated circuit layout related to the core functions of the chip, the core performance of the chip and signal transmission; the non-target position in the integrated circuit layout is the regional position of the integrated circuit layout other than the target position in the integrated circuit layout and the position that meets the requirements of the layout. Figure 1 The location of the area outside the area of ​​the integrated circuit layout with consistent position conditions.

[0026] Optionally, the using preset evaluation rules to respectively evaluate the effect of the SRAF feature information to obtain the effect evaluation result of each information includes:

[0027] If the SRAF feature information contains information of conflicting signals of positional conflicts between SRAF graphics, or information of a problem in which a target position in the integrated circuit layout lacks a corresponding type and / or number of SRAF graphics, it is determined that the SRAF graphic information to be evaluated meets the first defect evaluation rule, and a first effect evaluation result is obtained;

[0028] If the SRAF feature information contains Figure 1 If the difference value between the SRAF graphics in the area of ​​the integrated circuit layout with the consistent position condition is greater than a preset threshold, it is determined that the SRAF graphic information to be evaluated meets the second defect evaluation rule, and a second effect evaluation result is obtained;

[0029] If the SRAF feature information contains information about SRAF graphic problems of corresponding types and / or quantities missing from non-target locations in the integrated circuit layout, it is determined that the SRAF graphic information to be evaluated meets the third defect evaluation rule, and a third effect evaluation result is obtained.

[0030] Optionally, outputting the defect problem currently existing in the SRAF placement rule file according to the effect evaluation result includes:

[0031] If the evaluation result is the first effect evaluation result, outputting that the SRAF placement rule file currently has a fatal defect problem;

[0032] If the evaluation result is the second effect evaluation result, outputting that the SRAF placement rule file currently has a serious defect problem;

[0033] If the evaluation result is the third effect evaluation result, it is output that the SRAF placement rule file currently has a general defect problem.

[0034] Optionally, the prompting the user to adjust the design of the SRAF graphic includes:

[0035] SRAF information of corresponding levels is displayed in the output report through problem display methods corresponding to defect problems of different levels, and target SRAF information corresponding to the defect problems is displayed in the output report, so as to prompt the user to make design adjustments to the corresponding SRAF graphics according to the problem display method and the target SRAF information.

[0036] In a second aspect, the present application discloses a SRAF placement effect evaluation device, comprising:

[0037] An information parsing and extracting module, used to obtain a SRAF placement rule file written by a user, and parse the SRAF placement rule file to identify SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout;

[0038] An effect evaluation module, used to perform effect evaluation on the SRAF feature information respectively using preset evaluation rules to obtain effect evaluation results of each information;

[0039] The graphic adjustment module is used to output the current defect problems of the SRAF placement rule file according to the effect evaluation result, and prompt the user to adjust the design of the SRAF graphic.

[0040] In a third aspect, the present application discloses an electronic device, comprising:

[0041] Memory, used to store computer programs;

[0042] The processor is used to execute the computer program to implement the steps of the aforementioned SRAF placement effect evaluation method disclosed above.

[0043] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned SRAF placement effect evaluation method disclosed above are implemented.

[0044] It can be seen that the present application discloses a SRAF placement effect evaluation method, including: obtaining a SRAF placement rule file written by a user, and parsing the SRAF placement rule file to identify the SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes the position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout; using preset evaluation rules to respectively evaluate the effect of the SRAF feature information to obtain the effect evaluation results of each information; outputting the current defect problems of the SRAF placement rule file according to the effect evaluation results, and prompting the user to make design adjustments to the SRAF graphic. It can be seen that by directly parsing and evaluating the effect based on the SRAF placement rule file written by the user, multiple links such as OPC verification, ORC inspection, and process window inspection in the prior art are skipped, which greatly shortens the entire evaluation cycle, can provide a basis for subsequent SRAF graphic design adjustments more quickly, and effectively speed up the integrated circuit process development and verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0046] Figure 1 A flow chart of a SRAF placement effect evaluation method disclosed in this application;

[0047] Figure 2 A schematic diagram of a fatal defect disclosed in this application;

[0048] Figure 3 A schematic diagram of another fatal defect disclosed in this application;

[0049] Figure 4 A schematic diagram of a serious defect disclosed in this application;

[0050] Figure 5 A general defect schematic diagram disclosed in this application;

[0051] Figure 6 A schematic diagram of the structure of a SRAF placement effect evaluation device disclosed in this application;

[0052] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0054] The pre-process of OPC (Optical Proximity Correction) in EDA software is to add SRAF (SubResolution Assist Feature) to the layout. SRAF is used in the field of integrated circuit manufacturing. OPC process engineers use EDA software to place SRAF in the layout to improve the process window. However, in application, due to the different number, position, and shape of SRAF, it is difficult to predict the improvement of the process window, resulting in the final SRAF to go through multiple cycles of SRAF design -> OPC verification -> ORC check -> process window check -> SRAF adjustment -> SRAF redesign. With the increase in transistor density on integrated circuits, the corresponding layout data has increased exponentially, which in turn causes an increase in the SRAF design-verification time cost, which in turn seriously affects the process development and verification speed of advanced processes.

[0055] To this end, the present invention also discloses a SRAF placement effect evaluation scheme, which can quickly detect the SRAF placement effect after the SRAF design is completed, thereby reducing the verification cycle of the SRAF design.

[0056] Reference Figure 1 As shown, an embodiment of the present invention discloses a method for evaluating the effect of SRAF placement, including:

[0057] Step S11: obtaining a SRAF placement rule file written by a user, and parsing the SRAF placement rule file to identify SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout.

[0058] In this embodiment, firstly, a SRAF placement rule file written by a user is obtained. The SRAF placement rule file is written in combination with production technology and user experience, and its content mainly includes SRAF position information, type information, quantity information and priority information.

[0059] In a specific implementation, the SRAF placement rule file may be written before SRAF placement to guide SRAF placement. In this case, the SRAF placement rule is similar to a blueprint or plan, telling the system how to place SRAF graphics on the layout, including information such as the placement location, type, quantity, and priority.

[0060] In another specific implementation, the SRAF placement rule file is written after the SRAF has been preliminarily placed on the integrated circuit layout. This is based on the summary and specification of the preliminary placement situation, or is a basis for adjusting the placed SRAF. For example, some tentative SRAF placements are first performed, and then according to these placement situations, rules are written to further refine and optimize the placement strategy.

[0061] In this embodiment, the coordinate information and the layout area of ​​each SRAF graphic in the integrated circuit layout are identified to obtain the position information of each SRAF graphic; the geometric features of each SRAF graphic are identified to determine the type information of each SRAF graphic, and the quantity information of the SRAF graphics is counted; based on the area label of the layout area where each SRAF graphic is located, the priority information of each SRAF graphic is determined; and the SRAF feature information is acquired based on the position information, the type information, the quantity information, and the priority information.

[0062] Specifically, the integrated circuit layout is divided according to the layout hierarchy or layout area to obtain an integrated circuit layout carrying corresponding area labels; the coordinate information of each SRAF graphic in the preset coordinate system and the layout area of ​​the SRAF graphic in the current integrated circuit layout carrying the corresponding area label are identified to obtain the position information of each SRAF graphic; the geometric features of each SRAF graphic are identified to obtain the geometric features to be classified, and the SRAF type corresponding to the geometric features to be classified is determined according to the first mapping relationship between the geometric features of different SRAF graphics and the corresponding SRAF types to obtain the type information of each SRAF graphic; the SRAF graphics are counted according to the preset counting rule to obtain the total number of SRAF graphics; the SRAF graphics are prioritized according to the preset priority identification rule to obtain the priority information of each SRAF graphic; wherein the preset coordinate system is a coordinate system constructed based on the layout information of the current integrated circuit layout.

[0063] It is understandable that after obtaining the rule file, it is parsed and processed, specifically including: SRAF position information parsing, SRAF type information parsing, SRAF quantity information parsing, and SRAF priority information parsing, wherein the SRAF position information parsing includes determining the two-dimensional coordinate information of each SRAF graphic based on the coordinate system. Specifically, the integrated circuit layout is usually constructed based on a two-dimensional coordinate system. The SRAF placement rule will contain the absolute position coordinates or relative position coordinates of the SRAF graphic in this coordinate system. For example, the placement rule specifies that the center position coordinates of a certain SRAF are (x, y), or the offset relative to a known pattern (such as the boundary of a functional module in the chip or the starting point of the main line). The parsing module can determine the position of the SRAF in the layout by identifying the information related to these coordinates. The SRAF position information parsing also includes regional division identification. Specifically, the layout is also divided into different areas, such as functional areas, wiring areas, etc. The SRAF placement rule can determine the position of the SRAF through the regional label. For example, the rule mentions that a specific type of SRAF is placed near the data line in the storage unit area, and the parsing module will determine the specific position of the SRAF based on the description of these regional divisions and relative positions.

[0064] It is understandable that the type information analysis includes graphic feature recognition, that is, different types of SRAFs have different geometric features. The parsing module can determine the type of the SRAF graphic by identifying its geometric properties such as shape, size ratio, etc. For example, an SRAF used to improve the roughness of line edges is an elongated rectangular shape, while an SRAF used to assist in graphic spacing lithography is a smaller circle or square. By matching and identifying these geometric features, the type of SRAF can be determined. Label or identifier association: Different types of SRAFs are assigned specific labels or identifiers in the placement rules. The parsing module can determine the type of SRAF by identifying these labels. For example, the rule stipulates that "place the SRAF marked as Type-A at the position...", and the parsing module can determine the type of the SRAF by looking up the type definition corresponding to the Type-A label.

[0065] It is understandable that the analysis of quantity information includes the application of counting rules, that is, the placement rules clearly give the quantity requirements of SRAFs in a certain area or the entire layout. For example, the rule mentions "place 3 specific SRAFs at the edge of each functional module", and the analysis module can calculate the total number of SRAFs based on the number of functional modules in the layout and this clear quantity requirement. The analysis of quantity information also includes repetitive pattern recognition, that is, if the placement of SRAFs has a certain repetitive pattern, the analysis module can determine the number by identifying this pattern. For example, the rule stipulates "place an SRAF at a certain distance", and the analysis module can calculate the number of SRAFs based on the size of the layout and this spacing distance.

[0066] It is understandable that the priority information parsing includes level mark recognition, that is, the placement rules will set different priority levels for SRAFs and represent them with specific marks. For example, the rule mentions "place SRAFs with high priority (marked as High-Priority) first in the critical area", and the parsing module can determine the priority of the SRAF by identifying these priority level marks. It also includes critical area association, that is, the priority is also associated with the critical area in the layout. The parsing module can determine the priority of the SRAF by judging whether it is located in a pre-defined critical area (such as the core functional area of ​​the chip, the high-precision wiring area, etc.). If an SRAF is located in a critical area, its priority will be set to a higher level.

[0067] Step S12: using preset evaluation rules to perform effect evaluation on the SRAF feature information respectively to obtain effect evaluation results of each information.

[0068] In this embodiment, before the effect evaluation of the SRAF feature information is performed using the preset evaluation rules to obtain the effect evaluation results of each information, it also includes: setting a first defect evaluation rule for conflict signals with position conflicts between SRAF graphics, and SRAF graphics problems with corresponding types and / or quantities missing at target positions in the integrated circuit layout; setting a first defect evaluation rule for the problem of meeting the layout requirements; Figure 1 A second defect assessment rule is set for the problem that the difference value between the SRAF graphics in the area of ​​the integrated circuit layout that meets the consistent position condition is greater than a preset threshold; a third defect assessment rule is set for the problem that the non-target position in the integrated circuit layout lacks the corresponding type and / or number of SRAF graphics; a preset assessment rule is constructed based on the first defect assessment rule, the second defect assessment rule, and the third defect assessment rule; wherein the target position in the integrated circuit layout is the regional position of the integrated circuit layout related to the core function of the chip, the core performance of the chip, and the signal transmission; the non-target position in the integrated circuit layout is the position of the integrated circuit layout other than the target position in the integrated circuit layout, the position of the integrated circuit layout that meets the layout condition, and the position of the integrated circuit layout that meets the layout condition. Figure 1The area outside the area of ​​the integrated circuit layout with the consistent position condition. It can be understood that before using the SRAF placement effect evaluation rule generation module to evaluate each SRAF feature information, each evaluation rule is generated in advance. Specifically, the first defect evaluation rule, the second defect evaluation rule and the third defect evaluation rule are constructed. The preset evaluation rule is constructed through the above three evaluation rules to evaluate each SRAF feature information. Specifically, if there is an MRC (Mask Rule Check) problem in the SRAF generated in the layout, it will affect the mask production, and then have a fatal impact on the lithography process window. MRC mainly checks whether the photomask design rules meet the requirements of the lithography process, such as the minimum line width, minimum spacing, overlap rules, etc. are subject to its constraints. Generally speaking, MRC problems include SRAF minimum / maximum width, SRAF minimum / maximum length, SRAF minimum / maximum area, minimum spacing between SRAFs, minimum spacing between SRAFs and other graphics, etc. For example, when the spacing between SRAF and other patterns does not meet the minimum spacing requirements that can be achieved by the lithography process, or when the line width of SRAF itself is too thin and exceeds the limit that can be resolved by lithography, and other violations of the MRC rules occur, this is a fatal defect situation with MRC problems. This is because the SRA design that does not meet the rules cannot accurately transfer the corresponding pattern to the silicon wafer during the actual mask production and subsequent lithography process, resulting in the inability to carry out the entire lithography process normally, seriously damaging the process window, and making it difficult for lithography to achieve the expected effect. Figure 2 As shown in the figure, there is a mask rule check (MRC) problem between the SRAF and Main Pattern. Figure 2 In the figure, you can see that a square with a diagonal texture represents the Main Pattern, and a long strip represents the SRAF. When they are close to each other, they do not meet the design rules (minimum spacing), which will affect the mask production and is a fatal defect. If the generated SRAF in the layout has an MRC problem, it will affect the mask production, which will lead to the OPC process of the integrated circuit layout not converging, and the process window is too small to be lithographed. Therefore, the first defect assessment rule is set for the above situation.

[0069] In another case, when the layout lacks the SRAF at the target position (key position), or the SRAF shape, area and other parameters at the key position are greater than the design deviation threshold, it is considered that a fatal SRAF defect occurs, such as Figure 3As shown in the figure, the dotted line marks the missing SRAF, and the dotted line is the key position of the layout. It is set that if the SRAF at the key position in the layout is missing, or the parameters and design deviations of the SRAF shape, area, etc. at the key position are greater than the threshold, it is considered that a fatal SRAF defect has occurred. This fatal SRAF defect will cause the OPC process of the integrated circuit layout to not converge, and then cause the process window to be too small for lithography. Therefore, the first defect evaluation rule is also set for the above situation. It should be noted that the SRAF at the missing target position, that is, the SRAF with the highest current priority, is not located at the target position of the layout, resulting in the missing corresponding SRAF graphic at the target position.

[0070] In this embodiment, according to the layout design requirements, all layout design consistency positions are determined from the layout, where the design consistency positions are to ensure that the same type of design positions (such as certain positions in a specific functional module or the same wiring level) can maintain consistent lithography effects under the rule constraints, and these layout positions are determined as design consistency positions. For these design consistency positions, corresponding second defect assessment rules are set, and the specific rules are set as follows: when the difference between the SRAF graphics at the design consistency positions is greater than a preset threshold, a corresponding severe defect will be generated. Figure 4 As shown in the figure, if the difference between the SRAFs at the design consistency position is greater than the threshold, it is considered that a serious SRAF defect occurs. This serious SRAF defect will lead to poor consistency of the OPC results of the integrated circuit layout, which will in turn cause the process window to shift, making it difficult to unify the lithography in the entire layout, which can easily lead to low chip yield.

[0071] In this embodiment, the third defect assessment rule for the SRAF pattern defect inspection at the general position is designed as follows: the positions in the layout other than the key positions and the design consistency positions are marked as general positions. The general positions have relatively little impact on the core functions of the chip, but still contribute to the entire lithography process. The main role of the general positions is auxiliary. For example, in some non-critical wiring areas or around patterns that do not require so much precision, their SRAF placement and design are mainly to cooperate with the lithography of the overall layout, and to optimize the lithography effect as much as possible without affecting the key functions. Therefore, if the missing SRAF pattern at the general position is set, or the parameters and design deviation of the SRAF shape, area, etc. at the general position are greater than the threshold, it is considered that a general SRAF defect has occurred, such as Figure 5 as shown in . Figure 5 The dotted rectangular box indicates that the SRAF pattern is indeed at the general position, and the current situation meets the third defect assessment rule.

[0072] In this embodiment, if the SRAF feature information contains information of conflicting signals of positional conflicts between SRAF graphics, or information of SRAF graphics problems of corresponding types and / or quantities missing from the target position in the integrated circuit layout, it is determined that the SRAF graphics information to be evaluated meets the first defect evaluation rule, and a first effect evaluation result is obtained; if the SRAF feature information meets the layout requirement, the first effect evaluation result is obtained. Figure 1 If the difference value between the SRAF graphics in the area of ​​the integrated circuit layout with consistent position conditions is greater than a preset threshold, then the SRAF graphic information to be evaluated is determined to meet the second defect evaluation rule, and a second effect evaluation result is obtained; if the SRAF feature information contains information that there is a problem of missing SRAF graphics of corresponding types and / or quantities in non-target positions in the integrated circuit layout, then the SRAF graphic information to be evaluated is determined to meet the third defect evaluation rule, and a third effect evaluation result is obtained.

[0073] Step S13: outputting the current defect problems of the SRAF placement rule file according to the effect evaluation result, and prompting the user to adjust the design of the SRAF graphic.

[0074] In this embodiment, if the evaluation effect is the first effect evaluation result, then it is output that the SRAF placement rule file currently has a fatal defect problem; if the evaluation effect is the second effect evaluation result, then it is output that the SRAF placement rule file currently has a serious defect problem; if the evaluation effect is the third effect evaluation result, then it is output that the SRAF placement rule file currently has a general defect problem.

[0075] In this embodiment, SRAF information of corresponding levels is displayed in the output report through problem display methods corresponding to defect problems of different levels, and target SRAF information corresponding to the defect problems is displayed in the output report, so as to prompt the user to design and adjust the corresponding SRAF graphics according to the problem display method and the target SRAF information.

[0076] It can be seen that the present application discloses a SRAF placement effect evaluation method, including: obtaining a SRAF placement rule file written by a user, and parsing the SRAF placement rule file to identify the SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes the position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout; using preset evaluation rules to respectively evaluate the effect of the SRAF feature information to obtain the effect evaluation results of each information; outputting the current defect problems of the SRAF placement rule file according to the effect evaluation results, and prompting the user to make design adjustments to the SRAF graphic. It can be seen that by directly parsing and evaluating the effect based on the SRAF placement rule file written by the user, multiple links such as OPC verification, ORC inspection, and process window inspection in the prior art are skipped, which greatly shortens the entire evaluation cycle, can provide a basis for subsequent SRAF graphic design adjustments more quickly, and effectively speed up the integrated circuit process development and verification.

[0077] Reference Figure 6 As shown, the present invention also discloses a SRAF placement effect evaluation device, comprising:

[0078] The information parsing and extracting module 11 is used to obtain the SRAF placement rule file written by the user, and parse the SRAF placement rule file to identify the SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes the position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout;

[0079] The effect evaluation module 12 is used to perform effect evaluation on the SRAF feature information respectively using preset evaluation rules to obtain effect evaluation results of each information;

[0080] The graphic adjustment module 13 is used to output the current defect problems of the SRAF placement rule file according to the effect evaluation result, and prompt the user to adjust the design of the SRAF graphic.

[0081] It can be seen that the present application discloses obtaining a SRAF placement rule file written by a user, and parsing the SRAF placement rule file to identify the SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes the position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout; using preset evaluation rules to respectively evaluate the effect of the SRAF feature information to obtain the effect evaluation results of each information; outputting the current defect problems of the SRAF placement rule file according to the effect evaluation results, and prompting the user to make design adjustments to the SRAF graphic. It can be seen that by directly parsing and evaluating the effect based on the SRAF placement rule file written by the user, multiple links such as OPC verification, ORC inspection, and process window inspection in the prior art are skipped, which greatly shortens the entire evaluation cycle, can provide a basis for subsequent SRAF graphic design adjustments more quickly, and effectively speed up the integrated circuit process development and verification.

[0082] Furthermore, the present application also discloses an electronic device. Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0083] Figure 7 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the SRAF placement effect evaluation method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0084] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0085] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0086] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0087] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the SRAF placement effect evaluation method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data received by the electronic device and transmitted from an external device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0088] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed SRAF placement effect evaluation method is implemented. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0089] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0090] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly with hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory RAM (Random Access Memory), memory, read-only memory ROM (Read Only Memory), electrically programmable EPROM (Electrically Programmable Read Only Memory), electrically erasable programmable EEPROM (ElectricErasable Programmable Read Only Memory), register, hard disk, removable disk, CD-ROM (CompactDisc-Read Only Memory), or any other form of storage medium known in the technical field.

[0091] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0092] The scheme provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for evaluating the effect of SRAF placement, characterized in that: include: Obtaining a SRAF placement rule file written by a user, and parsing the SRAF placement rule file to identify SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout; Using preset evaluation rules to evaluate the effects of the SRAF feature information respectively to obtain effect evaluation results of each information; Outputting the current defect problems of the SRAF placement rule file according to the effect evaluation result, and prompting the user to make design adjustments to the SRAF graphics; Wherein, before performing effect evaluation on the SRAF feature information respectively by using preset evaluation rules to obtain effect evaluation results of each information, it also includes: Setting a first defect assessment rule for conflict signals where there is a position conflict between SRAF patterns, and a problem where a corresponding type and / or number of SRAF patterns are missing from a target position in an integrated circuit layout; Setting a second defect assessment rule for a region of the integrated circuit layout that satisfies the layout consistency position condition where the difference value between the SRAF patterns is greater than a preset threshold; Setting a third defect assessment rule for a problem in which a corresponding type and / or number of SRAF patterns are missing from a non-target position in an integrated circuit layout; Constructing a preset assessment rule based on the first defect assessment rule, the second defect assessment rule, and the third defect assessment rule; Among them, the target position in the integrated circuit layout is the regional position of the integrated circuit layout related to the core function of the chip, the core performance of the chip and the signal transmission; the non-target position in the integrated circuit layout is the regional position other than the target position in the integrated circuit layout and the region of the integrated circuit layout that meets the layout consistency position conditions.

2. The SRAF placement effect evaluation method according to claim 1, characterized in that: The SRAF feature information for identifying the SRAF graphic includes: Identify the coordinate information and layout area of ​​each SRAF graphic in the integrated circuit layout to obtain the position information of each SRAF graphic; Identify the geometric features of each of the SRAF graphics to determine the type information of each of the SRAF graphics, and count the quantity information of the SRAF graphics; Determining priority information of each of the SRAF graphics based on the region label of the layout region where each of the SRAF graphics is located; SRAF feature information is acquired based on the location information, the type information, the quantity information, and the priority information.

3. The SRAF placement effect evaluation method according to claim 2, characterized in that: The coordinate information and layout area of ​​each SRAF graphic in the integrated circuit layout are identified to obtain the position information of each SRAF graphic; the geometric features of each SRAF graphic are identified to determine the type information of each SRAF graphic, and the quantity information of the SRAF graphics is counted; Determining priority information of each SRAF graphic based on the region label of the layout region where each SRAF graphic is located includes: Dividing the integrated circuit layout according to the layout hierarchy or layout regions to obtain the integrated circuit layout carrying corresponding region labels; Identify the coordinate information of each SRAF graphic in a preset coordinate system and the layout area of ​​the SRAF graphic in the integrated circuit layout currently carrying the corresponding area label, so as to obtain the position information of each SRAF graphic; Identifying the geometric features of each of the SRAF graphics to obtain the geometric features to be classified, and determining the SRAF types corresponding to the geometric features to be classified according to the first mapping relationship between the geometric features of different SRAF graphics and the corresponding SRAF types to obtain the type information of each of the SRAF graphics; Counting the number of the SRAF graphics according to a preset counting rule to obtain the total number of SRAF graphics; Performing priority identification on the SRAF graphics according to a preset priority identification rule to obtain priority information of each SRAF graphic; The preset coordinate system is a coordinate system constructed based on the layout information of the current integrated circuit layout.

4. The SRAF placement effect evaluation method according to claim 1, characterized in that: The using of preset evaluation rules to respectively evaluate the effect of the SRAF feature information to obtain the effect evaluation results of each information includes: If the SRAF feature information contains information of conflicting signals of positional conflicts between SRAF graphics, or information of a problem in which a target position in the integrated circuit layout lacks a corresponding type and / or number of SRAF graphics, it is determined that the SRAF graphic information to be evaluated meets the first defect evaluation rule, and a first effect evaluation result is obtained; If the SRAF feature information contains information that the difference value between the SRAF graphics in the area of ​​the integrated circuit layout that meets the layout consistency position condition is greater than a preset threshold, it is determined that the SRAF graphic information to be evaluated meets the second defect evaluation rule, and a second effect evaluation result is obtained; If the SRAF feature information contains information about SRAF graphic problems of corresponding types and / or quantities missing from non-target locations in the integrated circuit layout, it is determined that the SRAF graphic information to be evaluated meets the third defect evaluation rule, and a third effect evaluation result is obtained.

5. The SRAF placement effect evaluation method according to claim 4, characterized in that: Outputting the defect problem currently existing in the SRAF placement rule file according to the effect evaluation result includes: If the evaluation result is the first effect evaluation result, outputting that the SRAF placement rule file currently has a fatal defect problem; If the evaluation result is the second effect evaluation result, outputting that the SRAF placement rule file currently has a serious defect problem; If the evaluation result is the third effect evaluation result, it is output that the SRAF placement rule file currently has a general defect problem.

6. The SRAF placement effect evaluation method according to any one of claims 1 to 5, characterized in that: The prompting the user to adjust the design of the SRAF graphic includes: SRAF information of corresponding levels is displayed in the output report through problem display methods corresponding to defect problems of different levels, and target SRAF information corresponding to the defect problems is displayed in the output report, so as to prompt the user to make design adjustments to the corresponding SRAF graphics according to the problem display method and the target SRAF information.

7. A SRAF placement effect evaluation device, characterized in that: include: An information parsing and extracting module, used to obtain a SRAF placement rule file written by a user, and parse the SRAF placement rule file to identify SRAF feature information of the SRAF graphic; wherein the SRAF feature information includes position information, type information, quantity information and priority information of the SRAF graphic in the integrated circuit layout; An effect evaluation module, used to perform effect evaluation on the SRAF feature information respectively using preset evaluation rules to obtain effect evaluation results of each information; A graphic adjustment module, used for outputting the current defect problems of the SRAF placement rule file according to the effect evaluation result, and prompting the user to make design adjustments to the SRAF graphic; The SRAF placement effect evaluation device is also used to set a first defect evaluation rule for conflict signals with position conflicts between SRAF graphics and problems with SRAF graphics of corresponding types and / or quantities missing from target positions in the integrated circuit layout; set a second defect evaluation rule for problems with difference values ​​between SRAF graphics in an area of ​​the integrated circuit layout that meets the layout consistency position condition being greater than a preset threshold; set a third defect evaluation rule for problems with SRAF graphics of corresponding types and / or quantities missing from non-target positions in the integrated circuit layout; and construct preset evaluation rules based on the first defect evaluation rule, the second defect evaluation rule, and the third defect evaluation rule; wherein the target position in the integrated circuit layout is a regional position of the integrated circuit layout related to the core functions, core performance, and signal transmission of the chip; and the non-target position in the integrated circuit layout is a regional position other than the target position in the integrated circuit layout and the area of ​​the integrated circuit layout that meets the layout consistency position condition.

8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the SRAF placement effect evaluation method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the SRAF placement effect evaluation method according to any one of claims 1 to 6 are implemented.

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