Deep convolutional network verification system based on ZYNQ and DSP

Abstract

The invention provides a deep convolutional network verification system based on ZYNQ and DSP, which belongs to the technical field of radar systems and comprises a ZYNQ processor and a DSP processor. A trained deep convolutional network is stored in the ZYNQ processor; the DSP processor is used for acquiring and processing experimental test data from the avionics upper computer to obtain sum path and difference path original data; the DSP processor sends the sum path original data and the difference path original data to a ZYNQ processor so as to simulate the process of processing the actual radiation radar echo data according to frames; the ZYNQ processor inputs the original data into the deep convolutional network, and the deep convolutional network outputs a detection result; the ZYNQ processor sends a detection result to the DSP, and the DSP packages detection result data and sends the data to the upper computer. Through the processing scheme provided by the invention, a reliable performance verification and evaluation approach is provided for rapid application of the deep convolutional network in a radar system.

Description

Technical Field

[0001] The present application relates to the field of radar systems, and in particular to a deep convolutional network verification system based on ZYNQ and DSP. Background Art

[0002] Airborne weather / collision avoidance radar can detect and warn of weather, terrain and low-altitude obstacles in front of the aircraft, providing protection for flight safety. Dangerous weather, high-voltage wires / towers and isolated obstacles are important targets for airborne weather / collision avoidance radar detection. However, due to the variability and complexity of the flight environment, during radar target detection, the radar echo of weak reflectivity clouds is easily "blocked" by the side lobes caused by the echo of strong reflectivity rainfall clouds, and the high-voltage wire point radar echo is easily "blocked" by the side lobes caused by the echo of high-voltage towers, signal towers, etc., and is also interfered by ground clutter. The traditional radar target detection method based on CFAR detection and feature extraction has problems such as high false alarm rate and weak scene adaptability. Summary of the invention

[0003] In view of this, the present application provides a deep convolutional network verification system based on ZYNQ and DSP, which solves the problems in the prior art and provides a reliable performance verification and evaluation approach for the rapid application of deep convolutional networks in radar systems.

[0004] The deep convolutional network verification system based on ZYNQ and DSP provided in this application adopts the following technical solutions:

[0005] A deep convolutional network verification system based on ZYNQ and DSP, including a ZYNQ processor and a DSP processor;

[0006] The ZYNQ processor stores the trained deep convolutional network;

[0007] The DSP processor is used to obtain and process experimental test data from the avionics host computer to obtain the original data of the sum path and the difference path;

[0008] The DSP processor sends the original data of the sum path and the difference path to the ZYNQ processor to simulate the process of processing the actual radiation radar echo data frame by frame;

[0009] The ZYNQ processor inputs raw data into a deep convolutional network, which outputs detection results;

[0010] The ZYNQ processor sends the test results to the DSP processor, and the DSP processor packages the test result data and sends it to the host computer.

[0011] Optionally, the ZYNQ processor includes a ZYNQ chip, the ZYNQ chip includes an ARM and an FPGA module, and the FPGA module is used to store the deep convolutional network burned into the ZYNQ processor through a network port or RS422.

[0012] Optionally, the DSP processor is connected to an avionics host computer via a network port, and the DSP processor acquires experimental test data frame by frame from the avionics host computer;

[0013] The DSP processor analyzes the experimental test data format, finds the frame header of the original data, and intercepts the data of the corresponding length backward to obtain the original data of the sum path and the difference path according to the original data length information contained in the measured data;

[0014] The data is parsed in the format of frame header information + packet header information + raw data when stored in the recorder. The frame header information and packet header information contain the internal control information of the radar, and the raw data contains the sum path data and the difference path data.

[0015] Optionally, the ZYNQ processor and the DSP processor are connected via an SRIO bus, and the FPGA module of the ZYNQ chip receives the original data of the sum path and the difference path from the DSP processor frame by frame via the SRIO bus. When the accumulated number of frames reaches the input width of the deep convolutional network, the accumulated data is subjected to sliding window detection in the length direction according to a preset step size, and the detected line tower points are output and saved. The FPGA module of the ZYNQ chip continues to receive the original data of the sum path and the difference path frame by frame and output the detected line tower points until all the data of a sector is processed.

[0016] Optionally, the ZYNQ processing includes a storage module externally mounted on the ZYNQ chip. After the FPGA module of the ZYNQ chip completes processing of a sector of data, the detection result is sent to the ARM module on the ZYNQ chip through the storage module. The ARM module eliminates false alarms in the tower points and performs correlation processing on the remaining detection results to obtain the detection target required for the collision avoidance task.

[0017] Optionally, the ZYNQ processor and the DSP processor are connected via a PCI E bus, and the ZYNQ chip sends the detection result back to the DSP processor via the PCIE bus.

[0018] Optionally, the DSP processor packages the detection results in the format of frame header information + high-voltage line point + isolated object point + terrain point, and sends the packaged data to the avionics host computer through the network port for display.

[0019] In summary, this application includes the following beneficial technical effects:

[0020] High integration: This application can be used to simultaneously realize the playback of radar measured data and the verification of the deep convolutional network FPGA implementation model, and can quickly realize the application verification of the deep convolutional network model in the field of radar detection;

[0021] Rich interface resources and chip communication resources, strong scalability: ZYNQ and DSP chips have sufficient external interface resources, flexible software debugging and burning methods, and can also further adapt or integrate more technologies and equipment;

[0022] Miniaturization: weight ≤ 200g, power consumption ≤ 16W;

[0023] The system of the present application can be used in the fields of radar and flight safety monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A block diagram of the system for verifying deep convolutional networks based on Zynq and DSP;

[0026] Figure 2 Verify the system logic control flow chart for deep convolutional networks based on ZYNQ and DSP. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0028] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0029] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0030] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0031] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0032] An embodiment of the present application provides a deep convolutional network verification system based on ZYNQ and DSP.

[0033] A ZYNQ and DSP-based deep convolutional network verification system includes a ZYNQ processor and a DSP processor.

[0034] The ZYNQ processor stores the trained deep convolutional network; the DSP processor is used to obtain and process the experimental test data from the avionics host computer to obtain the original data of the sum and difference paths; the DSP processor sends the original data of the sum and difference paths to the ZYNQ processor to simulate the process of processing the actual radiation radar echo data frame by frame; the ZYNQ processor inputs the original data into the deep convolutional network, and the deep convolutional network outputs the detection results; the ZYNQ processor sends the detection results to the DSP processor, and the DSP processor packages the detection result data and sends it to the host computer.

[0035] In order to facilitate the rapid verification of the application effect of deep convolutional networks on radar, this application proposes a deep convolutional network verification system based on ZYNQ and DSP, which has the characteristics of miniaturization and high integration. The FPGA configuration of the deep convolutional network is realized on the ZYNQ platform using logic programming and control methods, and the frame-by-frame playback of radar measured data is realized using DSP to simulate the radar echo acquisition process, and sent to ZYNQ through SRIO communication to verify the real-time target detection performance of the deep convolutional network, which provides a reliable performance verification and evaluation method for the rapid application of deep convolutional networks in radar systems.

[0036] The ZYNQ processor includes a ZYNQ chip, the ZYNQ chip includes an ARM and an FPGA module, and the FPGA module is used to store a deep convolutional network burned into the ZYNQ processor through a network port or RS422. The burned deep convolutional network is trained offline.

[0037] The DSP processor is connected to the avionics host computer through the network port, and the DSP processor obtains the experimental test data from the avionics host computer frame by frame; the format of the measured data is frame header information + packet header information + original data; the DSP processor analyzes the experimental test data format, finds the frame header of the original data, and according to the original data length information contained in the measured data, intercepts the data of the corresponding length backward to obtain the sum path and difference path original data; and parses the data according to the format of frame header information + packet header information + original data when stored in the recorder, wherein the frame header information and packet header information contain the internal control information of the radar, and the original data contains the sum path data and the difference path data.

[0038] The ZYNQ processor and the DSP processor are connected via an SRIO bus. The FPGA module of the ZYNQ chip receives the original data of the sum path and the difference path from the DSP processor frame by frame via the SRIO bus. When the accumulated number of frames reaches the input width of the deep convolutional network, the accumulated data is subjected to sliding window detection in the length direction according to a preset step size, and the detected line tower points are output and saved. The FPGA module of the ZYNQ chip continues to receive the original data of the sum path and the difference path frame by frame and output the detected line tower points until all the data of a sector is processed.

[0039] The ZYNQ processing includes a storage module externally mounted on the ZYNQ chip. After the FPGA module of the ZYNQ chip completes processing of a sector of data, the detection result is sent to the ARM module on the ZYNQ chip through the storage module. The ARM module eliminates false alarms in the tower points and performs correlation processing on the remaining detection results to obtain the detection targets required for the collision avoidance task; the detection targets include high-voltage lines, isolated objects and terrain.

[0040] The ZYNQ processor and the DSP processor are connected via a PC IE bus, and the ZYNQ chip sends the detection result back to the DSP processor via the PC IE bus.

[0041] The DSP processor packages the detection results in the format of frame header information + high-voltage line point + isolated object point + terrain point, and sends the packaged data to the avionics host computer through the network port for display.

[0042] In one embodiment, Figure 1 As shown, the system of this application uses the XQ7Z045-2FFG900 I model chip as the core hardware platform, equipped with the Linux operating system for underlying hardware resource management and scheduling. The system mainly includes: a deep learning FPGA implementation module based on the ZYNQ processor and a measured data playback module based on the DSP processor. Among them, the deep learning FPGA implementation module based on the ZYNQ processor mainly includes: 1 ZYNQ-7Z045 chip, which contains 2 ARM and FPGA modules; 4 ZYNQ-7Z045 chips with a total of 2GB DDR3 SDRAM; ZYNQ-7Z045 chip PC IE configuration 4x full-duplex, 2.5Gbps, used to communicate with DSP; ZYNQ-7Z045 chip SRIO configuration 4x full-duplex. 5Gbps, used to communicate with DSP; 1 EM IF, communicating with DSP; 1 Gigabit Ethernet / network port; 1 RS422; 1 RS232; 8bit discrete quantity. The measured data playback module based on DSP processor mainly includes: 1 DSP C6678 chip, DSP C6678 chip is an octa-core processor; DSP C6678 chip external 2GB 64-bit DDR3 SDRAM; DSP C6678 chip external 128MB SPI Nor Flash; DSP C6678 chip external 128KB I 2C EEPROM; DSP C6678 chip external 128MB EM IF NAND Flash; connected to ZYNQ-7Z045 chip through SRIO 4X; connected to ZYNQ-7Z045 chip through PC I e 4X; 1 Gigabit Ethernet / network port, used to connect to the avionics host computer; 1 RS422; 1 8bit discrete quantity, connected to the external power supply

[0043] like Figure 2 As shown, in this embodiment, the control logic of the deep convolutional network verification system based on ZYNQ and DSP is as follows:

[0044] Step 1: Power on the system:

[0045] Step 1-1, the DSP C6678 chip is powered on through discrete quantity control.

[0046] Step 1-2, ZYNQ-7Z045 is powered on through discrete quantity control, and the Linux operating system is started.

[0047] Step 2: Burn the offline trained deep convolutional network model into the ZYNQ-7Z045 chip through the network port or RS422.

[0048] Step 3: Play back the measured data based on the DSP C6678 chip:

[0049] Step 3-1, connect to the avionics host computer through the network port, and the measured data playback software of the avionics host computer reads the local measured data and sends it frame by frame to the DSP C6678 chip. After reading the local measured data, the measured data playback software starts to search for the frame header synchronization header set when recording data from the file header. After finding the synchronization header, it intercepts the content of one frame of data length backward according to the format of the recorded data and sends it, and then repeats the operation of finding the next frame header synchronization header and intercepting and sending it until the end of the file, so as to realize the frame-by-frame sending of measured data.

[0050] Step 3-2, DSP C6678 chip receives measured data, completes measured data analysis, and sends the obtained sum and difference path raw data to ZYNQ-7Z045 chip. The measured data analysis is performed in the format of frame header information + packet header information + raw data when the recorder is stored, where the frame header information and packet header information contain radar internal control information, and the raw data contains sum and difference path data.

[0051] Step 4: After the measured data analysis is completed, the DSP C6678 chip sends the original data of the sum and difference paths to the ZYNQ-7Z045 chip frame by frame in a fixed format through the SRIO bus to simulate the process of processing the actual radiation radar echo data frame by frame;

[0052] Step 5: Deep learning FPGA implementation based on Zynq processor:

[0053] Step 5-1, the PL end of the ZYNQ-7Z045 chip receives the original data of the sum path and the difference path, and calculates the line tower point detection result through the convolution network; the ZYNQ-7Z045 chip receives the playback data from the DSP C6678 chip frame by frame, and when the accumulated number of frames reaches the network input width, the accumulated data is subjected to sliding window detection in the length direction according to the specified step length, and the detected line tower points are output and saved. Repeat this step until all the data of a sector is processed.

[0054] Step 5-2, the PS end of the ZYNQ-7Z045 chip further processes the detection results of the line tower points to obtain the detection results of high-voltage lines, isolated objects and terrain. After the PL end of the ZYNQ-7Z045 chip completes the processing of a sector of data, it sends the detection results to the ARM processor of the PS end through BRAM. The PS end eliminates false alarms in the line tower points according to the corresponding algorithm program and further processes the remaining detection results to obtain the detection targets required for the anti-collision task such as high-voltage lines, isolated objects and terrain.

[0055] Step 6: The PS end of the ZYNQ-7Z045 chip feeds back the detection results, and sends the detection results of the high-voltage line, isolated objects and terrain of a sector back to the DSP C6678 chip through the PC IE bus.

[0056] Step 7: The DSP C6678 chip receives the detection results, packages the data in the format of frame header information + high-voltage line point + isolated object point + terrain point, and sends the packaged data to the avionics host computer through the network port for display.

[0057] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A deep convolutional network verification system based on ZYNQ and DSP, characterized in that: Including ZYNQ processor and DSP processor; The ZYNQ processor stores trained deep convolutional networks; The DSP processor is used to obtain and process experimental test data from the avionics host computer to obtain the original data of the sum path and difference path; The DSP processor sends the original data of the sum path and the difference path to the ZYNQ processor to simulate the process of processing the actual radiation radar echo data frame by frame; The ZYNQ processor inputs raw data into a deep convolutional network, which outputs detection results; The ZYNQ processor sends the test results to the DSP processor, and the DSP processor packages the test result data and sends it to the host computer.

2. The deep convolutional network verification system based on ZYNQ and DSP according to claim 1, characterized in that: The ZYNQ processor includes a ZYNQ chip, the ZYNQ chip includes an ARM and an FPGA module, and the FPGA module is used to store a deep convolutional network burned into the ZYNQ processor through a network port or RS422.

3. The deep convolutional network verification system based on ZYNQ and DSP according to claim 1, characterized in that: The DSP processor is connected to the avionics host computer through a network port, and the DSP processor obtains experimental test data frame by frame from the avionics host computer; The DSP processor analyzes the experimental test data format, finds the frame header of the original data, and intercepts the data of the corresponding length backward to obtain the original data of the sum path and the difference path according to the original data length information contained in the measured data; The data is parsed in the format of frame header information + packet header information + raw data when stored in the recorder. The frame header information and packet header information contain the internal control information of the radar, and the raw data contains the sum path data and the difference path data.

4. The deep convolutional network verification system based on ZYNQ and DSP according to claim 2, characterized in that: The ZYNQ processor and the DSP processor are connected via an SRIO bus. The FPGA module of the ZYNQ chip receives the original data of the sum path and the difference path from the DSP processor frame by frame via the SRIO bus. When the accumulated number of frames reaches the input width of the deep convolutional network, the accumulated data is subjected to sliding window detection in the length direction according to a preset step size, and the detected line tower points are output and saved. The FPGA module of the ZYNQ chip continues to receive the original data of the sum path and the difference path frame by frame and output the detected line tower points until all the data of a sector is processed.

5. The deep convolutional network verification system based on ZYNQ and DSP according to claim 2, characterized in that: The ZYNQ processing includes a storage module externally mounted on the ZYNQ chip. After the FPGA module of the ZYNQ chip completes processing of a sector of data, the detection result is sent to the ARM module on the ZYNQ chip through the storage module. The ARM module eliminates false alarms in the tower points and performs correlation processing on the remaining detection results to obtain the detection target required for the collision avoidance task.

6. The deep convolutional network verification system based on ZYNQ and DSP according to claim 2, characterized in that: The ZYNQ processor and the DSP processor are connected via a PCIE bus, and the ZYNQ chip sends the detection result back to the DSP processor via the PCIE bus.

7. The deep convolutional network verification system based on ZYNQ and DSP according to claim 1, characterized in that: The DSP processor packages the detection results in the format of frame header information + high-voltage line point + isolated object point + terrain point, and sends the packaged data to the avionics host computer through the network port for display.

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