Light-emitting driving circuit and display panel

Abstract

The invention relates to the field of display panels, and provides a light-emitting driving circuit and a display panel, the light-emitting driving circuit comprises multiple stages of light-emitting driving units and a time sequence controller, each stage of light-emitting driving unit comprises ten transistors, three capacitors, a signal input end, a signal output end and two time sequence control ends, the timing controller includes a first timing control signal line and a second timing control signal line. According to the light-emitting driving circuit and the display panel, by providing a new 10T3C light-emitting driving unit circuit, switching between high and low levels of an output signal is enabled to be pulled down in a step-free step mode, an intermediate voltage is prevented from being influenced by a threshold voltage of a transistor or process fluctuation, the falling edge time is shortened, the starting speed of the transistor is increased, and the display effect is improved. The response time of the circuit is reduced; by reducing the use of time sequence control signal lines and transistors, the number of components of the circuit is reduced, so that the frame width of the display panel is reduced, and the display panel adapts to the narrow frame trend of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a light-emitting driving circuit and a display panel. Background Art

[0002] The display panel includes a pixel array and a scanning drive circuit and a light-emitting drive circuit for controlling the pixel array. The display panel adopts a row-by-row scanning display mode, wherein the scanning drive circuit is used to generate a scanning signal to turn on each row of pixels in turn, and the light-emitting drive circuit is used to provide a data signal to a row of pixels when it is turned on to realize the display of the pixels. The light-emitting drive circuit includes a plurality of cascaded light-emitting drive units, wherein each level of the light-emitting drive unit is usually mainly composed of a number of transistors and capacitors, and a level signal is output at the output end by inputting a clock signal and a start pulse signal to the light-emitting drive unit.

[0003] In the current light-emitting drive circuit, the process of pulling the output of the circuit from a high level to a low level needs to be performed in a "step" manner, that is, it is completely stepped from a high level to a low level in two steps. This "step" step results in a longer falling time, namely the "falling edge (Tf)", which slows down the turn-on speed of the transistor (TFT) and increases the response time of the circuit.

[0004] Figure 1 FIG. 2 shows a circuit diagram of a light-emitting driving unit in the prior art. Figure 1 As shown, Chinese patent CN105741749A discloses a light-emitting drive circuit. The reason for the "step" in the circuit is that when the potential of the clock signal c1 changes from high to low, the potential of the gate node N4 of the M2 transistor is pulled down to the same potential as the power supply VEE by the low-level input signal, and M2 is turned on, but is limited by the threshold voltage Vth, and the output voltage Vout-V(N4)=Vth<0; when the potential of c2 needs to change from high to low, and the gate N4 of M2 is pulled down to a value lower than VEE by capacitive coupling and exceeds the Vth value, Vout can be pulled down to the VEE voltage.

[0005] Figure 2 FIG. 2 shows a circuit diagram of another light-emitting driving unit in the prior art. Figure 2 As shown, U.S. Patent US9548026B2 discloses a light-emitting drive circuit. The reason for the "step" in the circuit is that when the potential of the clock signal CLK1 changes from high to low, the potential of the gate node N1 of the M10 transistor is pulled down to the same potential as the power supply VGL by the low-level input signal, and M10 is turned on, but is limited by the threshold voltage Vth, and the output voltage Vout-V(N1)=Vth<0; when the potential of CLK2 needs to change from high to low, the gate N1 of M10 is pulled down to below VGL by capacitive coupling and exceeds the Vth value, Vout can be pulled down to the VGL voltage.

[0006] This "step" type of step requires two sets of clock signals to pull down the output signal potential respectively. When the potential of one of the clock signals changes from high to low, the output signal En changes from a high level to an intermediate level; when the potential of the next clock signal changes from high to low, the output signal En changes from an intermediate level to a low level. The intermediate level is affected by the threshold voltage of the TFT and is more obviously affected by the fluctuation of the process.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0008] In view of this, the present invention provides a light-emitting drive circuit and a display panel. The light-emitting drive circuit and the display panel of the present invention provide a new 10T3C light-emitting drive unit circuit, so that the switching between the high and low levels of the output signal is not step-type step-down, thereby avoiding the influence of the intermediate voltage on the transistor threshold voltage or process fluctuation, reducing the falling edge time, accelerating the turn-on speed of the transistor, and reducing the response time of the circuit; in addition, the present invention reduces the number of components of the light-emitting drive circuit by reducing the use of timing control signal lines and transistors, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of the display panel.

[0009] One aspect of the present invention provides a light-emitting driving circuit, comprising a multi-stage light-emitting driving unit, wherein the light-emitting driving unit comprises:

[0010] A first transistor, wherein a first electrode of the first transistor is connected to a first power supply, a second electrode is connected to a third node, and a gate is connected to a signal input terminal;

[0011] a second transistor, wherein a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the fourth node, and a gate of the second transistor is connected to the third node;

[0012] a third transistor, wherein a first electrode of the third transistor is connected to the third node, a second electrode of the third transistor is connected to the second power supply, and a gate of the third transistor is connected to the first timing control terminal;

[0013] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the fourth node, a second electrode of the fourth transistor is connected to the second timing control terminal, and a gate of the fourth transistor is connected to the second timing control terminal;

[0014] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the first node;

[0015] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first power supply, a second electrode of the sixth transistor is connected to the first node, and a gate of the sixth transistor is connected to the second node;

[0016] a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node;

[0017] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the second power supply, and a gate of the eighth transistor is connected to the fifth node;

[0018] a ninth transistor, wherein a first electrode of the ninth transistor is connected to the second node, a second electrode of the ninth transistor is connected to the fifth node, and a gate of the ninth transistor is connected to the second power supply;

[0019] a tenth transistor, wherein a first electrode of the tenth transistor is connected to the second node, a second electrode of the tenth transistor is connected to the signal input terminal, and a gate of the tenth transistor is connected to the second timing control terminal;

[0020] a first capacitor, wherein a first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the signal output end;

[0021] a second capacitor, wherein a first electrode of the second capacitor is connected to the first power supply, and a second electrode of the second capacitor is connected to the first node;

[0022] A third capacitor, wherein a first electrode of the third capacitor is connected to the fourth node, and a second electrode of the third capacitor is connected to the third node.

[0023] In some embodiments, a timing controller is further included, and the timing controller includes a first timing control signal line and a second timing control signal line.

[0024] In some embodiments, the first timing control signal line is used to output a first timing control signal; and the second timing control signal line is used to output a second timing control signal.

[0025] In some embodiments, the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0026] In some embodiments, the light-emitting driving unit is used to perform delay processing on the signal received from the signal input end under the control of the first timing control signal and the second timing control signal, and the processed signal is output from the signal output end.

[0027] In some embodiments, the light-emitting driving unit at the previous stage outputs a light-emitting driving signal to the light-emitting driving unit at the next stage, and the light-emitting driving unit at the last stage outputs a light-emitting driving signal.

[0028] In some embodiments, in the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

[0029] In some embodiments, in the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

[0030] In some embodiments, the first transistor to the tenth transistor are all P-type MOS transistors.

[0031] Another aspect of the present invention further provides a display panel, characterized by comprising any one of the light emitting drive circuits described above.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0034] Figure 1 A circuit diagram showing a light-emitting driving unit of the prior art;

[0035] Figure 2 A circuit diagram showing another light-emitting driving unit of the prior art;

[0036] Figure 3 A schematic diagram showing a display panel of the present invention;

[0037] Figure 4 A cascade schematic diagram showing a light-emitting drive circuit of the present invention;

[0038] Figure 5 A circuit diagram showing a light-emitting driving unit of the present invention;

[0039] Figure 6 Show Figure 5 The waveform diagram of the light-emitting driving unit when it is working is shown.

[0040] Reference numerals:

[0041] 10 Display Panel

[0042] 11 Display area

[0043] 20 Timing Controller

[0044] 30 Light-emitting drive circuit

[0045] CKE1 The first timing control signal line

[0046] CKE2 Second timing control signal line

[0047] c1 The first timing control terminal

[0048] c2 Second timing control terminal

[0049] IN signal input terminal

[0050] Eout signal output terminal

[0051] T1 first transistor

[0052] T2 Second transistor

[0053] T3 The third transistor

[0054] T4 Fourth transistor

[0055] T5 Fifth transistor

[0056] T6 Sixth transistor

[0057] T7 Seventh transistor

[0058] T8 Eighth transistor

[0059] T9 Ninth transistor

[0060] T10 The tenth transistor

[0061] C1 First capacitor

[0062] C2 Second capacitor

[0063] C3 Third capacitor

[0064] VDD First power supply

[0065] VEE Second power supply

[0066] n1 first node

[0067] n2 Second node

[0068] n3 The third node

[0069] n4 fourth node

[0070] n5 fifth node DETAILED DESCRIPTION

[0071] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated description will be omitted.

[0072] The words "first", "second" and the like used in the specific description do not indicate any order, quantity or importance, but are only used to distinguish different components. In addition, in the description of the present invention, the orientation or position relationship indicated by the terms "upper" and "lower" are based on the orientation or position relationship shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0073] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0074] The inventor of this case has provided a solution to the problems existing in the prior art through careful and in-depth research. Figure 3 A schematic diagram showing a display panel of the present invention; Figure 4 A cascade schematic diagram showing a light-emitting drive circuit of the present invention; Figure 5 FIG. 2 shows a circuit diagram of a light-emitting driving unit of the present invention. Figures 3 to 5 As shown, the present invention discloses a light-emitting driving circuit 30 and a display panel 10, wherein the light-emitting driving circuit 30 includes a multi-stage light-emitting driving unit and a timing controller 20. Each stage of the light-emitting driving unit specifically includes 10 transistors, 3 capacitors, a signal input terminal, a signal output terminal and two timing control terminals. The timing controller 20 includes two timing control signal lines. The light-emitting driving circuit and the display panel of the present invention, by providing a new 10T3C light-emitting driving unit circuit, enable the switching between the high and low levels of the output signal to be pulled down without a step-by-step step, thereby avoiding the intermediate voltage from being affected by the transistor threshold voltage or process fluctuation, reducing the falling edge time, accelerating the turn-on speed of the transistor, and reducing the response time of the circuit; in addition, the present invention reduces the number of components of the light-emitting driving circuit by reducing the use of timing control signal lines and transistors, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of the display panel.

[0075] The specific implementation modes of the present invention are further described in detail below with reference to the accompanying drawings.

[0076] like Figure 3As shown, the present invention provides a display panel 10, which includes a display area 11 and a non-display area. Among them, the light-emitting driving circuit 30, the data driver and the scanning driving circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes light-emitting pixels and pixel circuits arranged in an array. The light-emitting pixels emit light under the joint action of the light-emitting driving circuit 30, the data driver, the scanning driving circuit and the pixel circuit.

[0077] like Figure 3 and 4 As shown, the present invention further provides a light-emitting driving circuit 30 , which includes a multi-stage light-emitting driving unit and a timing controller 20 .

[0078] In some embodiments, Figure 5 As shown, the light-emitting driving unit includes 10 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Eout, a first timing control terminal c1, and a second timing control terminal c2. Each level of light-emitting driving unit outputs a light-emitting driving signal, which is input into a row of pixel circuits in the display area 11 of the display panel 10 to drive the row of pixels to emit light. The previous level of light-emitting driving unit simultaneously outputs the light-emitting driving signal to the signal input terminal IN of the next level of light-emitting driving unit as a start signal. Since the last level of light-emitting driving unit does not exist in the next level, the light-emitting driving signal outputted is only input into the pixel circuit of the row.

[0079] Specifically, Figure 4 In the figure, five cascaded light-emitting driving units are taken as an example. The signal input terminal IN1 of the first-stage light-emitting driving unit E1 inputs the start pulse signal STE as an input signal. The signal output terminal Eout1 of the first-stage light-emitting driving unit E1 outputs a light-emitting driving signal as an input signal of the second-stage light-emitting driving unit E2, and the signal output terminal Eout1 of the first-stage light-emitting driving unit E1 is connected to the signal input terminal IN2 of the second-stage light-emitting driving unit E2. The signal output terminal Eout2 of the second-stage light-emitting driving unit E2 outputs a light-emitting driving signal as an input signal of the third-stage light-emitting driving unit E3, and the signal output terminal Eout2 of the second-stage light-emitting driving unit E2 is connected to the signal input terminal IN3 of the third-stage light-emitting driving unit E3. The signal output terminal Eout3 of the third-stage light-emitting driving unit E3 outputs a light-emitting driving signal as an input signal of the fourth-stage light-emitting driving unit E4, and the signal output terminal Eout3 of the third-stage light-emitting driving unit E3 is connected to the signal input terminal IN4 of the fourth-stage light-emitting driving unit E4. The signal output terminal Eout4 of the fourth-stage light-emitting driving unit E4 outputs a light-emitting driving signal as an input signal of the fifth-stage light-emitting driving unit E5, and the signal output terminal Eout4 of the fourth-stage light-emitting driving unit E4 is connected to the signal input terminal IN5 of the fifth-stage light-emitting driving unit E5... The subsequent-stage light-emitting driving units repeat this to form a light-emitting driving circuit 30.

[0080] Figure 6 Show Figure 5 The waveform diagram of the light-emitting driving unit when it is working is shown in FIG. Figures 3 to 6 As shown, the timing controller 20 includes a first timing control signal line CKE1 and a second timing control signal line CKE2. The first timing control signal line CKE1 is used to output a first timing control signal. The second timing control signal line CKE2 is used to output a second timing control signal. The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0081] In some embodiments, Figure 4 As shown, in the first-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the second-level light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. In the third-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the fourth-level light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. In the fifth-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal... and so on, it is obtained that: in the odd-numbered light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal, and the second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the even-numbered light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal, and the second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal.

[0082] In some embodiments of the present invention, Figure 5As shown, each level of light-emitting driving unit specifically includes 10 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Eout, a first timing control terminal c1 and a second timing control terminal c2.

[0083] In this embodiment, specifically, the light-emitting driving unit includes: a first transistor T1 to a tenth transistor T10. Among them, the first electrode of the first transistor T1 is connected to the first power supply VDD, the second electrode is connected to the third node n3, and the gate is connected to the signal input terminal IN. The first electrode of the second transistor T2 is connected to the first node n1, the second electrode is connected to the fourth node n4, and the gate is connected to the third node n3. The first electrode of the third transistor T3 is connected to the third node n3, the second electrode is connected to the second power supply VEE, and the gate is connected to the first timing control terminal c1. The first electrode of the fourth transistor T4 is connected to the fourth node n4, the second electrode is connected to the second timing control terminal c2, and the gate is connected to the second timing control terminal c2. The first electrode of the fifth transistor T5 is connected to the first power supply VDD, the second electrode is connected to the second node n2, and the gate is connected to the first node n1. The first electrode of the sixth transistor T6 is connected to the first power supply VDD, the second electrode is connected to the first node n1, and the gate is connected to the second node n2. The first electrode of the seventh transistor T7 is connected to the first power supply VDD, the second electrode is connected to the signal output terminal Eout, and the gate is connected to the first node n1. The first electrode of the eighth transistor T8 is connected to the signal output terminal Eout, the second electrode is connected to the second power supply VEE, and the gate is connected to the fifth node n5. The first electrode of the ninth transistor T9 is connected to the second node n2, the second electrode is connected to the fifth node n5, and the gate is connected to the second power supply VEE. The first electrode of the tenth transistor T10 is connected to the second node n2, the second electrode is connected to the signal input terminal IN, and the gate is connected to the second timing control terminal c2.

[0084] In this embodiment, the light-emitting driving unit further includes: a first capacitor C1, a second capacitor C2 and a third capacitor C3. The first electrode of the first capacitor C1 is connected to the fifth node n5, and the second electrode is connected to the signal output terminal Eout. The first electrode of the second capacitor C2 is connected to the first power supply VDD, and the second electrode is connected to the first node n1. The first electrode of the third capacitor C3 is connected to the fourth node n4, and the second electrode is connected to the third node n3.

[0085] In this embodiment, the first transistor T1 to the tenth transistor T10 are all P-type MOS transistors. Among them, the control end of the PMOS transistor is the gate, the first pole is the source, the second pole is the drain, or the first pole is the drain, and the second pole is the source. The on level of the PMOS transistor is a low level, and the off level is a high level. In some other embodiments, it is easy for a person skilled in the art to conclude that the light-emitting driving unit provided by the present invention can be easily changed to all N-type MOS transistors. In addition, the light-emitting driving unit provided by the present invention can also be easily changed to a CMOS transistor, etc.

[0086] In some embodiments of the present invention, reference Figures 3 to 6 , Figure 6 The waveform diagram of each stage of two cycles when the light-emitting driving unit of the present invention is working is specifically shown, and the process from t1 to t6 in one cycle is noted. In these stages, the output signal of the signal output terminal Eout of the light-emitting driving unit completes a process from setting to resetting. Figure 6 The waveform and Figure 5 The circuit diagram analyzes the relationship between the input and output of the light-emitting drive unit in the above 6 processes:

[0087] In this embodiment, refer to Figure 5 and 6 , during t1, the signal input terminal IN inputs a high level, the first timing control signal line CKE1 inputs a low level, and the second timing control signal line CKE2 inputs a high level. As a result, the fourth node n4 is written to a high potential, and the third node n3 is written to an intermediate potential. Then the first node n1 is written to a high potential, and the fifth node n5 is written to a low potential. Among them, only the third node n3 and the fifth node n5 have three states: high potential, intermediate potential, and low potential. The same is true for the following stages, which will not be repeated. Finally, the signal output terminal Eout outputs a low potential.

[0088] In this embodiment, refer to Figure 5 and 6 In the process t2, the signal input terminal IN inputs a high level, the first timing control signal line CKE1 inputs a high level, and the second timing control signal line CKE2 inputs a low level. As a result, the fourth node n4 is written to a low potential, and the third node n3 is written to a low potential. Furthermore, the first node n1 is written to a low potential, and the fifth node n5 is written to a high potential. Finally, the signal output terminal Eout outputs a high potential.

[0089] In this embodiment, refer to Figure 5 and 6In the process t3, the signal input terminal IN inputs a high level, the first timing control signal line CKE1 inputs a low level, and the second timing control signal line CKE2 inputs a high level. As a result, the fourth node n4 is written to a low potential, and the third node n3 is written to a low potential. Furthermore, the first node n1 is written to a low potential, and the fifth node n5 is written to a high potential. Finally, the signal output terminal Eout outputs a high potential.

[0090] In this embodiment, refer to Figure 5 and 6 In the process t4, the signal input terminal IN inputs a high level, the first timing control signal line CKE1 inputs a high level, and the second timing control signal line CKE2 inputs a low level. As a result, the fourth node n4 is written to a low potential, and the third node n3 is written to a low potential. Furthermore, the first node n1 is written to a low potential, and the fifth node n5 is written to a high potential. Finally, the signal output terminal Eout outputs a high potential.

[0091] In this embodiment, refer to Figure 5 and 6 In the process of t5, the signal input terminal IN inputs a low level, the first timing control signal line CKE1 inputs a low level, and the second timing control signal line CKE2 inputs a high level. As a result, the fourth node n4 is written to a low potential, and the third node n3 is written to an intermediate potential. Furthermore, the first node n1 is written to a low potential, and the fifth node n5 is written to a high potential. Finally, the signal output terminal Eout outputs a high potential.

[0092] In this embodiment, refer to Figure 5 and 6 In the process of t6, the signal input terminal IN inputs a low level, the first timing control signal line CKE1 inputs a high level, and the second timing control signal line CKE2 inputs a low level. As a result, the fourth node n4 is written to a low potential, and the third node n3 is written to a high potential. Furthermore, the first node n1 is written to a high potential, and the fifth node n5 is written to a low potential. Finally, the signal output terminal Eout outputs a low potential.

[0093] In this embodiment, the light driving unit starts to display the next frame after the process t6, and the start pulse signal STE or the signal input terminal IN inputs a high potential, and re-enters the next round of process t1.

[0094] In this embodiment, the relationship between the input and output of the light-emitting driving unit is: when the start pulse signal STE or the signal input terminal IN inputs a high-level signal at the beginning of a process, the signal output terminal Eout outputs a high-level signal when the next process starts; when the start pulse signal STE or the signal input terminal IN inputs a low-level signal in a process, the signal output terminal Eout outputs a low-level signal when the current process ends and the next process starts. At other times, the signal output by the signal output terminal Eout and the signal input by the start pulse signal STE or the signal input terminal IN are both low-level signals.

[0095] In this embodiment, the light-emitting driving circuit of the present invention provides a new 10T3C light-emitting driving unit circuit, so that the third node n3 and the fifth node n5 have three states of high potential, intermediate potential and low potential, so that the step-type step-down of switching between high and low levels is completed at the third node n3, thereby making the switching between the high and low levels of the output signal of the signal output terminal Eout without step-type step-down, thereby avoiding the intermediate voltage from being affected by the transistor threshold voltage or process fluctuation, reducing the falling edge time, accelerating the turn-on speed of the transistor, and reducing the response time of the circuit. In addition, the present invention reduces the number of components of the light-emitting driving circuit by reducing the use of the timing control signal line and the transistor, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of the display panel.

[0096] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel 10 provided in the embodiment of the present invention. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. The implementation of the display device can refer to the embodiment of the display panel 10 above, and the repeated technical solutions and technical effects will not be repeated.

[0097] In summary, the light-emitting driving circuit and display panel of the present invention provide a new 10T3C light-emitting driving unit circuit, so that the switching between the high and low levels of the output signal is not step-pull-down, thereby avoiding the intermediate voltage from being affected by the transistor threshold voltage or process fluctuations, reducing the falling edge time, accelerating the turn-on speed of the transistor, and reducing the response time of the circuit; in addition, the present invention reduces the number of components of the light-emitting driving circuit by reducing the use of timing control signal lines and transistors, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0098] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A light-emitting driving circuit, characterized in that: A multi-stage light-emitting driving unit is included, and the light-emitting driving unit includes: A first transistor, wherein a first electrode of the first transistor is connected to a first power supply, a second electrode is connected to a third node, and a gate is connected to a signal input terminal; a second transistor, wherein a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the fourth node, and a gate of the second transistor is connected to the third node; a third transistor, wherein a first electrode of the third transistor is connected to the third node, a second electrode of the third transistor is connected to the second power supply, and a gate of the third transistor is connected to the first timing control terminal; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the fourth node, a second electrode of the fourth transistor is connected to the second timing control terminal, and a gate of the fourth transistor is connected to the second timing control terminal; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the first node; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first power supply, a second electrode of the sixth transistor is connected to the first node, and a gate of the sixth transistor is connected to the second node; a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node; an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the second power supply, and a gate of the eighth transistor is connected to the fifth node; a ninth transistor, wherein a first electrode of the ninth transistor is connected to the second node, a second electrode of the ninth transistor is connected to the fifth node, and a gate of the ninth transistor is connected to the second power supply; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the second node, a second electrode of the tenth transistor is connected to the signal input terminal, and a gate of the tenth transistor is connected to the second timing control terminal; a first capacitor, wherein a first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the signal output end; a second capacitor, wherein a first electrode of the second capacitor is connected to the first power supply, and a second electrode of the second capacitor is connected to the first node; A third capacitor, wherein a first electrode of the third capacitor is connected to the fourth node, and a second electrode of the third capacitor is connected to the third node.

2. The light-emitting driving circuit according to claim 1, characterized in that: The invention also includes a timing controller, wherein the timing controller includes a first timing control signal line and a second timing control signal line.

3. The light-emitting driving circuit according to claim 2, characterized in that: The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

4. The light-emitting driving circuit according to claim 3, characterized in that: The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

5. The light-emitting driving circuit according to claim 3, characterized in that: The light-emitting driving unit is used for delaying the signal received from the signal input end under the control of the first timing control signal and the second timing control signal, and the processed signal is outputted from the signal output end.

6. The light-emitting driving circuit according to claim 2, characterized in that: The light-emitting driving unit of the previous stage outputs a light-emitting driving signal to the light-emitting driving unit of the next stage, and the light-emitting driving unit of the last stage outputs a light-emitting driving signal.

7. The light-emitting driving circuit according to claim 6, characterized in that: In the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

8. The light-emitting driving circuit according to claim 7, characterized in that: In the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

9. The light-emitting driving circuit according to claim 1, characterized in that: The first transistor to the tenth transistor are all P-type MOS transistors.

10. A display panel, characterized in that: The invention comprises a light emitting driving circuit according to any one of claims 1 to 9.

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