Control gate voltage generation circuit applied to nonvolatile memory

Abstract

The invention discloses a control gate voltage generation circuit applied to a nonvolatile memory. After the nonvolatile memory leaves a factory, the control gate voltage generating circuit can properly adjust the control gate voltage according to the characteristic change of the memory cell. During a reading action, the control gate voltage generating circuit provides the adjusted control gate voltage to the control gate lines in the array structure so as to ensure that the reference current is between the reading current in the programming state and the reading current in the erasing state, so that the storage state of the selected memory cell can be correctly judged, and the reliability of the memory cell is improved. And the service life of the nonvolatile memory is prolonged.

Description

Technical Field

[0001] The invention relates to an internal circuit of a non-volatile memory, and in particular to a control grid voltage generating circuit used in the non-volatile memory. Background Art

[0002] As we all know, non-volatile memory has been widely used in various electronic products. For example, SD cards, solid state drives (SSDs), etc. Basically, the memory array in the non-volatile memory includes multiple memory cells. The memory cell includes a memory transistor, which can be a charge-trap transistor or a floating gate transistor. The following briefly introduces the structure of the memory cell.

[0003] Please refer to Figure 1A and Figure 1B , which is a cross-sectional view of a memory cell and a schematic diagram of a circuit symbol. The memory cell 100 includes a select transistor (M S ) and a storage transistor M M . With p-type selection transistor M S With the p-type storage transistor M M Let’s take this as an example.

[0004] like Figure 1A As shown, the surface of the N-type well region NW includes three p-doped regions 51, 53, and 55, the gate structure 10 is located on the surface of the N-type well region NW between the p-doped regions 53 and 55, and the gate structure 20 is located on the surface of the N-type well region NW between the p-doped regions 51 and 53. The gate structure 10 includes: a gate dielectric layer 11 and a select gate layer 13. The gate structure 20 includes: a charge storage structure 26 and a control gate layer 27. The charge storage structure 26 also includes: a gate dielectric layer 21, a charge storage layer 23, and an insulating layer 25. Among them, the N-type well region NW, the p-doped regions 53, 55 and the gate structure 10 form a select transistor M. S The N-type well region NW, the p-doped regions 51 and 53 and the gate structure 20 form a storage transistor M.M .

[0005] Furthermore, the selection gate layer 13 and the control gate layer 27 may be polysilicon layers. The gate dielectric layers 11, 21 and the insulating layer 25 may be oxide layers. The charge storage layer 23 may be a nitride layer or a polysilicon layer. In other words, the charge storage structure 26 is an oxide-nitride-oxide (ONO) structure or an oxide-polysilicon-oxide structure. When the charge storage structure 26 is an ONO structure, the storage transistor M M Alternatively, when the charge storage structure 26 is an oxide layer-polysilicon layer-oxide layer structure, the storage transistor M M That is a floating gate transistor.

[0006] Furthermore, the memory cell 100 includes four terminals. The first terminal T1 of the memory cell 100 is electrically connected to the p-doped region 51, the second terminal T2 of the memory cell 100 is electrically connected to the p-doped region 55, and the control gate terminal (T CG ) is electrically connected to the control gate layer 27, the select gate terminal (T SG ) is electrically connected to the selection gate layer 13.

[0007] Therefore, if Figure 1B As shown, the storage transistor M M A charge storage layer 23 is included. Furthermore, the storage transistor M M The first drain / source terminal of the storage transistor M is connected to the first terminal T1 of the memory cell 100. M The second drain / source terminal is connected to the selection transistor M S The first drain / source terminal of the selection transistor M S The second drain / source terminal of the transistor M is connected to the second terminal T2 of the memory cell 100. S The select gate of the memory cell 100 is connected to the select gate terminal T SG , storage transistor M M The control gate of the memory cell 100 is connected to the control gate terminal T CG .

[0008] Basically, by providing appropriate bias voltages to the four terminals of the memory cell 100, the memory cell 100 can be programmed and erased. M When the charge storage layer 23 does not store carriers, the memory cell 100 is in an erase state. M The charge storage layer 23 makes the storage transistor M M The charge storage layer 23 stores carriers, and the memory cell 100 becomes a program state. In addition, when the memory cell 100 is erased, the carriers exit the storage transistor M. M The charge storage layer 23 is formed so that the memory cell 100 is in an erased state. The carriers may be electrons or holes.

[0009] Please refer to Figure 2A , which is a schematic diagram of bias voltage when performing a read action on a memory cell 100 in a programmed state. Figure 2B , which is a schematic diagram of bias voltage when a reading operation is performed on the memory cell 100 in an erased state.

[0010] When performing a read operation on the memory cell 100, a first read voltage (read voltage, V RD1 ) to the first terminal T1, the second read voltage V RD2 To the second terminal T2, provide a start voltage V ON To the select gate terminal T SG , providing control gate voltage V CG_RD To the control gate terminal T CG Among them, the first read voltage V RD1 Greater than the second read voltage V RD2 For example, the first read voltage V RD1 is 2.5V, the second reading voltage V RD2 is 0.5V, the start voltage V ON is 0.5V, the control gate voltage V CG_RD is 2.0V.

[0011] like Figure 2A As shown, when the gate terminal T SG Receiver start voltage V ON When the transistor M is selected S When turned on, a read current I RD_P From the first terminal T1 to the second terminal T2.M The charge storage layer 23 stores carriers (eg, electrons), so the memory cell 100 generates a larger read current I RD_P .

[0012] like Figure 2B As shown, when the gate terminal T SG Receiver start voltage V ON When the transistor M is selected S When turned on, a read current I RD_E From the first terminal T1 to the second terminal T2. M No carriers are stored in the charge storage layer 23, so the memory cell 100 generates a smaller read current I RD_E That is, the read current I RD_E Less than the read current I in the programmed state RD_P .

[0013] For example, a current comparator is designed in a data sensor of a non-volatile memory. The current comparator receives a read current and a reference current I REF , and set the reference current I REF The size of the read current I RD_P And the read current I in the erase state RD_E When reading the current I RD_P Greater than the reference current I REF , the current comparator can determine that the memory cell 100 is in the programming state. RD_E Less than the reference current I REF , the current comparator can determine that the memory cell 100 is in the erase state.

[0014] Furthermore, a plurality of memory cells can be formed into an array structure and matched with peripheral circuits to form a non-volatile memory.

[0015] Please refer to Figure 3 , which is a conventional non-volatile memory 300. The non-volatile memory 300 includes a source line voltage generator 310, a control gate line voltage generator 320, a word line driver 330, a bit line driver 340, a data sensor 350 and an array structure 360.

[0016] The array structure 360 ​​consists of X×Y memory cells c 1，1 ~c X，Y where X and Y are positive integers. For the convenience of explanation, Figure 3 Only two rows are shown in the array structure 360. 1，1 ~c X，Y The structure is the same as Figure 1A and Figure 1B , I will not go into details here.

[0017] In the first row of the array structure 360, Y memory cells c 1，1 ~c 1，Y The first end of Y memory cells c is connected to the source line SL. 1，1 ~c 1，Y The second end of the bit line is connected to the corresponding bit line BL1~BL Y , Y memory cells c 1，1 ~c 1，Y The select gate terminal of Y memory cells c is connected to the word line WL1. 1，1 ~c 1，Y The control gate terminal of the memory cell c is connected to the control gate line CGL. Similarly, in the second row of the array structure 360, the Y memory cells c 2，1 ~c 2，Y The first end of Y memory cells c is connected to the source line SL. 2，1 ~c 2，Y The second end of the bit line is connected to the corresponding bit line BL1~BL Y , Y memory cells c 2，1 ~c 2，Y The select gate terminal of Y memory cells c is connected to the word line WL2. 2，1 ~c 2，Y The control gate terminal of the memory cell is connected to the control gate line CGL. And so on. That is, in the array structure 360, all memory cells c 1，1 ~c X，Y Both are connected to the source line SL and the control gate line CGL.

[0018] The source line voltage generator 310 is connected to the source line SL, and the control gate line voltage generator 320 is connected to the control gate line CGL. The word line driver 330 is connected to the word lines WL1~WL Y The bit line driver 340 is connected to the bit lines BL1 to BL Y Furthermore, the data sensor 350 is connected to the bit line driver 340, and the data sensor 350 can generate output data D OUT .

[0019] Basically, the source line voltage generator 310 and the control gate line voltage generator 320 can provide appropriate voltages so that the nonvolatile memory 300 can control the memory cells in the array structure 360. 1，1 ~c X，Y Perform a program action, erase action, or read action. The read action is used as an example to illustrate.

[0020] During the reading operation, the source line voltage generator 310 provides a first reading voltage V RD1 (e.g., 2.5V) to the source line SL, the control gate line voltage generator 320 provides the control gate voltage V CG_RD (e.g., 2.0V) to the control gate line CGL. Furthermore, the word line driver 330 activates X word lines WL1-WL X The bit line driver 340 can activate at least one of the bit lines BL1-BL Y , to determine the selected memory cell in the selected row.

[0021] For example, the word line driver 330 provides a turn-on voltage V ON (e.g. 0.5V) to word line WL1 and provide a shutdown voltage V OFF (e.g. 2.5V) to other word lines WL2~WL X At this time, the word line driver 330 activates the word line WL1, and the first row in the array structure 360 ​​is the selected row. Furthermore, when the bit line driver 340 only provides the second read voltage V RD2 When the voltage (e.g., 0.5V) is applied to the bit line BL1, it means that the bit line driver 340 only operates the bit line BL1, and only the memory cell c is selected on the row. 1，1 Furthermore, the bit line driver 340 also selects the memory cell c 1，1 The generated read current is transmitted to the data sensor 350. Therefore, the data sensor 350 compares the selected memory cell c 1，1 The read current and reference current are used to determine the selected memory cell c 1，1 The storage state and generate one bit of output data D OUT .

[0022] Of course, the bit line driver 340 can also provide a second read voltage V RD2 (e.g., 0.5V) to the bit lines BL1-BL8 to activate the bit lines BL1-BL8 so that the memory cells c on the selected row1，1 ~c 1，8 Furthermore, the bit line driver 340 also selects the memory cell c 1，1 ~c 1，8 The generated read current is transmitted to the data sensor 350. The data sensor 350 can output one byte of output data D OUT , representing eight selected memory cells c 1，1 ~c 1，8 storage status.

[0023] In addition to the reading operation, during the programming operation and the erasing operation, the source line voltage generator 310 and the control gate line voltage generator 320 will provide corresponding voltages to the source line SL and the control gate line CGL. For example, during the programming operation, the control gate line voltage generator 320 will provide the control gate voltage V CG_PGM To the control gate line CGL. During the erase operation, the control gate line voltage generator 320 provides a control gate voltage V CG_ERS To the control gate line CGL. For example, the control gate voltage V CG_PGM is 8.0V, the control gate voltage V CG_ERS is -10V.

[0024] Generally speaking, after a memory cell has been programmed and erased for many times, the characteristics of the memory cell will deteriorate. When the characteristics of the memory cell deteriorate, the read current I RD_P will become smaller, and the read current I generated by the erased state memory cell RD_E Will get bigger.

[0025] Please refer to Figure 4 , which shows the relationship between the program / erase cycling time (P / E cycling time) and the read current of a known memory cell. Basically, after the known non-volatile memory leaves the factory, the reference current I REF and the control gate voltage V CG_RD All settings are completed. For example, the reference current I REF Set to 10μA, control gate voltage V CG_RD Set to 2.0V. That is to say, it is known that after the non-volatile memory leaves the factory, when performing a read operation, the reference current I REF and the control gate voltage V CG_RD Nothing will change anymore.

[0026] like Figure 4As shown, when the P / E times of the memory cell are less than S1 times, for example, before the P / E times are less than 300 times, the memory cell has better characteristics, and the read current I generated by the memory cell in the programming state RD_P The maximum is about 20μA, and the read current I generated by the erased state memory cell is RD_E The smaller is almost equal to 0. Therefore, the data sensor 350 can use the reference current I REF The storage state of the selected memory cell is determined by the magnitude of the read current.

[0027] When the P / E times of the memory cell 100 exceed S1 times but have not reached S2 times, for example, when the P / E times exceed 300 times but have not reached 1000 times, the characteristics of the memory cell will gradually degrade as the P / E times increase. RD_P The magnitude will gradually decrease, and the read current I generated by the erased state memory cell RD_E The value will gradually increase, and the data sensor 350 can still use the reference current I REF The storage state of the selected memory cell is determined by the magnitude of the read current.

[0028] When the P / E times of the memory cell exceed S2 times, for example, when the P / E times exceed 1000 times, the read current I generated by the memory cell in the programmed state RD_P The size will be smaller than the reference current I REF That is, during the reading operation, the memory cell in the programmed state may be misjudged as being in the erased state by the data sensor 350, and a read fail may occur.

[0029] As is known to all, after non-volatile memory is shipped out of the factory, the characteristics of the memory cell will inevitably deteriorate gradually. How to continuously and correctly determine the storage state of the memory cell during the deterioration of the memory cell to extend the life of the non-volatile memory is the purpose of the present invention. Summary of the invention

[0030] The present invention relates to a control gate voltage generating circuit used in a non-volatile memory. The non-volatile memory cell includes an array structure, the array structure is connected to a source line and a control gate line, the control gate voltage generating circuit is connected to the control gate line, and the control gate voltage generating circuit includes: 2N reference memory cells, a first end of the 2N reference memory cells is connected to the source line, a control gate end of the 2N reference memory cells is connected to the control gate line, a selection gate end of the 2N reference memory cells is connected to a reference word line, and a second end of the 2N reference memory cells is connected to corresponding 2N reference bit lines, wherein N is a positive integer; a switch circuit, connected to the 2N reference bit lines; wherein, in a reading action, the source line receives a first reading voltage, the reference word line receives a turn-on voltage, the switch circuit connects the 2N reference bit lines to a first node, and the 2N reference memory cells generate a total current to the first node ; wherein a first number of the 2N reference memory cells are in a programmed state, a second number of the 2N reference memory cells are in an erased state, the sum of the first number and the second number is equal to 2N, and the read current generated by the first number of reference memory cells plus the read current generated by the second number of reference memory cells is equal to the total current; a current mirror, a current input terminal of the current mirror receives a reference current, a current mirror terminal of the current mirror is connected to the first node, for receiving the total current; wherein the ratio of the reference current to the total current is 1 / (2N); and, a voltage tracking circuit, having a first input terminal, a second input terminal and an output terminal; wherein the first input terminal of the voltage tracking circuit receives a second read voltage, the second input terminal of the voltage tracking circuit is connected to the first node, and the output terminal of the voltage tracking circuit generates a first control gate voltage and transmits it to the control gate line.

[0031] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1A and Figure 1B is a cross-sectional view of a memory cell and a schematic diagram of its circuit symbols;

[0033] Figure 2A is a schematic diagram of bias voltage when performing a read action on a memory cell 100 in a programmed state;

[0034] Figure 2B A schematic diagram of bias voltage when performing a reading operation on the memory cell 100 in an erased state;

[0035] Figure 3is a known non-volatile memory;

[0036] Figure 4 A schematic diagram showing the relationship between the number of program-erase times (P / E times) and the read current of a known memory cell;

[0037] Figure 5 The control gate voltage generating circuit of the first embodiment of the present invention;

[0038] Figure 6 A schematic diagram of the relationship between the number of program-erase times (P / E times) and the read current of the memory cell of the present invention; and

[0039] Figure 7 This is a control gate voltage generating circuit according to a second embodiment of the present invention.

[0040]

Explanation of symbols

[0041] 10, 20: Gate structure

[0042] 11, 21: Gate dielectric layer

[0043] 13: Select gate layer

[0044] 26: Charge storage structure

[0045] 23: Charge storage layer

[0046] 25: Insulation layer

[0047] 27: Control gate layer

[0048] 100: Memory Cell

[0049] 300: Non-volatile memory

[0050] 310: Source line voltage generator

[0051] 320: Control gate line voltage generator

[0052] 330: Word line driver

[0053] 340: Bit line driver

[0054] 350: Data Sensor

[0055] 360, 560: Array structure

[0056] 500, 600: Control gate voltage generating circuit

[0057] 510: Current Mirror

[0058] 520, 620: Voltage tracking circuit

[0059] 525: Operational Amplifier

[0060] 530: Select Circuit

[0061] 540, 640: Switching circuit

[0062] 550: Sensing circuit

[0063] 625: Comparator

[0064] 627: Controller

[0065] 629: Multiplexer DETAILED DESCRIPTION

[0066] The present invention provides a control gate voltage generating circuit for use in a non-volatile memory. The control gate voltage generating circuit can replace Figure 3 The control gate line voltage generator 320 of the known nonvolatile memory 300 is combined with the control gate line voltage generator 320 of the known nonvolatile memory 300 to form a new nonvolatile memory.

[0067] Basically, during the read operation, the gate voltage V CG_RD The amount of carriers stored in the charge storage layer 23 will affect the storage transistor M in the memory cell. M The opening degree of the storage transistor M M The degree of opening will be related to the magnitude of the read current.

[0068] According to an embodiment of the present invention, after the non-volatile memory is shipped out of the factory, the control gate voltage generating circuit can appropriately adjust the control gate voltage V according to the change of the memory cell characteristics. CG_RD During the reading operation, the reference current I REF is a fixed current, the control gate voltage generating circuit will adjust the control gate voltage V CG_RD Provided to the control gate line CGL in the array structure. This adjusted control gate voltage V CG_RD The read current I of the erase state will be forced to control RD_E Less than the reference current I REF , and forcibly controls the read current I of the programming state RD_P Greater than the reference current I REF Therefore, it can be ensured that the reference current I REF The magnitude of the read current I RD_P And the read current I in the erase state RD_E Therefore, the storage state of the selected memory cell can be correctly determined and the lifetime of the non-volatile memory can be extended.

[0069] Please refer to Figure 5, which illustrates a control gate voltage generating circuit according to a first embodiment of the present invention.

[0070] like Figure 5 As shown, the control gate voltage generating circuit 500 includes a current mirror 510, a voltage tracking circuit 520, a selecting circuit 530, and reference memory cells c1-c 2N , a switching circuit 540, and a sensing circuit 550. Among them, 2N reference memory cells c1-c 2N The nonvolatile memory array structure 560 is designed in the nonvolatile memory array structure 560. That is, the nonvolatile memory array structure 560 includes two parts. The first part includes X×Y memory cells c 1，1 ~c X，Y (not shown), the second part includes 2N reference memory cells c1~c 2N The first part of the X×Y memory cells c 1，1 ~c X，Y The circuit is similar to Figure 3 , and its structure will not be described here. In addition, refer to the memory cells c1~c 2N The structure is the same as Figure 1A and Figure 1B Furthermore, N is a positive integer, for example, N is equal to 8.

[0071] 2N reference memory cells c1~c 2N The first end of the memory cell c1~c 2N The second end is connected to the corresponding reference bit line BL R1 ~BL R2N , 2N reference memory cells c1~c 2N The select gate terminal is connected to the reference word line WL REF , 2N reference memory cells c1~c 2N The control gate terminal of is connected to the control gate line CGL, and the control gate line CGL is connected to the node a.

[0072] The switch circuit 540 receives the control signal Ctrl1. Furthermore, the switch circuit 540 includes 2N switches sw1-sw 2N , 2N switches sw1~sw 2N The first end is connected to the corresponding 2N reference bit lines BL R1 ~BL R2N, the second ends of the 2N switches sw1 are connected to the node c, and the third ends of the 2N switches sw1 are connected to the sensing circuit 550. The 2N switches sw1~sw 2N All of them operate according to the control signal Ctrl1. For example, during the reading operation, the control signal Ctrl1 controls 2N switches sw1~sw 2N The first terminal is connected to the second terminal. In addition, during programming and erasing operations, the control signal Ctrl1 controls 2N switches sw1~sw 2N Connect the first terminal to the third terminal. That is, during the read operation, all reference bit lines BL R1 ~BL R2N All reference bit lines BL are connected to node c. During a programming action (including a programming verification action) or an erasing action (including an erasing verification action), all reference bit lines BL R1 ~BL R2N It is connected to the sensing circuit 550 for performing program verification operation and erase verification operation.

[0073] The current mirror 510 has a current input terminal and a current mirroring terminal. The current input terminal is connected to the node b, the current mirroring terminal is connected to the node c, and the current input terminal receives the reference current I REF . Furthermore, the current mirror 510 includes transistors M1 and M2, and the size ratio of the transistors M1 and M2 is 1:2N. The first drain / source terminal of the transistor M1 is connected to the node b, the second drain / source terminal of the transistor M1 is connected to the ground terminal GND, and the gate terminal of the transistor M2 is connected to the node b. The first drain / source terminal of the transistor M2 is connected to the node c, the second drain / source terminal of the transistor M2 is connected to the ground terminal GND, and the gate terminal of the transistor M2 is connected to the node b.

[0074] The voltage tracking circuit 520 is connected to the node c and receives the second read voltage V RD2 During the reading operation, the voltage tracking circuit 520 can further output the control gate voltage V CG_RD For example, the voltage tracking circuit 520 includes an operational amplifier 525. The negative input terminal of the operational amplifier 525 receives the second read voltage V RD2 The positive input terminal of the operational amplifier 525 is connected to the node c, and the output terminal of the operational amplifier 525 generates the control gate voltage V CG_RDBasically, the operational amplifier 525 generates a control gate voltage V according to the voltage difference between the positive input terminal and the negative input terminal. CG_RD .

[0075] The selection circuit 530 has three input terminals, the first input terminal, the second input terminal and the third input terminal respectively receiving the control gate voltage V CG_RD 、V CG_PGM 、V CG_ERS , the control end of the selection circuit 530 receives the control signal Ctrl2, and the output end of the selection circuit 530 is connected to the node a. According to the control signal Ctrl2, the selection circuit 530 sets the three control gate voltages V CG_RD 、V CG_PGM 、V CG_ERS One of them is transmitted to node a. Node a is the output terminal of the control gate voltage generating circuit 500. For example, during the reading operation, the first input terminal of the selection circuit 530 is connected to node a, and the control gate voltage generating circuit 500 outputs the control gate voltage V CG_RD To the control gate line CGL, and used for reading operation (gate control voltage V CG_RD During programming, the second input terminal of the selection circuit 530 is connected to the node a, and the control gate voltage generating circuit 500 outputs the control gate voltage V CG_PGM To the control gate line CGL, and used for programming action (gate controlvoltage V CG_PGM During the erase operation, the third input terminal of the selection circuit 530 is connected to the node a, and the control gate voltage generating circuit 500 outputs the control gate voltage V CG_ERS To the control gate line CGL, and used for erase operation (gate control voltage V CG_ERS for erase).

[0076] According to the first embodiment of the present invention, during the programming operation, the control gate voltage generating circuit 500 outputs the control gate voltage V CG_PGM , is transmitted to the array structure 560 of the non-volatile memory via the control gate line CGL, so that the non-volatile memory can perform programming operations. During the erasing operation, the control gate voltage generating circuit 500 outputs the control gate voltage V CG_ERS , is transmitted to the array structure 560 of the non-volatile memory via the control gate line CGL, so that the non-volatile memory can perform an erase operation. That is, during the programming operation and the erase operation, the operation mode of the control gate voltage generating circuit 500 is similar to Figure 3 The control gate line generator 320 of the nonvolatile memory 300 .

[0077] As mentioned above, since the reference memory cells c1~c 2N Designed in the array structure 560, the non-volatile memory can also reference the word line WL during programming. REF and the reference bit line BL R1 ~BL R2N , used to selectively program part of the reference memory cells c1~c 2N Of course, during the erase operation, the reference memory cells c1~c 2N Furthermore, during programming and erasing, the operation of the sensing circuit 550 is similar to Figure 3 According to the first embodiment of the present invention, in the 2N reference memory cells c1-c 2N In the example, N reference memory cells are programmed to a programmed state, and another N reference memory cells are erased to an erased state. N In the programming state, the other N reference memory cells c N+1 ~c 2N The state is erased.

[0078] During the reading operation, the control gate voltage generating circuit 500 of the present invention can appropriately adjust the control gate voltage V according to the change of the memory cell characteristics. CG_RD , to forcibly control the reading current I RD_E Less than the reference current I REF , and forcibly controls the reading current I RD_P Greater than the reference current I REF The following is a detailed description of the operating principle of the control gate voltage generating circuit 500 during the reading operation.

[0079] like Figure 5 As shown, during the reading operation, the source line SL receives the first reading voltage V RD1 Furthermore, a start voltage V ON To the reference word line WL REF , with action reference word line WL REF , and make 2N reference memory cells c1~c 2N In addition, the selection circuit 530 connects the output terminal of the operational amplifier 525 to the node a, and the switch circuit 540 turns on all reference bit lines BL R1 ~BL R2N Connected to node c. That is, 2N reference bit lines BL R1 ~BL R2N Connected to the current mirror emitter terminal of the current mirror 510 .

[0080] Since 2N reference memory cells c1~c 2N In the N reference memory cells c1~c N In the programming state, the other N reference memory cells c N+1 ~c 2N Therefore, the 2N reference memory cells c1~c 2N The total current (I TOTAL ) is [N×(I RD_P +I RD_E )]. That is, the read current I generated by the reference memory cells in the N programming states RD_P Add the read current I generated by N erased memory cells RD_E That is the total current I TOTAL .

[0081] As is known to all, the input impedance of the operational amplifier 525 is infinite, so the total current I TOTAL will not flow into the positive input terminal of the operational amplifier 525, and the total current I TOTAL The current will flow to the current mirror emitter terminal of the current mirror 510.

[0082] In the current mirror 510, since the size ratio of the transistors M1 and M2 is 1:2N, the reference current I REF With the total current I TOTAL The ratio is 1 / (2N). That is, [2N×I REF =N×(I RD_P +I RD_E )]. Therefore, (I RD_P +I RD_E ) / 2=I REF .

[0083] In addition, due to negative feedback, the voltage at the positive input terminal of the operational amplifier 525 will eventually be almost the same as the voltage at the negative input terminal, that is, all 2N reference bit lines BL R1 ~BL R2N The voltage will eventually be equal to the second read voltage V RD2 .

[0084] According to an embodiment of the present invention, the negative feedback amplifier 525 adjusts the control gate voltage V CG_RD To control 2N reference memory cells c1~c 2NFurthermore, the negative feedback operational amplifier 525 will maintain the proportional relationship between the current input terminal and the current mirror terminal. That is, when the 2N reference bit lines BL R1 ~BL R2N The voltage is equal to the second read voltage V RD2 When (I RD_P +I RD_E ) / 2= I REF relationship.

[0085] Obviously, due to the read current I RD_P will be greater than the read current I in the erase state RD_E So the control gate voltage V CG_RD To control the read current I of the programming state RD_P And the read current I in the erase state RD_E The size of the reference current I REF The size will be between the read current I RD_P And the read current I in the erase state RD_E between.

[0086] Furthermore, the control gate voltage V CG_RD will also be transmitted to node a, so that the control gate voltage generating circuit 500 outputs the adjusted control gate voltage V CG_RD The current I is transmitted to the selected memory cell in the array structure 560 via the control gate line CGL. Therefore, if the selected memory cell is in the programmed state, the read current I RD_P will be greater than the reference current I REF If the selected memory cell is in the erase state, the read current I RD_E Will be less than the reference current I REF That is, using the reference current I REF The storage state of the selected memory cell can be correctly determined.

[0087] According to the above description, during the reading operation, the control gate voltage V output by the voltage tracking circuit 520 is CG_RD It is composed of 2N reference memory cells c1~c 2N The non-volatile memory needs to ensure that 2N reference memory cells c1~c 2N has poor characteristics, so that the control gate voltage generating circuit 500 outputs an appropriate control gate voltage V CG_RD to the control gate line CGL. The control gate voltage V CG_RD The first portion of the X×Y memory cells c in the nonvolatile memory array structure 560 may be further transmitted. 1，1 ~cX，Y To perform a read action, a program verification action, or an erase verification action.

[0088] In addition, when the nonvolatile memory array structure 560 has a memory cell c 1，1 ~c X，Y When performing an erase operation, the 2N reference memory cells c1-c 2N An erase operation is also required. In order to make the 2N reference memory cells c1~c 2N The characteristics are poor. N reference memory cells in the erased state can be programmed to become the programmed state, so that all 2N reference memory cells c1~c 2N Then, the reference memory cells c1~c 2N Performing the erase operation will ensure that 2N reference memory cells c1~c 2N The P / E times will increase by 1. After the above-mentioned erasing operation is completed, the non-volatile memory performs programming operation on N reference memory cells to become the programmed state, while the other N reference memory cells remain in the erased state. Therefore, among the 2N reference memory cells c1~c 2N In the embodiment, N reference memory cells are maintained in a programmed state, while the other N reference memory cells are maintained in an erased state. That is, compared to the X×Y memory cells c in the array structure 560, 1，1 ~c X，Y , 2N reference memory cells c1~c 2N The P / E times will be larger, representing 2N reference memory cells c1~c 2N Has poor characteristics.

[0089] Please refer to Figure 6 , which is a schematic diagram showing the relationship between the number of programming and erasing times (P / E times) of the memory cell of the present invention and the read current.

[0090] When the P / E times of the memory cell are less than S1 times, for example, before the P / E times are less than 300 times, the memory cell has better characteristics, and the read current I RD_P The maximum is about 20μA, and the read current I RD_E is smaller and almost equal to 0. At this time, the control gate voltage V CG_RD There is almost no change of about 2.0V, using the reference current I REF The storage state of the selected memory cell can be correctly determined by the magnitude of the read current.

[0091] When the P / E times of the memory cell 100 exceed S1 times but have not reached S2 times, for example, the P / E times exceed 300 times but have not reached 1000 times, the characteristics of the memory cell will gradually degrade as the P / E times increase. RD_P The size will gradually decrease, and the read current I RD_E The size will gradually increase. At this time, the control gate voltage V CG_RD Also gradually decreases, and using the reference current I REF The size of the read current can still correctly determine the storage state of the selected memory cell.

[0092] When the P / E times of the memory cell exceed S2 times, for example, the P / E times exceed 1000 times. The control gate voltage V CG_RD It also drops to about 1.05V to further turn on the floating gate transistor in the memory cell. REF The size of the read current can still correctly determine the storage state of the selected memory cell.

[0093] From the above description, it can be seen that the present invention provides a control gate voltage generating circuit for non-volatile memory. After the non-volatile memory is shipped, the control gate voltage generating circuit can appropriately adjust the control gate voltage V according to the change of memory cell characteristics. CG_RD During the reading operation, the control gate voltage generating circuit adjusts the control gate voltage V CG_RD Provided to the control gate line CGL in the array structure 560 to ensure that the reference current I REF The size will be between the read current I RD_P And the read current I in the erase state RD_E Therefore, the storage state of the selected memory cell can be correctly determined and the life time of the non-volatile memory can be extended.

[0094] In the control gate voltage generating circuit 500 of the first embodiment, 2N reference memory cells c1-c 2NHalf of the reference memory cells will be controlled in the programming state, while the other N reference memory cells will be controlled in the erased state. In fact, the present invention does not limit the number of reference memory cells in the programming state to be equal to the number of reference memory cells in the erased state. The present invention only needs to set a specific proportional relationship between the number of reference memory cells in the programming state and the number of reference memory cells in the erased state. For example, a first number of reference memory cells are controlled to be in the programming state, and a second number of reference memory cells are controlled to be in the erased state. Among them, the first number and the second number are both positive integers greater than zero, the first number may be equal to or not equal to the second number, and the sum of the first number and the second number is equal to 2N. In addition, during the reading operation, the total current I generated by the 2N reference memory cells is also TOTAL is input to the current mirror 510. Therefore, the control gate voltage V CG_RD Adjustments can be made so that the storage state of the selected memory cell can be correctly determined.

[0095] In addition, since the operating principle of the switch circuit 540 is similar to that of the bit line driver in the non-volatile memory, the switch circuit of the present invention can be designed in the bit line driver. Similarly, the operating principle of the sensing circuit 550 is similar to that of the data sensor in the non-volatile memory, so the sensing circuit 550 of the present invention can be designed in the data sensor.

[0096] exist Figure 5 In the first embodiment, the voltage tracking circuit 520 is implemented by using an analog operational amplifier 525. In fact, the voltage tracking circuit 520 can also be implemented by using a digital circuit.

[0097] Please refer to Figure 7 , which illustrates a control gate voltage generating circuit according to a second embodiment of the present invention.

[0098] The control gate voltage generating circuit 600 includes a current mirror 510, a voltage tracking circuit 620, a selection circuit 530, and reference memory cells c1-c 2N , switch circuit 640, and sensing circuit 550. Compared with the first embodiment, the difference lies in the voltage tracking circuit 620. In addition, the second embodiment further illustrates the detailed circuit of the switch circuit 640. Of course, technicians in this field can also use other electronic components to implement the switch circuit. The following only introduces the voltage tracking circuit 620 and the switch circuit 640. The other circuits are the same as the first embodiment and will not be repeated.

[0099] The switch circuit 640 receives a control signal Ctrl1, and the control signal Ctrl1 includes two sub-control signals Ctrl 1_1 , Ctrl 1_2 The switch circuit 640 includes 2N switches sw1~sw2N , 2N switches sw1~sw 2N The structures of the switch sw1 are the same. The switch sw1 includes two transistors m1 and t1. N It includes two transistors m N ,t N . Switch sw N+1 It includes two transistors m N+1 ,t N+1 . Switch sw 2N It includes two transistors m 2N ,t 2N .

[0100] Taking switch sw1 as an example, the first drain / source terminal of transistor m1 is connected to the reference bit line BL R1 , the second drain / source terminal of transistor m1 is connected to node c, and the gate terminal of transistor m1 receives the sub-control signal Ctrl 1_1 Furthermore, the first drain / source terminal of transistor t1 is connected to the reference bit line BL R1 The second drain / source terminal of transistor t1 is connected to the sensing circuit 550, and the gate terminal of transistor t1 receives the sub-control signal Ctrl 1_2 When reading an action, the sub-control signal Ctrl 1_1 Action and sub-control signal Ctrl 1_2 No action, all reference bit lines BL R1 ~BL R2N Connect to node c. During programming or erasing, the sub-control signal Ctrl 1_1 No action and sub-control signal Ctrl 1_2 action, all reference bit lines BL R1 ~BL R2N Connected to sensing circuit 550 .

[0101] The voltage tracking circuit 620 is connected to the node c and receives the second read voltage V RD2 During the reading operation, the voltage tracking circuit 620 can further output the control gate voltage V CG_RD The voltage tracking circuit 620 includes a comparator 625 , a controller 627 , and a multiplexer 629 .

[0102] The negative input terminal of the comparator 625 receives the second read voltage V RD2, the positive input terminal of the comparator 625 is connected to the node c, and the output terminal of the comparator 625 generates a comparison output signal CMP. That is, the comparator 625 generates the comparison output signal CMP according to the voltage difference between the positive input terminal and the negative input terminal. The controller 627 receives the comparison output signal CMP, and generates a control signal Ctrl3 to the multiplexer 629 according to the comparison output signal CMP. Furthermore, the multiplexer 629 has multiple input terminals, which receive different input voltages, such as 2.0V, 1.8V...0.2V, respectively. The output terminal of the multiplexer 629 is connected to the first input terminal of the selection circuit 530. According to the control signal Ctrl3 of the controller 627, the multiplexer 629 transmits one of the multiple input voltages to the output terminal of the multiplexer and serves as the control gate voltage V CG_RD .

[0103] For example, during a read operation, when the voltage at the positive input terminal of the comparator 625 (ie, the voltage at the node c) is less than the second read voltage V RD2 When the controller 627 controls the multiplexer 629 to reduce the output control gate voltage V according to the comparison output signal CMP, CG_RD , to increase the total current I TOTAL On the contrary, when the voltage at the positive input terminal of the comparator 625 (ie, the voltage at the node c) is greater than the second read voltage V RD2 When the controller 627 controls the multiplexer 629 to increase the output control gate voltage V according to the comparison output signal CMP, CG_RD , to reduce the total current I TOTAL .

[0104] Therefore, the control gate voltage generating circuit 600 of the second embodiment of the present invention can appropriately adjust the control gate voltage V CG_RD .

[0105] In summary, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A control gate voltage generating circuit for a non-volatile memory, the non-volatile memory cell comprising an array structure, the array structure being connected to a source line and a control gate line, the control gate voltage generating circuit being connected to the control gate line, and the control gate voltage generating circuit comprising: 2N reference memory cells, wherein first terminals of the 2N reference memory cells are connected to the source line, control gate terminals of the 2N reference memory cells are connected to the control gate line, select gate terminals of the 2N reference memory cells are connected to the reference word line, and second terminals of the 2N reference memory cells are connected to corresponding 2N reference bit lines, wherein N is a positive integer; a switch circuit connected to the 2N reference bit lines; wherein, during a read operation, the source line receives a first read voltage, the reference word line receives a turn-on voltage, the switch circuit connects the 2N reference bit lines to a first node, and the 2N reference memory cells generate a total current to the first node; wherein a first number of the reference memory cells among the 2N reference memory cells are in a programmed state, a second number of the reference memory cells among the 2N reference memory cells are in an erased state, the sum of the first number and the second number is equal to 2N, and the read current generated by the first number of the reference memory cells plus the read current generated by the second number of the reference memory cells is equal to the total current; a current mirror, wherein a current input terminal of the current mirror receives a reference current, and a current mirror emitter terminal of the current mirror is connected to the first node for receiving the sum current; wherein a ratio of the reference current to the sum current is 1 / (2N); and A voltage tracking circuit has a first input terminal, a second input terminal and an output terminal; wherein the first input terminal of the voltage tracking circuit receives a second read voltage, the second input terminal of the voltage tracking circuit is connected to the first node, and the output terminal of the voltage tracking circuit generates a first control gate voltage and transmits it to the control gate line.

2. The control gate voltage generating circuit as claimed in claim 1, further comprising: A selection circuit, wherein the first input terminal of the selection circuit is connected to the output terminal of the voltage tracking circuit, and the output terminal of the selection circuit is connected to the control gate line; wherein, during the reading action, the first input terminal of the selection circuit is connected to the output terminal of the selection circuit, so that the first control gate voltage is transmitted to the control gate line and applied to the reading action.

3. The control gate voltage generating circuit as claimed in claim 2, wherein the selection circuit further comprises: A second input terminal, receiving a second control gate voltage; as well as A third input terminal receives a third control gate voltage; In which, during the programming action, the second end of the selection circuit is connected to the output end of the selection circuit, so that the control gate line outputs the second control gate voltage and is used in the programming action; during the erasing action, the third end of the selection circuit is connected to the output end of the selection circuit, so that the control gate line outputs the third control gate voltage and is used in the erasing action.

4. The control gate voltage generating circuit as claimed in claim 1, wherein a first reference memory cell among the 2N reference memory cells comprises: A storage transistor, wherein a first drain / source terminal of the storage transistor serves as the first terminal of the first reference memory cell, and a control gate of the storage transistor serves as the control gate terminal of the first reference memory cell; as well as A selection transistor, the first drain / source terminal of the selection transistor is connected to the second drain / source terminal of the storage transistor, the second drain / source terminal of the selection transistor serves as the second terminal of the first reference memory cell, and the selection gate of the selection transistor serves as the selection gate terminal of the first reference memory cell. 5 . The control gate voltage generating circuit as claimed in claim 4 , wherein the storage transistor is a charge trapping transistor or a floating gate transistor.

6. The control gate voltage generating circuit as described in claim 1, wherein among the 2N reference memory cells, N reference memory cells are in the programmed state and the other N memory cells are in the erased state; and the read current generated by the N reference memory cells in the programmed state plus the read current generated by the N memory cells in the erased state is the total current.

7. The control gate voltage generating circuit as described in claim 6, wherein when the multiple memory cells in the array structure are erased, the 2N reference memory cells are also erased; and, after the erase, N reference memory cells among the 2N reference memory cells are programmed and become the programmed state, and the other N memory cells are maintained in the erased state.

8. The control gate voltage generating circuit as claimed in claim 1, wherein the current mirror comprises: a first transistor, wherein a first drain / source terminal of the first transistor serves as the current input terminal of the current mirror, a second drain / source terminal of the first transistor is connected to a ground terminal, and a gate terminal of the first transistor is connected to the first drain / source terminal of the first transistor; as well as a second transistor, wherein a first drain / source terminal of the second transistor serves as the current mirror end of the current mirror, a second drain / source terminal of the second transistor is connected to the ground end, and a gate terminal of the second transistor is connected to the gate terminal of the first transistor; The size ratio of the first transistor to the second transistor is 1:2N.

9. The control gate voltage generating circuit as claimed in claim 1, wherein the voltage tracking circuit comprises: An operational amplifier is provided, wherein a negative input terminal of the operational amplifier receives the second read voltage, a positive input terminal of the operational amplifier is connected to the first node, and an output terminal of the operational amplifier generates the first control gate voltage.

10. The control gate voltage generating circuit as claimed in claim 1, wherein the voltage tracking circuit comprises: A comparator, wherein a negative input terminal of the comparator receives the second read voltage, a positive input terminal of the comparator is connected to the first node, and an output terminal of the comparator generates a comparison output signal; A controller receives the comparison output signal and generates a control signal; as well as A multiplexer, wherein the multiple input terminals of the multiplexer receive multiple input voltages, and the multiplexer transmits one of the input voltages to the output terminal of the multiplexer as the first control grid voltage according to the control signal.

11. The control gate voltage generating circuit as described in claim 1 further includes a sensing circuit connected to the switch circuit, and the sensing circuit receives the reference current, and during a programming action or an erasing action, the switch circuit connects the 2N reference bit lines to the sensing circuit.

12. The control gate voltage generating circuit as claimed in claim 11, wherein the switch circuit comprises: 2N switches, the first ends of the 2N switches are connected to the corresponding 2N reference bit lines, the second ends of the 2N switches are connected to the first node, and the third ends of the 2N switches are connected to the sensing circuit; wherein, during the reading action, the first end of each of the 2N switches is connected to the second end; and, during the programming action or the erasing action, the first end of each of the 2N switches is connected to the third end.

13. The control gate voltage generating circuit as claimed in claim 12, wherein a first switch of the 2N switches comprises: a first transistor, a first drain / source terminal of the first transistor being connected to a first reference bit line, a second drain / source terminal of the first transistor being connected to the first node, and a gate terminal of the first transistor receiving a first sub-control signal; as well as a second transistor, a first drain / source terminal of the second transistor being connected to the first reference bit line, a second drain / source terminal of the second transistor being connected to the sensing circuit, and a gate terminal of the second transistor receiving a second sub-control signal; Wherein, during the reading action, the first sub-control signal is in action, the second sub-control signal is inactive, and the first reference bit line is connected to the first node; During the programming action or the erasing action, the first sub-control signal is inactive, the second sub-control signal is active, and the first reference bit line is connected to the sensing circuit.

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