Manufacturing method of shield gate device
The defects are repaired by etching and removing the nail head structure and recrystallization, and the interface cavity is repaired in combination with thermal oxidation method, which solves the leakage problem caused by holes and gaps in the shielded gate device, improves the electrical reliability of the device and reduces costs.
Patent Information
- Application Number
- CN202311041614.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-17
- Publication Date
- 2025-02-21
AI Technical Summary
Existing shielded gate devices are prone to holes and gaps when filling the gate polysilicon layer, resulting in defects and leakage problems. The existing improvement methods are costly, complex in processes and difficult to meet the needs of small voltages.
The nail head structure is removed by etching the first polysilicon material layer, which facilitates filling of the second polysilicon material layer, and recrystallizes the second polysilicon material layer at a preset temperature to repair defects. At the same time, the interface cavity between gate oxygen and gate polysilicon is repaired by thermal oxidation.
The gap defects in the second polysilicon material layer and the interface voids of the gate oxygen layer are effectively repaired, which improves the electrical reliability of the device, reduces costs, and adapts to small voltage requirements.
Smart Images
Figure CN119495560A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a shielding gate device. Background Art
[0002] In shielded gate (SGT) devices, the trench needs to be filled with gate oxide layer and gate polysilicon layer. When filling the gate polysilicon layer, holes and gaps are easily generated in the gate polysilicon, resulting in defects in the gate polysilicon. Moreover, due to the existence of holes and gaps, contaminants such as etching byproducts, water vapor or corrosive gases are easily left in the holes and gaps after subsequent injection / etching processes. After the contaminants are precipitated, defects will also be generated, resulting in product ID leakage and device electrical failure. In addition, SGT products are increasingly developing towards lower voltages, and the thickness of the gate oxide layer is getting thinner and thinner. Under the action of byproducts after back etching and polysilicon stress, the gate polysilicon will form voids at the interface between the gate polysilicon and the gate oxide layer, which will also cause product leakage.
[0003] There are two main ways to improve the holes and gaps in the gate polysilicon in the existing manufacturing methods. The first is to optimize the morphology of the groove after etching, forming a groove with a larger top and smaller bottom to facilitate the filling of polysilicon. However, in actual applications, due to the limitations of product design and machine capabilities, the morphology of larger top and smaller bottom cannot be met; the second is that the gate polysilicon is formed by multiple etchings and multiple depositions, but there are problems of high cost and complex process. At the same time, the damage to the gate oxide layer during multiple etchings and the thickness requirements of the etching stop layer in the non-groove area must also be considered. Although changing the gas ratio of the etching process can reduce etching damage, it is limited by the limitations of the gas ratio of the etching machine. In addition, by changing the polysilicon deposition temperature to reduce the influence of stress on the gate oxide layer, the purpose of repairing interface voids can be achieved, but due to the limitations on the resistance of polysilicon and the requirements for polysilicon grains, it may be limited to product applications.
[0004] Therefore, how to provide a method for manufacturing a shielded gate device to improve the ID leakage of the shielded gate device, improve reliability, and reduce costs has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing a shielded gate device to solve the problems in the prior art that gaps and holes are easily present in the gate polysilicon and that voids are easily present at the interface between the gate polysilicon and the gate oxide layer.
[0006] To achieve the above object and other related objects, the present invention provides a method for manufacturing a shielded gate device, comprising the following steps:
[0007] Providing a substrate, wherein a trench is formed in the substrate, a first silicon oxide material layer is formed on the sidewall and bottom of the trench, and a first polysilicon material layer is formed in the trench;
[0008] Etching the first polysilicon material layer to form a first polysilicon layer, wherein the top of the first polysilicon layer is lower than the top of the first silicon oxide material layer, and the top of the first polysilicon layer is not lower than the top of the substrate;
[0009] Etching the first silicon oxide material layer to form a first silicon oxide layer, wherein a top of the first silicon oxide layer is lower than a top of the groove, wherein the groove above the first silicon oxide layer constitutes a recessed space;
[0010] forming a second silicon oxide material layer at the bottom and sidewalls of the groove space, and forming a second polysilicon material layer in the groove space;
[0011] The second polysilicon material layer is recrystallized at a preset temperature to repair defects in the second polysilicon material layer.
[0012] Optionally, a temperature range of recrystallization of the second polysilicon material layer is 900-1100°C.
[0013] Optionally, after the second polysilicon material layer is recrystallized, the following steps are further included:
[0014] Etching the second polysilicon material layer to form gate polysilicon;
[0015] Oxygen is introduced into the cavity to partially oxidize the gate polysilicon at a preset temperature to repair the voids in the second silicon oxide material layer.
[0016] Optionally, the gate polysilicon oxidation temperature ranges from 1000° C. to 1100° C.
[0017] Optionally, after the gate polysilicon is partially oxidized, the thickness of the generated thermal oxide layer is in the range of
[0018] Optionally, the time interval between etching the second polysilicon material layer and thermally oxidizing the gate polysilicon is no more than 70 hours.
[0019] Optionally, before etching the first polysilicon material layer, the step of grinding the first polysilicon material layer using chemical mechanical grinding is also included to make the upper surface of the first polysilicon material layer flush with the upper surface of the first silicon oxide material layer, and then etching the first polysilicon material layer using dry etching to form the first polysilicon layer.
[0020] Optionally, the first silicon oxide material layer is etched by wet etching to form the first silicon oxide layer.
[0021] Optionally, the thickness of the first silicon oxide material layer is in the range of The thickness of the first polysilicon material layer is in the range of
[0022] Optionally, the thickness of the second silicon oxide material layer is in the range of
[0023] As described above, in the method for manufacturing the shielded gate device of the present invention, the first polysilicon material layer is etched to remove the nail head structure, which is conducive to the subsequent filling of the second polysilicon material layer. After the second polysilicon material layer is filled, the gap defects in the second polysilicon material layer are repaired by a recrystallization method to improve the electrical reliability of the device. In addition, after the second polysilicon material layer is etched back to form gate polysilicon, the interface voids between the gate oxide and the gate polysilicon are repaired by a thermal oxidation method to further improve the electrical reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a schematic diagram showing forming a first silicon oxide material layer and a first polysilicon material layer in a trench in a method for manufacturing a shielded gate device.
[0025] Figure 2 It is a schematic diagram showing a method for manufacturing a shielded gate device using chemical mechanical polishing to polish a first polysilicon material layer.
[0026] Figure 3 It is a schematic diagram showing the etching of a first silicon oxide material layer to form a groove space in a method for manufacturing a shielded gate device.
[0027] Figure 4 It is a schematic diagram showing the process of filling a second silicon oxide material layer and a second polysilicon material layer in a groove space in a method for manufacturing a shielded gate device.
[0028] Figure 5 Shown is a schematic diagram of etching a second polysilicon material layer in a method for manufacturing a shielded gate device.
[0029] Figure 6 Shown is a flow chart of a method for manufacturing a shielded gate device of the present invention.
[0030] Figure 7 It is a schematic diagram showing the formation of a first silicon oxide material layer and a first polysilicon material layer during trench filling in the present invention.
[0031] Figure 8 It is a schematic diagram showing the use of chemical mechanical polishing to polish the first polysilicon material layer in the present invention.
[0032] Fig. 9 It is a schematic diagram showing etching of the first polysilicon material layer in the present invention.
[0033] Fig.10 It is a schematic diagram showing the etching of the first silicon oxide material layer to form a groove space in the present invention.
[0034] Fig.11 It is a schematic diagram showing the process of filling the groove space with a second silicon oxide material layer and a second polysilicon material layer in the present invention.
[0035] Fig.12 It is a schematic diagram showing the recrystallization of the second polysilicon material layer in the present invention.
[0036] Fig.13 It is a schematic diagram showing the etching of the second polysilicon material layer to form gate polysilicon in the present invention.
[0037] Fig.14 It is a schematic diagram showing the thermal oxidation of gate polysilicon in the present invention.
[0038] Component number description
[0039] 10 Base
[0040] 20 first silicon oxide material layer
[0041] 20a First silicon oxide layer
[0042] 30 first polysilicon material layer
[0043] 30a First polysilicon layer
[0044] 40 second silicon oxide material layer
[0045] 50 second polysilicon material layer
[0046] 50a Gate polysilicon
[0047] 60 Thermal Oxide Layer
[0048] Steps S1 to S5 DETAILED DESCRIPTION
[0049] See also Figures 1 to 5 , showing a method for manufacturing a shielded gate device, comprising the following steps: (1) Figure 1 As shown, a groove is formed in the substrate 10 by etching, and a first silicon oxide material layer 20 and a first polysilicon material layer 30 are filled in the groove; (2) as shown Figure 2 As shown, the first polysilicon material layer 30 above the first silicon oxide material layer 20 is removed by chemical mechanical polishing (CMP), and the top of the remaining first polysilicon material layer 30 presents a "nail head" structure; (3) Figure 3 As shown, the first silicon oxide material layer 20 is etched by wet etching to form a first silicon oxide layer 20a, and the groove above the first silicon oxide layer 20a constitutes a groove space, wherein the bottom of the groove space has a sharp corner and the top opening is small; (4) as shown Figure 4 As shown, a second silicon oxide material layer 40 is formed at the bottom and sidewalls of the groove space, and a second polysilicon material layer 50 is formed in the groove space; (5) as shown Figure 5 As shown, the second polysilicon material layer 50 is etched to form gate polysilicon 50a. Since the shape of the groove space is irregular, it is not conducive to the filling of the second silicon oxide material layer 40 and the second polysilicon material layer 50, and gaps and holes will be formed in the second polysilicon material layer 50, and the device is prone to leakage failure. In addition, the second silicon oxide material layer 40 is relatively thin as a gate oxide layer, and under the stress of the second polysilicon material layer 50, voids will be formed at the interface, which will also cause device leakage. Therefore, the present invention provides a new method to improve the problem of shielded gate device leakage.
[0050] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0051] See also Figures 6 to 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0052] See also Figure 6 , which is a flow chart of a method for manufacturing a shielded gate device of the present invention, comprising the following steps:
[0053] S1: providing a substrate, wherein a trench is formed in the substrate, a first silicon oxide material layer is formed on the sidewall and the bottom of the trench, and a first polysilicon material layer is formed in the trench;
[0054] S2: etching the first polysilicon material layer to form a first polysilicon layer, wherein the top of the first polysilicon layer is lower than the top of the first silicon oxide material layer, and the top of the first polysilicon layer is not lower than the top of the substrate;
[0055] S3: etching the first silicon oxide material layer to form a first silicon oxide layer, wherein a top of the first silicon oxide layer is lower than a top of the groove, wherein the groove above the first silicon oxide layer constitutes a recessed space;
[0056] S4: forming a second silicon oxide material layer at the bottom and sidewalls of the groove space, and forming a second polysilicon material layer in the groove space;
[0057] S5: recrystallizing the second polysilicon material layer at a preset temperature to repair defects in the second polysilicon material layer.
[0058] First, see Figure 7 and Figure 8 , performing step S1: providing a substrate 10, wherein a groove is formed in the substrate 10, a first silicon oxide material layer 20 is formed on the sidewall and the bottom of the groove, and a first polysilicon material layer 30 is formed in the groove.
[0059] As an example, the substrate 10 may be any suitable semiconductor substrate. In this embodiment, the substrate 10 is a silicon substrate.
[0060] As an example, the thickness of the first silicon oxide material layer 20 is in the range of The thickness of the first polysilicon material layer 30 is in the range of Wherein, the first silicon oxide material layer 20 is used as a shielding gate dielectric, and the first polysilicon material layer 30 is used as a shielding gate polysilicon; Figure 7 As shown, in the process of forming the first silicon oxide material layer 20 on the sidewall and bottom of the groove, the first silicon oxide material layer 20 is also formed on the upper surface of the substrate 10; in the process of forming the first polysilicon material layer 30 in the groove, the first polysilicon material layer 30 is also formed above the first silicon oxide material layer 20.
[0061] As an example, Figure 8 As shown, CMP grinding is used to remove the first polysilicon material layer 30 located above the first silicon oxide material layer 20, and the remaining first polysilicon material layer 30 is flush with the upper surface of the first silicon oxide material layer 20, wherein the top of the first polysilicon material layer 30 presents a "nail head" structure.
[0062] Next, see Fig. 9 , perform step S2: etch the first polysilicon material layer 30 to form a first polysilicon layer 30a, the top of the first polysilicon layer 30a is lower than the top of the first silicon oxide material layer 20, and the top of the first polysilicon layer 30a is not lower than the top of the substrate 10.
[0063] As an example, the first polysilicon material layer 30 is etched by dry etching to form the first polysilicon layer 30a, wherein the “nail head” structure on the top of the first polysilicon material layer 30 is removed.
[0064] Next, see Fig.10 , perform step S3: etch the first silicon oxide material layer 20 to form a first silicon oxide layer 20a, the top of the first silicon oxide layer 20a is lower than the top of the groove, wherein the groove above the first silicon oxide layer 20a constitutes a recess space.
[0065] As an example, the first silicon oxide material layer 20 is etched by wet etching to form the first silicon oxide layer 20a shown. Figure 3 In the structure shown, in this embodiment, since the "nail head" structure on the top of the first polysilicon material layer 30 is removed, the top of the groove space is completely opened.
[0066] Next, see Fig.11 , executing step S4: forming a second silicon oxide material layer 40 at the bottom and sidewalls of the groove space, and forming a second polysilicon material layer 50 in the groove space.
[0067] As an example, the second silicon oxide material layer 40 is used as gate oxide, and the second polysilicon material layer 50 is used as gate polysilicon. Since the top of the groove space is completely opened, relative to Figure 3 The structure shown is conducive to filling the groove space. Figure 4 As shown in the structure, in this embodiment, defects such as gaps or holes in the second polysilicon material layer 50 are reduced.
[0068] As an example, although the top of the groove space is completely open to reduce the gaps or holes in the second polysilicon material layer 50, since the groove space is formed by a wet etching process, the bottom of the groove space is inclined, and the upper surface of the second silicon oxide material layer 40 located at the bottom of the groove space has a height difference. The second polysilicon material layer 50 is formed by low-pressure furnace tube deposition. When deposited under low pressure, it will grow layer by layer along the morphology of the previous layer. Due to the irregular morphology of the second silicon oxide material layer 40, gaps and holes will still appear in the second polysilicon material layer 50.
[0069] As an example, the thickness of the second silicon oxide material layer 40 is in the range of The thinner the second silicon oxide material layer 40 is, the easier it is for voids to form at the interface between the second silicon oxide material layer 40 and the second polysilicon material layer 50 under the stress of the second polysilicon material layer 50 .
[0070] Next, see Fig.12 , executing step S5: recrystallizing the second polysilicon material layer 50 at a preset temperature to repair defects in the second polysilicon material layer 50.
[0071] As an example, the second polysilicon material layer 50 is recrystallized at a temperature of 900-1100° C. to repair the gaps and holes in the second polysilicon material layer 50 , and the polysilicon recrystallization does not affect the conductivity of the gate.
[0072] As an example, in other types of devices, when there are gap defects in polysilicon, the polysilicon gap defects can be repaired by a recrystallization method.
[0073] As an example, see Fig.13 , the second polysilicon material layer 50 is etched back to form gate polysilicon 50a. Since the second polysilicon material layer 50 repairs the gaps and holes through the recrystallization process, the electrical failure of the product caused by the existence of polysilicon holes and gaps is avoided, and the pollutants in the holes and gaps are prevented from releasing corrosive substances such as F ions during long-term storage to corrode and damage the second silicon oxide material layer 40.
[0074] As an example, see Fig.14 After forming the gate polysilicon 50a, oxygen is introduced into the cavity to oxidize the top of the gate polysilicon 50a at a preset temperature to repair the interface voids of the second silicon oxide material layer 40. In other trench power devices, especially those with thin gate oxide, the interface voids can be repaired by the thermal oxidation method of this embodiment.
[0075] As an example, the temperature range of the thermal oxidation of the gate polysilicon 50a is 1000-1100°C, and the thickness range of the generated thermal oxide layer 60 is The thermal oxide layer 60 can ensure that the interface voids of the second silicon oxide material layer 40 are completely filled and repaired, and will not affect the subsequent etching / implantation process.
[0076] As an example, polysilicon is usually etched using a F-containing gas. After the second polysilicon material layer 50 is etched back on the etching machine, it must go through the steps of cleaning and drying to remove etching byproducts and residual corrosive substances such as F ions, and then be placed on a deposition machine to thermally oxidize the gate polysilicon 50a. However, cleaning and drying cannot guarantee the complete removal of F ions. The precipitation of F ions will corrode the second silicon oxide material layer 40, etc. In this embodiment, the time interval between the second polysilicon material layer 50 being etched back and the thermal oxidation of the gate polysilicon 50a does not exceed 70 hours to avoid F ion corrosion of the second silicon oxide material layer 40, and the high temperature process of 1000-1100°C can remove the corrosive substances. Specifically, in this embodiment, the time interval between the second polysilicon material layer 50 being etched back and the thermal oxidation of the gate polysilicon 50a is 50-60 hours.
[0077] In summary, in the manufacturing method of the shielded gate device of the present invention, the first polysilicon material layer is etched to remove the nail head structure, which is conducive to the subsequent filling of the second polysilicon material layer. After the second polysilicon material layer is filled, the gap defects in the second polysilicon material layer are repaired by a recrystallization method to improve the electrical reliability of the device. In addition, after the second polysilicon material layer is back-etched to form gate polysilicon, the interface voids between the gate oxide and the gate polysilicon are repaired by a thermal oxidation method to further improve the electrical reliability of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0078] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a shielded gate device, characterized in that: The following steps are involved: Providing a substrate, wherein a trench is formed in the substrate, a first silicon oxide material layer is formed on the sidewall and bottom of the trench, and a first polysilicon material layer is formed in the trench; Etching the first polysilicon material layer to form a first polysilicon layer, wherein the top of the first polysilicon layer is lower than the top of the first silicon oxide material layer, and the top of the first polysilicon layer is not lower than the top of the substrate; Etching the first silicon oxide material layer to form a first silicon oxide layer, wherein a top of the first silicon oxide layer is lower than a top of the groove, wherein the groove above the first silicon oxide layer constitutes a recessed space; forming a second silicon oxide material layer at the bottom and sidewalls of the groove space, and forming a second polysilicon material layer in the groove space; The second polysilicon material layer is recrystallized at a preset temperature to repair defects in the second polysilicon material layer.
2. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The temperature range of recrystallization of the second polysilicon material layer is 900-1100°C.
3. The method for manufacturing a shielded gate device according to claim 1, characterized in that: After the second polysilicon material layer is recrystallized, the method further comprises the following steps: Etching the second polysilicon material layer to form gate polysilicon; Oxygen is introduced into the cavity to partially oxidize the gate polysilicon at a preset temperature to repair the voids in the second silicon oxide material layer.
4. The method for manufacturing a shielded gate device according to claim 3, characterized in that: The temperature range of the gate polysilicon oxidation is 1000-1100°C.
5. The method for manufacturing a shielded gate device according to claim 3, characterized in that: After the gate polysilicon is partially oxidized, the thickness of the generated thermal oxide layer is in the range of 6. The method for manufacturing a shielded gate device according to claim 3, characterized in that: The time interval between etching the second polysilicon material layer and thermally oxidizing the gate polysilicon is no more than 70 hours.
7. The method for manufacturing a shielded gate device according to claim 1, characterized in that: Before etching the first polysilicon material layer, the method also includes the step of grinding the first polysilicon material layer using chemical mechanical grinding to make the upper surface of the first polysilicon material layer flush with the upper surface of the first silicon oxide material layer, and then etching the first polysilicon material layer using dry etching to form the first polysilicon layer.
8. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The first silicon oxide material layer is etched by wet etching to form the first silicon oxide layer.
9. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The thickness of the first silicon oxide material layer is in the range of The thickness of the first polysilicon material layer is in the range of 10. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The thickness of the second silicon oxide material layer is in the range of