Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprising: providing a substrate, the substrate comprising a substrate, an active device formed on the substrate, wherein the active device comprises an interconnection region; forming a first dielectric layer and a first mask layer on the active device, the first mask layer having a first opening, the first opening at least partially coinciding with the interconnection region of the active device in a projection of the substrate; forming a second dielectric layer on the first mask layer, wherein the second dielectric layer is connected with the first dielectric layer through the first opening; removing part of the second dielectric layer and the first dielectric layer connected with the second dielectric layer, forming an interconnection trench exposing the interconnection region of the active device; and forming a metal interconnection structure in the interconnection trench. The scheme can simplify the forming process of the metal interconnection structure and reduce the process cost of forming the metal interconnection structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As semiconductor manufacturing technology becomes increasingly sophisticated, integrated circuits are undergoing significant changes. The number of components integrated on a single chip has increased from tens or hundreds initially to millions today. To meet the requirements of complexity and circuit density, semiconductor integrated circuit chip manufacturing processes utilize batch processing technology to form various types of complex devices on a substrate and interconnect them to achieve complete electronic functionality.

[0003] However, as the size of semiconductor devices continues to shrink, the manufacturing process of semiconductor devices produced by existing technologies is becoming increasingly complex. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, to simplify the formation process of metal interconnect structures and reduce the process cost of forming metal interconnect structures.

[0005] To address the above problems, embodiments of this application provide a method for forming a semiconductor structure, comprising:

[0006] A substrate is provided, the substrate including a substrate and active devices formed on the substrate, wherein the active devices include interconnect regions;

[0007] A first dielectric layer and a first mask layer are formed on the active device, the first mask layer having a first opening, the projection of the first opening onto the substrate at least partially coinciding with the interconnect region of the active device;

[0008] A second dielectric layer is formed on the first mask layer, wherein the second dielectric layer is in contact with the first dielectric layer through the first opening;

[0009] A portion of the second dielectric layer and the first dielectric layer adjoining the second dielectric layer are removed to form interconnect trenches that expose the interconnect regions of the active device;

[0010] A metal interconnect structure is formed within the interconnect trench.

[0011] Optionally, removing a portion of the second dielectric layer and the first dielectric layer adjacent to the second dielectric layer to form an interconnect trench exposing the interconnect region of the active device includes:

[0012] A second mask layer is formed on the second dielectric layer, the second mask layer having a second opening that exposes a portion of the second dielectric layer, the projection of the second opening onto the substrate at least covering the projection of the first opening onto the substrate;

[0013] Using the second mask layer as a mask, the second dielectric layer exposed by the second opening and the first dielectric layer connected to the two dielectric layers are etched to form interconnect trenches that expose the interconnect regions of the active device.

[0014] Optionally, the etching of the second dielectric layer exposed by the second opening and the first dielectric layer in contact with the second dielectric layer specifically involves using pulsed plasma etching to etch the second dielectric layer exposed by the second opening and the first dielectric layer in contact with the second dielectric layer.

[0015] Optionally, the substrate further includes a dielectric barrier layer covering the active device;

[0016] The formation of the first dielectric layer on the active device specifically involves forming the first dielectric layer on the dielectric barrier layer.

[0017] The step of removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnect trench exposing the interconnect region of the active device further includes removing the dielectric barrier layer exposed by the first dielectric layer.

[0018] Optionally, forming a first dielectric layer on the active device and a first mask layer located on the first dielectric layer includes:

[0019] A first dielectric layer is formed on the active device;

[0020] A first mask material layer is formed on the first dielectric layer;

[0021] The first mask material layer is graphically visualized, the first mask material layer in a preset area is removed to form the first opening, and the remaining first mask material layer is used as the first mask layer.

[0022] Optionally, forming a metal interconnect structure within the interconnect trench includes:

[0023] A metal interconnect material layer is formed within the interconnect trench, and the metal interconnect material layer completely covers the interconnect trench;

[0024] Remove the metal interconnect material layer on top of the second dielectric layer, and retain the metal interconnect material layer in the interconnect trench as the metal interconnect structure.

[0025] Optionally, the interconnect region of the active device is the interconnect metal layer of the active device.

[0026] Optionally, the second dielectric layer and the first dielectric layer are made of the same material.

[0027] Optionally, in the etching process, the etching gas used is one or more combinations of C4F6, C4F8, SF6, NF3, O2, CH2F2, CH3F, CHF3, CH4, Ar, Kr, and N2. The flow rate of the etching gas is 10 sccm to 250 sccm, the etching source power is 50 W to 6000 W, the bias power is 100 W to 1600 W, the pressure of the etching chamber is 0 mtorr to 50 mtorr, the etching frequency is 100 Hz to 8000 Hz, and the duty cycle is 10% to 80%.

[0028] This invention also provides a semiconductor structure, which is formed by the above-described semiconductor structure formation method.

[0029] Compared with the prior art, the technical solution of this application has the following advantages:

[0030] This invention provides a semiconductor structure and a method for forming the same. The method includes: providing a substrate, the substrate including a substrate and an active device formed on the substrate, wherein the active device includes an interconnect region; forming a first dielectric layer and a first mask layer on the first dielectric layer, the first mask layer having a first opening, the projection of the first opening onto the substrate at least partially coinciding with the interconnect region of the active device; forming a second dielectric layer on the first mask layer, wherein the second dielectric layer is connected to the first dielectric layer through the first opening; removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnect trench exposing the interconnect region of the active device; wherein the interconnect trench exposes the interconnect region of the active device based on the first opening; and forming a metal interconnect structure within the interconnect trench.

[0031] As can be seen, the forming method provided by the embodiments of the present invention forms a first mask layer on a first dielectric layer and connects the second dielectric layer to the first dielectric layer through a first opening in the first mask layer. This allows for the simultaneous removal of a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer, thereby forming interconnect trenches that expose the interconnect regions of active devices. Furthermore, an interconnect structure for electrical connection with active devices is formed through a primary interconnect structure forming process. Compared with forming corresponding sub-interconnect structures on the first and second dielectric layers respectively, the embodiments of the present invention significantly simplify the metal interconnect structure forming process, thereby reducing the process cost of forming the metal interconnect structure.

[0032] In addition, it is understood that when multiple sub-interconnect structures are connected together, contact resistance will be generated. If multiple sub-interconnect structures are connected together as the interconnect structure of the device, a large interconnect resistance will be formed. In contrast, the embodiment of the present invention forms a metal interconnect structure in one step, which can significantly reduce the interconnect resistance of the interconnect structure. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0034] Figures 1 to 7 This is a schematic diagram of a semiconductor structure;

[0035] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0036] As described in the background section, the process flow for semiconductor devices produced by existing technologies is too complex.

[0037] Below, we will analyze the reasons for this problem by combining an existing method for forming semiconductor structures.

[0038] refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram of the steps in a method for forming a semiconductor structure.

[0039] refer to Figure 1 A substrate is provided, the substrate including a substrate 1 and active devices (not shown) formed on the substrate 1, wherein the active devices include interconnect regions 2.

[0040] refer to Figure 2 A first dielectric layer 3 is formed on the active device;

[0041] refer to Figure 3 The first dielectric layer is graphically visualized to form a first interconnect trench 4, which exposes the interconnect region 2 of the active device.

[0042] refer to Figure 4 A first sub-interconnection structure 5 is formed within the first interconnect trench;

[0043] refer to Figure 5An isolation layer 6 and a second dielectric layer 7 are formed to cover the first sub-interconnect structure; wherein, the isolation layer 6 is used to protect the first sub-interconnect structure 5 from etching damage during the subsequent patterning of the second dielectric layer 7.

[0044] refer to Figure 6 The second dielectric layer 7 and the isolation layer 6 are graphically represented to form a second interconnect trench 8, which exposes the first sub-interconnect structure 5.

[0045] refer to Figure 7 A second sub-interconnect structure 9 is formed in the second interconnect trench, which is connected to the first sub-interconnect structure 5.

[0046] It is understandable that the first sub-interconnect structure 5 and the second sub-interconnect structure 9 together serve as the interconnect structure for active devices to achieve electrical connection with active devices.

[0047] It should be noted that, in Figure 4 In the process of forming the first sub-interconnect structure 5, it is necessary to form an interconnect material layer that completely covers the first interconnect trench and the top of the first dielectric layer, and then use a planarization process to grind away the interconnect material layer above the top of the first dielectric layer, retaining only the interconnect material layer within the first interconnect trench as the first sub-interconnect structure 5; while Figure 7 The same process is required to form the second sub-interconnect structure 9, thereby forming the first sub-interconnect structure 5 and the second sub-interconnect structure 9 one by one. Accordingly, to form the first sub-interconnect structure 5 and the second sub-interconnect structure 9 one by one, two patterning processes are required to form the corresponding trenches. At the same time, in order to avoid damage to the first sub-interconnect structure 5 by the second patterning process, an isolation layer 6 is also required to protect the first sub-interconnect structure 5.

[0048] The inventors believe that the process of forming metal interconnect structures in this way is too complicated.

[0049] In view of this, embodiments of the present invention provide a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate including a substrate and an active device formed on the substrate, wherein the active device includes an interconnect region; forming a first dielectric layer and a first mask layer on the first dielectric layer on the active device, the first mask layer having a first opening, the projection of the first opening onto the substrate at least partially coinciding with the interconnect region of the active device; forming a second dielectric layer on the first mask layer, wherein the second dielectric layer is connected to the first dielectric layer through the first opening; removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnect trench exposing the interconnect region of the active device; wherein the interconnect trench exposes the interconnect region of the active device based on the first opening; and forming a metal interconnect structure within the interconnect trench.

[0050] As can be seen, the forming method provided by the embodiments of the present invention forms a first mask layer on a first dielectric layer and connects the second dielectric layer to the first dielectric layer through a first opening in the first mask layer. This allows for the simultaneous removal of a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer, thereby forming interconnect trenches that expose the interconnect regions of active devices. Furthermore, an interconnect structure for electrical connection with active devices is formed through a primary interconnect structure forming process. Compared with forming corresponding sub-interconnect structures on the first and second dielectric layers respectively, the embodiments of the present invention significantly simplify the metal interconnect structure forming process, thereby reducing the process cost of forming the metal interconnect structure.

[0051] In addition, it is understood that when multiple sub-interconnect structures are connected together, contact resistance will be generated. If multiple sub-interconnect structures are connected together as the interconnect structure of the device, a large interconnect resistance will be formed. In contrast, the embodiment of the present invention forms a metal interconnect structure in one step, which can significantly reduce the interconnect resistance of the interconnect structure.

[0052] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0054] refer to Figure 8 A substrate is provided, the substrate including a substrate 100 and active devices (not shown) formed on the substrate 100, wherein the active devices include interconnect regions 101.

[0055] The substrate 100 provides the technological basis for the formation of semiconductor structures.

[0056] In this embodiment, the substrate 100 can be silicon. In other embodiments, the substrate 100 can also be made of other semiconductor materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate 100 can also be other types of substrates such as silicon on insulator or germanium on insulator.

[0057] In this embodiment, the substrate further includes active devices formed on the substrate, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors. The active devices include interconnect regions for electrical connection to the interconnect structure, thereby controlling the operation of the active devices.

[0058] In a specific example, the interconnect region 101 of the active device can be an interconnect metal layer of the active device. This interconnect metal layer can be located within the device dielectric layer 102 surrounding the active device. The interconnect metal layer is used to electrically connect specific structures of the active device, such as source / drain structures, gate structures, etc. The material of the interconnect metal layer includes Cu. In a further example, the interconnect metal layer can include one or more of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0059] In a further embodiment of the present invention, the substrate further includes a dielectric barrier layer 103 covering the active device, the dielectric barrier layer 103 being used to isolate and protect the interconnect region 101 during the subsequent formation of interconnect trenches corresponding to the metal interconnect structure.

[0060] The dielectric barrier layer 103 may be silicon nitride. In some optional examples, the dielectric barrier layer may be one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), and silicon oxycarbonitrile (SiOCN).

[0061] refer to Figure 9 and Figure 10 A first dielectric layer 104 and a first mask layer 105 located on the first dielectric layer 104 are formed on the active device.

[0062] The first dielectric layer 104 can be understood as a partial interlayer dielectric layer of the device. This partial interlayer dielectric layer is used to isolate and protect the active device while providing a process basis for forming a metal interconnect structure.

[0063] The first dielectric layer may be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0064] Specifically, the first dielectric layer can be formed by a deposition process. When a dielectric barrier layer is formed on the active device, the first dielectric layer can be specifically formed on the dielectric barrier layer.

[0065] The first mask layer 105 can be used to pattern the first dielectric layer 104. Specifically, the first mask layer 105 has a first opening 106. The projection of the first opening 106 onto the substrate at least partially overlaps with the interconnect region 101 of the active device, so that in subsequent processes, the first dielectric layer 104 exposed by the first opening 106 can be removed based on the first mask layer 105, thereby exposing the interconnect region 102 corresponding to the first opening 106.

[0066] The first mask layer may be silicon nitride. In some specific examples, the first mask layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. It should be noted that the first mask layer is made of a different material than the first dielectric layer to isolate and protect the first dielectric layer.

[0067] In an optional example, this can be achieved by first forming a first dielectric layer 104 (see reference). Figure 9 After that, a first mask layer 105 is formed on the first dielectric layer 104 (see reference). Figure 10 This step is executed in the manner described above.

[0068] The first mask layer is formed on the first dielectric layer through a deposition and etching process. For details, refer to... Figure 10 The process of forming the first mask layer may include: forming a first mask material layer on the first dielectric layer; patterning the first mask material layer; removing the first mask material layer in a preset area to form the first opening; and using the remaining first mask material layer as the first mask layer.

[0069] Specifically, the first mask material layer can be formed by a deposition process, and the patterning can be achieved by photolithography and etching processes. A photolithographic pattern is formed on the first mask material layer to expose a predetermined area of ​​the first mask material layer, and the first mask material layer exposed by the photolithographic pattern is removed by an etching process to form a first opening, thereby forming the first mask layer. The etching process can be a wet etching process, a dry etching process, or a combination of wet and dry etching processes.

[0070] refer to Figure 11 A second dielectric layer 107 is formed on the first mask layer 105, wherein the second dielectric layer 107 is connected to the first dielectric layer 104 through the first opening 106.

[0071] The second dielectric layer 107 can be understood as another part of the interlayer dielectric layer of the device.

[0072] In this embodiment of the invention, after forming the first mask layer, the first dielectric layer is not immediately patterned. Instead, a second dielectric layer is further formed, and the first dielectric layer is patterned simultaneously during the patterning process of the second dielectric layer. This allows interconnect trenches that expose the interconnect regions of active devices to be formed through a single patterning process, simplifying the process flow and reducing process costs.

[0073] It should be noted that, since the first mask layer has a first opening that exposes the first dielectric layer, the second dielectric layer can connect with the first dielectric layer through the first opening.

[0074] The material of the second dielectric layer can be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In a preferred example, the second dielectric layer and the first dielectric layer are made of the same material.

[0075] Specifically, the second dielectric layer can be formed through a deposition process.

[0076] refer to Figures 12 to 14 Remove a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form interconnect trenches that expose the interconnect regions of the active device;

[0077] It is understood that, based on the aforementioned steps, a first mask layer that can realize the graphical representation of the first dielectric layer has already been formed. In this step, during the removal of a portion of the second dielectric layer, the first dielectric layer that is connected to the second dielectric layer through the first opening of the first mask layer can be removed simultaneously, thereby simplifying the process flow and reducing process costs.

[0078] Furthermore, by removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer, an interconnect trench is formed to expose the interconnect region of the active device. This allows for the formation of an interconnect structure for electrical connection with the active device through a single interconnect structure formation process. Compared to forming corresponding sub-interconnect structures on the first and second dielectric layers respectively, this embodiment of the invention significantly simplifies the metal interconnect structure formation process and reduces the process cost of forming the metal interconnect structure.

[0079] In an optional example, the process of forming the interconnect trench may include the following steps:

[0080] refer to Figure 12A second mask layer 108 is formed on the second dielectric layer, the second mask layer 108 having a second opening 109 that exposes a portion of the second dielectric layer 107, the projection of the second opening 109 onto the substrate at least covering the projection of the first opening 106 onto the substrate.

[0081] The second mask layer is used to pattern the second dielectric layer. Correspondingly, a second opening is formed on the second mask layer to pattern the second dielectric layer. The projection of the second opening onto the substrate at least covers the projection of the first opening onto the substrate, so that the patterning process based on the second opening can expose the first opening of the first mask layer.

[0082] It should be noted that a second opening may correspond to a first opening, or, in optional examples, a second opening may correspond to multiple first openings. This invention does not impose any specific limitations on this.

[0083] The second mask layer can be silicon oxynitride. In some specific examples, the second mask layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron nitride silicon, and boron nitride silicon carbide. It should be noted that the material of the second mask layer can be the same as or different from the material of the first mask layer. Compared to the scheme where corresponding sub-interconnect structures are formed on the first and second dielectric layers respectively, where the material of the second mask layer is different from the material of the first mask layer to avoid simultaneous etching of the second mask layer during patterning of the first mask layer, the material selection in the embodiments of the present invention is broader and the process is simpler.

[0084] It is understood that the formation process of the second mask layer can refer to the formation process of the first mask layer, and will not be described again here.

[0085] refer to Figure 13 Using the second mask layer 108 as a mask, the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer are etched to form an interconnect trench 110 that exposes the interconnect region of the active device.

[0086] After the second mask layer is formed, the second dielectric layer can be patterned based on the second opening of the second mask layer. At the same time, since the second dielectric layer and the first dielectric layer are connected based on the first opening, the first dielectric layer can also be patterned based on the first opening while the second dielectric layer is being patterned.

[0087] In a specific example, the etching of the second dielectric layer exposed by the second opening and the first dielectric layer in contact with the second dielectric layer specifically involves using pulsed plasma etching to etch the second dielectric layer exposed by the second opening and the first dielectric layer in contact with the second dielectric layer. The pulsed plasma etching method allows the etching equipment to output power in a pulsed manner, thereby enabling the etching equipment to intermittently and discontinuously excite the etching gas for etching.

[0088] The inventors believe that the size of the etching area usually affects the etching rate of plasma etching because, during plasma etching, the etching gas reacts with the material being etched to form deposits that hinder the etching process. However, the etching equipment in this embodiment generates pulsed power output, causing the etching process to proceed intermittently and discontinuously. After a certain period of etching, the etching is stopped, at which point the etching equipment temporarily stops activating the etching gas. This allows the polymers already formed on the etching surface to have time to leave the surface, thereby reducing the degree of polymer aggregation, minimizing the obstacle to the etching rate, and improving the process efficiency of the etching technology.

[0089] In an optional example, the etching gas used in the etching process can be one or more combinations of C4F6, C4F8, SF6, NF3, O2, CH2F2, CH3F, CHF3, CH4, Ar, Kr, and N2. The flow rate of the etching gas can be 10 sccm to 250 sccm, the etching source power can be 50 W to 6000 W, the bias power can be 100 W to 1600 W, the pressure of the etching chamber can be 0 mtorr to 50 mtorr, the etching frequency can be 100 Hz to 8000 Hz, and the duty cycle can be 10% to 80%.

[0090] In other examples, when the substrate further includes a dielectric barrier layer 103 covering the active device, refer to Figure 14 In the process of removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnect trench exposing the interconnect area of ​​the active device, after removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer in the above steps, the dielectric barrier layer exposed by the first dielectric layer may be further removed, thereby forming an interconnect trench exposing the interconnect area of ​​the active device.

[0091] Next, refer to Figures 15 to 16 A metal interconnect structure 112 is formed within the interconnect trench.

[0092] Based on the interconnect trenches formed in the aforementioned steps that expose the interconnect regions of the active devices, this step can directly form a metal interconnect structure in the interconnect trenches. Compared with forming corresponding sub-interconnect structures in the first dielectric layer and the second dielectric layer respectively, the embodiments of the present invention greatly simplify the formation process of the metal interconnect structure and reduce the process cost of forming the metal interconnect structure.

[0093] Specifically, the formation process of the metal interconnect structure can be as follows:

[0094] refer to Figure 15 A metal interconnect material layer 111 is formed in the interconnect trench, and the metal interconnect material layer 111 completely covers the interconnect trench.

[0095] The metal interconnect material is used to provide a process basis for forming metal interconnect structures.

[0096] It is understood that the interconnect trench penetrates the first dielectric layer and the second dielectric layer, and correspondingly, the metal interconnect material layer completely covers the interconnect trench, thereby forming a metal interconnect structure that simultaneously penetrates the first dielectric layer and the second dielectric layer.

[0097] The material of the metal interconnect material layer is determined based on the material of the metal interconnect structure. In an optional example, the material of the metal interconnect structure can be one or more of W, Al, Cu, Ag, Au, Pt, Ni, or Ti. In this example, the material of the metal interconnect structure can be Cu. Correspondingly, the material of the metal interconnect material layer can be one or more of W, Al, Cu, Ag, Au, Pt, Ni, or Ti. In this example, the material of the metal interconnect material layer is Cu.

[0098] The metal interconnect material layer can be formed by processes such as deposition, sputtering or electroplating, and the present invention does not make specific limitations.

[0099] refer to Figure 16 Remove the metal interconnect material layer on top of the second dielectric layer, and retain the metal interconnect material layer in the interconnect trench as the metal interconnect structure 112.

[0100] In this process, a second mask layer can be used as a stop layer, and a planarization process can be used to grind away the metal interconnect layer above the second dielectric layer, thereby retaining the metal interconnect material layer in the interconnect trench as the metal interconnect structure.

[0101] It is understood that the embodiments of the present invention can be applied to large-size top-layer vias (e.g., 55nm UTV) and ultra-thick metal (UTM) interconnect processes that utilize deep trenches to form metal interconnects, thereby simplifying the process flow and reducing process costs.

[0102] During UTM etching, the loss of oxide layer in the non-copper layer stop area of ​​large-size structures should be strictly controlled.

[0103] In addition, it is understood that when multiple sub-interconnect structures are connected together, contact resistance will be generated. If multiple sub-interconnect structures are connected together as the interconnect structure of the device, a large interconnect resistance will be formed. In contrast, the embodiment of the present invention forms a metal interconnect structure in one step, which can significantly reduce the interconnect resistance of the interconnect structure.

[0104] In another embodiment of the present invention, a semiconductor structure is also provided, which is formed based on the semiconductor structure formation method provided in the foregoing embodiments, wherein, with reference to Figure 16 The semiconductor structure includes:

[0105] The substrate includes a substrate 100 and active devices (not shown) disposed on the substrate 100, wherein the active devices include interconnect regions 101.

[0106] In this embodiment, the substrate 100 can be silicon. In other embodiments, the substrate 100 can also be made of other semiconductor materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate 100 can also be other types of substrates such as silicon on insulator or germanium on insulator.

[0107] In this embodiment, the substrate further includes active devices formed on the substrate, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors. The active devices include interconnect regions for electrical connection to the interconnect structure, thereby controlling the operation of the active devices.

[0108] In a specific example, the interconnect region 101 of the active device can be an interconnect metal layer of the active device. This interconnect metal layer can be located within the device dielectric layer 102 surrounding the active device. The interconnect metal layer is used to electrically connect specific structures of the active device, such as source / drain structures, gate structures, etc. The material of the interconnect metal layer includes Cu. In a further example, the interconnect metal layer can include one or more of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0109] In a further embodiment of the present invention, the substrate further includes a dielectric barrier layer 103 covering the active device, the dielectric barrier layer 103 being used to isolate and protect the interconnect region 101 during the subsequent formation of interconnect trenches corresponding to the metal interconnect structure.

[0110] The dielectric barrier layer 103 may be silicon nitride. In some optional examples, the dielectric barrier layer may be one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), and silicon oxycarbonitrile (SiOCN).

[0111] The first dielectric layer 104 is located on the active device and the first mask layer 105 is located on the first dielectric layer 104. The first dielectric layer 104 can be understood as a partial interlayer dielectric layer of the device. This partial interlayer dielectric layer is used to isolate and protect the active device while providing a process basis for forming a metal interconnect structure.

[0112] The first dielectric layer may be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0113] The first mask layer 105 has a first opening, the projection of which onto the substrate at least partially coincides with the interconnect region of the active device.

[0114] The first mask layer may be silicon nitride. In some specific examples, the first mask layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. It should be noted that the first mask layer is made of a different material than the first dielectric layer to isolate and protect the first dielectric layer.

[0115] The second dielectric layer 107 is located on the first mask layer 105. The second dielectric layer 107 can be understood as another part of the interlayer dielectric layer of the device.

[0116] The material of the second dielectric layer can be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In a preferred example, the second dielectric layer and the first dielectric layer are made of the same material.

[0117] An interconnect trench extends through the second dielectric layer and through the first opening into the first dielectric layer, and a metal interconnect structure 112 is located within the interconnect trench. The material of the metal interconnect structure can be one or more of W, Al, Cu, Ag, Au, Pt, Ni, or Ti. In this example, the material of the metal interconnect structure can be Cu.

[0118] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0119] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate and active devices formed on the substrate, wherein the active devices include interconnect regions; A first dielectric layer and a first mask layer are formed on the active device, the first mask layer having a first opening, the projection of the first opening onto the substrate at least partially coinciding with the interconnect region of the active device; A second dielectric layer is formed on the first mask layer, wherein the second dielectric layer is in contact with the first dielectric layer through the first opening; Simultaneously, a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer are removed to form interconnect trenches that expose the interconnect regions of the active device; A metal interconnect structure is formed within the interconnect trench; The step of simultaneously removing a portion of the second dielectric layer and the first dielectric layer adjacent to the second dielectric layer to form an interconnect trench exposing the interconnect region of the active device includes: A second mask layer is formed on the second dielectric layer, the second mask layer having a second opening that exposes a portion of the second dielectric layer, the projection of the second opening onto the substrate at least covering the projection of the first opening onto the substrate; Using the second mask layer as a mask, the second dielectric layer exposed by the second opening and the first dielectric layer connected to the two dielectric layers are simultaneously etched to form interconnect trenches that expose the interconnect regions of the active device; Specifically, the simultaneous etching of the second dielectric layer exposed by the second opening and the first dielectric layer in contact with the second dielectric layer is performed by using pulsed plasma etching to simultaneously etch the second dielectric layer exposed by the second opening and the first dielectric layer in contact with the two dielectric layers.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate also includes a dielectric barrier layer covering the active device; The formation of the first dielectric layer on the active device specifically involves forming the first dielectric layer on the dielectric barrier layer. The step of removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnect trench exposing the interconnect region of the active device further includes removing the dielectric barrier layer exposed by the first dielectric layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of forming a first dielectric layer on the active device and a first mask layer located on the first dielectric layer includes: A first dielectric layer is formed on the active device; A first mask material layer is formed on the first dielectric layer; The first mask material layer is graphically visualized, the first mask material layer in a preset area is removed to form the first opening, and the remaining first mask material layer is used as the first mask layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The formation of a metal interconnect structure within the interconnect trench includes: A metal interconnect material layer is formed within the interconnect trench, and the metal interconnect material layer completely covers the interconnect trench; Remove the metal interconnect material layer on top of the second dielectric layer, and retain the metal interconnect material layer in the interconnect trench as the metal interconnect structure.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The interconnect region of the active device is the interconnect metal layer of the active device.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second dielectric layer is made of the same material as the first dielectric layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the etching process, the etching gas used is one or more combinations of C4F6, C4F8, SF6, NF3, O2, CH2F2, CH3F, CHF3, CH4, Ar, Kr, and N2. The flow rate of the etching gas is 10 sccm to 250 sccm, the etching source power is 50 W to 6000 W, the bias power is 100 W to 1600 W, the pressure of the etching chamber is 0 mtorr to 50 mtorr, the etching frequency is 100 Hz to 8000 Hz, and the duty cycle is 10% to 80%.

8. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method described in any one of claims 1 to 7.

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