Semiconductor package and integrated circuit device

Abstract

The invention provides a semiconductor package and an integrated circuit device. The semiconductor package includes: a package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on the package substrate and spaced apart from the first semiconductor chip; and a bridging die on the package substrate and under the first semiconductor chip and the second semiconductor chip, wherein the bridging die includes a first surface facing the first semiconductor chip and the second semiconductor chip, a second surface facing the package substrate, a connection wiring structure at the first surface and electrically connecting the first semiconductor chip and the second semiconductor chip; and a power supply wiring structure at the second surface and supplying power to the first semiconductor chip and the second semiconductor chip.

Description

Technical Field

[0001] The inventive concept relates to semiconductor packages and integrated circuit devices. Background Art

[0002] In response to the rapid development of the electronics industry and the needs of users, electronic devices are becoming smaller, lighter and more functional, and semiconductor packages used in electronic devices are also required to become smaller, lighter and more functional. To this end, by combining two or more types of semiconductor chips into one semiconductor package, high capacity and multi-functions of the semiconductor package can be provided while significantly reducing the size of the semiconductor package. Summary of the invention

[0003] Aspects of the inventive concept provide a semiconductor package having improved product reliability.

[0004] Aspects of the inventive concept also provide an integrated circuit device having improved product reliability.

[0005] However, aspects of the inventive concept are not limited to those set forth herein. The above and other aspects of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept pertains by referring to the detailed description of the inventive concept given below.

[0006] According to some aspects of the present invention, a semiconductor package is provided, which includes: a packaging substrate; a first semiconductor chip on the packaging substrate; a second semiconductor chip on the packaging substrate separated from the first semiconductor chip; and a bridge chip on the packaging substrate and below the first semiconductor chip and the second semiconductor chip, wherein the bridge chip includes a first side facing the first semiconductor chip and the second semiconductor chip, a second side facing the packaging substrate, a connection wiring structure at the first side and electrically connecting the first semiconductor chip and the second semiconductor chip, and a power wiring structure at the second side and configured to provide power to the first semiconductor chip and the second semiconductor chip.

[0007] According to some aspects of the present invention, a semiconductor package is provided, which includes: a packaging substrate; a first semiconductor chip, which is on the packaging substrate and includes a first power bump on a first lower surface facing the packaging substrate; a second semiconductor chip, which is on the packaging substrate and is spaced apart from the first semiconductor chip and includes a second power bump on a second lower surface facing the packaging substrate; and a bridge core, which is on the packaging substrate and below the first semiconductor chip and the second semiconductor chip and electrically connects the first semiconductor chip and the second semiconductor chip, wherein the bridge core includes a connection wiring structure at a first surface facing the first semiconductor chip and the second semiconductor chip and electrically connecting the first semiconductor chip and the second semiconductor chip, a power wiring structure at a second surface facing the packaging substrate and spaced apart from the connection wiring structure, and a separation substrate between the connection wiring structure and the power wiring structure, wherein the packaging substrate includes a power ball on the lower surface of the packaging substrate and electrically connected to the power wiring structure, and the power wiring structure is electrically connected to the first power bump and the second power bump.

[0008] According to some aspects of the present invention, a semiconductor package is provided, which includes: a packaging substrate; a first semiconductor chip, which is on the packaging substrate and includes a first power bump on a first lower surface facing the packaging substrate; a second semiconductor chip, which is on the packaging substrate and is spaced apart from the first semiconductor chip and includes a second power bump on a second lower surface facing the packaging substrate; and a bridge core, which is on the packaging substrate and below the first semiconductor chip and the second semiconductor chip and electrically connects the first semiconductor chip and the second semiconductor chip, wherein the bridge core includes a connection wiring structure at a first surface facing the first semiconductor chip and the second semiconductor chip and electrically connecting the first semiconductor chip and the second semiconductor chip, connection bumps between the connection wiring structure and the first semiconductor chip and between the connection wiring structure and the second semiconductor chip, a power wiring structure at a second surface facing the packaging substrate and not connected to the connection wiring structure, a separation substrate between the connection wiring structure and the power wiring structure, and a third power bump between the power wiring structure and the packaging substrate, wherein the third power bump is electrically connected to the first power bump and the second power bump, and a width of the bridge core is less than a width of the first semiconductor chip and a width of the second semiconductor chip.

[0009] According to some aspects of the present invention, an integrated circuit device is provided, which includes: a packaging substrate; a first semiconductor chip on the packaging substrate; a second semiconductor chip on the packaging substrate and separated from the first semiconductor chip; and a bridge chip on the packaging substrate and between the first semiconductor chip and the second semiconductor chip, wherein the bridge chip includes a first side facing the first semiconductor chip and the second semiconductor chip, a second side facing the packaging substrate, a connection wiring structure at the first side and electrically connecting the first semiconductor chip and the second semiconductor chip, and a power wiring structure at the second side and configured to provide power to the first semiconductor chip and the second semiconductor chip, wherein the level of a signal provided to the connection wiring structure is lower than the level of a signal provided to the power wiring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the inventive concept will become more apparent by describing in detail some example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1 is an example layout diagram for illustrating a semiconductor package according to some example embodiments;

[0012] Figure 2 It is along Figure 1 A schematic cross-sectional view taken along line AA of ;

[0013] Figure 3 It is shown Figure 2 An enlarged view of a portion P;

[0014] Figure 4 and Figure 5 is a diagram for explaining the operation of an integrated circuit device according to some example embodiments;

[0015] Figure 6 are diagrams for explaining semiconductor packages according to some example embodiments; and

[0016] Figures 7 to 15 are diagrams for explaining semiconductor packages according to some example embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, example embodiments of technical concepts according to the present inventive concept will be described with reference to the accompanying drawings.

[0018] In order to clearly describe the inventive concept, parts or portions irrelevant to the description are omitted, and the same or similar constituent elements are denoted by the same reference numerals throughout the specification.

[0019] Furthermore, in the drawings, the size and thickness of each element are arbitrarily shown for ease of description, and the present inventive concept is not necessarily limited to those shown in the drawings.

[0020] Throughout the specification, when a component is “connected” to another component, this includes not only a case where the components are “directly connected” but also a case where the components are “indirectly connected” with another component therebetween.

[0021] It will be understood that when an element (such as a layer, film, region, area or substrate) is referred to as being "on" or "over" another element, it can be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "over..." indicate positioning on or under an object part, and do not necessarily mean positioning on the upper side of the object part based on the direction of gravity.

[0022] Figure 1 are example layout diagrams for illustrating semiconductor packages according to some example embodiments. Figure 2 It is along Figure 1 A schematic cross-sectional view taken along line AA. Figure 3 It is shown Figure 2 An enlarged view of part P.

[0023] Reference Figures 1 to 3 , a semiconductor package according to some example embodiments may include a package substrate 100, a first semiconductor chip 210, a second semiconductor chip 220, and a bridge die 300. A semiconductor package according to some example embodiments may refer to an integrated circuit device.

[0024] The package substrate 100 may be a wiring structure for packaging. For example, the package substrate 100 may be a printed circuit board (PCB) wiring structure, a ceramic wiring structure, etc. Alternatively, it goes without saying that the package substrate 100 may be a wiring structure for a wafer-level package (WLP) manufactured at a wafer level. The package substrate 100 may include a lower surface and an upper surface opposite to each other.

[0025] The package substrate 100 may include a first insulating layer 110 and a package wiring structure 120. The first insulating layer 110 may include a first substrate 111, a first lower passivation film 113, and a first upper passivation film 112. The package wiring structure 120 may include a first lower pad 123, a first wiring 122, and a first upper pad 121.

[0026] The first substrate 111 may be, for example, a printed circuit board (PCB) or a ceramic substrate. However, the technical concept of the present inventive concept is not limited thereto.

[0027] When the first substrate 111 is a printed circuit board, the first insulating layer 110 may be composed of at least one material selected from phenolic resin, epoxy resin and / or polyimide. The first insulating layer 110 may include, for example, at least one material selected from FR-4, tetrafunctional epoxy resin, polyphenylene oxide, epoxy resin / polyphenylene oxide (epoxy / polyphenylene oxide), BT (bismaleimide triazine), polyamide fiber non-woven fabric (thermount), cyanate ester, polyimide and / or liquid crystal polymer. The surface of the first substrate 111 may be covered with a solder resist. That is, the first lower passivation film 113 and / or the first upper passivation film 112 formed on the surface of the first substrate 111 may be a solder resist. However, the technical concept of the inventive concept is not limited thereto.

[0028] The package wiring structure 120 may be located inside the first insulating layer 110. The package wiring structure 120 may be composed of a first wiring 122 for electrically connecting the first lower pad 123 and the first upper pad 121. The first wiring 122 may include a plurality of wiring patterns 122a and a plurality of vias 122b for connecting each wiring pattern 122a.

[0029] Although the first substrate 111 is shown as a single layer, this is only for convenience of explanation. For example, it goes without saying that the first substrate 111 may be composed of multiple layers to form multiple layers of first wirings 122.

[0030] In some example embodiments, the external connection terminals 140 may be formed on a lower surface of the package substrate 100. The external connection terminals 140 may be attached to the first lower pads 123. The external connection terminals 140 may have, for example, but not limited to, a spherical shape or an elliptical shape.

[0031] The external connection terminal 140 may electrically connect the package wiring structure 120 to an external device. Therefore, the external connection terminal 140 may provide an electrical signal to the package wiring structure 120, or may provide an electrical signal provided from the package wiring structure 120 to an external device.

[0032] The external connection terminal 140 may include a power ball 141 and a signal ball 142. The power ball 141 and the signal ball 142 may be spaced apart from each other. The power ball 141 may be positioned to overlap the bridge die 300. Most of the signal ball 142 may not overlap the bridge die 300.

[0033] The power ball 141 may supply power supplied to the first and second semiconductor chips 210 and 220 to the power wiring structure 330. The power ball 141 may be electrically connected to the power wiring structure 330 bridging the die 300. The power ball 141 may be electrically connected to the power wiring structure 330 through the first wiring 122.

[0034] The signal ball 142 may provide a signal to be input to the first semiconductor chip 210 and the second semiconductor chip 220. The signal ball 142 may receive a signal output from the first semiconductor chip 210 and the second semiconductor chip 220. The signal ball 142 may be connected to the first chip bump 215 and the second chip bump 225. The signal ball 142 may be connected to the first chip bump 215 and the second chip bump 225 through the first wiring 122. The signal ball 142 may send and receive signals to and from the first semiconductor chip 210 and the second semiconductor chip 220 through the first chip bump 215 and the second chip bump 225.

[0035] The external connection terminal 140 may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi) and / or a combination thereof, but the technical concept of the inventive concept is not limited thereto.

[0036] The first semiconductor chip 210 and the second semiconductor chip 220 may be located on the package substrate 100. The first semiconductor chip 210 and the second semiconductor chip 220 may be located on the bridge die 300. That is, the first semiconductor chip 210 and the second semiconductor chip 220 may each be located in a vertical direction (eg, Figure 2 The first semiconductor chip 210 and the second semiconductor chip 220 may overlap with the bridge die 300 in the Z direction (as shown). The first semiconductor chip 210 and the second semiconductor chip 220 may be spaced apart from each other.

[0037] The first semiconductor chip 210 and the second semiconductor chip 220 may each be positioned to overlap a portion of the bridge die 300. The first semiconductor chip 210 and the second semiconductor chip 220 may be connected through a connection wiring structure 320 of the bridge die 300. The first semiconductor chip 210 and the second semiconductor chip 220 may transmit and receive signals to and from each other through the connection wiring structure 320.

[0038] The first semiconductor chip 210 and the second semiconductor chip 230 may each be an integrated circuit (IC) in which hundreds to millions of semiconductor elements are integrated into a single chip. For example, the first semiconductor chip 210 and the second semiconductor chip 220 may each include, for example but not limited to, an application processor (AP) chip (such as a microprocessor and a microcontroller), a CPU (central processing unit), a modem, a logic chip (such as an ASIC (application specific IC) and an FPGA (field programmable gate array)), or a volatile memory chip (such as a DRAM (dynamic random access memory) or an SRAM (static random access memory)), a non-volatile memory chip (such as a PRAM (phase change random access memory), an MRAM (magnetoresistive random access memory), a FeRAM (ferroelectric random access memory) and an RRAM (resistance random access memory)), a flash memory or an HBM (high bandwidth memory) or a combination thereof.

[0039] In some example embodiments, the first semiconductor chip 210 and the second semiconductor chip 220 may be different types of semiconductor chips. As an example, the first semiconductor chip 210 may be an application processor chip or a logic chip, and the second semiconductor chip 220 may be a memory chip.

[0040] The first semiconductor chip 210 may include a first semiconductor substrate 211 and a first wiring structure 212 , and the second semiconductor chip 220 may include a second semiconductor substrate 221 and a second wiring structure 222 .

[0041] The first semiconductor substrate 211 and the second semiconductor substrate 221 may each be bulk silicon or SOI (silicon on insulator). In contrast, the first semiconductor substrate 211 and the second semiconductor substrate 221 may each be a silicon substrate, or may include other materials such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Optionally, the first semiconductor substrate 211 and the second semiconductor substrate 221 may each have an epitaxial layer formed on a base substrate.

[0042] The first wiring structure 212 may be formed on the first semiconductor substrate 211. The second wiring structure 222 may be formed on the second semiconductor substrate 221. The first wiring structure 212 and the second wiring structure 222 may each include a multi-layered wiring pattern and an insulating layer for insulating the multi-layered wiring pattern from each other.

[0043] A plurality of circuit elements may be formed on each of the first semiconductor substrate 211 and the second semiconductor substrate 221. The first wiring structure 212 may be electrically connected to the circuit elements on the first semiconductor substrate 211, and the second wiring structure 222 may be electrically connected to the circuit elements on the second semiconductor substrate 221.

[0044] The first semiconductor chip 210 may include a first chip pad 213. The first chip pad 213 may be used to electrically connect the first semiconductor chip 210 to other components. For example, the first chip pad 213 may be electrically connected to the first wiring structure 212. The first chip pad 213 may be exposed from the lower surface of the first wiring structure 212.

[0045] The second semiconductor chip 220 may include a second chip pad 223. The second chip pad 223 may be used to electrically connect the second semiconductor chip 220 to other components. For example, the second chip pad 223 may be electrically connected to the second wiring structure 222. The second chip pad 223 may be exposed from the lower surface of the second wiring structure 222.

[0046] The first chip pad 213 and the second chip pad 223 may each include a conductive material, such as but not limited to copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, and the like.

[0047] The first chip pad 213 may be in contact with or in direct contact with the first chip bump 215 and the first connection bump 324. The first chip pad 213 may be connected to the first chip bump 215 and the first connection bump 324. The first chip pad 213 may electrically connect the first chip bump 215 and the first wiring structure 212. The first chip pad 213 may electrically connect the first connection bump 324 and the first wiring structure 212. The first chip pad 213 may electrically connect the first semiconductor chip 210 to the connection wiring structure 320 through the first connection bump 324.

[0048] The second chip pad 223 may be in contact with or in direct contact with the second chip bump 225 and the second connection bump 326. The second chip pad 223 may be connected to the second chip bump 225 and the second connection bump 326. The second chip pad 223 may electrically connect the second chip bump 225 and the second wiring structure 222. The second chip pad 223 may electrically connect the second connection bump 326 and the second wiring structure 222. The second chip pad 223 may electrically connect the second semiconductor chip 220 to the connection wiring structure 320 through the second connection bump 326.

[0049] The first chip bump 215 may be formed on a lower surface of the first chip pad 213. The first chip bump 215 may connect the first chip pad 213 and the package wiring structure 120. That is, the first semiconductor chip 210 may be electrically connected to the package substrate 100 through the first chip bump 215 and the first chip pad 213. The first semiconductor chip 210 may transmit and receive electrical signals to and from the package substrate 100 through the first chip bump 215 and the first chip pad 213.

[0050] The first chip bumps 215 may include first power bumps 216 and first signal bumps 218. The first semiconductor chip 210 may receive power through the first power bumps 216. The first semiconductor chip 210 may receive or output a signal through the first signal bumps 218.

[0051] The first power bump 216 and the first signal bump 218 may be spaced apart from each other. For example, the first signal bump 218 may be located outside the first power bump 216. However, example embodiments are not limited thereto. For example, the first power bump 216 may be located outside the first signal bump 218.

[0052] The first power bump 216 may be positioned closer to the bridge die 300 than the first signal bump 218. For example, the first power bump 216 may be located further inward than the first signal bump 218. The distance between the power wiring structure 330 of the bridge die 300 and the first power bump 216 may be smaller than the distance between the power wiring structure 330 and the first signal bump 218.

[0053] The first power bump 216 and the first signal bump 218 may contact or directly contact the first chip pad 213 and the first upper pad 121. The first power bump 216 and the first signal bump 218 may be electrically connected to the first wiring structure 212 of the first semiconductor chip 210 through the first chip pad 213. The first power bump 216 and the first signal bump 218 may be electrically connected to the package wiring structure 120 through the first upper pad 121.

[0054] The first power bump 216 may be electrically connected to the power wiring structure 330. Specifically, the first power bump 216 may be connected to the bridge power bump 335 through the package wiring structure 120 of the package substrate 100. That is, the first semiconductor chip 210 and the power wiring structure 330 may be electrically connected through the first power bump 216, the package wiring structure 120, and the bridge power bump 335.

[0055] The first signal bump 218 may be electrically connected to the connection wiring structure 320. Specifically, the first signal bump 218 may be connected to the first connection bump 324 through the first wiring structure 212 of the first semiconductor chip 210. That is, the package substrate 100 and the connection wiring structure 320 may be electrically connected through the first signal bump 218, the first wiring structure 212, and the first connection bump 324.

[0056] The first power bump 216 may include a first upper power bump 216a and a first lower power bump 216b. The first signal bump 218 may include a first upper signal bump 218a and a first lower signal bump 218b. The first upper power bump 216a and the first upper signal bump 218a may contact or directly contact the first chip pad 213. The first lower power bump 216b and the first lower signal bump 218b may contact or directly contact the first upper pad 121.

[0057] The second chip bump 225 may be formed on the lower surface of the second chip pad 223. The second chip bump 225 may connect the second chip pad 223 and the package wiring structure 120. That is, the second semiconductor chip 220 may be electrically connected to the package substrate 100 through the second chip bump 225 and the second chip pad 223. The second semiconductor chip 220 may transmit and receive signals to and from the package substrate 100 through the second chip bump 225 and the second chip pad 223.

[0058] The second chip bumps 225 may include second power bumps 226 and second signal bumps 228. The second semiconductor chip 220 may receive power through the second power bumps 226. The second semiconductor chip 220 may receive or output a signal through the second signal bumps 228.

[0059] The second power bump 226 and the second signal bump 228 may be spaced apart from each other. For example, the second signal bump 228 may be located further outward than the second power bump 226. However, example embodiments are not limited thereto. For example, the second power bump 226 may be located further outward than the first signal bump 228.

[0060] The second power bump 226 may be positioned closer to the bridge die 300 than the second signal bump 228. For example, the second power bump 226 may be located further inward than the second signal bump 228. The distance between the power wiring structure 330 of the bridge die 300 and the second power bump 226 may be smaller than the distance between the power wiring structure 330 and the second signal bump 228.

[0061] The second power bump 226 and the second signal bump 228 may contact or directly contact the second chip pad 223 and the first upper pad 121. The second power bump 226 and the second signal bump 228 may be electrically connected to the second wiring structure 222 of the second semiconductor chip 220 through the second chip pad 223. The second power bump 226 and the second signal bump 228 may be electrically connected to the package wiring structure 120 through the first upper pad 121.

[0062] The second power bump 226 may be electrically connected to the power wiring structure 330. Specifically, the second power bump 226 may be electrically connected to the bridge power bump 335 through the package wiring structure 120 of the package substrate 100. That is, the second semiconductor chip 220 and the power wiring structure 330 may be electrically connected through the second power bump 226, the package wiring structure 120, and the bridge power bump 335.

[0063] The second signal bump 228 may be electrically connected to the connection wiring structure 320. Specifically, the second signal bump 228 may be electrically connected to the second connection bump 326 through the second wiring structure 222 of the second semiconductor chip 220. That is, the package substrate 100 and the connection wiring structure 320 may be electrically connected through the second signal bump 228, the second wiring structure 222, and the second connection bump 326.

[0064] The second power bump 226 may include a second upper power bump 226a and a second lower power bump 226b. The second signal bump 228 may include a second upper signal bump 228a and a second lower signal bump 228b. The second upper power bump 226a and the second upper signal bump 228a may contact or directly contact the second chip pad 223. The second lower power bump 226b and the second lower signal bump 228b may contact or directly contact the first upper pad 121.

[0065] The size of the first chip bump 215 and the second chip bump 225 may be greater than the size of the bridge power bump 335. The size of the first power bump 216, the first signal bump 218, the second power bump 226, and the second signal bump 228 may be greater than the size of the bridge power bump 335. For example, the width of the first chip bump 215 and the second chip bump 225 may be greater than the width of the bridge power bump 335. The height of the first chip bump 215 and the second chip bump 225 may be greater than the height of the bridge power bump 335.

[0066] For example, the sizes of the first upper power bump 216a, the first lower power bump 216b, the first upper signal bump 218a, and the first lower signal bump 218b may each be larger than the size of the bridge power bump 335. As another example embodiment, the size of each of the first upper power bump 216a and the first lower power bump 216b is smaller than the size of the bridge power bump 335, but the overall size of the first power bump 216 may be larger than the size of the bridge power bump 335. Although in some example embodiments, the size of each of the first upper signal bump 218a and the first lower signal bump 218b may be smaller than the size of the bridge power bump 335, the overall size of the first signal bump 218 may be larger than the size of the bridge power bump 335.

[0067] Similarly, the sizes of the second upper power bump 226a, the second lower power bump 226b, the second upper signal bump 228a, and the second lower signal bump 228b may each be larger than the size of the bridge power bump 335. In contrast, in some example embodiments, the size of each of the second upper power bump 226a and the second lower power bump 226b is smaller than the size of the bridge power bump 335, but the overall size of the second power bump 226 may be larger than the size of the bridge power bump 335. Although in some example embodiments, the size of each of the second upper signal bump 228a and the second lower signal bump 228b may be smaller than the size of the bridge power bump 335, the overall size of the second signal bump 228 may be larger than the size of the bridge power bump 335.

[0068] The first chip bumps 215 and the second chip bumps 225 may each be, for example but not limited to, solder bumps. Needless to say, the number, interval, arrangement form, etc. of each of the first chip bumps 215 and the second chip bumps 225 are not limited to those shown in the drawings and may vary according to design.

[0069] The bridge die 300 may be located on the package substrate 100 . The bridge die 300 may be located on lower surfaces of the first semiconductor chip 210 and the second semiconductor chip 220 . The bridge die 300 may overlap with the power ball 141 .

[0070] The bridge die 300 may be located between the first semiconductor chip 210 and the second semiconductor chip 220. Specifically, the bridge die 300 may overlap a portion of the first semiconductor chip 210 and a portion of the second semiconductor chip 220. The bridge die 300 may overlap a space where the first semiconductor chip 210 and the second semiconductor chip 220 are spaced apart from each other. A width W300 of the bridge die 300 may be smaller than a width W210 of the first semiconductor chip 210 and a width W220 of the second semiconductor chip 220.

[0071] The bridge die 300 may include a separation substrate 310 , a connection wiring structure 320 , and a power wiring structure 330 .

[0072] The bridge die 300 may include a first face 300S1 facing the lower surface 210BS of the first semiconductor chip 210 and the lower surface 220BS of the second semiconductor chip 220 . The bridge die 300 may include a second face 300S2 facing the package substrate 100 .

[0073] The bridge die 300 may include a connection wiring structure 320 at the first side 300S1. The connection wiring structure 320 may include the first side 300S1. The connection wiring structure 320 may be opposite to the lower surface 210BS of the first semiconductor chip 210 and the lower surface 220BS of the second semiconductor chip 220. The connection wiring structure 320 may include a second insulating layer 321 and a connection wiring 322.

[0074] The bridge die 300 may include a power wiring structure 330 at the second side 300S2. The power wiring structure 330 may include the second side 300S2. The power wiring structure 330 may be opposite to the package substrate 100. The power wiring structure 330 may include a third insulating layer 331 and a power wiring 332.

[0075] The connection wiring structure 320 and the power wiring structure 330 may be spaced apart from each other with the separation substrate 310 interposed therebetween. The connection wiring structure 320 and the power wiring structure 330 may not be electrically connected to each other.

[0076] The separation substrate 310 may be located between the first surface 300S1 and the second surface 300S2. For example, the separation substrate 310 may be located between the first surface 300S1 and the second surface 300S2 in the vertical direction. The separation substrate 310 may be located between the connection wiring structure 320 and the power wiring structure 330. The separation substrate 310 may not electrically connect the connection wiring structure 320 and the power wiring structure 330. For example, the separation substrate 310 may not include a through-path that electrically connects the connection wiring structure 320 and the power wiring structure 330. The separation substrate 310 may be bulk silicon.

[0077] The bridge die 300 may connect the first semiconductor chip 210 and the second semiconductor chip 220. Specifically, the connection wiring structure 320 of the bridge die 300 may connect the first semiconductor chip 210 and the second semiconductor chip 220. For example, the connection wiring structure 320 may provide a signal output by the first semiconductor chip 210 to the second semiconductor chip 220. As another example, the connection wiring structure 320 may provide a signal output by the second semiconductor chip 220 to the first semiconductor chip 210.

[0078] The bridge die 300 may include a first connection bump 324 and a second connection bump 326. The first connection bump 324 and the second connection bump 326 may be located on the first side 300S1 of the bridge die 300. The first connection bump 324 may be located between the first side 300S1 of the bridge die 300 and the lower surface 210BS of the first semiconductor chip 210. The second connection bump 326 may be located between the first side 300S1 of the bridge die 300 and the lower surface 220BS of the second semiconductor chip 220.

[0079] The first connection bump 324 may be located between the connection wiring structure 320 and the first semiconductor chip 210. The first connection bump 324 may be in contact with or in direct contact with the first chip pad 213. The second connection bump 326 may be located between the connection wiring structure 320 and the second semiconductor chip 220. The second connection bump 326 may be in contact with or in direct contact with the second chip pad 223.

[0080] The connection wiring structure 320 may be connected to the first wiring structure 212 of the first semiconductor chip 210 through the first connection bumps 324. The connection wiring structure 320 may transmit and receive electrical signals to and from the first semiconductor chip 210 through the first connection bumps 324.

[0081] The connection wiring structure 320 may be connected to the second wiring structure 222 of the second semiconductor chip 220 through the second connection bumps 326. The connection wiring structure 320 may transmit and receive electrical signals to and from the second semiconductor chip 220 through the second connection bumps 326.

[0082] The bridge die 300 may include a bridge power bump 335. The bridge power bump 335 may be located on the second side 300S2. The bridge power bump 335 may be located between the second side 300S2 of the bridge die 300 and the upper surface of the package substrate 100.

[0083] The bridge power bump 335 may be located between the power wiring structure 330 and the package substrate 100. The bridge power bump 335 may be in contact with the first upper pad 121 or in direct contact.

[0084] The bridge power bump 335 may electrically connect the power wiring structure 330 and the package substrate 100 .

[0085] For example, the power wiring structure 330 may be electrically connected to the package wiring structure 120 of the package substrate 100 through the bridging power bump 335. The power wiring structure 330 may receive power from the package wiring structure 120 through the bridging power bump 335.

[0086] The bridge power bump 335 may electrically connect the power wiring structure 330 , the first semiconductor chip 210 , and the second semiconductor chip 220 .

[0087] For example, the first semiconductor chip 210 and the second semiconductor chip 220 may be electrically connected to the power wiring structure 330 through the bridge power bump 335. Specifically, the first power bump 216 and the second power bump 226 may be electrically connected to the power wiring structure 330 through the bridge power bump 335 and the package wiring structure 120. Therefore, power may be supplied to the first semiconductor chip 210 through the first power bump 216, the package wiring structure 120, the bridge power bump 335, and the power wiring structure 330. In addition, power may be supplied to the second semiconductor chip 220 through the second power bump 226, the package wiring structure 120, the bridge power bump 335, and the power wiring structure 330.

[0088] The connection wiring structure 320 may provide a signal between the first semiconductor chip 210 and the second semiconductor chip 220. For example, the connection wiring structure 320 may transmit a signal output by the first semiconductor chip 210 to the second semiconductor chip 220. As another example, the connection wiring structure 320 may transmit a signal output by the second semiconductor chip 220 to the first semiconductor chip 210. The signal provided to the first semiconductor chip 210 and the second semiconductor chip 220 by the connection wiring structure 320 may have a lower level than the signal provided to the first semiconductor chip 210 and the second semiconductor chip 220 by the power wiring structure 330.

[0089] The power wiring structure 330 may include a power integrated circuit (power IC) for providing a power signal to the first semiconductor chip 210 and the second semiconductor chip 220. For example, the power wiring structure 330 may provide power to the first semiconductor chip 210. As another example, the power wiring structure 330 may provide power to the second semiconductor chip 220. The level of power provided by the power wiring structure 330 to the first semiconductor chip 210 and the second semiconductor chip 220 may be greater than the level of the signal provided by the connection wiring structure 320 to the first semiconductor chip 210 and the second semiconductor chip 220.

[0090] Figure 4 and Figure 5 is a diagram for explaining the operation of an integrated circuit device according to some example embodiments. For reference, Figure 4 2 is a diagram for explaining an operation of supplying power to the first semiconductor chip 210 and the second semiconductor chip 200 . Figure 5 1 is a diagram for explaining a signal connection operation between the first semiconductor chip 210 and the second semiconductor chip 200 .

[0091] Reference Figure 4 , power may be supplied from the outside to the package substrate 100 through the power ball 141. The power ball 141 may supply power to the bridge power bump 335. The power supplied to the power ball 141 may be supplied to the power wiring structure 330 through the bridge power bump 335.

[0092] The power wiring structure 330 may include a structure for redistributing power supplied to the first semiconductor chip 210 and the second semiconductor chip 220. The power wiring structure 330 may supply power to the first semiconductor chip 210 by bridging the power bump 335 and the first power bump 216. The power wiring structure 330 may supply power to the second semiconductor chip 220 by bridging the power bump 335 and the second power bump 226.

[0093] Reference Figure 5 , the first semiconductor chip 210 and the second semiconductor chip 220 may transmit and receive signals to and from the outside through the signal balls 142. In addition, the first semiconductor chip 210 and the second semiconductor chip 220 may transmit and receive signals to and from each other through the connection wiring structure 320.

[0094] The signal ball 142 may receive a signal from the outside. The signal may be provided from the outside to the package substrate 100 through the signal ball 142. For example, the signal provided to the signal ball 142 may include a command regarding the operation of the first semiconductor chip 210 and the second semiconductor chip 220.

[0095] The signal balls 142 may provide signals to the first signal bumps 218 and the second signal bumps 228. The first signal bumps 218 and the second signal bumps 228 may provide signals to the first wiring structure 212 of the first semiconductor chip 210 and the second wiring structure 222 of the second semiconductor chip 220, respectively.

[0096] The first semiconductor chip 210 and the second semiconductor chip 220 may output signals to the outside through the signal balls 142. The first semiconductor chip 210 may provide signals to the package substrate 100 through the first signal bumps 218. The second semiconductor chip 220 may provide signals to the package substrate 100 through the second signal bumps 228. The package substrate 100 may output signals provided from the first semiconductor chip 210 and the second semiconductor chip 220 to the outside through the signal balls 142.

[0097] The first semiconductor chip 210 may provide a signal to the second semiconductor chip 220. Specifically, the first semiconductor chip 210 may provide a signal to the connection wiring structure 320 through the first connection bumps 324. The connection wiring structure 320 may provide a signal to the second semiconductor chip 220 through the second connection bumps 326.

[0098] Similarly, the second semiconductor chip 220 may provide a signal to the first semiconductor chip 210. Specifically, the second semiconductor chip 220 may provide a signal to the connection wiring structure 320 through the second connection bumps 326. The connection wiring structure 320 may provide a signal to the first semiconductor chip 210 through the first connection bumps 324.

[0099] The connection wiring structure 320 may include a structure for rewriting signals provided to the first semiconductor chip 210 and the second semiconductor chip 220. The first semiconductor chip 210 and the second semiconductor chip 220 may directly transmit and receive signals through the connection wiring structure 320.

[0100] Figure 6 is a diagram for explaining a semiconductor package according to some example embodiments. For ease of explanation, the description will focus on Figures 1 to 3 The points described are different.

[0101] Reference Figure 6 , a semiconductor package according to some example embodiments may include a first passive element 410. For example, the first passive element 410 may be located on a lower surface of the package substrate 100. The first passive element 410 may be spaced apart from the external connection terminal 140 on the lower surface of the package substrate 100.

[0102] Despite Figure 6 The first passive element 410 is shown as being located between the power ball 141 and the signal ball 142, but example embodiments are not limited thereto. For example, the first passive element 410 may be located outside the signal ball 142 and may not be located near the power ball 141. As another example, the first passive element 410 may be located further inside than the power ball 141 and the signal ball 142 and located between a plurality of power balls 141.

[0103] The first passive element 410 may include, for example, an inductor. The first passive element 410 may be used when power is supplied from the power ball 141 to the first and second semiconductor chips 210 and 220 through the power wiring structure 330.

[0104] Figures 7 to 15 is a diagram for explaining a semiconductor package according to some example embodiments. For ease of explanation, the description will focus on Figures 1 to 6 The points described are different.

[0105] Reference Figure 7, the package substrate 100 may include a recess R100. The bridging power bump 335 may be located within the recess R100. For example, the lower surface of the power wiring structure 330 may be located on the same plane as the upper surface of the package substrate 100. However, example embodiments are not limited thereto.

[0106] Reference Figure 7 ,and Figure 2 In contrast, when the bridge power bump 335 is located in the recess R100, the distance between the package substrate 100, the first semiconductor chip 210 and the second semiconductor chip 220 can be relatively reduced. Therefore, the first chip bump 215 and the second chip bump 225 can each be composed of a single bump without including an upper bump and a lower bump. For example, the first power bump 216 may not include a first upper power bump ( Figure 2 216a) and the first lower power bump ( Figure 2 The first signal bump 218 may not include a first upper signal bump ( Figure 2 218a) and the first lower signal bump ( Figure 2 The second power bump 226 may not include a second upper power bump ( Figure 2 226a) and the second lower power bump ( Figure 2 The second signal bump 228 may not include a second upper signal bump ( Figure 2 228a) and the second lower signal bump ( Figure 2 228b).

[0107] although Figure 7 Only the bridging power bump 335 is shown to be located in the recess R100, but example embodiments are not limited thereto. For example, the bridging power bump 335 and the power wiring structure 330 may be located in the recess R100. In this case, the upper surface of the packaging substrate 100 and the lower surface of the separation substrate 310 may be located on the same plane.

[0108] Reference Figure 8 , a semiconductor package according to some example embodiments may include a silicon capacitor 420. The silicon capacitor 420 may be located within the package substrate 100. The silicon capacitor 420 may be located adjacent to the power wiring structure 330. For example, the silicon capacitor 420 may be located further inside than the first signal bump 218 and the second signal bump 228. Although the silicon capacitor 420 is shown as being connected to the first power bump 216 and the second power bump 226, example embodiments are not limited thereto.

[0109] When power is supplied from the power ball 141 to the first and second semiconductor chips 210 and 220 through the power wiring structure 330 , the silicon capacitor 420 may be used.

[0110] Reference Fig. 9 , a semiconductor package according to some example embodiments may include a first interposer 500 .

[0111] The first interposer 500 may be located on the bridge die 300. The first interposer 500 may be connected to the package substrate 100 through the first pillar structure 610. The first pillar structure 610 may pass through the first mold film 601. The first interposer 500 may be located on the first mold film 601.

[0112] The bridge die 300 may be located within the first molding film 601. The first molding film 601 may surround the bridge die 300. The first molding film 601 may include, for example but not limited to, an insulating polymer material such as EMC (Epoxy Molding Compound).

[0113] The first passive component 410 may be located within the first molding film 601. The first passive component 410 may be located between the first pillar structure 610 and the bridge die 300. The first passive component 410 may be located closer to the bridge die 300 than the first pillar structure 610.

[0114] The first interposer 500 may include a fourth insulating layer 510 and a first interposer wiring 520. The fourth insulating layer 510 may include a second substrate 511, a second lower passivation film 513, and a second upper passivation film 512. The first interposer wiring 520 may include a second lower pad 523, a second wiring 522, and a second upper pad 521.

[0115] The first chip bumps 215 of the first semiconductor chip 210 and the second chip bumps 225 of the second semiconductor chip 220 may be located on the first interposer 500. The first semiconductor chip 210 may be electrically connected to the first interposer wiring 520 of the first interposer 500 through the first chip bumps 215. The second semiconductor chip 220 may be electrically connected to the first interposer wiring 520 of the first interposer 500 through the second chip bumps 225.

[0116] The power ball 141 may provide power to the first semiconductor chip 210 and the second semiconductor chip 220 through the package wiring structure 120, the power wiring structure 330, the first pillar structure 610, and the first interposer wiring 520. For example, the power wiring structure 330 may redistribute the power provided from the power ball 141 and provide power to the first semiconductor chip 210 and the second semiconductor chip 220 through the package wiring structure 120, the first pillar structure 610, and the first interposer wiring 520.

[0117] The first semiconductor chip 210 and the second semiconductor chip 220 may transmit and receive signals through the first interposer wiring 520 and the connection wiring structure 320. For example, a signal output from the first semiconductor chip 210 may be provided to the connection wiring structure 320 through the first chip bump 215 and the first interposer wiring 520. The connection wiring structure 320 may provide the signal provided from the first semiconductor chip 210 to the second semiconductor chip 220 through the first interposer wiring 520 and the second chip bump 225. Similarly, a signal output from the second semiconductor chip 220 may be provided to the connection wiring structure 320 through the second chip bump 225 and the first interposer wiring 520. The connection wiring structure 320 may provide the signal provided from the second semiconductor chip 220 to the first semiconductor chip 210 through the first interposer wiring 520 and the first chip bump 215.

[0118] The first semiconductor chip 210 and the second semiconductor chip 220 may provide signals to the package substrate 100 through the first interposer wiring 520 and the first pillar structure 610. The first semiconductor chip 210 and the second semiconductor chip 220 may output signals to the first interposer wiring 520. The first interposer wiring 520 may provide signals provided from the first semiconductor chip 210 and the second semiconductor chip 220 to the package substrate 100 through the first pillar structure 610.

[0119] Reference Fig.10 , a semiconductor package according to some example embodiments may include a third semiconductor chip 230 , a fourth semiconductor chip 240 , and a second interposer 700 .

[0120] The first semiconductor chip 210 and the second semiconductor chip 220 may be located within the second mold film 602. The second mold film 602 may surround the first semiconductor chip 210 and the second semiconductor chip 220. The second mold film 602 may include, for example but not limited to, an insulating polymer material such as EMC (Epoxy Molding Compound).

[0121] The second interposer 700 may be located on the first semiconductor chip 210 and the second semiconductor chip 220. The second interposer 700 may be located on the second mold film 602. The second interposer 700 may include a fifth insulating layer 710 and a second interposer wiring 720. The fifth insulating layer 710 may include a third substrate 711, a third lower passivation film 713, and a third upper passivation film 712. The second interposer wiring 720 may include a third lower pad 723, a third wiring 722, and a third upper pad 721.

[0122] The third semiconductor chip 230 and the fourth semiconductor chip 240 may be located on the second interposer 700. The third semiconductor chip 230 may include a third semiconductor substrate 231 and a third wiring structure 232, and the fourth semiconductor chip 240 may include a fourth semiconductor substrate 241 and a fourth wiring structure 242. The third semiconductor chip 230 may be electrically connected to the second interposer wiring 720 of the second interposer 700 through a third chip bump 235. The fourth semiconductor chip 240 may be electrically connected to the second interposer wiring 720 of the second interposer 700 through a fourth chip bump 245. The third semiconductor chip 230 and the fourth semiconductor chip 240 may include a third chip pad 233 and a fourth chip pad 243, respectively.

[0123] The second pillar structure 620 may pass through the second mold film 602. The second pillar structure 620 may extend from the first interposer 500 to the second interposer 700 inside the second mold film 602. The second pillar structure 620 may electrically connect the first interposer wiring 520 of the first interposer 500 and the second interposer wiring 720 of the second interposer 700.

[0124] The third semiconductor chip 230 and the fourth semiconductor chip 240 may be provided with power through the package wiring structure 120, the power wiring structure 330, the first pillar structure 610, the first interposer 500, the second pillar structure 620, and the second interposer 700. However, example embodiments are not limited thereto. For example, the power wiring structure 330 is used when power is provided to the first semiconductor chip 210 and the second semiconductor chip 220, but the power wiring structure 330 may not be used when power is provided to the third semiconductor chip 230 and the fourth semiconductor chip 240.

[0125] Reference Fig.11 , the first interposer 500 may include a first sub-interposer 501 and a second sub-interposer 502 .

[0126] The first separation space 500SP may be located between the first sub-interposer 501 and the second sub-interposer 502. The second mold film 602 may fill the first separation space 500SP.

[0127] The first semiconductor chip 210 may be located on the first sub-interposer 501 . The second semiconductor chip 220 may be located on the second sub-interposer 502 .

[0128] The bridge die 300 may be located under the first sub interposer 501 and the second sub interposer 502. The connection wiring structure 320 may be located under the first sub interposer 501 and the second sub interposer 502. The connection wiring structure 320 may be positioned to overlap a portion of the first sub interposer 501 and a portion of the second sub interposer 502.

[0129] The first connection bump 324 may be located on the lower surface of the first sub-interposer 501. The first connection bump 324 may be connected to the second lower pad 523 of the first sub-interposer 501. The second connection bump 326 may be located on the lower surface of the second sub-interposer 502. The second connection bump 326 may be connected to the second lower pad 523 of the second sub-interposer 502.

[0130] Reference Fig.12 , the second interposer 700 may include a third sub-interposer 701 and a fourth sub-interposer 702 .

[0131] The second separation space 700SP may be located between the third sub-intersperse 701 and the fourth sub-intersperse 702. The second separation space 700SP may be filled with the second mold film 602. The upper surface of the second mold film 602 in the second separation space 700SP may be located on the same plane as the upper surfaces of the third sub-intersperse 701 and the fourth sub-intersperse 702.

[0132] The third semiconductor chip 230 may be located on the third sub-interposer 701. The fourth semiconductor chip 240 may be located on the fourth sub-interposer 702. The third chip bumps 235 of the third semiconductor chip 230 may be connected to the second interposer wiring 720 of the third sub-interposer 701. The fourth chip bumps 245 of the fourth semiconductor chip 240 may be connected to the second interposer wiring 720 of the fourth sub-interposer 702.

[0133] Reference Fig.13 , the mold film may not be located in the second separation space 700SP between the third sub-intersperse 701 and the fourth sub-intersperse 702. The second mold film 602 may be located below the third sub-intersperse 701 and the fourth sub-intersperse 702. The upper surface of the second mold film 602 may be located on the same plane as the lower surface of the third sub-intersperse 701 and the lower surface of the fourth sub-intersperse 702.

[0134] Reference Fig.14 , the package substrate 100 may include a first sub-substrate 101 and a second sub-substrate 102. The third separation space 100SP may be located between the first sub-substrate 101 and the second sub-substrate 102. The lower surface of the first mold film 601 may be exposed to the third separation space 100SP.

[0135] The power balls 141 may be located on a lower surface of the first sub-substrate 101 and a lower surface of the second sub-substrate 102 .

[0136] Power supplied to the first semiconductor chip 210 by the power ball 141 may be supplied to the first semiconductor chip 210 through the package wiring structure 120 , the power wiring structure 330 , the first pillar structure 610 , and the first sub interposer 501 of the first sub substrate 101 .

[0137] The power supplied to the second semiconductor chip 220 by the power ball 141 may be supplied to the second semiconductor chip 220 through the package wiring structure 120 of the second sub-substrate 102 , the power wiring structure 330 , the first pillar structure 610 , and the second sub-interposer 502 .

[0138] The bridge die 300 may be located over the first sub-substrate 101 and the second sub-substrate 102. The bridge die 300 may be located to overlap a portion of the first sub-substrate 101 and a portion of the second sub-substrate 102. The power wiring structure 330 may be located over the first sub-substrate 101 and the second sub-substrate 102.

[0139] A portion of the bridge power bump 335 may be located on the first sub-substrate 101. A portion of the bridge power bump 335 may be electrically connected to the package wiring structure 120 of the first sub-substrate 101. Another portion of the bridge power bump 335 may be located on the second sub-substrate 102. Another portion of the bridge power bump 335 may be electrically connected to the package wiring structure 120 of the second sub-substrate 102.

[0140] Reference Fig.15 , the second passive element 430 may be located within the second mold film 602. The second passive element 430 may be located between the first semiconductor chip 210 and the second pillar structure 620. The second passive element 430 may be located between the second semiconductor chip 220 and the second pillar structure 620. The second mold film 602 may cover the second passive element 430. The second passive element 430 may include, for example, an inductor. The second passive element 430 may be used when power is supplied from the power ball 141 to the first semiconductor chip 210 and the second semiconductor chip 220 through the power wiring structure 330.

[0141] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the inventive concept are used only in a general and descriptive sense, and not for the purpose of limitation.

[0142] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0106375 filed in the Korean Intellectual Property Office on August 14, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising: Package substrate; A first semiconductor chip, on the packaging substrate; a second semiconductor chip, on the packaging substrate and spaced apart from the first semiconductor chip; as well as a bridge die on the package substrate and below the first semiconductor chip and the second semiconductor chip, The bridge core comprises: a first surface facing the first semiconductor chip and the second semiconductor chip, The second side faces the packaging substrate. a connection wiring structure at the first face and electrically connecting the first semiconductor chip and the second semiconductor chip, and A power wiring structure is at the second surface and is configured to supply power to the first semiconductor chip and the second semiconductor chip.

2. The semiconductor package according to claim 1, The connection wiring structure and the power supply wiring structure are not connected.

3. The semiconductor package according to claim 1, wherein the bridging die further comprises a spacer substrate between the first face and the second face, and The connection wiring structure and the power wiring structure are spaced apart from each other, and the separation substrate is interposed between the connection wiring structure and the power wiring structure.

4. The semiconductor package according to claim 1, The width of the bridge die is smaller than the width of the first semiconductor chip and the width of the second semiconductor chip.

5. The semiconductor package according to claim 1, further comprising: a first chip bump, between the first semiconductor chip and the packaging substrate; a second chip bump, between the second semiconductor chip and the packaging substrate; as well as A power bump is between the bridge die and the package substrate and connected to the power wiring structure.

6. The semiconductor package according to claim 5, The size of the first chip bump and the size of the second chip bump are greater than the size of the power bump.

7. The semiconductor package according to claim 5, wherein the package substrate comprises a recess at an upper surface of the second side facing the bridge die, and The power bump is within the recess, or the power bump and the power wiring structure are within the recess.

8. The semiconductor package according to claim 1, further comprising: an interposer on the package substrate, wherein the first semiconductor chip and the second semiconductor chip are above the interposer, and The bridge die is beneath the interposer.

9. The semiconductor package according to claim 8, further comprising: A pillar structure extends between the interposer and the package substrate and is spaced apart from the bridge die.

10. The semiconductor package according to claim 1, wherein the first semiconductor chip is a logic chip, and The second semiconductor chip is a memory chip.

11. The semiconductor package according to claim 1, further comprising: Passive components are on the lower surface of the packaging substrate.

12. The semiconductor package according to claim 1, further comprising: A molding film is between the package substrate and the first semiconductor chip and between the package substrate and the second semiconductor chip and surrounds a side surface of the bridge die.

13. The semiconductor package according to claim 1, The bridge die overlaps a portion of the first semiconductor chip and a portion of the second semiconductor chip.

14. A semiconductor package, comprising: Package substrate; a first semiconductor chip on the package substrate and including a first power bump on a first lower surface facing the package substrate; a second semiconductor chip on the package substrate and spaced apart from the first semiconductor chip, and including a second power bump on a second lower surface facing the package substrate; as well as a bridge die on the package substrate and below the first semiconductor chip and the second semiconductor chip, and electrically connecting the first semiconductor chip and the second semiconductor chip, The bridge core comprises: a connection wiring structure at a first face facing the first semiconductor chip and the second semiconductor chip and electrically connecting the first semiconductor chip and the second semiconductor chip, a power wiring structure, at the second surface facing the packaging substrate and spaced apart from the connection wiring structure, and a separation substrate, between the connection wiring structure and the power wiring structure, wherein the package substrate includes a power ball on a lower surface of the package substrate and electrically connected to the power wiring structure, and The power wiring structure is electrically connected to the first power bump and the second power bump.

15. The semiconductor package according to claim 14, wherein the first semiconductor chip further includes a first signal bump on the first lower surface that is spaced apart from the first power bump, The second semiconductor chip further includes a second signal bump on the second lower surface spaced apart from the second power bump, The package substrate further includes a signal ball, the signal ball being on the lower surface of the package substrate and spaced apart from the power ball, and The first signal bump and the second signal bump are electrically connected to the signal ball.

16. The semiconductor package according to claim 15, further comprising: A passive component is between the power ball and the signal ball and on the lower surface of the packaging substrate.

17. The semiconductor package according to claim 14, The power ball overlaps with the bridge core.

18. The semiconductor package according to claim 14, further comprising: an interposer on the package substrate, wherein the first semiconductor chip and the second semiconductor chip are on the interposer, and The bridge die is beneath the interposer.

19. The semiconductor package according to claim 18, The intermediate layer includes: a first sub-interposer, beneath the first semiconductor chip, and a second sub-interposer spaced apart from the first sub-interposer and below the second semiconductor chip, and The bridge die overlaps a portion of the first sub-interposer and a portion of the second sub-interposer.

20. An integrated circuit device comprising: Package substrate; A first semiconductor chip, on the packaging substrate; a second semiconductor chip, on the packaging substrate and spaced apart from the first semiconductor chip; as well as a bridge die on the package substrate and between the first semiconductor chip and the second semiconductor chip, The bridge core comprises: a first surface facing the first semiconductor chip and the second semiconductor chip, The second side faces the packaging substrate. a connection wiring structure at the first face and electrically connecting the first semiconductor chip and the second semiconductor chip, and a power wiring structure at the second surface and configured to supply power to the first semiconductor chip and the second semiconductor chip, The level of the signal provided to the connection wiring structure is lower than the level of the signal provided to the power supply wiring structure.

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