Package architecture with bridge die with air gap around via

Abstract

An embodiment of a semiconductor die includes a first bond pad on a first surface to couple to a package substrate; a second bond pad on a second surface, the second surface being opposite the first surface; a hole passing through the semiconductor die; a conductive pillar within the hole separated from a sidewall of the hole by an air gap, the conductive pillar coupled to the first bond pad and the second bond pad; and a path conductively coupling at least two integrated circuit (IC) dies proximate the second surface.

Description

Technical Field

[0001] The present disclosure relates to techniques, methods, and apparatus for a package architecture having a bridge die with air gaps around vias. Background Art

[0002] Electronic circuits, when typically fabricated on wafers of semiconductor material such as silicon, are referred to as integrated circuits (ICs). Wafers with such ICs are typically cut into many individual die. The die may be packaged into an IC package, which contains one or more die and other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated into an electronic system such as a consumer electronic system or a server such as a mainframe. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. In the figures of the accompanying drawings, the embodiments are shown by way of example and not by way of limitation.

[0004] Figure 1 is a schematic cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure.

[0005] Figure 2A According to some embodiments of the present disclosure Figure 1 Schematic cross-sectional view of an example through-hole with an air gap in a microelectronic assembly of FIG.

[0006] Figure 2B According to some other embodiments of the present disclosure Figure 1 Schematic cross-sectional view of another example through-hole with an air gap in a microelectronic assembly of FIG.

[0007] Figure 2C yes Figure 2A Schematic plan view of an example through hole with an air gap.

[0008] Figure 3 According to another embodiment of the present disclosure Figure 1 Schematic cross-sectional view of a portion of an example microelectronic assembly.

[0009] Figure 4 is a simplified cross-sectional plan view of a detail of an example microelectronic assembly according to various embodiments of the present disclosure.

[0010] Figures 5A-5D are simplified cross-sectional views of various stages of fabrication of an example via with an air gap according to various embodiments of the present disclosure.

[0011] Figure 6is a top view of a wafer including one or more semiconductor dies of a microelectronic package according to any embodiment disclosed herein.

[0012] Figure 7 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any embodiment disclosed herein.

[0013] Figure 8 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any embodiment disclosed herein.

[0014] Fig. 9 is a block diagram of an example computing device including one or more microelectronic assemblies according to any embodiment disclosed herein. DETAILED DESCRIPTION Overview

[0015] In order to explain the IC packaging described herein, it is important to understand the phenomena that may come into play during the assembly and packaging of the IC. The following basic information can be considered as the basis on which the present disclosure can be properly explained. Such information is provided for the purpose of explanation only, and therefore, should not be interpreted in any way to limit the broad scope of the present disclosure and its potential applications.

[0016] The demand for increased integration of form factor miniaturization and high performance is driving complex packaging methods in the semiconductor industry. Advances in semiconductor processing and logic design have allowed an increase in the number of logic circuits that can be included in processors and other IC devices. Therefore, many processors now have multiple cores monolithically integrated on a die. In general, these types of monolithic ICs are also called planar because they take the form of a flat surface and are typically built on a single silicon wafer made of a single crystal silicon boule. The typical manufacturing process for such a monolithic IC is called a planar process, which allows lithography, etching, thermal diffusion, oxidation and other such processes to occur on the surface of the wafer so that active circuit elements (such as transistors and diodes) are formed on the planar surface of the silicon wafer.

[0017] Current technology allows hundreds or thousands of such active circuit elements to be formed on a single die, making it possible to implement many logic circuits on it. In such a monolithic die, the manufacturing process must be optimized equally for all circuits, resulting in trade-offs between different circuits. Furthermore, due to the constraint that the circuits must be placed on a planar surface, some circuits are located farther away from some others, resulting in reduced performance, such as longer delays. Manufacturing yields may also be severely affected, since if even one circuit fails, the entire die may have to be discarded.

[0018] One solution used to overcome such negative effects of monolithic dies is to decompose the circuit into smaller dies (e.g., chiplets, tiles) electrically coupled by interconnect bridges. The smaller dies are part of an assembly of interconnected dies that together form a complete IC in terms of application and / or functionality, such as a memory chip, a microprocessor, a microcontroller, a commercial IC (e.g., a chip for repetitive processing routines, simple tasks, dedicated ICs, etc.), and a system on a chip (SOC). In other words, individual dies are connected to create the functionality of a monolithic IC. By using separate dies, each individual die can be optimized for specific functionality. For example, a processor core containing logic circuits can be targeted for performance and therefore may require an extremely fast optimized layout; this has different manufacturing requirements than a USB controller, which is built to meet certain USB standards rather than for processing speed; by separating different parts of the overall design into different dies, each die is optimized in design and manufacturing, and the overall yield and cost of the combined die solution can be improved.

[0019] The connection between these dies can be achieved in a variety of ways. For example, in a 2.5D packaging solution, silicon interposers and through-silicon vias (TSVs) connect the dies at silicon interconnect speeds in a minimal footprint. In another example, a silicon bridge embedded under the edge of two interconnected dies facilitates electrical coupling between them. The bridge die can be embedded in the package substrate, which allows the top packaged chip to communicate with other chips horizontally using the bridge die, and vertically with other chips using through-mold vias (TMVs) in the package substrate. Such die partitioning enables miniaturization and high performance in a small form factor without the yield issues that occur with other methods, but requires fine die-to-die interconnects. Bridge dies can facilitate such high-density interconnects by inserting the bridge die only where needed.

[0020] However, many bridge dies are limited in power delivery due to the lack of TSVs. Although bridge dies can be manufactured with TSVs, the electrical parasitics (e.g., resistance, capacitance, inductance, etc.) of such TSVs can limit their electrical efficiency. Therefore, currently, power delivery using bridge dies is achieved by routing wires around the bridge die, which results in design limitations on routing and trace placement on the die and substrate.

[0021] Thus, embodiments described herein implement an IC package that includes: a package substrate having a surface with a blind cavity extending partially from the surface through the package substrate; a plurality of IC dies attached to the surface of the package substrate; and a bridge die attached to the plurality of IC dies in the blind cavity. The bridge die has a conductive path that conductively couples the IC dies in the plurality of IC dies, a TSV extending through the thickness of the bridge die, and an air gap surrounding at least one TSV. The air gap is used to reduce parasitic effects, such as impedance and dielectric constant, and corresponding losses around the TSV.

[0022] Some embodiments described herein implement a semiconductor die (e.g., a bridge die) having: a first bonding pad on a first surface for coupling to a packaging substrate; a second bonding pad on a second surface, the second surface being opposite to the first surface; a hole through the semiconductor die, the hole having a first end on the first surface and a second end on the second surface; a conductive column within the hole, which is separated from a sidewall of the hole by an air gap, the conductive column being directly coupled to the first bonding pad and the second bonding pad; and a path that conductively couples at least two IC dies proximate to the second surface.

[0023] Some other embodiments described herein provide a package substrate including a buildup layer, a cavity in the buildup layer, and a semiconductor die in the cavity. The semiconductor die has a plurality of conductive vias near its periphery. Each conductive via can extend through the thickness of the semiconductor die, and an air gap can surround each conductive via.

[0024] Embodiments disclosed herein also provide a method for making an air gap around a conductive via through a bridge die, the method comprising: providing a wafer of semiconductor material having a first surface and an opposing second surface, forming through holes in the wafer, each through hole extending through the thickness of the wafer between the first surface and the second surface, adding conductive material in the through holes such that there is a gap laterally between the sidewall of each through hole and the conductive material, and forming bonding pads on the first surface and the second surface, at least a subset of the bonding pads covering each through hole on the first surface and the second surface such that the conductive material in each through hole is directly coupled to the bonding pads on the first surface and the second surface. In some embodiments, the through holes can be formed by reactive ion etching.

[0025] Each of the structures, assemblies, packages, methods, devices, and systems disclosed herein may have several innovative aspects, no single one of which is solely responsible for all of the desirable properties disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0026] In the following detailed description, various aspects of the illustrative implementations may be described using terms that are commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

[0027] The terms "circuit" and "circuit module" refer to one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide a desired functionality. The terms also refer to analog circuit modules, digital circuit modules, hardwired circuit modules, programmable circuit modules, microcontroller circuit modules, and / or any other type of physical hardware electrical and / or electronic components.

[0028] The term "integrated circuit" refers to an electrical circuit that is integrated into a single piece of semiconductor or similar material.

[0029] In some embodiments, the IC die disclosed herein may include a substantially single-crystal semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body), on which integrated circuits are manufactured using conventional semiconductor processing methods. The semiconductor base material may include, for example, an N-type or P-type material. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more of the IC dies may include an alternative material, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In other embodiments, the base material may include a compound semiconductor, for example, a first sublattice having at least one element from Group III of the periodic table (e.g., Al, Ga, In), and a second sublattice having at least one element from Group V of the periodic table (e.g., P, As, Sb). In still other embodiments, the base material may include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, there may be a nominal impurity doping level. In still other embodiments, the die may include an amorphous material, such as a polymer; for example, the base material may include a silicon dioxide-filled epoxy. In other embodiments, the base material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Typically, the base material may include one or more of: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although a few examples of materials for the die are described herein, any material or structure that can be used as a foundation (e.g., a base material) falls within the spirit and scope of the present disclosure on which IC circuits and structures as described herein can be built.

[0030] Unless otherwise specified, an IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a certain functionality. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuit modules (e.g., ICs that implement one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "computing die" may be used to describe a die that includes one or more ICs that implement logic / computing circuit modules (e.g., ICs that implement one or more of I / O functions, arithmetic operations, data pipelining, etc.).

[0031] In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die." Note that the terms "chip," "die," and "IC die" are used interchangeably herein.

[0032] The term "optical structure" includes an arrangement made in an IC to receive, convert and / or transmit an optical signal as described herein. It may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light emitting diodes (LEDs), and optoelectronic devices such as photodetectors.

[0033] In various embodiments, any photonic IC (PIC) described herein may include semiconductor materials, including, for example, N-type or P-type materials. The PIC may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor materials) or an SOI structure (or a semiconductor-on-insulator structure in general). In some embodiments, the PIC may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, aluminum indium arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of Group III-N or Group IV materials. In some embodiments, the PIC may include amorphous materials, such as polymers. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be non-uniform, including a carrier material (e.g., glass or silicon carbide) as a base material with a thin semiconductor layer, above which is an active side including transistors and similar components. Although several examples of materials for PICs are described herein, any material or structure that can be used as a base upon which a PIC can be built falls within the spirit and scope of the present disclosure.

[0034] Unless otherwise specified, the term "insulation" means "electrical insulation" and the term "conduction" means "conductive conduction." With respect to optical signals and / or devices, components and elements that operate or use optical signals, the term "conduction" may also mean "optical conduction."

[0035] The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

[0036] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0037] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material that solidifies after treatment as described herein) that is substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide, or combinations thereof. They may include dielectric materials, high polarizability materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfills and mold or mold-like materials used in packaging applications, including, for example, materials used for organic interposers, package supports, and other such components.

[0038] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those elements that are monolithically integrated within the IC, mounted on the IC, or connected to the IC. The IC described herein may be analog or digital and may be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC described herein may be used in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0039] In various embodiments of the present disclosure, the transistor described herein may be a field effect transistor (FET), such as a MOSFET. In many embodiments, the FET is a four-terminal device. In SOI or nanoribbon or full gate (GAA) FET, the FET is a three-terminal device, including source, drain and gate terminals, and uses an electric field to control the current flowing through the device. FETs typically include a channel material, a source region and a drain region provided in and / or on the channel material, and a gate stack, the gate stack including a gate electrode material (alternatively referred to as a "work function" material) provided on a portion of the channel material ("channel portion") between the source region and the drain region, and optionally also including a gate dielectric material between the gate electrode material and the channel material.

[0040] In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, thereby facilitating the communication of optical signals between them. As used herein, the term "interconnect" includes both electrical and optical interconnects. The nature of the interconnect described herein will be understood with reference to the signal medium associated therewith. Therefore, when used with reference to an electronic device (e.g., an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material that is used to provide an electrical connection to one or more elements associated with the IC and / or between various such elements. In such a case, the term "interconnect" may refer to both conductive traces (sometimes also referred to as "wires", "conducting wires", "metal wires" or "grooves") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, to highlight the fact that these elements include conductive materials (e.g., metals). Likewise, when used with reference to a device that also operates on optical signals, such as a photonic IC (PIC), "interconnect" may also describe any element formed from optically conductive materials that is used to provide an optical connection to one or more elements associated with a PCI. In such cases, the term "interconnect" may refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0041] The term "waveguide" refers to any structure used to guide light to propagate from one location to another, typically through a substrate material such as silicon or glass. In various examples, the waveguide can be formed of silicon, doped silicon, silicon nitride, glass such as silicon dioxide (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), etc. The waveguide can be formed using various techniques, including but not limited to in-situ waveguide formation. For example, in some embodiments, the waveguide can be formed in-situ in glass using low temperature glass-glass bonding or by laser direct writing. The waveguide formed in-situ can have lower loss characteristics.

[0042] The term "conductive trace" may be used to describe conductive elements separated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided within the IC die. Within package substrates and PCBs, such insulating materials include organic materials such as Ajinomoto buildup films (ABF), polyimide, or epoxy. Such conductors are typically arranged in several levels or layers of a metallization stack.

[0043] The term "conductive via" may be used to describe an electrically conductive element that interconnects two or more conductors of different levels of a metallization stack. To this end, a via may be provided that is substantially perpendicular to the plane of the IC die / chip or a supporting structure over which the IC structure is provided and may interconnect two conductors in adjacent levels or two conductors in non-adjacent levels.

[0044] The term "package substrate" may be used to describe any substrate material that facilitates packaging together any collection of semiconductor dies and / or other electrical components such as passive electrical components. As used herein, a package substrate may be formed of any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate including a buildup layer (e.g., an ABF layer).

[0045] The term "metallization stack" may be used to refer to one or more interconnect stacks used to provide connections to different circuit components of an IC die / chip and / or a package substrate.

[0046] As used herein, the term "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0047] In the context of a stack of dies coupled to each other, or in the context of a die coupled to a package substrate, the term "interconnect" may also refer to a die-to-die (DTD) interconnect and a die-to-package substrate (DTPS) interconnect, respectively. A DTD interconnect may also be referred to as a first-level interconnect (FLI). A DTPS interconnect may also be referred to as a second-level interconnect (SLI).

[0048] Although not specifically shown in all of the figures in this illustration in order not to clutter the drawings, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the second die or package substrate may include a second set of conductive contacts. One or more conductive contacts of the first set may then be electrically and mechanically coupled to some of the conductive contacts of the second set via the DTD or DTPS interconnect.

[0049] In some embodiments, the pitch of the DTD interconnects may be different than the pitch of the DTPS interconnects, although in other embodiments these pitches may be substantially the same.

[0050] The DTPS interconnect disclosed herein can take any suitable form. In some embodiments, a group of DTPS interconnects can include solder (e.g., solder bumps or balls that undergo thermal reflow to form DTPS interconnects). DTPS interconnects including solder can include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth or other alloys. In some embodiments, a group of DTPS interconnects can include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive glues. Anisotropic conductive materials can include conductive materials dispersed in non-conductive materials. In some embodiments, anisotropic conductive materials can include microscopic conductive particles embedded in an adhesive or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy resin or an acrylic-based material). In some embodiments, conductive particles can include polymers and / or one or more metals (e.g., nickel or gold). For example, conductive particles can include nickel-coated gold or silver-coated copper, which are coated with polymers in turn. In another example, the conductive particles can include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the compressed area can contact each other to form a conductive path from one side of the film to the other side in the compressed area.

[0051] The DTD interconnect disclosed herein can take any suitable form. In some embodiments, some or all of the DTD interconnects in the microelectronic assembly or IC package as described herein can be metal-metal interconnects (e.g., copper-copper interconnects or electroplated interconnects). In such embodiments, the conductive contacts on either side of the DTD interconnect can be joined together (e.g., under elevated pressure and / or temperature) without using intermediate solder or anisotropic conductive materials. In some metal-metal interconnects, dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbide) can be present between the metals joined together (e.g., between copper pads or copper rods providing associated conductive contacts). In some embodiments, one side of the DTD interconnect can include a metal post (e.g., a copper post), and the other side of the DTD interconnect can include a metal contact (e.g., a copper contact) recessed in the dielectric. In some embodiments, a metal-metal interconnect (e.g., a copper-copper interconnect) can include a noble metal (e.g., gold) or a metal (e.g., silver) conductive of its oxide. In some embodiments, a metal-metal interconnect can include a metal nanostructure (e.g., a nanorod) that can have a reduced melting point. Metal-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be limited to mitigate mechanical failure.

[0052] In some embodiments, the dies on either side of a set of DTD interconnects may be bare (eg, unpackaged) dies.

[0053] In some embodiments, the DTD interconnect may include solder. For example, the DTD interconnect may include a conductive bump or column (e.g., a copper bump or column) attached to a corresponding conductive contact portion by solder. In some embodiments, a thin solder cap may be used in a metal-metal interconnect to accommodate planarity, and the solder may become an intermetallic compound during processing. In some embodiments, the solder used in some or all of the DTD interconnects in the DTD interconnect may have a higher melting point than the solder included in some or all of the DTPS interconnects in the DTPS interconnect. For example, when the DTD interconnect in the IC package is formed before the DTPS interconnect is formed, the solder-based DTD interconnect may use a higher temperature solder (e.g., where the melting point is above 200 degrees Celsius), while the DTPS interconnect may use a lower temperature solder (e.g., where the melting point is below 200 degrees Celsius). In some embodiments, the higher temperature solder may include tin; tin and gold; or tin, silver and copper (e.g., 96.5% tin, 3% silver and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (eg, eutectic tin-bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0054] In some embodiments, a set of DTD interconnects may include anisotropic conductive materials, such as any of the materials described above for DTPS interconnects. In some embodiments, DTD interconnects may be used as data transmission channels, while DTPS interconnects may be used for power and ground lines, among other things.

[0055] In a microelectronic assembly or IC package as described herein, some or all of the DTD interconnects in the DTD interconnects may have a finer spacing than the DTPS interconnects. In some embodiments, the DTPS interconnects disclosed herein may have a spacing between about 80 microns and 300 microns, while the DTD interconnects disclosed herein may have a spacing between about 0.5 microns and 100 microns, depending on the type of the DTD interconnects. The density of some DTD interconnects provides an example of silicon-level interconnect density. In some embodiments, the DTD interconnects may have a spacing that is too fine to be directly coupled to the package substrate (e.g., too fine to be used as a DTPS interconnect). The DTD interconnects may have a smaller spacing than the DTPS interconnects because the materials in the different dies on either side of a set of DTD interconnects are more similar than the materials between the die and the package substrate on either side of a set of DTPS interconnects. Specifically, due to the heat generated during operation (and the heat applied during various manufacturing operations), the differences in the material composition of the die and the package substrate may result in different expansions and contractions of the die and the package substrate. To mitigate damage (e.g., cracking, solder bridging, etc.) caused by such differential expansion and contraction, the DTPS interconnects of any microelectronic assembly or IC package as described herein can be formed larger and spaced farther apart than the DTD interconnects, which can experience less thermal stress because the materials of a pair of dies on either side of the DTD interconnect are more similar.

[0056] It will be appreciated that one or more levels of underfill (e.g., organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC packages described herein and may not be labeled to avoid cluttering the drawings. In various embodiments, the underfill of the levels may include the same or different insulating materials. In some embodiments, the underfill of the levels may include a thermosetting epoxy with silicon oxide particles; in some embodiments, the underfill of the levels may include any suitable material capable of performing the function of an underfill (e.g., supporting the die and reducing thermal stress on the interconnect). In some embodiments, the selection of the underfill material may be based on design considerations such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of the underfill material may be based on material properties and processing conditions such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of the underfill may be based on both design and processing considerations.

[0057] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided in the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may not be photoimageable.

[0058] The terms "substantially," "close," "approximately," "near," and "approximately" generally mean within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value), based on the context of a specific value as described herein or as known in the art.

[0059] Terms indicating the orientation of various elements (e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements) generally mean within + / - 5%-20% of the target value based on the context of the specific value as described herein or as known in the art.

[0060] The term "connected" means a direct connection between the objects being connected (which may be one or more of a mechanical, electrical and / or thermal connection) without any intermediary devices, while the term "coupled" means a direct connection between the objects being connected, or an indirect connection through one or more passive or active intermediary devices.

[0061] This description uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments.

[0062] Furthermore, the terms "comprising," "including," "having," and the like as used with respect to embodiments of the present disclosure are synonymous.

[0063] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0064] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers, or may have one or more intervening layers. Conversely, a first layer described as being "on" a second layer refers to the layer that is in direct contact with that second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0065] As used herein, the term "disposed" refers to a position, location, placement, and / or arrangement, rather than to any particular method of formation.

[0066] When used with reference to a measuring range, the term "between" includes the ends of the measuring range.

[0067] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0068] Although certain elements may be mentioned in the singular form herein, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0069] Unless otherwise stated, the use of ordinal adjectives "first," "second," and "third," etc., to describe common objects merely indicates that different instances of similar objects are referenced and is not intended to imply that the objects so described must be in a given order in time, space, ranking, or in any other manner.

[0070] In the following detailed description, reference is made to the accompanying drawings which form a part of the specification and in which embodiments that may be implemented are shown by way of illustration. It is to be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be construed as limiting.

[0071] The drawings are not necessarily drawn to scale.

[0072] In the drawings, the same reference numerals refer to the same or similar elements / materials shown, such that, unless otherwise indicated, explanations of elements / materials with a given reference numeral provided in the context of one of the drawings apply to other drawings, in which elements / materials with the same reference numerals may be shown. In addition, singular and plural forms of references may be used with reference numerals to refer to a single or multiple, respectively, of the same or similar type, kind, or class of elements.

[0073] Furthermore, in the accompanying drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with exact right angles and straight lines, but it is to be understood that when any structure described herein is examined using, for example, images of a suitable characterization tool (e.g., scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers), such schematic illustrations may not reflect real-life process limitations that may cause features to appear less than "ideal." In such images of real structures, possible processing and / or surface defects are also visible, such as surface roughness, deviations in curvature or profile, pits or scratches, imperfectly straight edges of materials, tapered through holes or other openings, inadvertent rounded corners or thickness variations of different material layers, occasional spiral, edge or combined dislocations within (one or more) crystal regions, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing and / or packaging.

[0074] Note that in the drawings, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces), which is merely for ease of illustration; in reality, some or all of them may be misaligned. In addition, there may be other components (e.g., bonding pads, landing pads, metallization, etc.) present in the assembly, which are not shown in the drawings to prevent confusion. In addition, the drawings are intended to illustrate the relative arrangement of the components within their assemblies, and generally, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functionality, electrical connections, or thermal relief). For example, in some additional embodiments, the assemblies shown may include more dies and other electrical components. In addition, although some components of the assemblies are shown in the drawings as planar rectangles or formed by rectangular solid lines, this is merely for ease of illustration, and embodiments of these assemblies may be curved, circular, or otherwise irregularly shaped, as determined by the manufacturing process used to manufacture the various components, and sometimes unavoidable due to the manufacturing process used to manufacture the various components.

[0075] In the drawings, specific numbers and arrangements of structures and components are presented for illustrative purposes, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0076] Furthermore, unless otherwise stated, the structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes and operating conditions.

[0077] For convenience, if there is a set of figures designated with different letters (e.g., Figures 10A-10C), such a set may be referred to herein without letters (e.g., referred to as "Figure 10"). Similarly, if there is a set of reference numerals designated with different letters (e.g., 112a-112e), such a set may be referred to herein without letters (e.g., referred to as "112").

[0078] Various operations can be described as multiple discrete actions or operations in turn in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations are necessarily sequence-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted. Example Embodiments

[0079] Figure 1 is a schematic cross-sectional view of an example microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes a bridge die 102 that provides a conductive path to electrically couple two (or more) IC dies 104, such as 104a and 104b. Note that although two IC dies 104a and 104b are shown, more than two IC dies 104 may be conductively coupled via the bridge die 102 within the broad scope of the embodiments. The bridge die 102 includes a semiconductor material, such as silicon or other materials listed in the previous subsection as suitable for IC dies, and may also be referred to herein as a semiconductor die 102.

[0080] The bridge die 102 and the IC die 104 may be coupled to a packaging substrate 106. The packaging substrate 106 may include multiple built-up layers of organic materials (e.g., polyimide, epoxy, etc.) with conductive traces and vias, including, for example, copper. In some other embodiments, the packaging substrate 106 may include an inorganic material, such as a ceramic. Any suitable material may be provided in the packaging substrate 106 within the broad scope of embodiments. In various embodiments, the bridge die 102 may be in a blind cavity 108 in the packaging substrate 106 and coupled thereto by an interconnect 110. The cavity 108 may extend partially from a surface 112 of the packaging substrate 106 into the packaging substrate 106. In some embodiments (not shown), a die attach adhesive may be present between the bridge die 102 and the bottom of the cavity 108. In some other embodiments (not shown), the interconnect 110 may be surrounded by an underfill material. The bridge die 102 may include one or more conductive pillars 114 extending therethrough. The one or more conductive pillars 114 may be surrounded by corresponding air gaps 116.

[0081] During operation, the conductive pillars 114 may function as through silicon vias (TSVs) to enable electrical connections between the package substrate 106 and the IC die 104. In some such embodiments, the conductive pillars 114 may form part of a power delivery network for high frequency applications for delivering power from (or through) the package substrate 106 to the IC die 104; in such embodiments, the air gaps 116 may improve the electrical performance of the conductive pillars 114, for example, by reducing parasitic losses from impedance. By way of illustration only and not limitation, the bridge die 102 without the air gaps 116 around the conductive pillars 114 may be able to deliver 1.2 mA of current to the IC die 104, while with the air gaps 116 around the conductive pillars 114, the delivered current may be approximately 7 mA, with everything else remaining the same.

[0082] IC die 104a and 104b may be coupled to package substrate 106 and bridge die 102 via interconnect 118. Interconnect 118a may couple IC die 104a to package substrate 106; interconnect 118b may couple IC die 104a to conductive via 114, and interconnect 118c may couple IC die 104a to a conductive path (not shown) that conductively couples IC die 104a to IC die 104b via bridge die 102. In some embodiments, interconnect 118 may be of multiple types. In various embodiments, interconnect 118a may include SLI, and interconnects 118b and 118c may include FLI. In some such embodiments, interconnect 118a may be similar in size and spacing to interconnect 118b and / or interconnect 110, and different in size and spacing to interconnect 118c. In other embodiments, the size and spacing of interconnect 118 across surface 112 may be similar. In various embodiments, interconnects 118 and 110 may include solder. In other embodiments, interconnects 118 and / or 110 may be of other types (eg, copper pillar based, hybrid bonding, etc.), as listed in the previous subsections.

[0083] Figure 2A is a simplified cross-sectional view of an example conductive via 114 surrounded by an air gap 116. Bridge die 102 may have two opposing surfaces 202 and 204. In some embodiments, surface 202 may be near the bottom of cavity 108 and surface 204 may be near IC die 104; in other embodiments, the configuration may be reversed so that surface 202 is near IC die 104 and surface 204 is near the bottom of cavity 108. A hole 206 having sidewalls 208 may extend between surfaces 202 and 204. A bonding pad 210 may cover an end of hole 206 at surface 202. Another bonding pad 210 may cover an opposite end of hole 206 at surface 204. A conductive pillar 114 may be within hole 206 and separated from sidewalls 208 by air gap 116. Conductive pillar 114 may be directly attached to bonding pads 210 and 212. The bond pads 210 and / or 212 may be much larger than the holes 206 so that there is no significant structural bending or other issues due to the absence of solid material around the conductive pillars 114 near the bond pads 210 and / or 212 .

[0084] In various embodiments, the bridge die 102 may have a thickness 214. The conductive pillar 114 may extend through the entire thickness 214. The conductive pillar 114 may be manufactured using an additive manufacturing process (e.g., physical vapor deposition). This is different from conventional electroplating techniques used to manufacture TSVs in silicon dies. Conventional electroplating techniques typically completely fill any available space with electroplating material, thereby intentionally preventing the formation of any air gaps (e.g., voids may occur due to various process conditions, but such voids are uncontrolled and generally undesirable). Therefore, such conventional electroplating techniques may not be suitable for manufacturing a conductive pillar 114 having a controlled air gap 116 around it. Therefore, in various embodiments, there may be no liner material and seed material around the conductive pillar 114 as aspects of the electroplating process.

[0085] The manufacturing process used in the embodiments of the present invention can sequentially deposit layers of conductive material (e.g., copper) within the hole 206, resulting in the conductive pillar 114 being tapered toward the surface 204, so that the conductive pillar 114 is wider near the surface 202 than near the surface 204. Because the conductive pillar 114 is not supported by any solid material at its periphery, its structural integrity can depend on its aspect ratio. For example, the taller the conductive pillar 114 is, the less structural integrity it may have, and the easier it may be to bend and / or break. On the other hand, the wider the conductive pillar 114 is, the higher its structural integrity is, and the less likely it may be to break. Therefore, the process used to manufacture the conductive pillar 114 can be appropriately selected based on the degree of control that can be exercised over the aspect ratio of the conductive pillar 114. In an exemplary embodiment, electron beam physical vapor deposition at a pressure of less than 1 microbar can be used to manufacture the conductive pillar 114 to achieve a desired shape based on specific needs.

[0086] In addition, the height of the conductive pillars 114 is proportional to the thickness 214 of the bridge die 102. Therefore, the thickness 214 of the bridge die 102 can inform (e.g., influence, limit, etc.) the width (e.g., diameter) 216 of the conductive pillars 114 at the surface 202 and the width (e.g., diameter) 218 ​​of the conductive pillars 114 at the surface 204. For example, consider two different bridge dies 102a and 102b, having respective thicknesses 214a and 214b. For purposes of explanation only, assume that the thickness 214a is greater than the thickness 214b. It is also assumed that the conductive pillar 114a in the bridge die 102a has the same width 216 at the surface 202 as another conductive pillar 114b in the bridge die 102b. Accordingly, the width 218a of conductive pillar 114a in bridge die 102a may be smaller than the width 218b of conductive pillar 114b due to the greater thickness 214a of bridge die 102a given the same aspect ratio (ie, taper) of conductive pillars 114a and 114b.

[0087] The shape of the hole 206 can directly affect the shape of the air gap 116. Because the presence, size, and shape of the air gap 116 affect the electrical performance of the conductive pillar 114 during operation, the shape of the hole 206 and the width of the conductive pillar 114 can be such that the air gap 116 is retained during operation according to the desired electrical characteristics of the conductive pillar 114. In various embodiments, the hole 206 can be formed by reactive ion etching. Many process parameters can be adjusted to generate a hole 206 with an appropriately tapered, vertical, or concave sidewall 208 as desired and based on specific needs. In some embodiments, as shown, the hole 206 has a substantially vertical sidewall 208, wherein the width 220 near the surface 202 is substantially similar to the width 222 near the surface 204.

[0088] Figure 2B Another embodiment is shown in which, depending on process parameters, the hole 206 has a tapered sidewall 208, wherein a width 220 near the surface 202 is less than a width 222 near the surface 204. The sidewall 208 may also have additional features, such as chamfers (e.g., bevels), undercuts, notches, or other shapes resulting from the etching process. In some other embodiments (not shown), the hole 206 may have a concave sidewall 208, wherein a width 220 near the surface 202 is greater than a width 222 near the surface 204. Within the broad scope of embodiments, any suitable sidewall profile may be provided based on particular needs. Thus, the overall size and shape of the conductive pillar 114 and the air gap 116 may be based on (among other factors): (i) the manufacturing process of the conductive pillar 114 and the hole 206, (ii) the structural integrity of the conductive pillar 114 taking into account the thickness 214 of the bridge die 102, and (iii) the desired electrical performance of the conductive pillar 114 during operation.

[0089] In various embodiments, the thickness 214 of the bridge die 102 can vary between 1 micron and 500 microns. The width 216 of the conductive pillar 114 near the surface 202 (e.g., facing the bottom of the blind cavity 108) can vary between 0.5 microns and 100 microns. The width 218 of the conductive pillar 114 near the surface 204 (e.g., facing the die 104) can vary between 0.5 microns and 200 microns. The average width of the conductive pillar 114 can vary between 0.5 microns and 100 microns. The width 220 of the hole 206 near the surface 202 (e.g., facing the bottom of the blind cavity 108) can vary between 5 microns and 400 microns. The width 222 of the hole 206 near the surface 204 (e.g., facing the die 104) can vary between 6 microns and 600 microns.

[0090] Figure 2CA plan view of the conductive pillar 114 and the air gap 116 across the cross section CC' is shown. Note that in the figure, the hole 206 and the conductive pillar 114 are shown as circular structures. This is only for ease of illustration and should not be construed as limiting. Within the broad scope of the embodiments herein, the cross-sections of the hole 206 and the conductive pillar 114 can have any suitable shape.

[0091] Figure 3 is a schematic cross-sectional view of a portion of a microelectronic assembly 100 according to an embodiment of the present disclosure. The bridge die 102 may include two mutually exclusive portions 302 and 304. The conductive pillar 114 may be disposed in the portion 304 and may provide a conductive path in the portion 304 that conductively couples the IC die 104. The bridge die may include a semiconductor substrate portion 306 including, for example, a semiconductor material such as bulk silicon. Other example materials are listed in the previous subsection. A back-end-of-line (BEOL) portion 308 may be provided over the semiconductor substrate 306. In various embodiments, the bridge die 102 may not include any front-end-of-line (FEOL) portion having active semiconductor elements such as transistors and diodes. The conductive path of the conductively coupled IC die 104 may be disposed in the BEOL portion 308. The conductive path may include a bonding pad 310 coupled to a metallization layer through a conductive via 312, the metallization layer including a conductive trace 314 in an interlayer dielectric (ILD) material 316. Examples of ILD materials include compounds containing silicon and oxygen (e.g., silicon dioxide), silicon, oxygen, and nitrogen (e.g., silicon oxynitride), silicon and nitrogen (e.g., silicon nitride), etc., as listed in the previous subsection. ILD material 316 can be disposed in layers between conductive traces 314 and between layers of conductive traces 314. Conductive vias 312 can be disposed in ILD material 316 between layers of conductive traces 314. Bonding pads 310 can be directly coupled to interconnects 118 (e.g., 118c) of IC die 104. In various embodiments, bonding pads 212 can be larger than bonding pads 310 (e.g., larger diameter, wider, etc.). In some embodiments, bonding pads 212 can be distributed at a greater pitch than bonding pads 310. In various embodiments, conductive pillars 114 can be wider than conductive vias 312.

[0092] In various embodiments (not shown), as discussed with reference to the previous figures, the hole 206 may pass through the semiconductor substrate 306 and the BEOL portion 308. In some such embodiments, the hole 206 and the conductive pillar 114 may be formed in a via-last process after the BEOL portion 308 is fabricated. In some other embodiments (as shown), the hole 206 may only exist in the semiconductor substrate 306, and the conductive pillar 114 may include a conductive via through the ILD material 316, without the air gap 116 in the BEOL portion 308. Note that the figures are not drawn to scale, and the BEOL portion 308 may be several orders of magnitude thinner than the semiconductor substrate 306. The thickness of the BEOL portion 308 may vary depending on the number of metallization layers, and may range between 2 microns and 200 microns. Therefore, in embodiments in which the BEOL portion 308 is relatively thin, the lack of the air gap 116 in the BEOL portion 308 may not significantly affect the overall electrical characteristics of the conductive pillar 114. In some such embodiments, the holes 206 may be formed prior to fabricating the BEOL portion 308 , and the conductive pillars 114 may be completed during fabrication of the BEOL portion 308 .

[0093] Figure 4 304 is a simplified cross-sectional plan view of a detail of a microelectronic assembly 100 according to various embodiments of the present disclosure. Portions 302 may be disposed along the periphery of the bridge die 102, and portions 304 including conductive paths may be provided toward the center of the bridge die 102. In the cross-sectional plan view shown, the bonding pads 212 and 310 have been removed, exposing the conductive pillars 114, the air gaps 116, and the through-holes 312. Note that the drawings are not drawn to scale for ease of illustration only. Any number of conductive pillars 114 and through-holes 312 may be provided in the bridge die 102 without departing from the scope of the embodiments. In addition, although portion 304 is shown as surrounding portion 302, in some embodiments, portion 302 may extend to the periphery in some areas. However, portions 302 and 304 may be mutually exclusive, such that a conductive pillar 114 having an air gap 116 may not be disposed between the through-hole 312 and the conductive trace 314.

[0094] In various embodiments, reference is made to Figure 1-4Any of the features discussed in any of the above may be combined with any other features to form a package with one or more IC dies as described herein. For example, in some embodiments, there may be several bridge dies 102 in the bridge die 102. In some embodiments, based on specific needs, some conductive pillars 114 may be surrounded by air gaps 116, while other conductive pillars 114 may not be surrounded by air gaps 116. Some such combinations are described above, however, in various embodiments, additional combinations and modifications are possible. The various different embodiments described in the different figures may be appropriately combined based on specific needs within the broad scope of the embodiments. Example Method

[0095] Figures 5A-5D 1 is a schematic cross-sectional view of a portion of a microelectronic assembly 100 at various stages of manufacture according to some embodiments of the present disclosure. Note that for ease of illustration, only a portion of the structure is shown in the figure. In practice, the process can be performed at the wafer level or the panel level as needed and based on specific needs. Figure 5A , operation 500 is shown in which a wafer including a bridge die 102 may be provided. For example, by appropriate use of a mask and a reactive ion etching process, a hole 206 may be formed in the bridge die 102 at a desired location. Appropriate control of process parameters may achieve a desired profile of a sidewall 208 of the hole 206. In various embodiments, at this stage, the bridge die 102 may include only the semiconductor substrate 306. In other embodiments, the bridge die 102 may also include a BEOL portion 308, such that the hole 206 is also formed through the BEOL portion 308.

[0096] Figure 5BOperation 502 is shown following operation 500. At 502, a conductive pillar 114 is formed within the hole 206. Note that the wafer containing the bridge die 102 may be supported on a suitable surface (e.g., a chuck, a panel, etc.) lined with a material from which the conductive material can be easily removed, such that the conductive pillar 114 is deposited on the lined surface within the hole 206. The conductive material (e.g., copper) may be deposited in the hole 206 by an additive process (e.g., electron beam physical vapor deposition at a low pressure (e.g., 1 microbar)). When the conductive pillar 114 is formed to be tapered within the hole 206, the process may be selected to achieve control of the aspect ratio of the conductive pillar 114. In this figure, the conductive pillar 114 is shown as tapering toward the surface 204, while the hole 206 is tapered away from the surface 204. In other embodiments, the sidewall 208 of the hole 206 may be vertical. In yet other embodiments, the sidewall 208 of the hole 206 may be tapered toward the surface 204. All such variations are included within the broad scope of the embodiments. The process parameters for depositing the conductive material to form the conductive pillar 114 may be appropriately controlled so that it does not completely fill the hole 206 and leaves an air gap 116 between the conductive pillar 114 and the sidewall 208 of the hole 206 .

[0097] Figure 5C Operation 504 is shown following operation 502. At 504, a bonding pad 212 may be formed on surface 204, for example, by electroplating. Another method that may be used to form bonding pad 212 is low pressure chemical vapor deposition (CVD) of a conductive metal. This method is a linear deposition method that does not laterally fill the material, which prevents hole 206 from being filled with conductive material while preserving air gap 116 during the formation of bonding pad 212. In some other embodiments, BEOL portion 308 may be formed in another operation between operations 504 and 502, and conductive pillar 114 may extend through BEOL portion 308 using a conventional via formation process to form a conductive via as described in reference. Figure 3 The structure described.

[0098] Figure 5D Operation 506 is shown following operation 504. The wafer containing the bridge die 102 may be flipped, and bond pads 210 may be formed on the surface 202, for example, by electroplating or low pressure CVD, for example, similar to the formation of bond pads 212. In various embodiments, chemical mechanical polishing may be performed prior to any electroplating, for example, to expose the conductive pillars 114 for a seeding process associated with the electroplating.

[0099] although Figures 5A-5DVarious operations are shown to be performed in a particular order, but this is merely illustrative, and the operations discussed herein may be reordered and / or repeated as appropriate. In addition, additional processes not shown may also be performed without departing from the scope of the present disclosure. In addition, the descriptions herein regarding Figures 5A-5D Various operations in the operations discussed herein may be used to manufacture other microelectronic assemblies in the microelectronic assembly 100 disclosed herein. Figures 5A-5D , but the operations may be repeated as often as desired. For example, one or more operations may be performed in parallel to manufacture and test multiple microelectronic assemblies substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a particular microelectronic assembly, which may include one or more substrates or other components as described herein.

[0100] also, Figures 5A-5D The operations shown in the figure may be combined or may include more details than described. For example, for IC dies that do not have semiconductor substrates but are manufactured on other materials such as glass or ceramic materials, the operations may be appropriately modified without departing from the scope of the present disclosure. Further, the various operations shown and described may also include other manufacturing operations related to the manufacture of other components of the microelectronic assembly described herein or any device that may include the microelectronic assembly as described herein. For example, operations not shown in the figure may include various cleaning operations, additional surface planarization operations, surface roughening operations, operations including barrier layers and / or adhesion layers as needed, and / or operations for combining the microelectronic assembly as described herein into or with an IC assembly, a computing device, or any desired structure or device. Example Devices and Components

[0101] The packaging disclosed herein (e.g. Figure 1 -5 or any additional embodiments described herein) may be included in any suitable electronic component. Figure 6-9 Various examples of packages, assemblies, and devices are shown that may be used with or include any IC package as disclosed herein.

[0102] Figure 62002 and die 2002. The wafer 2000 may be comprised of a semiconductor material and may include one or more die 2002 having an IC structure formed on a surface of the wafer 2000. The individual die 2002 may be a repeating unit of an IC product including any suitable IC. After the manufacture of the semiconductor product is complete, the wafer 2000 may undergo a singulation process in which the die 2002 are separated from one another to provide discrete "chips" (e.g., example die 2004) of an IC product. The example die 2004 may be any of the die 102 and 104 disclosed herein. The die 2004 may include one or more transistors, supporting circuit modules that route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. In some embodiments, wafer 2000 or die 2004 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 2004. For example, a memory array formed by multiple memory devices may be coupled to a processor unit (e.g., Fig. 9 The microelectronic assemblies disclosed herein may be fabricated using die-to-wafer assembly techniques in which some of the dies are attached to a wafer 2000 that includes other dies, and the wafer 2000 is subsequently singulated.

[0103] Figure 7 is a side cross-sectional view of an example IC package 2200, which may include an IC package according to any embodiment disclosed herein. In some embodiments, the IC package 2200 may be a SIP. Figure 7 At least some of the components described in the drawings may be substantially similar to those in the previous drawings (e.g. Figure 1 ) described in .

[0104] As shown in the figure, the package substrate 2252 may be formed of an insulator (e.g., ceramic, a built-up film, an epoxy film with filler particles therein, etc.), and may have conductive paths extending through the insulator between the first side 2272 and the second side 2274, or between different locations on the first side 2272, and / or between different locations on the second side 2274. These conductive paths may take the form of any interconnect structure including wires and / or vias.

[0105] The packaging substrate 2252 may include conductive contacts 2263 coupled to conductive paths 2262 through the packaging substrate 2252, allowing the die 2256 and / or circuit modules within the interposer 2257 to be electrically coupled to various conductive contacts in the conductive contacts 2264 (or other devices included in the packaging substrate 2252, not shown).

[0106] IC package 2200 may include interposer 2257 coupled to package substrate 2252 via conductive contacts 2261 of interposer 2257, first level interconnects 2265, and conductive contacts 2263 of package substrate 2252. The first level interconnects 2265 shown in the figure are solder bumps, but any suitable first level interconnects 2265 may be used, such as solder bumps, solder pillars, or bond wires.

[0107] The IC package 2200 may include one or more dies 2256 coupled to an interposer 2257 via conductive contacts 2254 of the die 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, allowing circuit modules within the die 2256 to be electrically coupled to various conductive contacts in the conductive contacts 2261 (or other devices included in the interposer 2257, not shown). The first-level interconnects 2258 shown in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder columns, or bonding wires. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) used as an interface between different components; the conductive contact may be recessed into a surface of a component, flush with a surface of a component, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0108] In some embodiments, an underfill material 2266 can be disposed around the first level interconnect 2265 between the package substrate 2252 and the interposer 2257, and a mold 2268 can be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 can be the same as the mold 2268. An example material that can be used for the underfill material 2266 and the mold 2268 is a suitable epoxy. A second level interconnect 2270 can be coupled to the conductive contact 2264. The second level interconnect 2270 shown in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second level interconnect 2270 can be used (e.g., a pin in a pin grid array arrangement or a contact in a contact grid array arrangement). The second level interconnect 2270 can be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference Figure 8 discussed.

[0109] In various embodiments, any of the dies 2256 may be a microelectronic assembly 100 as described herein. In embodiments where the IC package 2200 includes a plurality of dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuit modules that perform any desired functionality. For example, in addition to one or more of the dies 2256 being a microelectronic assembly 100 as described herein, one or more of the dies 2256 may be a logic die (e.g., a silicon-based die), one or more of the dies 2256 may be a memory die (e.g., an HBM), etc. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the foregoing figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0110] Although the IC package 2200 shown in the figure is a flip chip package, other packaging architectures may also be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252, or disposed on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0111] In some embodiments, interposer 2257 may not be included in IC package 2200 ; instead, die 2256 may be coupled directly to conductive contacts 2263 at first side 2272 through first level interconnects 2265 .

[0112] Figure 8 is a cross-sectional side view of an IC device assembly 2300 that can include components having one or more microelectronic assemblies 100 according to any embodiment disclosed herein. Figure 8 At least some of the components described in the drawings may be substantially similar to those in the previous drawings (e.g. Figure 1 ) described in . IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). IC device assembly 2300 includes components disposed on a first side 2340 of circuit board 2302 and an opposing second side 2342 of circuit board 2302; typically, the components may be disposed on one or both of sides 2340 and 2342. In particular, any suitable assembly of components in IC device assembly 2300 may include any microelectronic assembly in one or more microelectronic assemblies 100 according to any embodiment disclosed herein; for example, any IC package discussed below with reference to IC device assembly 2300 may take the form of an IC package discussed above with reference to Figure 7 Any of the embodiments of IC package 2200 discussed.

[0113] In some embodiments, circuit board 2302 may be a PCB comprising multiple metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in conjunction with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB packaging substrate.

[0114] As shown, in some embodiments, the IC device assembly 2300 may include a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling component 2316. The coupling component 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and may include solder balls (as shown), protrusions and recesses of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0115] The package structure 2336 on the interposer may include an IC package 2320 coupled to the interposer 2304 via a coupling component 2318. The coupling component 2318 may take any suitable form, such as the form discussed above with reference to the coupling component 2316, depending on the desired functionality. In some embodiments, the IC package 2320 may be or include the IC package 2200, for example, as described above with reference to FIG. 5. In some embodiments, the IC package 2320 may include at least one microelectronic assembly 100 as described herein. In order not to clutter the drawings, the microelectronic assembly 100 is not specifically shown in the drawings.

[0116] Although a single IC package 2320 is shown, multiple IC packages can be coupled to interposer 2304; in fact, additional interposers can be coupled to interposer 2304. Interposer 2304 can provide an intermediate package substrate for bridging circuit board 2302 and IC package 2320. Typically, interposer 2304 can redistribute connections to a wider spacing or reroute connections to different connections. For example, interposer 2304 can couple IC package 2320 to a BGA of coupling assembly 2316 for coupling to circuit board 2302.

[0117] In the embodiment shown in the figure, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0118] The interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials used in the semiconductor substrate, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and through-holes 2310, including but not limited to TSV 2306. The interposer 2304 may also include embedded devices 2314, including both passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 2304. The interposer package structure 2336 may take the form of any interposer package structure known in the art.

[0119] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0012] In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second side 2342 of circuit board 2302 via coupling component 2328. Package-on-package structure 2334 may include IC package 2326 and IC package 2332 coupled together via coupling component 2330, such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any embodiment of coupling component 2316 described above, and IC packages 2326 and / or 2332 may take the form of any embodiment of IC package 2320 described above. Package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0121] Fig. 9 2400, which may include one or more components having one or more IC packages according to any embodiment disclosed herein. For example, any suitable components of the components of computing device 2400 may include a microelectronic assembly (e.g., 100) according to any embodiment disclosed herein. In another example, any one or more components of the components of computing device 2400 may include any embodiment of IC package 2200 (e.g., Figure 7 In yet another example, any one or more of the components of the computing device 2400 may include the IC device assembly 2300 (e.g., as shown in Figure 8 ).

[0122] A number of components are shown in the figure as included in computing device 2400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single SOC die.

[0123] Additionally, in various embodiments, computing device 2400 may not include one or more of the components shown in the figure, but computing device 2400 may include an interface circuit module for coupling to one or more components. For example, computing device 2400 may not include display device 2406, but may include a display device interface circuit module (e.g., a connector and a driver circuit module) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include an audio input or output device interface circuit module (e.g., a connector and a supporting circuit module) to which audio input device 2418 or audio output device 2408 may be coupled.

[0124] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin-transfer torque magnetic random access memory (STT-MRAM).

[0125] In some embodiments, computing device 2400 may include communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications to transmit data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which may communicate data using modulated electromagnetic radiation via a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0126] The communication chip 2412 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), LTE projects and any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability tests of the IEEE802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication chip 2412 may operate in accordance with other wireless protocols. The computing device 2400 may include an antenna 2422 for facilitating wireless communications and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0127] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 2412 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, and the second communication chip 2412 can be dedicated to wired communications.

[0128] Computing device 2400 may include battery / power circuit module 2414. Battery / power circuit module 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit modules for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0129] Computing device 2400 may include display device 2406 (or corresponding interface circuit modules, as discussed above). Display device 2406 may include any visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0130] Computing device 2400 may include audio output device 2408 (or corresponding interface circuit modules, as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earphones.

[0131] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuit module, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as, for example, a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0132] Computing device 2400 may include GPS device 2416 (or a corresponding interface circuit module, as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0133] Computing device 2400 may include other output devices 2410 (or corresponding interface circuit modules, as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0134] The computing device 2400 may include other input devices 2420 (or corresponding interface circuit modules, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse, a stylus, a touchpad), a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0135] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data. Select Example

[0136] Example 1 provides a semiconductor die, comprising: a first bonding pad on a first surface, which is used to couple to a packaging substrate; a second bonding pad on a second surface, the second surface being opposite to the first surface; a hole passing through the semiconductor die; a conductive column within the hole, which is separated from the sidewall of the hole by an air gap, the conductive column coupled to the first bonding pad and the second bonding pad; and a path, which conductively couples at least two integrated circuit (IC) dies near the second surface.

[0137] Example 2 provides the semiconductor die of Example 1, wherein the first bonding pad and the second bonding pad are wider than the hole.

[0138] Example 3 provides the semiconductor die of any of Examples 1-2, wherein the first bond pad is directly coupled to an interconnect of one of the IC dies.

[0139] Example 4 provides the semiconductor die of Example 3, wherein the interconnect comprises solder.

[0140] Example 5 provides the semiconductor die of any of Examples 1-4, wherein the second bond pad is directly coupled to an interconnect of the package substrate.

[0141] Example 6 provides the semiconductor die of Example 5, wherein the interconnect comprises solder.

[0142] Example 7 provides the semiconductor die of any of Examples 1-6, wherein the semiconductor die is located within a cavity in a packaging substrate.

[0143] Example 8 provides the semiconductor die of any of Examples 1-7, wherein the conductive pillar has a first width proximate the first bonding pad and a second width proximate the second bonding pad, and the first width is greater than the second width.

[0144] Example 9 provides the semiconductor die of any of Examples 1-8, wherein the conductive pillar is in a first portion of the semiconductor die, the path is in a second portion of the semiconductor die, and the first portion and the second portion are mutually exclusive.

[0145] Example 10 provides the semiconductor die of Example 9, wherein the first portion is near a periphery of the semiconductor die and the second portion is near a center of the semiconductor die.

[0146] Example 11 provides the semiconductor die of any of Examples 1-10, wherein the semiconductor die is coupled to the IC die through a first interconnect and a second interconnect, the first interconnect being physically coupled to the conductive pillar and the second interconnect being physically coupled to the path.

[0147] Example 12 provides the semiconductor die of Example 11, wherein the first interconnect is larger than the second interconnect.

[0148] Example 13 provides the semiconductor die of any of Examples 1-12, wherein the path includes a conductive trace and a conductive via in an interlayer dielectric (ILD) material.

[0149] Example 14 provides the semiconductor die of Example 13, wherein the conductive pillar is wider than any of the conductive vias.

[0150] Example 15 provides the semiconductor die of any of Examples 13-14, wherein the ILD material includes a compound of silicon and oxygen.

[0151] Example 16 provides the semiconductor die of any of Examples 1-15, wherein a thickness of the semiconductor die between the first surface and the second surface is less than 50 microns.

[0152] Example 17 provides the semiconductor die of any of Examples 1-16, wherein the semiconductor die does not include any active semiconductor elements.

[0153] Example 18 provides the semiconductor die of any of Examples 1-17, wherein the average width of the conductive pillars is less than 10 microns.

[0154] Example 19 provides the semiconductor die of any of Examples 1-18, wherein a portion of the semiconductor die includes bulk silicon.

[0155] Example 20 provides the semiconductor die of any of Examples 1-19, wherein the conductive pillar comprises copper.

[0156] Example 21 provides an integrated circuit (IC) package, comprising: a package substrate having a surface, the surface having a blind cavity extending from the surface partially through the package substrate; a plurality of IC dies attached to the surface of the package substrate; and a bridge die attached to the plurality of IC dies in the blind cavity, the bridge die comprising: a conductive path that conductively couples at least one pair of the plurality of IC dies; a through silicon via (TSV) extending through the thickness of the bridge die; and an air gap surrounding at least one TSV.

[0157] Example 22 provides the IC package of Example 21, wherein at least one TSV is tapered toward the surface.

[0158] Example 23 provides the IC package of Example 21, wherein at least one TSV is tapered away from the surface.

[0159] Example 24 provides the IC package of Example 21, wherein the air gap closer to the surface is wider than the air gap farther from the surface.

[0160] Example 25 provides the IC package of Example 21, wherein the TSV is in a hole having substantially parallel sidewalls perpendicular to the surface, and an air gap is between the TSV and the sidewalls.

[0161] Example 26 provides the IC package of any of Examples 21-25, wherein the plurality of IC dies are directly coupled to the bridge die through at least a first interconnect and a second interconnect, and the first interconnect is larger than the second interconnect.

[0162] Example 27 provides the IC package of Example 26, wherein the plurality of IC dies are directly coupled to the package substrate via a third interconnect, and the third interconnect is larger than the second interconnect.

[0163] Example 28 provides the IC package of Example 27, wherein the third interconnect is similar in size to the first interconnect.

[0164] Example 29 provides the IC package of Example 26, wherein the bridge die is directly coupled to the package substrate via a third interconnect, and the third interconnect is similar in size to the first interconnect.

[0165] Example 30 provides the IC package of Example 29, wherein the TSV is directly coupled to the first interconnect and the third interconnect.

[0166] Example 31 provides a packaging substrate comprising: a stacking layer; a cavity in the stacking layer; and a semiconductor die in the cavity, the semiconductor die comprising: a plurality of conductive vias near the periphery of the semiconductor die, wherein each conductive via extends through the thickness of the semiconductor die and an air gap surrounds each conductive via.

[0167] Example 32 provides the packaging substrate of Example 31, wherein each air gap is covered by a bonding pad on either end of the air gap, and corresponding conductive vias within the air gap are directly coupled to the bonding pads on either end of the air gap.

[0168] Example 33 provides the packaging substrate of Example 32, wherein the bonding pad is wider than the air gap.

[0169] Example 34 provides a packaging substrate as described in any of Examples 31-33, wherein the semiconductor die includes a substrate comprising silicon; a metallization layer including conductive traces; an interlayer dielectric (ILD) material in the layers between the layers and between the conductive traces; and conductive vias passing through the ILD material, and an air gap around each conductive via extending through the substrate and the ILD material.

[0170] Example 35 provides the packaging substrate of any of Examples 31-34, wherein the semiconductor die is coupled to interconnects at a bottom of the cavity, and each interconnect is directly coupled to one of the conductive vias.

[0171] Example 36 provides a method comprising: providing a semiconductor material wafer having a first surface and an opposing second surface; forming through holes in the wafer, each through hole extending through the thickness of the wafer between the first surface and the second surface; adding conductive material in the through holes so that there is a gap laterally between the sidewalls of each through hole and the conductive material; and forming bonding pads on the first surface and the second surface, at least a subset of the bonding pads covering each through hole on the first surface and the second surface, so that the conductive material in each through hole is directly coupled to the bonding pads on the first surface and the second surface.

[0172] Example 37 provides the method of Example 36, further comprising: planarizing the first surface and the second surface before forming the bonding pad.

[0173] Example 38 provides the method of any of Examples 36-37, wherein the bonding pad is formed on the first surface before the bonding pad is formed on the second surface.

[0174] Example 39 provides the method of any of Examples 36-38, wherein the through-holes are formed by reactive ion etching.

[0175] Example 40 provides the method of any of Examples 36-39, wherein the conductive material is added to the through-holes by electron beam physical vapor deposition at a pressure less than 1 microbar.

[0176] The above description of the illustrated implementation of the present disclosure (including the content of the description in the Abstract) is not intended to be exhaustive or limit the present disclosure to the exact form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, as will be appreciated by those skilled in the relevant art, various equivalent modifications are possible within the scope of the present disclosure.

Claims

1. A semiconductor die, comprising: a first bonding pad on the first surface for coupling to a package substrate; a second bonding pad on a second surface, the second surface being opposite to the first surface; a hole through the semiconductor die; a conductive post within the hole separated from a sidewall of the hole by an air gap, the conductive post coupled to the first bonding pad and the second bonding pad; as well as A path conductively couples at least two integrated circuit (IC) dies proximate to the second surface.

2. The semiconductor die of claim 1, wherein: The first bonding pad and the second bonding pad are wider than the hole.

3. The semiconductor die of claim 1 , wherein: The first bond pad is directly coupled to an interconnect of one of the IC dies.

4. The semiconductor die of claim 1 , wherein: The second bond pad is directly coupled to an interconnect of the package substrate.

5. The semiconductor die of claim 1, wherein: The semiconductor die is located within a cavity in the package substrate.

6. The semiconductor die of any one of claims 1 to 5, wherein: The conductive pillar has a first width proximate the first bonding pad and a second width proximate the second bonding pad, and The first width is greater than the second width.

7. The semiconductor die of any one of claims 1 to 5, wherein: The conductive pillar is in a first portion of the semiconductor die, The path is in a second portion of the semiconductor die, and The first portion and the second portion are mutually exclusive.

8. The semiconductor die of claim 7, wherein: The first portion is proximate a periphery of the semiconductor die, and The second portion is proximate a center of the semiconductor die.

9. The semiconductor die of any one of claims 1 to 5, wherein: the semiconductor die is coupled to the IC die via a first interconnect and a second interconnect, The first interconnect is physically coupled to the conductive pillar, and The second interconnect is physically coupled to the path.

10. The semiconductor die according to any one of claims 1 to 5, wherein: The paths include conductive traces and conductive vias in inter-layer dielectric (ILD) materials.

11. An integrated circuit (IC) package, comprising: a package substrate having a surface with a blind cavity extending from the surface partially through the package substrate; a plurality of IC dies attached to the surface of the packaging substrate; and A bridge die attached to the plurality of IC dies in the blind cavity, the bridge die comprising: a conductive path conductively coupling at least one pair of IC dies among the plurality of IC dies; a through silicon via (TSV) extending through a thickness of the bridge die; and An air gap is formed around at least one TSV.

12. The IC package of claim 11, wherein: The TSV is in the hole, The holes have substantially parallel side walls perpendicular to the surface, and The air gap is located between the TSV and the sidewall.

13. The IC package according to claim 11 or 12, wherein: The plurality of IC dies are directly coupled to the bridge die via at least a first interconnect and a second interconnect, and The first interconnect is larger than the second interconnect.

14. The IC package according to claim 13, wherein: The second interconnect is similar in size to the first interconnect.

15. The IC package of claim 13, wherein: The bridge die is directly coupled to the package substrate via a third interconnect, and The third interconnect is similar in size to the first interconnect.

16. A packaging substrate, comprising: accumulation layer; A cavity in the stacked layer; and a semiconductor die in the cavity, the semiconductor die comprising a plurality of conductive vias proximate a perimeter of the semiconductor die, wherein: Each conductive via extends through the thickness of the semiconductor die, and An air gap surrounds each conductive via.

17. The packaging substrate according to claim 16, wherein: Each air gap is covered by a bonding pad on either end of the air gap, and Corresponding conductive vias within the air gap are directly coupled to the bond pads on either end of the air gap.

18. The packaging substrate according to claim 17, wherein: The bonding pad is wider than the air gap.

19. The packaging substrate according to any one of claims 16 to 18, wherein: The semiconductor die comprises: a substrate comprising silicon; a metallization layer including conductive traces; interlayer dielectric (ILD) material in the layers between the layers and between the conductive traces; and conductive vias through the ILD material, and The air gap around each conductive via extends through the substrate and the ILD material.

20. The packaging substrate according to any one of claims 16 to 18, wherein: The semiconductor die is coupled to an interconnect at a bottom of the cavity, and Each interconnect is directly coupled to one of the conductive vias.

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