Package and method of forming same

Abstract

The package includes a first integrated circuit die and a second integrated circuit die over and bonded to the first integrated circuit die. The first surface region of the second integrated circuit die is hydrophobic, and the first integrated circuit die and the second integrated circuit die are bonded together with a dielectric-to-dielectric bond and a metal-to-metal bond. The package also includes a first insulating material over the first integrated circuit die and surrounding the second integrated circuit die. The first insulating material contacts the first surface region. The embodiment of the invention also relates to a method of forming the package.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of forming the same. Background Art

[0002] Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) In large part, these improvements in integration density have come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

[0003] These integration improvements are essentially two-dimensional (2D) in nature, as the area occupied by the integrated components is essentially on the surface of the semiconductor wafer. The increased density of integrated circuits and the corresponding area reduction have generally exceeded the ability to directly bond the integrated circuit chips to the substrate. Interposers have been used to redistribute the ball contact area from the area of ​​the chip to the larger area of ​​the interposer. In addition, interposers have allowed three-dimensional packages that include multiple chips. Other packages have also been developed to incorporate three-dimensional aspects. Summary of the invention

[0004] Some embodiments of the present application provide a package, comprising: a first integrated circuit die; a second integrated circuit die located above the first integrated circuit die and bonded to the first integrated circuit die, wherein a first surface area of ​​the second integrated circuit die is hydrophobic, and wherein the first integrated circuit die and the second integrated circuit die are bonded together using dielectric-to-dielectric bonding and metal-to-metal bonding; and a first insulating material located above the first integrated circuit die and surrounding the second integrated circuit die, wherein the first insulating material contacts the first surface area.

[0005] Other embodiments of the present application provide a package, comprising: a first integrated circuit die; a first insulating material surrounding the first integrated circuit die; a second integrated circuit die located above the first integrated circuit die and bonded to the first integrated circuit die, wherein a first surface area of ​​the second integrated circuit die comprises fluorine, wherein a fluorine concentration of the first surface area is at least 5 wt %; and a second insulating material located above the first integrated circuit die and surrounding the second integrated circuit die, wherein the first surface area is disposed at an interface between the second insulating material and the second integrated circuit die.

[0006] Still other embodiments of the present application provide a method for forming a package, comprising: etching a groove through an interconnect structure and extending into a semiconductor substrate, the groove being arranged in a scribe line area, the scribe line area being arranged between a first integrated circuit die and a second integrated circuit die; performing surface treatment in the groove to form a first surface area in a first side wall of the first integrated circuit die, wherein the first surface area is hydrophobic; depositing a protective layer covering the groove above the first integrated circuit die; attaching a tape to a surface of the protective layer opposite to the first integrated circuit die; performing backside planarization on a surface of the semiconductor substrate opposite to the tape; and after performing the backside planarization, removing the protective layer and the tape to completely separate the first integrated circuit die from the second integrated circuit die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 5 and Figure 6 Cross-sectional views of various intermediate steps in singulating an integrated circuit die are shown according to various embodiments.

[0009] Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14A and Fig. 14B Cross-sectional views of various intermediate steps in packaging an integrated circuit die according to various embodiments are shown.

[0010] Fig.15 , Fig.16 , Fig.17 , Fig.18A and Fig.18B Cross-sectional views of various intermediate steps in packaging an integrated circuit die according to various embodiments are shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] According to various embodiments, a segmentation process is performed to separate the individual semiconductor dies from the wafer. The segmentation process may include: patterning grooves in the scribe line area of ​​the wafer; and performing a surface treatment to provide hydrophobic sidewalls in the grooves. In some embodiments, the surface treatment is a fluorine-based treatment. The hydrophobic sidewalls can prevent a protective layer (e.g., a backside anti-reflective coating (BARC) layer, etc.) from being deposited in the grooves during a subsequent segmentation step. A planarization process may then be performed to remove the back side of the wafer, separating the semiconductor dies along the grooves.

[0014] The protective coating layer can protect the semiconductor die during the planarization process, and the cleaning process can be used to remove the protective layer after the planarization process. Because the protective layer is not deposited in the groove, the cleaning process can more effectively remove the protective layer, thereby improving the yield and reducing the reconstructed wafer (RW) tool failure. For example, when the protective layer fills the groove, the semiconductor die may not be successfully separated from the wafer, resulting in RW failure. As another example, when the semiconductor die is packaged in a semiconductor package with other components, the protective layer retained on the sidewalls of the segmented semiconductor die may cause defects. By converting the sidewalls of the groove into hydrophobic through fluorine-based treatment, such defects can be avoided and the yield can be improved.

[0015] Figure 14 is a cross-sectional view of a wafer 40, which includes an integrated circuit die 50. The integrated circuit die 50 will be packaged in a subsequent process to form an integrated circuit package. Each integrated circuit die 50 can be a logic device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc. or a combination thereof (e.g., a system on chip (SoC) die). The integrated circuit die 50 can be formed in a wafer 40, and the wafer 40 can include different device regions that are divided in a subsequent step to form a plurality of integrated circuit dies 50. Specifically, the device regions can be separated by a scribe line region 48, and a subsequent dividing process is implemented in the scribe line region 48. In some embodiments, scribe line regions 48 provide test lines that can be used to perform electrical testing and / or yield testing during the manufacturing process. Integrated circuit dies 50 each include a semiconductor substrate 52 , an interconnect structure 54 , and bonding pads 66 disposed in an insulating bonding layer 68 .

[0016] The semiconductor substrate 52 may be an active layer of a silicon substrate (doped or undoped) or a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., a surface facing upward) and an inactive surface (e.g., a surface facing downward). The device is located at the active surface of the semiconductor substrate 52. The device may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. The inactive surface may be free of devices.

[0017] The interconnect structure 54 is located above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices of the semiconductor substrate 52 to form one or more integrated circuits. The interconnect structure 54 may include a metallization pattern 54A located in one or more dielectric layers 54B. Acceptable dielectric materials for the dielectric layer 54B include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon nitride, etc. Other dielectric materials may also be used. The metallization pattern 54A may include conductive vias and / or wires to interconnect the devices of the semiconductor substrate 52. The metallization pattern 54A may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The interconnect structure 54 may also include a metal pad 54C (e.g., an aluminum pad, a copper pad, etc.) connected to the topmost metallization pattern 54A of the interconnect structure 54 through one or more passivation layers. An additional insulating layer (e.g., a passivation layer 54D) may be formed around the metal pad 54C to provide a flat surface on which to form the upper components (e.g., bonding pad 66 and insulating bonding layer 68, see FIG. Figure 6 ).

[0018] Figures 2 to 4C is a modified view of an intermediate step during the singulation process of separating the integrated circuit die 50 from the wafer 40. Figure 2 Initially, trenches 58 are formed extending through interconnect structure 54 and into semiconductor substrate 52. Trenches 58 may be patterned in scribe areas 48 between adjacent integrated circuit dies 50. In some embodiments, scribe areas 48 may be wide enough to accommodate trenches 58 and test line areas for wafer 40.

[0019] In some embodiments, the groove 58 is formed with a combination of photolithography and etching processes. For example, the groove 58 can be formed in the scribe area 48 in a plasma cutting process. The plasma cutting process may include forming a patterned mask 56 over the interconnect structure. The patterned mask 56 may be a photomask deposited over the interconnect structure 54 in a spin coating process and patterned by photolithography (e.g., exposure and development) to define an opening that exposes the interconnect structure 54 in the scribe area 48. The plasma cutting process etches the interconnect structure 54 and a portion of the semiconductor substrate 52 through a pattern (e.g., opening) in the patterned mask 55. In some embodiments, the plasma cutting is a dry plasma process, such as reactive ion etching (RIE) using fluorine-based plasma, argon-based plasma, oxygen-based plasma, nitrogen-based plasma, etc. The groove 58 may extend through the interconnect structure 54 to a desired depth in the semiconductor substrate 52. However, the groove 58 may not extend completely through the semiconductor substrate 52, and the lower portion of the semiconductor substrate 52 may be retained to connect the integrated circuit die 50 together in the wafer 40.

[0020] exist Figure 3 In the embodiment of the present invention, a surface treatment is performed in the trench 58 to form a surface region 60 on the exposed surface of the trench 58. The surface region 60 may be hydrophobic. In some embodiments, the surface treatment is a fluorine-based treatment, such as a wet cleaning process using a solution including fluorine, a fluorine-based plasma process, etc. In some embodiments, the fluorine-based plasma process may be performed at a temperature in the range of 25° C. to 500° C. and at a pressure of 0 Torr to 1.316×10 -3 Torr (one atmosphere). In other embodiments, other treatments to form a hydrophobic surface may be applied. The surface treatment makes the surface of the groove 58 hydrophobic so that the subsequently formed protective layer (e.g., protective layer 62, see Figure 4A ) can be deposited over the interconnect structure 54 without being significantly deposited in the trenches 58. When the surface treatment is a fluorine-based treatment, the resulting surface region 60 can also include fluorine and be referred to as a fluorinated protective layer 60. For example, the surface region 60 can include 5 weight percent (wt%) or more fluorine, which advantageously produces a hydrophobic surface in the trenches 58. It has been observed that when the surface regions 60 have less than 5 wt% fluorine, they can remain hydrophilic and do not significantly prevent subsequently formed protective layers from being deposited in the trenches 58. The surface region 60 can also include carbon, oxygen, silicon, nitrogen, or a combination thereof. The specific material composition of the surface region 60 can depend on the material of the interconnect structure 54 and / or the semiconductor substrate 52 on which the surface region 60 is formed. For example, the portion of the surface region 60 located on the semiconductor substrate can include fluorine and silicon, while the portion of the surface region 60 located on the interconnect structure 54 can include fluorine combined with carbon, oxygen, nitrogen and / or silicon. The thickness T1 of the surface region 60 can be between 100 and 200 nm. to 10μm range.

[0021] The surface treatment may be performed while the patterned mask 56 covers the interconnect structure 54. Thus, the surface region 60 may be selectively formed in the trench 58 without blanket forming the surface region 60 over the interconnect structure 54. For example, after the surface treatment, the top surface of the interconnect structure 54 may remain hydrophilic so that a protective layer (e.g., protective layer 62, see FIG. 4 ) may be deposited thereon. Figure 4A ). After the surface treatment, the patterned mask 56 may be removed. For example, when the patterned mask 56 is a photomask, the patterned mask 56 may be stripped using an ashing process.

[0022] exist Figure 4A In the embodiment of the present invention, a protective layer 62 is deposited over the interconnect structure 54. In some embodiments, the protective layer 62 is a BARC layer deposited by a spin coating process or the like. Due to the surface treatment and the hydrophobic surface region 60, the protective layer 62 may not be significantly deposited within the trench 58. Keeping the protective layer 62 from being deposited in the trench 58 achieves advantages such as reduced manufacturing defects and improved yield.

[0023] For example, Figure 4B The material 62' of the protective layer 62 is shown on the untreated substrate 52. Because the surface treatment process described above is not implemented, and Figure 4B Surface region 60 is not formed in the substrate 52, so the surface of substrate 52 remains hydrophilic. Specifically, the hydrophilic property of substrate 52 can be measured by a contact angle θ1 at a liquid-air interface between material 62' and semiconductor substrate 52 being less than 10°. Material 62' can be easily deposited on the hydrophilic surface (e.g., filling at least the upper portion of trench 58), and integrated circuit die 50 may not be completely separated after a subsequent planarization process (see Figure 5 ). For example, the protective layer 62 may plug the trenches 58 and adhere adjacent integrated circuit dies 50 together, preventing the integrated circuit dies 50 from being separated. Even when the integrated circuit dies 50 are fully singulated, the protective layer 62 may leave undesirable residues on the sidewalls of the singulated integrated circuit dies 50. During subsequent packaging processes, the residues may cause manufacturing defects (e.g., gap fill voids).

[0024] on the contrary, Figure 4CThe material 62' of the protective layer 62 is shown on the substrate 52 having the surface region 60, the surface region 60 being formed with the surface treatment described above. The surface region 60 provides a hydrophobic surface that repels the material 62' and prevents the material 62' from being deposited within the trench 58. The hydrophobic nature of the surface region 60 can be evidenced by the contact angle θ2 at the liquid-vapor interface between the material 62' and the surface region 60 being greater than 10°. Because the surface region 60 repels the protective layer 62, the integrated circuit die 50 can be more easily singulated, and undesirable residues on the sidewalls of the singulated integrated circuit die 50 can be avoided.

[0025] Likewise Figure 4A As shown, tape 64 is bonded to wafer 40, such as to the top surface of protective layer 62. Tape 64 supports wafer 40 during the subsequent singulation process, and protective layer 62 serves as an intermediate buffer between the wafer and tape 64. For example, protective layer 62 protects the top surface of interconnect structure 54 from direct contact with tape 64, reducing the risk of damage to interconnect structure 54.

[0026] exist Figure 5 In the process, a backside planarization process is performed to thin the semiconductor substrate 52. The planarization process may be performed to remove a portion of the semiconductor substrate 52 that exceeds the trench 58. Specifically, the planarization process removes a portion of the semiconductor substrate 52 that is connected to the integrated circuit die 50, and exposes the trench 58 from the back side of the semiconductor substrate 52. In some embodiments, the planarization process is a CMP process, a mechanical grinding process, an etch-back process, a combination thereof, or the like.

[0027] After the backside planarization process is performed on the semiconductor substrate 52, the tape 64 can be removed, and a cleaning process can be performed to remove the protective layer 62. The cleaning process can be a wet clean using a suitable cleaning solution, etc. In some embodiments, the cleaning solution can include deionized water (DI water), an alkaline solution, an ammonia solution (e.g., including Na, K, C, O, H, etc.), a combination thereof, etc. Because the protective layer 62 is not significantly deposited within the trench 58, the protective layer 62 can be more easily removed by the cleaning process without leaving undesirable residues or inadvertently bonding parts of the integrated circuit die 50 together. Therefore, the integrated circuit dies 50 can be completely separated from each other, such as Figure 6 shown.

[0028] Figure 6 Shown above in Figures 2 to 5. In the illustrated embodiment, due to the singulation process described above, surface regions 60 are formed on opposite sidewalls of the integrated circuit die 50. In other embodiments (e.g., when the integrated circuit die 50 is located, for example, at the edge of a wafer), at least one sidewall of the integrated circuit die 50 may be free of surface regions 60 (see, e.g., Fig. 14B and Fig.18B ).

[0029] In addition, bonding pads 66 are formed in insulating bonding layer 68 on front side 50F of integrated circuit die 50. Bonding pads 66 may be conductive pillars, pads, etc. that make external connections. Bonding pads 66 may be formed of metal, such as copper, aluminum, etc., and may be formed, for example, by plating, etc. In some embodiments, bonding pads 66 may be electrically connected to conductive features (e.g., metal pads 54C) of interconnect structure 54 through conductive vias (sometimes referred to as bonding pad vias).

[0030] The bonding pads 66 may be disposed in an insulating bonding layer 68 at the front side 50F of the integrated circuit die 50. The insulating bonding layer 68 may be made of a material suitable for subsequent dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, and the like. The insulating bonding layer 68 may be deposited on the interconnect structure, for example, by spin coating, lamination, chemical vapor deposition (CVD), and the like. The bonding pads 66 may be formed in the insulating bonding layer using, for example, a damascene process, and a planarization process (e.g., chemical mechanical polishing (CMP), etc.) may be implemented so that the top surfaces of the bonding pads 66 and the insulating bonding layer 68 are coplanar (within process variations) and exposed at the front side 50F of the integrated circuit die 50. As will be described in more detail below, the planarized front side 50F of the integrated circuit die 50 will be directly bonded to another package component, such as another integrated circuit die.

[0031] In some embodiments, the integrated circuit die 50 is a stacked device including multiple semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including multiple memory dies, such as a hybrid memory multidimensional cube (HMC) device, a high bandwidth memory (HBM) device, etc. In such an embodiment, the integrated circuit die 50 includes multiple semiconductor substrates 52 interconnected by through-substrate vias or through-silicon vias (TSVs). Each of the semiconductor substrates 52 may (or may not) have a separate interconnect structure 54.

[0032] Figures 7 to 14B is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package according to some embodiments, wherein an integrated circuit die 50 is packaged together with other packaging components. Figures 7 to 14B The details of the integrated circuit die 50 can be simplified. Figures 7 to 14BA particular packaging configuration is shown (e.g., a system-on-integrated chip (SoIC) packaging configuration), but it should be understood that other packaging configurations (e.g., integrated fan-out (InFO) packaging, chip-on-wafer-on-substrate (CoWoS) packaging, etc.) may also be used.

[0033] exist Figures 7 to 14B In the embodiment, an integrated circuit package 150 (labeled 150A and 150B, see FIG. 1 ) is formed by bonding an integrated circuit die 50 to an integrated circuit die 70 on a carrier substrate 100. Fig.14A and Fig. 14B Because the integrated circuit die 50 is bonded above the integrated circuit die 70 , the integrated circuit die 50 and the integrated circuit die 70 may also be referred to as a top integrated circuit die 50 and a bottom integrated circuit die 70 , respectively.

[0034] First reference Figure 7 , the integrated circuit die 70 is shown as being located on a carrier substrate 100. The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 100 may be a wafer, so that a plurality of packages may be formed simultaneously on the carrier substrate 100. An insulating bonding layer 102 is disposed on the top surface of the carrier substrate 100. The insulating bonding layer 102 may include a silicon-containing dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc., deposited using a suitable deposition process such as CVD, PVD, ALD, high density plasma chemical vapor deposition (HDPCVD), etc. In some embodiments, an alignment mark 101 is optionally disposed in the insulating bonding layer 102. The alignment mark 101 may facilitate accurate placement of a structure (e.g., the integrated circuit die 70) on the carrier substrate 100. Optionally, a planarization step may then be performed to level the top surface of the insulating bonding layer 102, so that the insulating bonding layer 102 has a high degree of planarity.

[0035] The integrated circuit die 70 may be attached to the carrier substrate 100. The integrated circuit die 70 is disposed face down such that a front side 70F of the integrated circuit die 70 faces the carrier substrate 100 and a back side 70B of the integrated circuit die 70 faces away from the carrier substrate 100. The integrated circuit die 70 includes a substrate 72, an interconnect structure 74, conductive vias 76 in the substrate 72, and an insulating bonding layer 78.

[0036] Substrate 72 may be a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. Substrate 72 may include: semiconductor materials such as silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used. Substrate 72 may be doped or undoped. In some embodiments, active devices such as transistors, diodes, and the like may be formed in and / or on the front side of substrate 72. In some embodiments, passive devices such as capacitors, resistors, and the like may be formed on the front side of substrate 72 in addition to or in place of active devices.

[0037] The interconnect structure 74 is located above the front side of the substrate 72 and is used to electrically connect the devices of the substrate 72. Therefore, the front side 70F of the integrated circuit die 70 can refer to the side of the substrate 72 on which the interconnect structure 74 and any devices are disposed. The interconnect structure 74 may include one or more dielectric layers and corresponding metallization patterns in the dielectric layers. Acceptable dielectric materials for the dielectric layers include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon nitride, etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc. The metallization pattern may include conductive vias and / or wires to interconnect any devices together and / or to external devices. The metallization pattern may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The interconnect structure 74 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.

[0038] Conductive vias 76 are embedded in substrate 72 and / or interconnect structure 74. Conductive vias 76 are electrically coupled to the metallization pattern of interconnect structure 74. Conductive vias 76 are sometimes also referred to as TSVs. As an example of forming conductive vias 76, grooves can be formed in interconnect structure 74 and / or substrate 72 by, for example, etching, milling, laser technology, combinations thereof, etc. A thin dielectric material can be formed in the groove, such as by using an oxidation technique. A thin barrier layer can be conformally deposited in the opening, such as by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The barrier layer can be formed of oxides, nitrides, carbides, combinations thereof, etc. Conductive materials can be deposited over the barrier layer and in the opening. Conductive materials can be formed by electrochemical plating processes, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive materials and barrier layers are removed from the surface of interconnect structure 74 or substrate 72 by, for example, CMP. The remaining portion of the barrier layer and the conductive material forms a conductive via 76. The conductive via 76 is electrically connected to the metallization pattern of the interconnect structure 74.

[0039] In some embodiments, the conductive vias 76 may be formed in the first region 71A of the integrated circuit die 70, but not in the second region 71B of the integrated circuit die 70. The second region 71B may correspond to a dummy die (e.g., dummy die 80, see FIG. 1 ) to which a dummy die may be subsequently bonded. Fig.10 ) for improved heat dissipation. In other embodiments, the conductive vias 76 may be formed uniformly throughout the integrated circuit die 70.

[0040] Initially, the integrated circuit die 70 may be formed as part of a wafer, and the wafer is subsequently singulated to separate the integrated circuit die 70 from other components of the wafer. In the illustrated embodiment, the integrated circuit die 70 is singulated without implementing the above-described Figures 2 to 5 Thus, the sidewall surface of the integrated circuit die 70 may be hydrophilic and may not have any surface area. For example, the sidewall of the integrated circuit die 70 may be completely free of any surface area including fluorine or have less than 5 wt % fluorine. In other embodiments, the singulation process may be substantially similar to that described above in Figures 2 to 5 In such an embodiment, the sidewalls of the integrated circuit die 70 may include a hydrophobic surface region (eg, a surface region including fluorine having more than 5 wt % fluorine). Such an embodiment is then Figures 15 to 18B Described in the embodiments of the present invention.

[0041] An insulating bonding layer 78 is formed on the front side of the integrated circuit die 70 (such as on the interconnect structure 74). The insulating bonding layer 78 can be formed of similar materials using a process similar to the insulating bonding layer 102 described above. The integrated circuit die 70 can be attached to the carrier substrate 100 by bonding the insulating bonding layers 102 and 78 together using a dielectric to dielectric bonding process (e.g., oxide to oxide bonding). Dielectric to dielectric bonding can start by activating the insulating bonding layer 102 and / or the insulating bonding layer 78 and subsequently applying pressure, heat and / or other bonding process steps to bond the insulating bonding layer 102 to the insulating bonding layer 78 surface. Activating the insulating bonding layer 102 and / or the insulating bonding layer 78 can be implemented using, for example, dry processing, wet processing, plasma processing, exposure to H2, exposure to N2, exposure to O2, combinations of these, etc. In an embodiment using wet processing, an RCA cleaning process, for example, can be used. Through the activation process, the number of OH groups at the surface of the insulating bonding layer 102 and / or the insulating bonding layer 78 increases. After activating the surface of the insulating bonding layer 102 and / or the insulating bonding layer 78, the insulating bonding layer 102 and the insulating bonding layer 78 can be contacted together at a relatively low temperature (e.g., room temperature) to form a weak bond. Subsequently, annealing is performed to strengthen the weak bond and form a molten bond. During annealing, H of the OH bond is removed, thereby forming a Si-O-Si bond between the insulating bonding layer 102 and the insulating bonding layer 78, thereby strengthening the bond (e.g., forming a covalent bond).

[0042] exist Figure 8 In the embodiment, an insulating material 104 is formed over the carrier substrate 100 and around the integrated circuit die 70. In some embodiments, the insulating material 104 is a dielectric gap filling material deposited by PVD, CVD, etc., such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, combinations thereof, etc. In some embodiments, the insulating material 104 is a molding material or compound formed by compression molding, transfer molding, etc. and a subsequent curing process. The molding material may or may not include a filling material (e.g., a silicon dioxide filler). The insulating material 104 may be formed over the back side 70B of the integrated circuit die 70 so that the integrated circuit die 70 is at least partially buried or covered. A planarization process may be implemented to planarize the top surface of the insulating material 104 and the back side 70B of the integrated circuit die 70. The planarization process may be CMP, etch back, combinations thereof, etc. In the illustrated embodiment, the integrated circuit die 70 is exposed by planarization of the insulating material 104 so that the top surfaces of the integrated circuit die 70 and the insulating material 104 are substantially flush (within process variations). Planarization may also remove portions of semiconductor substrate 72 to expose conductive vias 76. Insulating material 104 surrounds and protects integrated circuit die 70.

[0043] exist Fig. 9, the insulating bonding layer 108 and the bonding pad 106 are located on the back side 70B of the integrated circuit die 70. The insulating bonding layer 108 and the bonding pad 106 can be made of similar materials using similar processes as the insulating bonding layer 68 and the bonding pad 66, respectively, as described above. The insulating bonding layer 108 can be deposited to cover the back side 70B of the integrated circuit die 70 and the insulating material 104. The bonding pad 106 can be formed above the conductive via 76 and electrically connected to the conductive via 76. In an embodiment where the conductive via 76 is not provided in the second region 71B of the integrated circuit die 70, the bonding pad 106 may also not be formed above the second region 71B of the integrated circuit die 70.

[0044] exist Fig.10 , integrated circuit die 50 is bonded to integrated circuit die 70. In some embodiments, integrated circuit die 50 implements a different function than integrated circuit die 70. For example, integrated circuit die 70 may be a logic processing die, and integrated circuit die 50 may be a memory die. In other embodiments, integrated circuit dies 50 and 70 may implement functions different from logic processing / memory, or integrated circuit dies 50 and 70 may implement the same function.

[0045] The integrated circuit die 50 and the integrated circuit die 70 are directly bonded in a face-to-back manner by dielectric-to-dielectric bonding and metal-to-metal bonding processes (sometimes referred to as hybrid bonding), so that the front side 50F of the integrated circuit die 50 is bonded to the back side 70B of the integrated circuit die 70. Specifically, the insulating bonding layer 68 of the integrated circuit die 50 is bonded to the insulating bonding layer 108 on the integrated circuit die 70 by dielectric-to-dielectric bonding without using any adhesive material (e.g., die attach film), and the bonding pad 66 of the integrated circuit die 50 is bonded to the bonding pad 106 on the integrated circuit die 70 by metal-to-metal bonding without using any eutectic material (e.g., solder). Bonding may include surface activation, pre-bonding, and annealing. Surface activation may include: activating the insulating bonding layer 108 and / or the insulating bonding layer 68 may be implemented using, for example, dry processing, wet processing, plasma processing, exposure to H2, exposure to N2, exposure to O2, combinations of these, etc. In an embodiment using wet processing, for example, an RCA cleaning process may be used. By the activation treatment, the number of OH groups at the surface of the insulating bonding layer 108 and / or the insulating bonding layer 68 increases. After activating the surface of the insulating bonding layer 108 and / or the insulating bonding layer 68, pre-bonding is implemented by applying a small pressure to press the integrated circuit die 50 against the integrated circuit die 70. The pre-bonding is implemented at a low temperature, such as room temperature, such as a temperature in the range of about 15°C to about 30°C. Then, the bonding strength of the insulating bonding layers 68 and 108 is improved in a subsequent annealing step, wherein the insulating bonding layers 68 and 108 are annealed at a high temperature, such as a temperature in the range of about 100°C to about 450°C. After annealing, a bond, such as a covalent bond, is formed to bond the insulating bonding layers 68 and 108. The bonding pads 66 and 106 are connected to each other in a one-to-one manner. The bonding pads 66 and 106 can be in physical contact after pre-bonding, or can be expanded to physical contact during annealing. In addition, during the annealing, the materials (e.g., copper) of the bonding pads 66 and 106 mix, thereby also forming a metal-to-metal bond. Therefore, the resulting bond is a mixed bond including a dielectric-to-dielectric bond and a metal-to-metal bond. The integrated circuit die 50 can be bonded to the first region 71A of the integrated circuit die 70 in which the conductive vias 76 are disposed. Therefore, the circuit within the integrated circuit die 50 can be electrically connected to the circuit within the integrated circuit die 70 through the bonding pads 68 and the conductive vias 76.

[0046] Likewise Fig.10As shown, dummy die 80 is bonded over second region 71B of integrated circuit die 70. Dummy die 80 may be a bulk semiconductor die (e.g., a silicon die) or the like in which no devices are disposed. Dummy die 80 may be included to facilitate heat dissipation away from integrated circuit die 70 in a completed package. In some embodiments, dummy die 80 may initially be formed in a wafer and a process similar to that described above may be applied. Figures 2 to 5 The segmentation process described in the embodiment is used to separate the dummy die 80 from the wafer. Specifically, the dummy die 80 can be subjected to a surface treatment so that the dummy die 80 has a hydrophobic sidewall provided by the surface region 82. In an embodiment in which the surface treatment applied to the dummy die 80 is a fluorine-based treatment, the surface region 82 also includes fluorine. In some embodiments, the fluorine concentration of the surface region 82 can be at least 5wt% to provide a hydrophobic sidewall and achieve the benefits described above (e.g., clean separation and reduced residue on the dummy die 80). An insulating bonding layer 84 can be disposed on the dummy die 80, and the insulating bonding layer 84 can directly bond the dummy die 80 to the insulating bonding layer 108 using a dielectric to dielectric bonding process. Specifically, the insulating bonding layers 84 and 108 can be bonded together using a process similar to the bonding of the insulating bonding layers 78 and 102 described above.

[0047] exist Fig.11 In the embodiment of the present invention, an insulating material 110 is formed above the insulating bonding layer 108 and around the integrated circuit die 50 and the dummy die 80. The insulating material 110 can be formed of similar materials using a process similar to the insulating material 104 described above. For example, in some embodiments, the insulating material 110 is a dielectric gap filling material deposited by PVD, CVD, etc., such as silicon oxide, silicon nitride, silicon oxynitride, carbon nitride silicon oxide, combinations thereof, etc. In some embodiments, the insulating material 110 is a molding material or compound formed by compression molding, transfer molding, etc. and a subsequent curing process. The molding material may or may not include a filling material (e.g., a silicon dioxide filler). A planarization process may be implemented to planarize the top surface of the insulating material 110 and the back side 50B of the integrated circuit die 50. The planarization process may be CMP, etch back, combinations thereof, etc. In the illustrated embodiment, the integrated circuit die 50 and the dummy die 80 are exposed by planarization of the insulating material 110 such that top surfaces of the integrated circuit die 50 , the dummy die 80 , and the insulating material 110 are substantially flush (within process variations).

[0048] Because the above Figures 2 to 5In the singulation process described in the prior art, the sidewalls of the integrated circuit die 50 and / or the dummy die 80 can be hydrophobic and include the surface regions 60 and 82. The hydrophobic sidewalls repel any undesirable residues from previous process steps from accumulating on the sidewalls of the integrated circuit die 50 and / or the dummy die 80. Thus, the insulating material 110 can be deposited around the integrated circuit die 50 and the dummy die 80 with improved adhesion to the sidewalls of the integrated circuit die 50 and the dummy die 80, and manufacturing defects can be reduced.

[0049] exist Fig.12 , a carrier substrate 120 is attached over the integrated circuit die 50, the dummy die 80, and the insulating material 110. The carrier substrate 120 may be substantially similar to the carrier substrate 100 described above. In order to attach the carrier substrate 120, an insulating bonding layer 112A is deposited over the integrated circuit die 50, the dummy die 80, and the insulating material 110, and an insulating bonding layer 112B is deposited over the carrier substrate 120. The insulating bonding layers 112A and 112B may be made of similar materials using a process similar to the insulating bonding layer 102 described above. Then, the insulating bonding layers 112A and 112B may be bonded together using a dielectric-to-dielectric bonding process similar to the bonding insulating bonding layers 78 and 102 described above. The resulting bonded insulating bonding layers 112A and 112B may be collectively referred to as bonding layers 112. Therefore, the carrier substrate 120 is bonded over the integrated circuit die 50, the dummy die 80, and the insulating material 110.

[0050] exist Fig.13 In the embodiment of the present invention, the entire structure can be flipped over and the carrier substrate 100 can be removed from the front side 70F of the integrated circuit die 70. Removing the carrier substrate 100 can include a planarization process such as CMP, grinding, etch back, combinations thereof, etc. Removing the carrier substrate 100 can further remove the insulating bonding layer 102 and expose the integrated circuit die 70 and the insulating material 104.

[0051] exist Fig.14A and Fig. 14B In the embodiment, one or more passivation layers 114 are formed over the integrated circuit die 70 and the insulating material 110. The passivation layer 114 may include a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), a polymer material (e.g., polyimide, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymer, etc.), or a combination thereof. For example, the passivation layer 114 may include a dielectric layer 114A and a polymer layer 114B over the dielectric layer 114A. Other configurations of the passivation layer 114 are also possible.

[0052] In addition, an under-bump metal (UBM) 116 extending through the passivation layer 114 is formed on the passivation layer 114. The UBM 116 can be electrically connected to the metallization pattern in the interconnection structure 74 of the integrated circuit die 70. As an example of forming the UBM 116, an opening can be patterned in the passivation layer 114 to expose the interconnection structure 74. In some embodiments, the patterned opening can be achieved by a combination of photolithography and etching. In other embodiments, the opening in the passivation layer 114 can be achieved by, for example, laser drilling. A seed layer (not shown) is formed in the opening. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD, etc. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the UBM 116. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or chemical plating. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process. The remaining portion of the seed layer and the conductive material forms the UBM 116.

[0053] In addition, a conductive connector 118 is formed on the UBM 116. The conductive connector 118 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 118 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 118 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow may be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 118 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column may be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0054] Thus, semiconductor packages 150A and 150B are formed. Fig.14A Semiconductor package 150A is shown in which surface region 60 and surface region 82 are formed on all sidewalls of integrated circuit die 50 and dummy die 80, respectively. Thus, all sidewalls of integrated circuit die 50 and dummy die 80 are hydrophobic and may include fluorine. Fig. 14B A semiconductor package 150B is shown in which the surface region 60 and the surface region 82 are formed only on a subset of the sidewalls of the integrated circuit die 50 and the dummy die 80, respectively. Thus, some of the sidewalls of the integrated circuit die 50 and the dummy die 80 are hydrophobic and may include fluorine, while other sidewalls of the integrated circuit die 50 and the dummy die 80 are hydrophilic and may not include substantially any fluorine (e.g., less than 5 wt % fluorine).

[0055] Figures 7 to 14B FIG. 1 shows a packaging process in which the integrated circuit die 70 is not subjected to a surface treatment (e.g., a fluorine-based treatment) to form a hydrophobic sidewall region. Figures 2 to 5 A substantially similar process as described in is applied to the surface treatment of the integrated circuit die 70. In such an embodiment, the sidewalls of the integrated circuit die 70 can include a hydrophobic surface region (eg, a surface region including fluorine having more than 5 wt % fluorine). Figures 15 to 18B An intermediate processing step of packaging an integrated circuit die 70 having a hydrophobic surface area with the integrated circuit die 50 is shown. Figures 15 to 18B In the Figures 7 to 14B The same components of the embodiments are formed by the same process unless otherwise specified.

[0056] exist Fig.15 In FIG. 1 , an integrated circuit die 70 is attached to a carrier substrate 100. Each of the integrated circuit dies 70 includes a semiconductor substrate 72, an interconnect structure 74, and a conductive via 76 embedded in the semiconductor substrate 72, as shown in FIG. Figure 7 Initially, the integrated circuit die 70 may be formed as part of a wafer and then processed using the method described above. Figures 2 to 5 Specifically, trenches may be patterned in the wafer along the scribe line areas, such as Figure 2 Then, a surface treatment such as a fluorine-based treatment may be applied in the trenches, e.g. Figure 3. The fluorine-based treatment creates surface regions 90 on the sidewalls of the trenches (which also correspond to the sidewalls of the semiconductor substrate 72 and the interconnect structure 74). In some embodiments, the surface regions 90 include fluorine, such as fluorine at a concentration of 5 wt % or more, to create hydrophobic sidewalls in the trenches. It has been observed that when the surface regions 90 have less than 5 wt % fluorine, they can remain hydrophilic and do not significantly prevent subsequently formed protective layers from being deposited in the trenches. The surface regions 90 may also include carbon, oxygen, silicon, nitrogen, or a combination thereof. The specific material composition of the surface regions 90 may depend on the material of the interconnect structure 74 and / or the semiconductor substrate 72 on which the surface regions 90 are formed. For example, the portion of the surface region 90 located on the semiconductor substrate 72 may include fluorine and silicon, while the portion of the surface region 90 located on the interconnect structure 74 may include fluorine combined with carbon, oxygen, nitrogen and / or silicon. The thickness of the surface region 90 may be in the range of 100 to 100 wt %. to 10μm range.

[0057] After the surface treatment is performed, a backside planarization process can be performed to use Figure 5 The portion of the semiconductor substrate 72 that connects the integrated circuit die 70 to the wafer is removed by a process similar to that described in . The backside planarization process may or may not expose the conductive vias 76. During the backside planarization process, the wafer can be attached to the tape, and a protective layer can cover the front side of the wafer to prevent damage caused by direct contact with the tape. Due to the surface treatment and hydrophobic sidewalls in the trenches, material of the protective layer is not deposited within the trenches, thereby allowing improved separation of the integrated circuit die 70 and avoiding undesirable surface residues on the sidewalls of the integrated circuit die 70. The tape and protective layer can then be removed as described above, resulting in fully singulated integrated circuit dies 70. The singulated integrated circuit dies can then be separated by insulating bonding layers 78 and 102 to contact the above in . Figure 7 1 and 2. The method of bonding to the carrier substrate 100 is similar to that described in FIG. Fig.15 Two integrated circuit dies 70 are shown bonded to the carrier substrate 100 , but any number of integrated circuit dies 70 may be bonded to the carrier substrate 100 .

[0058] exist Fig.16 In the above Figure 8 Insulating material 104 is deposited around integrated circuit die 70 in a manner similar to that described in . Due to hydrophobic surface region 90, surface residues on the sidewalls of integrated circuit die 70 can be reduced, and insulating material 104 can be deposited with improved adhesion and fewer defects (e.g., gaps) around integrated circuit die 70. In addition, in Fig.16In the embodiment, an insulating bonding layer 108 is deposited over the integrated circuit die 70, and a bonding pad 106 is formed on the conductive via 76 of the integrated circuit die 70. The insulating bonding layer 108 and the bonding pad 106 may be formed in a manner similar to that of the above. Fig. 9 In an embodiment, where the integrated circuit die 70 includes an area without conductive vias 76 , the bonding pads 106 may also not be formed on the area without conductive vias 76 .

[0059] exist Fig.17 In the embodiment, the integrated circuit die 50 and the dummy die 80 are similar to those in the embodiment shown in FIG. Fig.10 . For example, integrated circuit die 50 can be directly bonded to integrated circuit die 70 by dielectric-to-dielectric and metal-to-metal bonding, and circuits within integrated circuit die 50 can be electrically connected to circuits within integrated circuit die 70 by conductive vias 76, bonding pads 106, and bonding pads 66. In addition, dummy die 80 can be directly bonded to integrated circuit die 70 by direct dielectric-to-dielectric bonding through insulating bonding layers 108 and 84. Integrated circuit die 50 and dummy die 80 can include hydrophobic surface regions 60 and 82, respectively, as described above. In addition, in Fig.17 In the above Fig.11 Insulating material 110 is formed around integrated circuit die 50 and dummy die 80 in a manner similar to that described in .

[0060] exist Fig.18A and Fig.18B In the embodiment, the carrier substrate 200 is bonded to the integrated circuit die 50, the dummy die 80 and the insulating material 110, and the carrier substrate 100 is bonded to the integrated circuit die 50, the dummy die 80 and the insulating material 110. Figure 12 to Figure 13 In addition, the same method as described above is used to remove Fig.14A and Fig. 14B One or more passivation layers 114 are formed over the integrated circuit die 70 and the insulating material 104 in a manner similar to that described in . Then, UBM 116 and conductive connectors 118 are formed through the passivation layer 114 to electrically connect to the integrated circuit dies 50 and 70, as described above in Fig.14A and Fig. 14B Described in .

[0061] Fig.18A Semiconductor package 152A is shown in which surface region 90 is formed on all sidewalls of integrated circuit die 70. Thus, all sidewalls of integrated circuit die 70 are hydrophobic and may include fluorine. Fig.18BSemiconductor package 152B is shown in which surface region 90 is formed on only a subset of the sidewalls of integrated circuit die 70. Thus, some sidewalls of integrated circuit die 70 are hydrophobic and may include fluorine, while other sidewalls of integrated circuit die 70 are hydrophilic and may not include substantially any fluorine (e.g., less than 5 wt % fluorine).

[0062] According to various embodiments, a segmentation process is performed to separate the individual semiconductor dies from the wafer. The segmentation process may include: patterning grooves in the scribe line area of ​​the wafer; and performing a surface treatment to provide hydrophobic sidewalls in the grooves. In some embodiments, the surface treatment is a fluorine-based treatment. The hydrophobic sidewalls can prevent a protective layer (e.g., a backside anti-reflective coating (BARC) layer, etc.) from being deposited in the grooves during a subsequent segmentation step. A planarization process may then be performed to remove the back side of the wafer, separating the semiconductor dies along the grooves.

[0063] The protective coating layer can protect the semiconductor die during the planarization process, and a cleaning process can be used to remove the protective layer after the planarization process. Because the protective layer is not deposited in the grooves, the cleaning process can more effectively remove the protective layer, thereby improving yield and reducing reconstructed wafer (RW) tool failures. For example, when the protective layer fills the grooves, the semiconductor die may not be successfully separated from the wafer, resulting in RW failures. In addition, the hydrophobic sidewalls prevent undesirable residues on the sidewalls of the integrated circuit die, which helps reduce manufacturing defects during the later packaging steps.

[0064] In some embodiments, the package includes: a first integrated circuit die; a second integrated circuit die located above and bonded to the first integrated circuit die; and a first insulating material located above and surrounding the second integrated circuit die. The first surface area of ​​the second integrated circuit die is hydrophobic, and the first integrated circuit die and the second integrated circuit die are bonded together using dielectric-to-dielectric bonding and metal-to-metal bonding. The first insulating material contacts the first surface area. In some embodiments, the first surface area of ​​the second integrated circuit die includes fluorine. In some embodiments, wherein the fluorine concentration of the first surface area is at least 5wt%. In some embodiments, the first surface area also includes carbon, oxygen, silicon, nitrogen, or a combination thereof. In some embodiments, the package also includes a dummy die bonded to the first integrated circuit die using dielectric-to-dielectric bonding, wherein the first insulating material surrounds the dummy die. In some embodiments, the second surface area of ​​the dummy die is hydrophobic and includes fluorine. In some embodiments, the third surface area of ​​the first integrated circuit die is hydrophobic and includes fluorine. In some embodiments, the package also includes a second insulating material surrounding the first integrated circuit die, wherein the second insulating material contacts the third surface area.

[0065] In some embodiments, the package includes: a first integrated circuit die; a first insulating material surrounding the first integrated circuit die; a second integrated circuit die located above the first integrated circuit die and bonded to the first integrated circuit die; and a second insulating material located above the first integrated circuit die and surrounding the second integrated circuit die. A first surface region of the second integrated circuit die includes fluorine, wherein the fluorine concentration of the first surface region is at least 5 wt%, and the first surface region is disposed at an interface between the second insulating material and the second integrated circuit die. In some embodiments, a second surface region of the first integrated circuit die includes fluorine, and the second surface region is disposed at an interface between the first insulating material and the first integrated circuit die. In some embodiments, the fluorine concentration of the second surface region is at least 5 wt%. In some embodiments, the package further includes a dummy die bonded to the first integrated circuit die and disposed at the same level as the second integrated circuit die, wherein a third surface region of the dummy die includes fluorine, wherein the fluorine concentration of the third surface region is at least 5 wt%, and wherein the third surface region is disposed at an interface between the second insulating material and the second integrated circuit die. In some embodiments, the second integrated circuit die is bonded to the first integrated circuit die using a dielectric-to-dielectric bond and a metal-to-metal bond.

[0066] In some embodiments, the method includes: etching a trench through the interconnect structure and extending into the semiconductor substrate, the trench being disposed in a scribe line region, the scribe line region being disposed between a first integrated circuit die and a second integrated circuit die; performing a surface treatment in the first trench to form a first surface region in a first sidewall of the first integrated circuit die, wherein the first surface region is hydrophobic; depositing a protective layer covering the trench over the first integrated circuit die; attaching a tape to a surface of the protective layer opposite to the first integrated circuit die; performing a backside planarization on a surface of the semiconductor substrate opposite to the tape; and after performing the backside planarization, removing the protective layer and the tape to completely separate the first integrated circuit die from the second integrated circuit die. In some embodiments, the surface treatment is a fluorine-based treatment. In some embodiments, the fluorine-based treatment is a wet cleaning process using a solution including fluorine or a fluorine-based plasma process. In some embodiments, the method further includes: bonding the first integrated circuit die to a third integrated circuit die; and depositing an insulating material around the first integrated circuit die, wherein the insulating material contacts the first surface region. In some embodiments, the third integrated circuit die includes a second surface region located in a second sidewall of the third integrated circuit die, wherein the second surface region is hydrophobic. In some embodiments, the method further comprises bonding the dummy die to the third integrated circuit die, wherein the dummy die comprises a third surface region in a third sidewall of the dummy die, wherein the third surface region is hydrophobic, and wherein the insulating material contacts the third surface region. In some embodiments, etching the trench comprises etching the trench through a patterned photoresist on a top surface of the interconnect structure, and wherein applying the surface treatment comprises applying the surface treatment while the patterned photoresist covers the top surface of the interconnect structure.

[0067] Some embodiments of the present application provide a package, comprising: a first integrated circuit die; a second integrated circuit die located above the first integrated circuit die and bonded to the first integrated circuit die, wherein a first surface area of ​​the second integrated circuit die is hydrophobic, and wherein the first integrated circuit die and the second integrated circuit die are bonded together using dielectric-to-dielectric bonding and metal-to-metal bonding; and a first insulating material located above the first integrated circuit die and surrounding the second integrated circuit die, wherein the first insulating material contacts the first surface area.

[0068] In some embodiments, the first surface region of the second integrated circuit die includes fluorine. In some embodiments, the fluorine concentration of the first surface region is at least 5 wt %. In some embodiments, the first surface region also includes carbon, oxygen, silicon, nitrogen, or a combination thereof. In some embodiments, the package also includes a dummy die bonded to the first integrated circuit die with a dielectric-to-dielectric bond, wherein the first insulating material surrounds the dummy die. In some embodiments, the second surface region of the dummy die is hydrophobic and includes fluorine. In some embodiments, the third surface region of the first integrated circuit die is hydrophobic and includes fluorine. In some embodiments, the package also includes a second insulating material surrounding the first integrated circuit die, wherein the second insulating material contacts the third surface region.

[0069] Other embodiments of the present application provide a package, comprising: a first integrated circuit die; a first insulating material surrounding the first integrated circuit die; a second integrated circuit die located above the first integrated circuit die and bonded to the first integrated circuit die, wherein a first surface area of ​​the second integrated circuit die comprises fluorine, wherein a fluorine concentration of the first surface area is at least 5 wt %; and a second insulating material located above the first integrated circuit die and surrounding the second integrated circuit die, wherein the first surface area is disposed at an interface between the second insulating material and the second integrated circuit die.

[0070] In some embodiments, a second surface region of the first integrated circuit die includes fluorine, wherein the second surface region is disposed at an interface between the first insulating material and the first integrated circuit die. In some embodiments, the fluorine concentration of the second surface region is at least 5 wt %. In some embodiments, the package further includes a dummy die bonded to the first integrated circuit die and disposed at the same level as the second integrated circuit die, wherein a third surface region of the dummy die includes fluorine, wherein the fluorine concentration of the third surface region is at least 5 wt %, and wherein the third surface region is disposed at an interface between the second insulating material and the second integrated circuit die. In some embodiments, the second integrated circuit die is bonded to the first integrated circuit die using a dielectric-to-dielectric bond and a metal-to-metal bond.

[0071] Still other embodiments of the present application provide a method for forming a package, comprising: etching a groove through an interconnect structure and extending into a semiconductor substrate, the groove being arranged in a scribe line area, the scribe line area being arranged between a first integrated circuit die and a second integrated circuit die; performing surface treatment in the groove to form a first surface area in a first side wall of the first integrated circuit die, wherein the first surface area is hydrophobic; depositing a protective layer covering the groove above the first integrated circuit die; attaching a tape to a surface of the protective layer opposite to the first integrated circuit die; performing backside planarization on a surface of the semiconductor substrate opposite to the tape; and after performing the backside planarization, removing the protective layer and the tape to completely separate the first integrated circuit die from the second integrated circuit die.

[0072] In some embodiments, the surface treatment is a fluorine-based treatment. In some embodiments, the fluorine-based treatment is a wet cleaning process using a solution including fluorine or a fluorine-based plasma process. In some embodiments, the method further comprises: bonding the first integrated circuit die to a third integrated circuit die; and depositing an insulating material around the first integrated circuit die, wherein the insulating material contacts the first surface area. In some embodiments, the third integrated circuit die includes a second surface area located in a second sidewall of the third integrated circuit die, wherein the second surface area is hydrophobic. In some embodiments, the method further comprises bonding a dummy die to the third integrated circuit die, wherein the dummy die includes a third surface area located in a third sidewall of the dummy die, wherein the third surface area is hydrophobic, and wherein the insulating material contacts the third surface area. In some embodiments, etching the trench comprises etching the trench through a patterned photoresist on a top surface of the interconnect structure, and wherein performing the surface treatment comprises performing the surface treatment while the patterned photoresist covers the top surface of the interconnect structure.

[0073] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A package comprising: a first integrated circuit die; a second integrated circuit die over and bonded to the first integrated circuit die, wherein a first surface area of ​​the second integrated circuit die is hydrophobic, and wherein the first integrated circuit die and the second integrated circuit die are bonded together using a dielectric-to-dielectric bond and a metal-to-metal bond; and A first insulating material is located over the first integrated circuit die and surrounds the second integrated circuit die, wherein the first insulating material contacts the first surface area.

2. The package according to claim 1, wherein: The first surface region of the second integrated circuit die includes fluorine.

3. The package according to claim 2, wherein: The fluorine concentration of the first surface region is at least 5 wt %.

4. The package according to claim 2, wherein: The first surface region further includes carbon, oxygen, silicon, nitrogen, or a combination thereof.

5. The package of claim 1 further comprising a dummy die bonded to the first integrated circuit die using a dielectric-to-dielectric bond, wherein The first insulating material surrounds the dummy die.

6. The package according to claim 5, wherein: The second surface region of the dummy die is hydrophobic and includes fluorine.

7. The package according to claim 1, wherein: A third surface region of the first integrated circuit die is hydrophobic and includes fluorine.

8. The package of claim 7, further comprising a second insulating material surrounding the first integrated circuit die, wherein: The second insulating material contacts the third surface region.

9. A package comprising: a first integrated circuit die; a first insulating material surrounding the first integrated circuit die; a second integrated circuit die over and bonded to the first integrated circuit die, wherein a first surface region of the second integrated circuit die comprises fluorine, wherein the first surface region has a fluorine concentration of at least 5 wt %; and A second insulating material is located over the first integrated circuit die and surrounds the second integrated circuit die, wherein the first surface region is disposed at an interface between the second insulating material and the second integrated circuit die.

10. A method of forming a package, comprising: etching a trench through the interconnect structure and extending into the semiconductor substrate, the trench being disposed in a scribe line region disposed between a first integrated circuit die and a second integrated circuit die; performing a surface treatment in the trench to form a first surface region in a first sidewall of the first integrated circuit die, wherein the first surface region is hydrophobic; depositing a protection layer over the first integrated circuit die covering the trench; attaching a tape to a surface of the protective layer opposite the first integrated circuit die; performing backside planarization on a surface of the semiconductor substrate opposite the strips; and After performing the backside planarization, the protective layer and the tape are removed to completely separate the first integrated circuit die from the second integrated circuit die.

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