Test Key test structure

Abstract

The invention provides a Test Key test structure, the structure comprises an active region, a contact hole and a gate structure, the active region comprises a plurality of first regions which extend in a first direction and are arranged at intervals and a plurality of second regions which extend in a second direction, and the first regions and the second regions are connected to enable the active region to be distributed in an S shape; the gate structures comprise a first edge gate structure, a second edge gate structure and a middle gate structure located between the first edge gate structure and the second edge gate structure; the contact holes are formed in the active region, a first middle contact hole and a second middle contact hole are formed between every two adjacent middle gate structures, a first end contact hole is formed in the side, away from the middle gate structures, of the first edge gate structure, and a second end contact hole is formed in the side, away from the middle gate structures, of the second edge gate structure. According to the invention, the problem that an existing test structure cannot reflect the real condition of the contact hole is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a Test Key test structure. Background Art

[0002] The yield loss of 28nmHV chips is mainly related to SRAM (static random access memory), most of which is caused by abnormal contact hole (CT) resistance in the SRAM area. The abnormal contact hole conditions include CT OPEN and NiSi abnormality (NiSi is formed in the contact hole). Moreover, WAT CT RC cannot reflect the actual situation of the SRAM contact hole, and the TEM slice shows that the spacing between the polysilicon in the SRAM area is small, which can easily lead to weak points in the process.

[0003] The Test Key test structure is a specific test structure used for wafer acceptance testing (WAT). It is usually placed in the scribe groove and tested by piercing the test probe into the test PAD. This test structure is designed to save chip design area and cost, ensure test consistency and hardware reuse. The existing test key for testing contact holes RC is mainly divided into two test structures: Via Chain and Kelvin (such as Figure 1 and Figure 2 However, neither of these two test structures has a definition of polysilicon Poly, and neither can reflect the actual situation of the contact holes in the SRAM area. Moreover, during the contact hole preparation process, process fluctuations can easily cause abnormal SRAM contact holes and normal WAT cannot be shipped. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a Test Key test structure to solve the problem that the existing test structure cannot reflect the actual situation of the contact hole.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a Test Key test structure, which includes: an active area, a contact hole and a gate structure.

[0006] The active area includes a plurality of first regions extending in a first direction and arranged at intervals in a second direction and a plurality of second regions extending in the second direction, wherein the first regions are connected to the second regions so that the active area is distributed in an S shape;

[0007] a plurality of the gate structures arranged at intervals, extending along the second direction and all having overlapping areas with the active area, wherein the gate structures include a first edge gate structure, a second edge gate structure and an intermediate gate structure located therebetween;

[0008] The contact hole is formed in the active area, and at least two intermediate contact holes arranged at intervals along the second direction are formed in each first area between two adjacent intermediate gate structures, which are respectively a first intermediate contact hole and a second intermediate contact hole. A first end contact hole is formed on a side of the first edge gate structure away from the intermediate gate structure, and a second end contact hole is formed on a side of the second edge gate structure away from the intermediate gate structure, wherein the first end contact hole is located at the starting end of the S-shaped active area, and the second end contact hole is located at the end of the S-shaped active area, and the first end contact hole, the first intermediate contact hole and the second end contact hole are connected in groups of two in sequence, and the second intermediate contact holes on the same first area are connected in groups of two.

[0009] Optionally, the first end contact hole, the second end contact hole, the first middle contact hole and the second middle contact hole are connected through a metal layer.

[0010] Optionally, when the first end contact hole, the first middle contact hole and the second end contact hole are connected in groups of two in sequence, they are connected in groups of two starting from the first end contact hole, from left to right, and then from right to left, until they are connected to the second end contact hole.

[0011] Optionally, a nickel silicide layer is formed at the bottom of the contact hole.

[0012] Optionally, the number of the gate structures is 5.

[0013] Optionally, the number of the first areas is 5, and the number of the second areas is 4.

[0014] Optionally, the gate structure includes polysilicon and sidewalls formed on both sides of the polysilicon.

[0015] Optionally, the Test Key test structure is formed in a test key area to reflect the contact hole resistance of the SRAM device area.

[0016] Optionally, applicable technology nodes include 28nm.

[0017] As described above, the Test Key test structure of the present invention adds a polysilicon layer in the test structure, so that the influence of polysilicon and sidewalls on the through hole is taken into account during the WAT test, thereby achieving the purpose of monitoring the contact hole resistance of the SRAM area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a schematic diagram of the existing CT Via Chain test structure.

[0019] Figure 2 Shown is a schematic diagram of the existing CT Kelvin test structure.

[0020] Figure 3 Shown is a schematic diagram of the Test Key test structure of the present invention. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0022] See also Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0023] like Figure 1 As shown, this embodiment provides a Test Key test structure, the structure includes: an active area, a contact hole and a gate structure,

[0024] The active area includes a plurality of first regions extending in a first direction and arranged at intervals in a second direction and a plurality of second regions extending in the second direction, wherein the first regions are connected to the second regions so that the active area is distributed in an S shape;

[0025] a plurality of the gate structures arranged at intervals, extending along the second direction and all having overlapping areas with the active area, wherein the gate structures include a first edge gate structure, a second edge gate structure and an intermediate gate structure located therebetween;

[0026] The contact hole is formed in the active area, and at least two intermediate contact holes arranged at intervals along the second direction are formed in each first area between two adjacent intermediate gate structures, which are respectively a first intermediate contact hole and a second intermediate contact hole. A first end contact hole is formed on a side of the first edge gate structure away from the intermediate gate structure, and a second end contact hole is formed on a side of the second edge gate structure away from the intermediate gate structure, wherein the first end contact hole is located at the starting end of the S-shaped active area, and the second end contact hole is located at the end of the S-shaped active area, and the first end contact hole, the first intermediate contact hole and the second end contact hole are connected in groups of two in sequence, and the second intermediate contact holes on the same first area are connected in groups of two.

[0027] like Figure 1 As shown, in this embodiment, the test structure can be formed simultaneously in the process of forming the NMOS device and the PMOS device in the SRAM device region. In this embodiment, X represents the first direction, and Y represents the second direction.

[0028] Specifically, the first end contact hole, the second end contact hole, the first middle contact hole, and the second middle contact hole are connected through a metal layer.

[0029] Specifically, when the first end contact hole, the first middle contact hole and the second end contact hole are connected in groups of two in sequence, they are connected in groups of two starting from the first end contact hole, from left to right, and then from right to left, until they are connected to the second end contact hole.

[0030] Specifically, a nickel silicide layer is formed at the bottom of the contact hole.

[0031] Specifically, the number of the gate structures is 5.

[0032] Specifically, the number of the first areas is 5, and the number of the second areas is 4.

[0033] Specifically, the gate structure includes polysilicon and sidewalls formed on both sides of the polysilicon.

[0034] Specifically, the Test Key test structure is formed in a test key region and is used to reflect the contact hole resistance of the SRAM device region.

[0035] Specifically, applicable technology nodes include 28nm.

[0036] In summary, the Test Key test structure of the present invention, by adding a polysilicon layer in the test structure, takes into account the influence of polysilicon and sidewalls on the through hole during WAT testing, thereby achieving the purpose of monitoring the contact hole resistance of the SRAM area. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A Test Key test structure, characterized in that: The structure comprises: an active area, a contact hole and a gate structure, wherein the active area comprises a plurality of first regions extending in a first direction and arranged at intervals in a second direction and a plurality of second regions extending in the second direction, wherein the first regions are connected to the second regions so that the active area is distributed in an S shape; a plurality of the gate structures arranged at intervals, extending along the second direction and all having overlapping areas with the active area, wherein the gate structures include a first edge gate structure, a second edge gate structure and an intermediate gate structure located therebetween; The contact hole is formed in the active area, and at least two intermediate contact holes arranged at intervals along the second direction are formed in each first area between two adjacent intermediate gate structures, which are respectively a first intermediate contact hole and a second intermediate contact hole. A first end contact hole is formed on a side of the first edge gate structure away from the intermediate gate structure, and a second end contact hole is formed on a side of the second edge gate structure away from the intermediate gate structure, wherein the first end contact hole is located at the starting end of the S-shaped active area, and the second end contact hole is located at the end of the S-shaped active area, and the first end contact hole, the first intermediate contact hole and the second end contact hole are connected in groups of two in sequence, and the second intermediate contact holes on the same first area are connected in groups of two.

2. The Test Key test structure according to claim 1, characterized in that: The first end contact hole, the second end contact hole, the first middle contact hole and the second middle contact hole are connected through a metal layer.

3. The Test Key test structure according to claim 1, characterized in that: When the first end contact holes, the first middle contact holes and the second end contact holes are connected in groups of two in sequence, they are connected in groups of two starting from the first end contact holes, from left to right, and then from right to left, until they are connected to the second end contact holes.

4. The Test Key test structure according to claim 1, characterized in that: A nickel silicide layer is formed at the bottom of the contact hole.

5. The Test Key test structure according to claim 1, characterized in that: The number of the gate structures is five.

6. The Test Key test structure according to claim 1, characterized in that: The number of the first regions is five, and the number of the second regions is four.

7. The Test Key test structure according to claim 1, characterized in that: The gate structure includes polysilicon and sidewalls formed on both sides of the polysilicon.

8. The Test Key test structure according to claim 1, characterized in that: The Test Key test structure is formed in the test key area and is used to reflect the contact hole resistance of the SRAM device area.

9. The Test Key test structure according to claim 1, characterized in that: Applicable technology nodes include 28nm.

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