A battery management circuit

Abstract

The present invention provides a battery management circuit, including a battery management chip, which includes a BAT pin, a VS2 pin, a VSS pin, an SRP pin, and an SRN pin. The battery management chip is separately connected to an external battery cell BAT1 and a sampling resistor, wherein the sampling resistor is connected to the negative electrode side of the battery cell BAT1 or to the positive electrode side of the battery cell BAT1; when the sampling resistor is connected to the negative electrode side of the battery cell BAT1, the VS2 pin is connected to the positive electrode of the battery cell BAT1, and the SRP pin is connected to the negative electrode of the battery cell BAT1, so as to achieve voltage sampling; when the sampling resistor is connected to the positive electrode side of the battery cell BAT1, the VS2 pin is connected to the negative electrode of the battery cell BAT1, and the SRN pin is connected to the positive electrode of the battery cell BAT1, so as to achieve voltage sampling; the battery management circuit has the beneficial effect of being flexibly applicable to applications in which the sampling resistor can be located on different sides of the battery cell.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a battery management circuit. Background Art

[0002] At present, the battery management circuit in the prior art is as follows Figure 1 As shown, the BMS chip includes a battery management chip, a charge control switch MN1, a discharge control switch MN2, a current sampling resistor R1, a battery cell BAT1, a capacitor C1, and a resistor R1. The SCL and SDA pins of the BMS chip are used for communication with other circuits, typically using the universal I2C interface protocol. Therefore, the existing circuit requires at least 11 pins. Using fewer pins allows for a smaller package, which reduces cost and occupies less printed circuit board area.

[0003] At the same time, in actual applications, the sampling resistor can be located on different sides of the battery cell; existing battery management chips are difficult to flexibly adapt to this and cannot automatically identify and adaptively process based on the corresponding connection method. Summary of the Invention

[0004] In view of the defects in the prior art, the present invention provides a battery management circuit that can be flexibly adapted to applications where sampling resistors can be located on different sides of a battery cell.

[0005] A battery management circuit includes a battery management chip, the battery management chip including a BAT pin, a VS2 pin, a VSS pin, an SRP pin, an SRN pin, a PACK pin, a CO pin, and a DO pin. The battery management chip is connected to an external battery cell BAT1 and a sampling resistor, and the sampling resistor is connected to the negative electrode side of the battery cell BAT1 or the positive electrode side of the battery cell BAT1.

[0006] When the sampling resistor is connected to the negative electrode side of the battery cell BAT1, the VS2 pin is connected to the positive electrode of the battery cell BAT1, and the SRP pin is connected to the negative electrode of the battery cell BAT1 to implement voltage sampling; the sampling resistor is connected between the SRP pin and the SRN pin to implement current sampling;

[0007] When the sampling resistor is connected to the positive electrode side of the battery cell BAT1, the VS2 pin is connected to the negative electrode of the battery cell BAT1, and the SRN pin is connected to the positive electrode of the battery cell BAT1 to achieve voltage sampling;

[0008] The sampling resistor is connected between the SRP pin and the SRN pin to perform current sampling.

[0009] As a specific preferred embodiment of the present application, the battery management chip includes an oscillator, a comparator, a voltage analog-to-digital converter, a current analog-to-digital converter, a controller, a first driver and a second driver;

[0010] The oscillator is used to generate a clock signal;

[0011] The comparator, voltage analog-to-digital converter, and current analog-to-digital converter are respectively connected to the oscillator and are controlled by the clock signal to operate;

[0012] The input end of the comparator is connected to the SRN pin and the VSS pin respectively, the output end of the comparator is connected to the voltage analog-to-digital converter through a set of control switches, and the output end of the comparator is further connected to the voltage analog-to-digital converter after passing through an inverter and another set of control switches;

[0013] The SRP pin is connected to one input terminal of the current analog-to-digital converter, and the other input terminal of the current analog-to-digital converter is connected to the SRN pin;

[0014] The VS2 pin is also connected to two sets of control switches respectively;

[0015] The output ends of the voltage analog-to-digital converter and the current analog-to-digital converter are respectively connected to the controller, the controller is connected to the CO pin through the first driver, and the controller is connected to the DO pin through the second driver.

[0016] As a specific preferred embodiment of the present application, the battery management chip further includes a short-circuit detection circuit, the input end of the short-circuit detection circuit is connected to the BAT pin and the PACK pin respectively, and the output end of the short-circuit detection circuit is connected to the controller.

[0017] As a specific preferred embodiment of the present application, the clock signal is at least two periodic signals with a duty cycle ranging from 0.5% to 10%, and when the clock signal is at a high level, the corresponding connected devices are controlled to operate.

[0018] As a specific preferred embodiment of the present application, the comparator is configured to determine whether the sampling resistor is connected to the negative electrode side or the positive electrode side of the battery cell BAT1 based on the voltage relationship between the SRN pin and the VSS pin.

[0019] As a specific preferred embodiment of the present application, determining whether the sampling resistor is connected to the negative electrode side or the positive electrode side of the battery cell BAT1 specifically includes:

[0020] If it is detected that the SRN voltage is greater than the reference voltage corresponding to the VSS pin, it is determined that the sampling resistor is connected to the positive side of the battery cell BAT1. At this time, the comparator output is a high level, and the set of control switches is controlled to be turned on, connecting SRN to the positive input terminal of the voltage analog-to-digital converter and connecting VS2 to the negative input terminal of the voltage analog-to-digital converter;

[0021] If it is detected that the SRN voltage is less than the reference voltage, it is determined that the sampling resistor is connected to the negative side of the battery cell BAT1. At this time, the comparator output is a low level, and the low level signal is converted into a high level through the inverter to control another set of control switches to turn on, connecting VS2 to the positive input terminal of the voltage analog-to-digital converter and connecting SRP to the negative input terminal of the voltage analog-to-digital converter.

[0022] As a specific preferred embodiment of the present application, the first driver and the second driver are both formed by an even number of inverters connected in series, and the driving capability of the latter inverter is greater than that of the previous inverter, and the driving capability is increased step by step.

[0023] As a specific preferred embodiment of the present application, the controller is further configured to calculate the internal resistance of the battery cell BAT1 based on the sampled voltage and current data, thereby estimating the health status of the battery cell.

[0024] As a specific preferred embodiment of the present application, the controller is further configured to calculate the remaining power of the battery cell based on the sampled voltage and current data.

[0025] As can be seen from the above technical solution, the battery management circuit provided by the present invention can automatically identify whether the sampling resistor is connected to the negative side or the positive side of the battery cell BAT1 according to the internal deployment of the battery management chip, and switch to the above-mentioned appropriate voltage sampling mode, thereby realizing flexible application of the sampling resistor being located on different sides of the battery cell. At the same time, since during sampling, whether it is connected to the negative side or the positive side of the battery cell BAT1, the voltage sampling and the current sampling share one pin, pin multiplexing is realized, and the number of pins used is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.

[0027] Figure 1 A circuit diagram of a battery management circuit is provided as background technology.

[0028] Figure 2A connection diagram of a sampling resistor connected to the negative electrode side of a battery cell BAT1 provided by an embodiment of the present invention.

[0029] Figure 3 A connection diagram of a sampling resistor connected to the positive electrode side of a battery cell BAT1 provided by an embodiment of the present invention.

[0030] Figure 4 A schematic diagram of the internal connections of a battery management chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following embodiments of the technical solution of the present invention are described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only examples and are not intended to limit the scope of protection of the present invention. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0032] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0033] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0034] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0035] It should be noted that, unless otherwise specified, the technical terms in this embodiment have the common meanings understood in the relevant technical field.

[0036] A battery management circuit provided by an embodiment of the present invention, see Figures 2 to 4, including a battery management chip, the battery management chip including a BAT pin, a VS2 pin, a VSS pin, a SRP pin, a SRN pin, a PACK pin, a CO pin and a DO pin, the battery management chip is connected to an external battery cell BAT1 and a sampling resistor, the sampling resistor is connected to the negative side of the battery cell BAT1 or to the positive side of the battery cell BAT1;

[0037] When the sampling resistor is connected to the negative electrode side of the battery cell BAT1, the VS2 pin is connected to the positive electrode of the battery cell BAT1, and the SRP pin is connected to the negative electrode of the battery cell BAT1 to implement voltage sampling; the sampling resistor is connected between the SRP pin and the SRN pin to implement current sampling;

[0038] When the sampling resistor is connected to the positive electrode side of the battery cell BAT1, the VS2 pin is connected to the negative electrode of the battery cell BAT1, and the SRN pin is connected to the positive electrode of the battery cell BAT1 to achieve voltage sampling;

[0039] The sampling resistor is connected between the SRP pin and the SRN pin to perform current sampling.

[0040] It should be noted that the battery management chip described in this embodiment is the BMS in the accompanying drawings; Figure 2 The current sampling resistor R1 is placed on the negative side of the battery cell BAT1; Figure 2 In the application, current sampling collects cell current information based on the voltage difference between SRP and SRN, and voltage sampling collects cell voltage information based on the voltage difference between VS2 and SRP;

[0041] Figure 3 The current sampling resistor R1 is placed on the positive side of the battery cell BAT1; Figure 3 In the application, current sampling collects cell current information based on the voltage difference between SRP and SRN, and voltage sampling collects cell voltage information based on the voltage difference between SRN and VS2.

[0042] In this embodiment, referring to Figure 4 The battery management chip includes an oscillator, a comparator, a voltage analog-to-digital converter, a current analog-to-digital converter, a controller, a first driver and a second driver;

[0043] The oscillator is used to generate a clock signal;

[0044] The comparator, voltage analog-to-digital converter, and current analog-to-digital converter are respectively connected to the oscillator and are controlled by the clock signal to operate;

[0045] The input end of the comparator is connected to the SRN pin and the VSS pin respectively, the output end of the comparator is connected to the voltage analog-to-digital converter through a set of control switches, and the output end of the comparator is further connected to the voltage analog-to-digital converter after passing through an inverter and another set of control switches;

[0046] The SRP pin is connected to one input terminal of the current analog-to-digital converter, and the other input terminal of the current analog-to-digital converter is connected to the SRN pin;

[0047] The VS2 pin is also connected to two sets of control switches respectively;

[0048] The output ends of the voltage analog-to-digital converter and the current analog-to-digital converter are respectively connected to the controller, the controller is connected to the CO pin through the first driver, and the controller is connected to the DO pin through the second driver.

[0049] It should be noted that, for the convenience of description, the oscillator is represented by OSC, the comparator is represented by com, the voltage analog-to-digital converter is represented by VADC, the current analog-to-digital converter is represented by IADC, the controller is represented by MCU, the short-circuit detection circuit is represented by SCD, the first driver is represented by driver1, the second driver is represented by driver2, one group of control switches is represented by S1 and S2, and the other group of control switches is represented by S3 and S4.

[0050] In this embodiment, the clock signal is at least two periodic signals with a duty cycle ranging from 0.5% to 10%. When the clock signal is at a high level, the corresponding connected devices are controlled to operate.

[0051] Specifically, the oscillator OSC generates clock signals CKV and CKI; wherein, when the CKV signal (for example, a periodic signal with a duty cycle of 2%, generally the duty cycle ranges from 0.5% to 10%, and a smaller duty cycle helps to save power consumption) is at a high level, the comparator com and VADC are controlled to work; when the CKI signal (for example, a periodic signal with a duty cycle of 2%, generally the duty cycle ranges from 0.5% to 10%, and a smaller duty cycle helps to save power consumption) is at a high level, the IADC is controlled to work; the corresponding connected devices here are the comparator, voltage analog-to-digital converter and current analog-to-digital converter.

[0052] Furthermore, the comparator is configured to determine whether the sampling resistor is connected to the negative electrode side or the positive electrode side of the battery cell BAT1 based on the voltage relationship between the SRN pin and the VSS pin, specifically including:

[0053] If it is detected that the SRN voltage is greater than the reference voltage corresponding to the VSS pin, it is determined that the sampling resistor is connected to the positive side of the battery cell BAT1. At this time, the comparator output is a high level, and the set of control switches is controlled to be turned on, connecting SRN to the positive input terminal of the voltage analog-to-digital converter and connecting VS2 to the negative input terminal of the voltage analog-to-digital converter;

[0054] If it is detected that the SRN voltage is less than the reference voltage, it is determined that the sampling resistor is connected to the negative side of the battery cell BAT1. At this time, the comparator output is a low level, and the low level signal is converted into a high level through the inverter to control another set of control switches to turn on, connecting VS2 to the positive input terminal of the voltage analog-to-digital converter and connecting SRP to the negative input terminal of the voltage analog-to-digital converter.

[0055] That is, when the CKV signal is high, the comparator com works. If it detects that the SRN voltage is greater than the reference voltage V1 (which can be between 0.2V and 2V), the sample is judged to be Figure 3 In the application mode (i.e., the current sampling resistor is connected to the high side), the comparator output ModeH is high, and switches S1 and S2 are turned on, connecting SRN to VSP (the positive input of VADC) and VS2 to VSN (the negative input of VADC). This allows voltage sampling and current sampling to reuse the SRN pin.

[0056] If the voltage of SRN is less than the reference voltage V1, the sampling is judged to be Figure 2 Application mode (i.e. the current sampling resistor is connected to the low side), at this time the comparator output ModeH is low level, the signal ModeL after the inverter inv1 is high level, the control switches S3 and S4 are turned on, VS2 is connected to VSP (the positive input terminal of VADC), and SRP is connected to VSN (the negative input terminal of VADC); the voltage sampling and current sampling are multiplexed on the SRP pin; it can be seen that whether it is Figure 2 Application method, or Figure 3 In the application mode, voltage sampling and current sampling share the same pin.

[0057] In this embodiment, the controller also senses the cell voltage based on the VADC data. When it is determined that the cell voltage is greater than a preset charge overvoltage threshold (for example, 4.5V), it is determined that a charge overvoltage state occurs, the output CO is low, and charging is prohibited; when it is determined that the cell voltage is less than a preset discharge overvoltage threshold (for example, 2.3V), it is determined that a discharge overvoltage state occurs, the output DO is low, and discharging is prohibited.

[0058] In this embodiment, the first driver and the second driver are both formed by an even number of inverters connected in series, and the driving capability of the subsequent inverter is greater than that of the previous inverter, and the driving capability is increased step by step to achieve stronger driving capability.

[0059] The controller also senses the cell current based on the IADC data. When it is determined that the cell current is greater than the discharge overcurrent threshold (for example, 5A for discharge), it is determined that a discharge overcurrent state has occurred, the output DO is low, and discharge is prohibited. When it is determined that the cell charging current is greater than the charging overcurrent threshold (for example, 5A for charge), it is determined that a charging overcurrent state has occurred, the output CO is low, and charging is prohibited.

[0060] The above solution can automatically identify whether the sampling resistor is connected to the negative or positive side of the battery cell BAT1 based on the internal deployment of the battery management chip, and switch to the above-mentioned appropriate voltage sampling method, thereby flexibly adapting to applications where the sampling resistor can be located on different sides of the battery cell. At the same time, since during sampling, whether the sampling resistor is connected to the negative or positive side of the battery cell BAT1, voltage sampling and current sampling share the same pin, pin reuse is achieved, and the number of pins used is reduced.

[0061] In another embodiment, based on the above technical solution, the battery management chip further includes a short-circuit detection circuit, the input end of the short-circuit detection circuit is connected to the BAT pin and the PACK pin respectively, and the output end of the short-circuit detection circuit is connected to the controller.

[0062] In this embodiment, the controller is further configured to calculate the internal resistance of the battery cell BAT1 based on the sampled voltage and current data, thereby estimating the health status of the battery cell;

[0063] For example, by adding an additional discharge current Ia, the battery voltage before the current increase is measured as V1, and the battery voltage after the current increase is measured as V2. The battery internal resistance can be calculated using (V1-V2) / Ia. For example, a normal battery's initial internal resistance is 20 milliohms. With aging, the value increases. If it increases to 60 milliohms, it can be determined that the battery's health has declined.

[0064] The controller is further configured to calculate the remaining capacity of the battery cell based on the sampled voltage and current data.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

Claims

1. A battery management circuit, comprising a battery management chip, the battery management chip including a BAT pin, a VS2 pin, a VSS pin, an SRP pin, an SRN pin, a PACK pin, a CO pin, and a DO pin, the battery management chip being connected to an external battery cell BAT1 and a sampling resistor, characterized in that: The sampling resistor is connected to the negative electrode side of the battery cell BAT1 or to the positive electrode side of the battery cell BAT1; When the sampling resistor is connected to the negative electrode side of the battery cell BAT1, the VS2 pin is connected to the positive electrode of the battery cell BAT1, and the SRP pin is connected to the negative electrode of the battery cell BAT1 to implement voltage sampling; the sampling resistor is connected between the SRP pin and the SRN pin to implement current sampling; When the sampling resistor is connected to the positive electrode side of the battery cell BAT1, the VS2 pin is connected to the negative electrode of the battery cell BAT1, and the SRN pin is connected to the positive electrode of the battery cell BAT1 to achieve voltage sampling; The sampling resistor is connected between the SRP pin and the SRN pin to perform current sampling; The battery management chip includes an oscillator, a comparator, a voltage analog-to-digital converter, a current analog-to-digital converter, a controller, a first driver and a second driver; The oscillator is used to generate a clock signal; The comparator, voltage analog-to-digital converter, and current analog-to-digital converter are respectively connected to the oscillator and are controlled by the clock signal to operate; The input end of the comparator is connected to the SRN pin and the VSS pin respectively, the output end of the comparator is connected to the voltage analog-to-digital converter through a set of control switches, and the output end of the comparator is further connected to the voltage analog-to-digital converter after passing through an inverter and another set of control switches; The SRP pin is connected to one input terminal of the current analog-to-digital converter, and the other input terminal of the current analog-to-digital converter is connected to the SRN pin; The VS2 pin is also connected to two sets of control switches respectively; The output ends of the voltage analog-to-digital converter and the current analog-to-digital converter are respectively connected to the controller, the controller is connected to the CO pin through the first driver, and the controller is connected to the DO pin through the second driver.

2. A battery management circuit according to claim 1, characterized in that: The battery management chip further includes a short-circuit detection circuit, the input end of the short-circuit detection circuit is connected to the BAT pin and the PACK pin respectively, and the output end of the short-circuit detection circuit is connected to the controller.

3. A battery management circuit according to claim 2, characterized in that: The clock signal is at least two periodic signals with a duty cycle ranging from 0.5% to 10%. When the clock signal is at a high level, the corresponding connected devices are controlled to operate.

4. A battery management circuit according to claim 2, characterized in that: The comparator is configured to determine whether the sampling resistor is connected to the negative electrode side or the positive electrode side of the battery cell BAT1 based on a voltage relationship between the SRN pin and the VSS pin.

5. A battery management circuit according to claim 4, characterized in that: The determining whether the sampling resistor is connected to the negative electrode side or the positive electrode side of the battery cell BAT1 specifically includes: If it is detected that the SRN voltage is greater than the reference voltage corresponding to the VSS pin, it is determined that the sampling resistor is connected to the positive side of the battery cell BAT1. At this time, the comparator output is a high level, and the set of control switches is controlled to be turned on, connecting SRN to the positive input terminal of the voltage analog-to-digital converter and connecting VS2 to the negative input terminal of the voltage analog-to-digital converter; If it is detected that the SRN voltage is less than the reference voltage, it is determined that the sampling resistor is connected to the negative side of the battery cell BAT1. At this time, the comparator output is a low level, and the low level signal is converted into a high level through the inverter to control another set of control switches to turn on, connecting VS2 to the positive input terminal of the voltage analog-to-digital converter and connecting SRP to the negative input terminal of the voltage analog-to-digital converter.

6. The battery management circuit according to claim 4, characterized in that: The first driver and the second driver are both formed by an even number of inverters connected in series, and the driving capability of the subsequent inverter is greater than that of the previous inverter, and the driving capability increases step by step.

7. A battery management circuit according to claim 6, characterized in that: The controller is further configured to calculate the internal resistance of the battery cell BAT1 based on the sampled voltage and current data, thereby estimating the health status of the battery cell.

8. The battery management circuit according to claim 7, characterized in that: The controller is further configured to calculate the remaining capacity of the battery cell based on the sampled voltage and current data.

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