Integrated modulation method and system for parallel ANPC three-level inverter

Abstract

The invention discloses an integrated modulation method and system for a parallel ANPC three-level inverter, and the method comprises the steps: carrying out the modeling of a common-mode voltage of a parallel ANPC three-level inverter system based on a five-level vector space, and selecting a parallel voltage vector which is zero in the common-mode voltage as a system voltage vector of a synthetic reference voltage vector; re-dividing six sectors through the system voltage vector, and judging the action time of the system voltage vector and a parallel system switch sequence according to the sectors; converting the five-level switch sequence generated by the parallel system into a three-level switch sequence and sending the three-level switch sequence to each ANPC three-level inverter; the redundant switching states in the ANPC three-level inverter are alternately used in two switching periods; according to the invention, the system voltage vector is distributed to the inverter, so that the system common-mode voltage is zero and the output current ripple effect is reduced; a redundant O state selection mode of the ANPC inverter is optimized, different O states are alternately used in a modulation period, and the effect of balanced distribution of switching loss is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of three-level converter control, and in particular to an integrated modulation method and system for parallel ANPC three-level inverters. Background Art

[0002] Compared with traditional two-level inverters, three-level inverters have been widely used in many industrial applications due to their lower voltage stress and smaller output current ripple. As power capacity continues to increase, the parallel application of three-level inverters provides a reasonable way to meet the requirements of larger current capacity, higher power levels and modularity in high-power applications. For pulse width modulation (PWM) converters, common mode voltage (CMV) is an inherent problem, which may cause winding insulation failure, current distortion, safety-related problems and electromagnetic interference. Therefore, it is necessary to take measures to suppress or eliminate CMV.

[0003] There are two main common-mode voltage suppression strategies: hardware and software. The hardware method mainly changes the circuit topology or adds passive components such as common-mode inductors, which has a series of problems such as high cost, large size, and increased weight. Compared with the system hardware modification and high cost of the hardware method, the software method mainly modifies the modulation strategy of the inverter to reduce or eliminate the common-mode voltage generated by modulation.

[0004] Software methods can be generally divided into two categories: common-mode voltage suppression and common-mode voltage elimination. From the perspective of space vectors, the basic idea of ​​these solutions is to select basic vectors with smaller (or zero) common-mode voltages as much as possible to synthesize voltage reference vectors. Compared with traditional center-symmetric space vector (CSV) modulation, these methods can reduce the amplitude of the common-mode voltage from one-third to one-sixth of the bus voltage. In applications with very strict requirements on common-mode voltage, zero common-mode voltage modulation methods are required. However, since all common-mode voltage suppression or elimination methods only use a portion of the basic vectors, the output current ripple is large. Summary of the invention

[0005] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0006] In view of the above existing problems, the present invention is proposed. Therefore, the present invention provides an integrated modulation method for parallel ANPC three-level inverters, which is used to solve the practical problem that the existing common-mode voltage elimination method is applied to the parallel ANPC inverter system with large output current harmonics and uneven distribution of ANPC inverter switching device losses.

[0007] In order to solve the above technical problems, the present invention provides the following technical solution, an integrated modulation method for parallel ANPC three-level inverters, comprising:

[0008] Based on the five-level vector space, the common-mode voltage of the parallel ANPC three-level inverter system is modeled, and the parallel voltage vector with zero in the common-mode voltage is selected as the system voltage vector of the synthetic reference voltage vector;

[0009] Taking the point where the system voltage vector at the center of the five-level vector space is located as the center of the circle, the vector space is divided into a number of new sectors; according to the amplitude and angle of the space where the reference voltage vector is located, the sector and area where the reference voltage vector is located are determined; through the area where the reference voltage vector is located, the action time of the corresponding system voltage vector is determined by using the volt-second balance principle;

[0010] With two switching cycles as one modulation cycle, the five-level switching sequence generated by the parallel system is converted into a three-level switching sequence and sent to each ANPC three-level inverter; two groups of the three-level switching sequences are used for modulation respectively, and the redundant switching states in the ANPC three-level inverter are used alternately in the two switching cycles to achieve uniform distribution of switching losses.

[0011] As a preferred solution of the integrated modulation method for parallel ANPC three-level inverters according to the present invention, modeling the common mode voltage of the parallel ANPC three-level inverter system includes:

[0012]

[0013] Among them, V ON is the common mode voltage of the parallel ANPC three-level inverter system, S x1 and S x2 Respectively represent the switching states of the x-phase bridge arms in the parallel ANPC three-level inverter 1 and inverter 2; V dc Refers to the DC bus voltage;

[0014] If the sum of the three-phase switch states of a parallel voltage vector is equal to 6, then the common mode voltage corresponding to the vector is zero, and the selected system voltage vector corresponds to the basic vector of the five-level vector space.

[0015] As a preferred solution of the integrated modulation method for parallel ANPC three-level inverters described in the present invention, the vector space is divided into several new sectors with the point where the system voltage vector at the center of the five-level vector space is located as the center of the circle, including:

[0016] Taking the system voltage vector V7, V 12 constitute the first sector; V7, V8 constitute the second sector; V8, V9 constitute the third sector; V9, V 10 Constitute the fourth sector; V 10 , V 11 Constitute the fifth sector; V 11 , V 12 Constitute the sixth sector.

[0017] As a preferred solution of the integrated modulation method for parallel ANPC three-level inverters described in the present invention, the sector and region where the reference voltage vector is located are determined according to the amplitude and angle of the space where the reference voltage vector is located, including:

[0018] The α and β axis components of the reference voltage vector voltage are represented as V α , V β , and set corresponding constraints, as shown below:

[0019] Region 1: V α ≤0.25;

[0020] Area 2: V α >0.25,

[0021] Region 3: V α >0.25,

[0022] Area 4: V α >0.25,

[0023] As a preferred solution of the integrated modulation method for parallel ANPC three-level inverters described in the present invention, wherein: by using the region where the reference voltage vector is located and utilizing the volt-second balance principle, determining the action time of the corresponding system voltage vector comprises:

[0024] The action time formula of the system voltage vector is:

[0025] T a V a +T b V b +T c V c =T s V ref

[0026] T s =T a +T b +T c

[0027] Among them, V ref is the reference voltage vector, V a 、V b 、V c are the three system voltage vectors in the area where the reference voltage vector is located, T b 、T b 、T c is the action time of the three system voltage vectors in the area where the reference voltage vector is located;

[0028] A five-stage switching sequence of the parallel system is determined according to three system voltage vectors in the area where the reference voltage vector is located.

[0029] As a preferred solution of the integrated modulation method for parallel ANPC three-level inverters described in the present invention, wherein: taking two switching cycles as one modulation cycle, converting the five-level switching sequence generated by the parallel system into a three-level switching sequence and sending it to each ANPC three-level inverter, comprising:

[0030] The conversion needs to ensure that the vectors in the three-level switching sequence are all neutral vectors or zero vectors, and within a switching cycle, the inverter switching state allocation method of the front and rear half cycles is reversed, and at the same time, the switching sequences of the two inverters in the front and rear two switching cycles are swapped.

[0031] As a preferred solution of the integrated modulation method for parallel ANPC three-level inverters of the present invention, wherein: two groups of the three-level switch sequences are used for modulation respectively, and redundant switch states in the ANPC three-level inverter are used alternately in the two switching cycles to achieve uniform distribution of switching losses, including:

[0032] When the output is in the O state, the redundant switch state of ANPC is used to output the O state in the positive half cycle of the AC power. 1+ , O 2+ Use alternately, use O in the negative half cycle of output AC 1- , O 2- Use alternately.

[0033] An integrated modulation system for parallel ANPC three-level inverters, comprising:

[0034] The common-mode voltage modeling module models the common-mode voltage of the parallel ANPC three-level inverter system based on the five-level vector space, and selects the parallel voltage vector with zero in the common-mode voltage as the system voltage vector of the synthetic reference voltage vector;

[0035] The voltage vector processing module divides the vector space into a number of new sectors with the point where the system voltage vector is located at the center of the five-level vector space as the center of the circle; determines the sector and area where the reference voltage vector is located according to the amplitude and angle of the space where the reference voltage vector is located; and determines the action time of the corresponding system voltage vector by using the volt-second balance principle through the area where the reference voltage vector is located;

[0036] The switch modulation module converts the five-level switch sequence generated by the parallel system into a three-level switch sequence and sends it to each ANPC three-level inverter, with two switching cycles as one modulation cycle; two groups of the three-level switch sequences are used for modulation respectively, and the redundant switch states in the ANPC three-level inverter are used alternately in the two switching cycles to achieve uniform distribution of switching losses.

[0037] A computer device comprises a memory and a processor, wherein the memory stores a computer program, wherein: when the processor executes the computer program, any step of the above method is implemented.

[0038] A computer-readable storage medium is provided, on which a computer program is stored, wherein: when the computer program is executed by a processor, any step of the above method is implemented.

[0039] Compared with the prior art, the beneficial effects of the invention are as follows: the present invention selects a parallel voltage vector with zero common-mode voltage as a system voltage vector of a synthetic reference voltage vector for a parallel ANPC three-level inverter system based on a five-level vector space, and then distributes the processed system voltage vector to the inverter, thereby achieving an effect of zero system common-mode voltage and reducing output current ripple; at the same time, the redundant O state selection method of the ANPC inverter is optimized, and different O states are used alternately within a modulation period to achieve an effect of balanced distribution of switching losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0041] Figure 1 The overall flow chart of an integrated modulation method for parallel ANPC three-level inverters according to an embodiment of the present invention;

[0042] Figure 2A topological structure diagram of a parallel ANPC three-level inverter system of an integrated modulation method for parallel ANPC three-level inverters according to an embodiment of the present invention;

[0043] Figure 3 A five-level zero common mode voltage vector space of an integrated modulation method for parallel ANPC three-level inverters according to an embodiment of the present invention;

[0044] Figure 4 A switching sequence of a first sector and a second region of a parallel ANPC three-level inverter of an integrated modulation method for parallel ANPC three-level inverters according to an embodiment of the present invention;

[0045] Figure 5 A common-mode voltage waveform diagram of a vector modulation algorithm of an integrated modulation method for parallel ANPC three-level inverters according to an embodiment of the present invention;

[0046] Figure 6 This is a line voltage waveform diagram of a vector modulation algorithm of an integrated modulation method for parallel ANPC three-level inverters according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0048] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0049] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0050] The present invention is described in detail with reference to schematic diagrams. When describing the embodiments of the present invention, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0051] At the same time, in the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "upper, lower, inner and outer" are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present invention. In addition, the terms "first, second or third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0052] In the present invention, unless otherwise clearly specified and limited, the terms "install, connect, connect" should be understood in a broad sense, for example: it can be a fixed connection, a detachable connection or an integral connection; it can also be a mechanical connection, an electrical connection or a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] Example 1

[0054] Reference Figures 1 to 4 , which is the first embodiment of the present invention, provides an integrated modulation method for parallel ANPC three-level inverters, comprising:

[0055] S1. Based on the five-level vector space, the common-mode voltage of the parallel ANPC three-level inverter system is modeled, and the parallel voltage vector with zero in the common-mode voltage is selected as the system voltage vector of the synthetic reference voltage vector;

[0056] It should be noted that the topology of the parallel ANPC three-level inverter system is as follows: Figure 2 As shown; the system connects two three-level ANPC inverters in parallel through a filter inductor; the positive ends of all bridge arms of the two ANPC three-level inverters are connected to the positive end of the DC bus, the negative ends of all bridge arms are connected to the negative end of the DC bus, and the midpoints of the clamping diodes of all bridge arms are connected to the neutral points of their respective DC sides; the parameters involved in the parallel ANPC three-level inverters are shown in Table 1;

[0057] Table 1

[0058] DC voltage 400V Grid voltage 190V Power frequency 50Hz Bus Capacitor 1120uF Bridge arm inductance 4mH Filter Inductor 3mH Switching frequency 2400Hz

[0059] Furthermore, the output voltage of each phase of the ANPC three-level inverter 1 and the inverter 2 can be expressed as:

[0060]

[0061] Among them, V x1N and V x2N They refer to the output voltage of phase x in ANPC three-level inverter 1 and inverter 2 respectively; S x1 and S x2 They refer to the switching states of the x-phase bridge arms in ANPC three-level inverter 1 and inverter 2 respectively; V dc Refers to the DC bus voltage;

[0062] Furthermore, the AC side output phase voltage formula at the reference point is:

[0063]

[0064] The common-mode voltage of the parallel ANPC three-level inverter is defined as the voltage difference between the neutral point of the AC (load or grid) and the midpoint of the DC bus. The formula is:

[0065]

[0066] Substituting into formula (3), we can obtain the common-mode voltage model of the parallel ANPC three-level inverter system:

[0067]

[0068] It should be noted that when the sum of the switching states of the two inverters is 6, the corresponding system common mode voltage is 0; the part of the parallel vector corresponding to the common mode voltage of zero is marked with a black dot in the five-level vector space as the system voltage vector, such as Figure 3 As shown; when modulating the parallel ANPC three-level inverter, the common mode voltage of the parallel ANPC three-level inverter system can be made zero by selecting a suitable vector from the black dot vector in the five-level vector space;

[0069] S2. Taking the point where the system voltage vector at the center of the five-level vector space is located as the center of the circle, the vector space is divided into several new sectors; according to the amplitude and angle of the space where the reference voltage vector is located, the sector and area where the reference voltage vector is located are determined; through the area where the reference voltage vector is located, the action time of the corresponding system voltage vector is determined by using the volt-second balance principle;

[0070] Furthermore, with the system voltage vector V7, V 12 constitute the first sector; V7, V8 constitute the second sector; V8, V9 constitute the third sector; V9, V 10 Constitute the fourth sector; V 10, V 11 Constitute the fifth sector; V 11 , V 12 It constitutes the sixth sector;

[0071] It should be noted that in each sector, an equilateral triangle formed by three adjacent system voltage vectors is taken as a small area, and a sector is divided into four small areas;

[0072] Furthermore, the α and β axis components of the reference voltage vector voltage are represented as V α , V β , and taking the first sector as an example, set the corresponding constraints as follows:

[0073] Region 1: V α ≤0.25;

[0074] Area 2: V α >0.25,

[0075] Region 3: V α >0.25,

[0076] Area 4: V α >0.25,

[0077] Furthermore, the α and β axis components are expressed as V α , V β , the formula is:

[0078] V α =V ref cosθ (5)

[0079] V β =V ref sinθ (6)

[0080] Among them, V ref is the reference voltage vector, V α is the component of the reference voltage vector decomposed into the α-axis, V β is the component of the reference voltage vector decomposed into the β axis;

[0081] Furthermore, the volt-second balance principle is used to determine the action time of the corresponding system voltage vector, and the formula is expressed as:

[0082] T a V a +T b V b +T c V c =T s V ref(7)

[0083] T s =T a +T b +T c (8)

[0084] Among them, V ref is the reference voltage vector, V a 、V b 、V c are the three system voltage vectors in the area where the reference voltage vector is located, T a 、T b 、T c is the action time of the three system voltage vectors in the area where the reference voltage vector is located;

[0085] Furthermore, by decomposing formula (7) and formula (8) to the α and β axes, we can obtain:

[0086]

[0087] Among them, V aα 、V bα 、V cα They are the synthetic reference vectors V ref The projections of the three system vectors on the α axis; V aβ 、V bβ 、V cβ They are the synthetic reference vectors V ref The projections of the three system vectors on the β axis;

[0088] It should be noted that, taking the first sector as an example, the system vector action time of its four small areas refers to Table 2;

[0089] Table 2

[0090]

[0091] Where k represents the modulation ratio,

[0092] Further, a five-stage switching sequence of the parallel system is determined based on the three system voltage vectors in the region where the reference voltage vector is located;

[0093] It should be noted that, since there are only three basic vectors in each region that can be used to synthesize the reference voltage vector, only a five-stage switching sequence can be used;

[0094] S3, with two switching cycles as one modulation cycle, convert the five-level switching sequence generated by the parallel system into a three-level switching sequence and send it to each ANPC three-level inverter; use two groups of three-level switching sequences for modulation respectively, and use the redundant switching states in the ANPC three-level inverter alternately in two switching cycles to achieve uniform distribution of switching losses;

[0095] Further, the five-level switching sequence generated by the parallel system is converted into a three-level switching sequence and sent to each ANPC three-level inverter;

[0096] It should be noted that the conversion needs to ensure that the vectors in the three-level switching sequence are all neutral vectors or zero vectors (111), and within a switching cycle, the inverter switching state allocation method of the front and rear half cycles is reversed, and at the same time, the switching sequences of the two inverters in the front and rear two switching cycles are swapped;

[0097] The switching sequence of the parallel ANPC three-level system and the switching sequence of the two inverters (first sector, first region) are shown in Table 3; the switching sequence of the first sector, second region of the parallel ANPC three-level inverter is shown in Table 3. Figure 4 As shown;

[0098] Table 3

[0099] 11 5L 222 312 321 321 312 222 Inv1 111 201 210 111 111 111 Inv2 111 111 111 210 201 111

[0100] Furthermore, two sets of three-level switch sequences are used for modulation respectively. When the output is in the O state, the ANPC redundant switch state is used to use the O state in the positive half cycle of the output AC power. 1+ , O 2+ Use alternately, use O in the negative half cycle of output AC 1- , O 2- Used alternately; among them, O 1+ , O 2+ , O 1- , O 2- The representation of is shown in Table 4;

[0101] Table 4

[0102] O <![CDATA[S x1 ]]> <![CDATA[S x2 ]]> <![CDATA[S x3 ]]> <![CDATA[S x4 ]]> <![CDATA[S x5 ]]> <![CDATA[S x6 ]]> <![CDATA[O 1+ ]]> 0 1 0 0 1 1 <![CDATA[O 2+ ]]> 1 0 1 0 0 1 <![CDATA[O 1- ]]> 0 0 1 0 1 1 <![CDATA[O 2- ]]> 0 1 0 1 1 0

[0103] Furthermore, this embodiment also provides an integrated modulation system for parallel ANPC three-level inverters, including:

[0104] The common-mode voltage modeling module models the common-mode voltage of the parallel ANPC three-level inverter system based on the five-level vector space, and selects the parallel voltage vector with zero in the common-mode voltage as the system voltage vector of the synthetic reference voltage vector;

[0105] The voltage vector processing module divides the vector space into several new sectors with the point where the system voltage vector is located at the center of the five-level vector space as the center of the circle; determines the sector and area where the reference voltage vector is located according to the amplitude and angle of the space where the reference voltage vector is located; determines the action time of the corresponding system voltage vector by using the volt-second balance principle through the area where the reference voltage vector is located;

[0106] The switch modulation module converts the five-level switch sequence generated by the parallel system into a three-level switch sequence and sends it to each ANPC three-level inverter, with two switching cycles as one modulation cycle. Two groups of three-level switch sequences are used for modulation respectively, and the redundant switch states in the ANPC three-level inverter are used alternately in two switching cycles to achieve uniform distribution of switching losses.

[0107] This embodiment further provides a computer device, which is applicable to the case of an integrated modulation method for parallel ANPC three-level inverters, including:

[0108] A memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute computer executable instructions to implement the integrated modulation method for parallel ANPC three-level inverters proposed in the above embodiment.

[0109] The computer device may be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device may be a touch layer covering the display screen, or a key, trackball or touchpad provided on the housing of the computer device, or an external keyboard, touchpad or mouse, etc.

[0110] This embodiment further provides a storage medium on which a computer program is stored. When the program is executed by a processor, the integrated modulation method for parallel ANPC three-level inverters proposed in the above embodiment is implemented.

[0111] The storage medium proposed in this embodiment and the data storage method proposed in the above embodiment belong to the same inventive concept. The technical details not fully described in this embodiment can be found in the above embodiment, and this embodiment has the same beneficial effects as the above embodiment.

[0112] Example 2

[0113] Reference Figure 5 and Figure 6 , which is a second embodiment of the present invention, provides an integrated modulation method for parallel ANPC three-level inverters, comprising:

[0114] By combining the vector processing with the control of the ANPC three-level inverter, efficient energy conversion and optimized output waveform are obtained by experimental simulation. Figure 5 shown in Figure 5 On this basis, the purpose of outputting the common-mode voltage of the parallel ANPC three-level inverter to zero can be achieved;

[0115] Depend on Figure 6 It can be seen that the parallel output line voltage of the traditional modulation method is 5 levels; when the five-level modulation processing proposed by the present invention is adopted, the parallel output line voltage is 9 levels; the waveform can effectively reduce the harmonic content of the parallel inverter output while ensuring zero common mode voltage.

[0116] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. An integrated modulation method for parallel ANPC three-level inverters, characterized in that: include: Based on the five-level vector space, the common-mode voltage of the parallel ANPC three-level inverter system is modeled, and the parallel voltage vector with zero in the common-mode voltage is selected as the system voltage vector of the synthetic reference voltage vector; Taking the point where the system voltage vector at the center of the five-level vector space is located as the center of the circle, the vector space is divided into a number of new sectors; according to the amplitude and angle of the space where the reference voltage vector is located, the sector and area where the reference voltage vector is located are determined; through the area where the reference voltage vector is located, the action time of the corresponding system voltage vector is determined by using the volt-second balance principle; With two switching cycles as one modulation cycle, the five-level switching sequence generated by the parallel system is converted into a three-level switching sequence and sent to each ANPC three-level inverter; two groups of the three-level switching sequences are used for modulation respectively, and the redundant switching states in the ANPC three-level inverter are used alternately in the two switching cycles to achieve uniform distribution of switching losses.

2. The integrated modulation method for parallel ANPC three-level inverters according to claim 1, characterized in that: Modeling of the common-mode voltage of a parallel ANPC three-level inverter system, including: Among them, V ON is the common mode voltage of the parallel ANPC three-level inverter system, S x1 and S x2 Respectively represent the switching states of the x-phase bridge arms in the parallel ANPC three-level inverter 1 and inverter 2; V dc Refers to the DC bus voltage; If the sum of the three-phase switch states of a parallel voltage vector is equal to 6, then the common mode voltage corresponding to the vector is zero, and the selected system voltage vector corresponds to the basic vector of the five-level vector space.

3. The integrated modulation method for parallel ANPC three-level inverters according to claim 2, characterized in that: Taking the point where the system voltage vector at the center of the five-level vector space is located as the center of the circle, the vector space is divided into several new sectors, including: Taking the system voltage vector V7, V 12 constitute the first sector; V7, V8 constitute the second sector; V8, V9 constitute the third sector; V9, V 10 Constitute the fourth sector; V 10 , V 11 Constitute the fifth sector; V 11 , V 12 Constitute the sixth sector.

4. The integrated modulation method for parallel ANPC three-level inverters according to claim 3, characterized in that: According to the amplitude and angle of the space where the reference voltage vector is located, the sector and area where the reference voltage vector is located are determined, including: The α and β axis components of the reference voltage vector voltage are represented as V α , V β , and set corresponding constraints, as shown below: Region 1: V α ≤0.25; Area 2: V α >0.25, Region 3: V α >0.25, Region 4: V α >0.25, 5. The integrated modulation method for parallel ANPC three-level inverters according to claim 3 or 4, characterized in that: By using the region where the reference voltage vector is located and utilizing the volt-second balance principle, the action time of the corresponding system voltage vector is determined, including: The action time formula of the system voltage vector is: T a V α +T b V b +T c V c =T s V ref T s =T a +T b +T c Among them, V ref is the reference voltage vector, V α 、V b 、V c are the three system voltage vectors in the area where the reference voltage vector is located, T a , T b , T c is the action time of the three system voltage vectors in the area where the reference voltage vector is located; A five-stage switching sequence of the parallel system is determined according to three system voltage vectors in the area where the reference voltage vector is located.

6. The integrated modulation method for parallel ANPC three-level inverters according to claim 5, characterized in that: With two switching cycles as one modulation cycle, the five-level switching sequence generated by the parallel system is converted into a three-level switching sequence and sent to each ANPC three-level inverter, including: The conversion needs to ensure that the vectors in the three-level switching sequence are all neutral vectors or zero vectors, and within a switching cycle, the inverter switching state allocation method of the front and rear half cycles is reversed, and at the same time, the switching sequences of the two inverters in the front and rear two switching cycles are swapped.

7. The integrated modulation method for parallel ANPC three-level inverters according to claim 6, characterized in that: Using two groups of the three-level switch sequences to perform modulation respectively, using the redundant switch states in the ANPC three-level inverter alternately in the two switching cycles to achieve uniform distribution of switching losses, including: When the output is in the O state, the redundant switch state of ANPC is used to output the O state in the positive half cycle of the AC power. 1+ , O 2+ Use alternately, use O in the negative half cycle of output AC 1-- , O 2- Use alternately.

8. An integrated modulation system for parallel ANPC three-level inverters, comprising: The common-mode voltage modeling module models the common-mode voltage of the parallel ANPC three-level inverter system based on the five-level vector space, and selects the parallel voltage vector with zero in the common-mode voltage as the system voltage vector of the synthetic reference voltage vector; The voltage vector processing module divides the vector space into a number of new sectors with the point where the system voltage vector is located at the center of the five-level vector space as the center of the circle; determines the sector and area where the reference voltage vector is located according to the amplitude and angle of the space where the reference voltage vector is located; and determines the action time of the corresponding system voltage vector by using the volt-second balance principle through the area where the reference voltage vector is located; The switch modulation module converts the five-level switch sequence generated by the parallel system into a three-level switch sequence and sends it to each ANPC three-level inverter, with two switching cycles as one modulation cycle; two groups of the three-level switch sequences are used for modulation respectively, and the redundant switch states in the ANPC three-level inverter are used alternately in the two switching cycles to achieve uniform distribution of switching losses.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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