Explosion-proof inverter circuit with capacitor and inverter

Abstract

The invention discloses an explosion-proof inverter circuit with a capacitor and an inverter, which are applied to the field of new energy, and comprise a multi-level inverter circuit and an explosion-proof circuit, and the explosion-proof circuit comprises a first discharge element, a second discharge element, a first switch and a second switch. When the upper half bus circuit in the multi-level inverter circuit is short-circuited due to a fault and the voltage at the two ends of the second capacitor in the lower half bus circuit is equal to the total voltage of the bus, the second capacitor is in overvoltage, the second switch is closed to conduct the second discharge element, and the energy stored in the second capacitor is discharged through the second discharge element. Similarly, when the lower half bus circuit in the multi-level inverter circuit is short-circuited, the first switch is closed to control the first discharge element to be switched on, energy stored by the first capacitor is released, high-voltage burst of the first capacitor is avoided, and the problem that the half bus circuit on one side in the current multi-level inverter circuit containing the upper and lower buses is short-circuited, and the reliability of the inverter circuit is improved is solved. And a capacitor in a semi-bus circuit on the other side is burst under high voltage.

Description

Technical Field

[0001] The present invention relates to the field of new energy, and in particular to an inverter circuit and an inverter with explosion-proof capacitors. Background Art

[0002] Capacitors have been widely used as voltage stabilization, filtering and energy storage components in multi-level inverter circuits with upper and lower half-bus circuits. Some multi-level topologies determine that the capacitors in the half-bus circuit need to lead out the intermediate level contact, that is, the bus midpoint potential end. In a multi-level inverter circuit, such as Figure 1 As shown, a TNPC three-level circuit, the bus positive input terminal BUS+ is a DC positive input, the bus negative input terminal BUS- is a DC negative input, and the bus midpoint potential terminal BUSN is a port for adjusting the voltage difference between the upper and lower half bus circuits. When any phase switch tube in the circuit fails, such as any group of transistors Q11 / Q13, Q21 / Q23, Q31 / Q33 short-circuit, it will cause the capacitor C1 in the upper half bus circuit to short-circuit; conversely, when any group of transistors Q12 / Q14, Q22 / Q24, Q32 / Q34 short-circuit, it will cause the capacitor C2 in the lower half bus circuit to short-circuit. At this time, the total bus voltage will be directly added to the capacitor of the other half bus circuit, causing the capacitor to be severely over-voltage and burst.

[0003] The current technology only sets a voltage detection circuit on the half-bus circuit. When a short circuit occurs in the half-bus circuit, the detection circuit detects an overvoltage fault and stops driving all switching devices. At this time, the total bus voltage will not increase. However, the capacitor voltage on the half-bus circuit will be equal to the total bus circuit voltage, and the energy cannot be released. The high voltage will still cause the capacitor on the half-bus circuit to explode, and the electrolyte of the capacitor will spray out, causing a high-voltage short circuit in the inverter's internal PCB, which will cause serious damage to the circuit or even a combustion accident.

[0004] It can be seen that the technical personnel in this field urgently need to solve the problem that when a half bus circuit on one side of a multi-level inverter circuit containing upper and lower buses is short-circuited, the capacitor in the half bus circuit on the other side will burst under high voltage. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide an inverter circuit and inverter with explosion-proof capacitors, which solves the problem that when a half-bus circuit on one side of a multi-level inverter circuit containing upper and lower buses is short-circuited, the capacitor in the half-bus circuit on the other side will explode at high voltage. The specific scheme is as follows:

[0006] In a first aspect, the present application provides an inverter circuit with capacitor explosion protection, including a multi-level inverter circuit and an explosion-proof circuit, wherein the explosion-proof circuit includes: a first discharge element, a second discharge element, a first switch, and a second switch;

[0007] The first discharge element and the first switch are connected in series and connected between the bus positive input terminal and the bus midpoint potential terminal, and are used to turn on the first switch when the lower half bus circuit is short-circuited, so as to discharge the electric energy of the upper half bus circuit through the first discharge element;

[0008] The second discharge element and the second switch are connected in series and connected between the bus negative input terminal and the bus midpoint potential terminal, and are used to turn on the second switch when the upper half bus circuit is short-circuited, so as to discharge the electric energy of the lower half bus circuit through the second discharge element.

[0009] Optionally, it also includes a first bus voltage detection circuit for detecting the voltage of the upper bus circuit, and a second bus voltage detection circuit for detecting the voltage of the lower bus circuit.

[0010] Optionally, the first bus voltage detection circuit includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor, a first operational amplifier and a first comparator;

[0011] The first end of the third resistor is connected to the bus positive input end as the first input end of the first bus voltage detection circuit;

[0012] The second end of the third resistor and the second end of the fourth resistor are connected to the non-inverting input terminal of the first operational amplifier, and the first end of the fourth resistor is grounded;

[0013] The first end of the fifth resistor is connected to the bus midpoint potential end as the second input end of the first bus voltage detection circuit;

[0014] The second end of the fifth resistor and the first end of the sixth resistor are connected to the inverting input terminal of the first operational amplifier;

[0015] The second end of the sixth resistor and the first end of the seventh resistor are connected to the output end of the first operational amplifier;

[0016] The second end of the seventh resistor and the first end of the third capacitor are connected to the non-inverting input terminal of the first comparator, and the second end of the third capacitor is grounded;

[0017] The inverting input terminal of the first comparator is connected to the reference voltage output terminal;

[0018] An output terminal of the first comparator is connected to a control terminal of the first switch.

[0019] Optionally, the second bus voltage detection circuit includes: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a fourth capacitor, a second operational amplifier, and a second comparator;

[0020] The first end of the eighth resistor is connected to the bus midpoint potential end as the first input end of the second bus voltage detection circuit;

[0021] The second end of the eighth resistor and the second end of the ninth resistor are connected to the non-inverting input terminal of the second operational amplifier, and the first end of the ninth resistor is grounded;

[0022] The first end of the tenth resistor is connected to the bus negative output end as the second input end of the second bus voltage detection circuit;

[0023] The second end of the tenth resistor and the first end of the eleventh resistor are connected to the inverting input terminal of the second operational amplifier;

[0024] The second end of the eleventh resistor and the first end of the twelfth resistor are connected to the output end of the second operational amplifier;

[0025] The second end of the twelfth resistor and the first end of the fourth capacitor are connected to the non-inverting input terminal of the second comparator, and the second end of the fourth capacitor is grounded;

[0026] The inverting input terminal of the second comparator is connected to the reference voltage output terminal;

[0027] An output terminal of the second comparator is connected to a control terminal of the second switch.

[0028] Optionally, the first discharge element and the second discharge element are both power resistors.

[0029] Optionally, the first switch and the second switch are both N-channel IGBT tubes.

[0030] Optionally, it also includes: a controller;

[0031] The controller is connected to the busbar midpoint potential terminal and is used to control the potential of the busbar midpoint potential terminal to be in dynamic balance.

[0032] Optionally, the controller is specifically used to: collect a first signal in the first bus voltage detection circuit and a second signal in the second bus voltage detection circuit, the first signal being a signal value reflecting the voltage across the first capacitor, and the second signal being a signal value reflecting the voltage across the second capacitor; calculating the difference between the first signal and the second signal; performing proportional and integral operations on the difference between the first signal and the second signal to obtain a first arithmetic value; superimposing the first arithmetic value and the sinusoidal pulse width modulation duty cycle of the inverter loop to obtain a second arithmetic value; and adjusting the potential of the bus midpoint potential end according to the second arithmetic value.

[0033] Optionally, it also includes a bus switch arranged on the bus input loop, which is used to disconnect the DC input of the bus when the voltage across the first capacitor or the second capacitor in the multi-level inverter circuit is over-voltage.

[0034] In a second aspect, the present application provides an inverter, including the inverter circuit with capacitor explosion-proof.

[0035] It can be seen that in this application, when the upper half bus circuit in the multi-level inverter circuit is short-circuited due to a fault, and the voltage across the second capacitor in the lower half bus circuit is equal to the total bus voltage, the second capacitor is over-voltage, and at this time, the second switch is closed to turn on the second discharge element, and the energy stored in the second capacitor is discharged through the second discharge element. Similarly, when the lower half bus circuit in the multi-level inverter circuit is short-circuited and the voltage across the first capacitor is over-voltage, the first switch is closed to turn on the first discharge element, releasing the energy stored in the first capacitor, avoiding the high-voltage burst of the first capacitor, and solving the problem that when one half bus circuit is short-circuited in the current multi-level inverter circuit containing upper and lower buses, the capacitor in the other half bus circuit will be over-voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A TNPC three-level circuit provided in an embodiment of the present application;

[0038] Figure 2 An inverter circuit with capacitor explosion protection provided in an embodiment of the present application;

[0039] Figure 3 A first bus voltage detection circuit provided in an embodiment of the present application;

[0040] Figure 4 A second bus voltage detection circuit provided in an embodiment of the present application;

[0041] Figure 5 A flow chart of a midpoint potential balance control algorithm provided in an embodiment of the present application;

[0042] The reference numerals are as follows: 10 is a multi-level inverter circuit. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The core of this application is to provide an inverter circuit with capacitor explosion protection.

[0045] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0046] Capacitors have been widely used in multi-level inverter circuits with upper and lower buses as components for voltage stabilization, filtering and energy storage. Some multi-level topologies determine that the capacitors in the half-bus circuit need to lead out the intermediate level contact, that is, the bus midpoint potential end. When a multi-level inverter circuit is included, such as Figure 1 As shown, a TNPC three-level circuit, the bus positive input terminal BUS+ is a DC positive input, the bus negative input terminal BUS- is a DC negative input, and the bus midpoint potential terminal BUSN is a port for adjusting the voltage difference between the upper and lower busbars. When any phase switch in the circuit fails, such as a short circuit of any group of transistors Q11 / Q13, Q21 / Q23, Q31 / Q33, the capacitor C1 in the upper half busbar circuit will be short-circuited; conversely, when any group of transistors Q12 / Q14, Q22 / Q24, Q32 / Q34 is short-circuited, the capacitor C2 in the lower half busbar circuit will be short-circuited. At this time, the total bus voltage will be directly added to the capacitor of the other half busbar circuit, causing the capacitor to be severely over-voltage and burst and damaged.

[0047] The current technology only sets a voltage detection circuit on the half-bus circuit. When a short circuit occurs in the half-bus circuit, the detection circuit detects an overvoltage fault and stops driving all switching devices. At this time, the total bus voltage will not increase. However, the capacitor voltage on the half-bus circuit will be equal to the total bus circuit voltage, and the energy cannot be released. The high voltage will still cause the capacitor on the half-bus circuit to burst, and the electrolyte of the capacitor will spray out, causing a high-voltage short circuit in the inverter's internal PCB, which will cause serious damage to the circuit or even a combustion accident.

[0048] It can be seen that the technical personnel in this field urgently need to solve the problem that when a half bus circuit on one side of a multi-level inverter circuit containing upper and lower buses is short-circuited, the capacitor in the half bus circuit on the other side will burst under high voltage.

[0049] Figure 2 An inverter circuit with capacitor explosion protection is provided in the embodiment of the present application. Figure 2As shown, in order to solve the above problems, this embodiment provides an inverter circuit with capacitor explosion-proof, including a multi-level inverter circuit and an explosion-proof circuit, the explosion-proof circuit including: a first discharge element R1, a second discharge element R2, a first switch Q1 and a second switch Q2;

[0050] The first discharge element R1 and the first switch Q1 are connected in series and connected between the bus positive input terminal and the bus midpoint potential terminal, so as to turn on the first switch Q1 when the lower half bus circuit is short-circuited, so as to discharge the electric energy of the upper half bus circuit through the first discharge element R1;

[0051] The second discharge element R2 and the second switch Q2 are connected in series and connected between the bus negative input terminal and the bus midpoint potential terminal, so as to turn on the second switch Q2 when the upper half bus circuit is short-circuited, so as to discharge the electric energy of the lower half bus circuit through the second discharge element R2.

[0052] like Figure 2 As shown, 10 is a multi-level inverter circuit. In the multi-level inverter circuit 10, the capacitor is used as an energy storage device. When the voltage at both ends exceeds the tolerance range of the device, the energy in the capacitor should be discharged in time. Therefore, the above-mentioned explosion-proof circuit is essentially a discharge circuit.

[0053] When the multi-level topology circuit has upper and lower bus DC inputs, the upper and lower buses are connected to a DC power supply and are often equipped with bus capacitors in the middle. The bus capacitor stores energy, filters and maintains the balance and stability of the upper and lower bus voltages, providing a stable DC voltage foundation for the circuit. The multiple power switching devices in the power inverter bridge are turned on and off according to the control signal, and the DC voltage between the upper and lower buses is converted into different level outputs in a specific combination. For example, by controlling the output to connect the upper bus BUS+ to obtain a positive level, the bus capacitor midpoint BUSN to obtain an intermediate level, and the lower bus BUS- to obtain a negative level. The duration of each level of the power inverter bridge is adjusted so that the output voltage mean changes according to the sine law to achieve multi-level output. At the same time, the first switch Q1 and the second switch Q2 in the explosion-proof circuit are both in the disconnected state, and the first discharge element R1 and the second discharge element R2 do not work, which will not affect the normal operation of the circuit.

[0054] When a short circuit occurs in the lower bus circuit, the bus voltage will be completely transferred to both ends of the upper bus circuit, and the first switch Q1 will be closed. At this time, the first discharge element R1 is connected to the circuit, and the electric energy of the upper bus forms a loop through the first discharge element R1 for discharge, thereby preventing the upper bus capacitor and other components from exploding due to overvoltage caused by the short circuit. The discharge process continues until the fault is eliminated or the electric energy is discharged to a safe range, at which time the first switch Q1 is controlled to be disconnected according to the situation.

[0055] When a short circuit fault of the upper bus circuit is detected, the second switch Q2 is closed, the second discharge element R2 is connected to the circuit, and the electric energy of the lower bus circuit is discharged through the second discharge element R2. The principle is similar to that when the lower bus circuit is short-circuited. The bus capacitor and other circuit components are protected by discharging electric energy to prevent explosion caused by overvoltage caused by short circuit. After the fault is handled, the second switch Q2 is controlled to be disconnected.

[0056] During the whole process, the explosion-proof circuit is used to discharge the short-circuit fault of the bus circuit in a targeted manner, which effectively improves the safety and reliability of the multi-level inverter circuit with capacitors, avoids serious accidents such as capacitor overvoltage explosion caused by short circuit, and ensures the stable operation of the circuit and related equipment. It solves the problem that if one half of the bus circuit on one side of the multi-level inverter circuit with upper and lower buses is short-circuited, the capacitor in the other half of the bus circuit will explode at high voltage.

[0057] According to the above embodiment, this embodiment provides a specific solution, which also includes: a first bus voltage detection circuit for detecting the voltage of the upper half bus circuit, and a second bus voltage detection circuit for detecting the voltage of the lower half bus circuit.

[0058] like Figure 2 As shown, when the first bus voltage detection circuit detects that a short circuit fault occurs in the upper bus circuit, a signal is immediately sent to the second switch Q2 to drive the second switch Q2 to close; when the second bus voltage detection circuit detects that a short circuit fault occurs in the lower bus circuit, a signal is immediately sent to the first switch Q1 to drive the first switch Q1 to close.

[0059] In a specific embodiment, the first bus voltage detection circuit and the second bus voltage detection circuit may be composed of a data processing module and a control module. The data processing module is used to collect the bus circuit voltage and determine whether the voltage at both ends of the half bus circuit is in a normal working range, which can be implemented by a chip, a comparator, etc. The control module is used to control the first switch Q1 or the second switch Q2 on and off according to the output result of the data processing module, which can be achieved by hardware implementation methods such as relays and comparators.

[0060] It can be seen that, in this embodiment, the voltage conditions of the upper bus circuit and the lower bus circuit of the multi-level inverter circuit can be monitored in real time and accurately through the first bus voltage detection circuit and the second bus voltage detection circuit, and voltage anomalies can be discovered in time and effective protection measures can be taken, thereby improving the reliability and safety of the entire inverter circuit system, and ensuring the stable operation of the load and the normal service life of the circuit components. In practical applications, the accuracy, response speed, etc. of the detection circuit can also be further optimized and adjusted according to specific circuit requirements and performance indicators.

[0061] Figure 3The first bus voltage detection circuit provided in the embodiment of the present application is as follows: Figure 3 As shown, according to the above embodiment, this embodiment provides a specific solution, the first bus voltage detection circuit includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a third capacitor C3, a first operational amplifier Amp1 and a first comparator Comp1;

[0062] A first end of the third resistor R3 is connected to the bus positive input end as a first input end of the first bus voltage detection circuit;

[0063] The second end of the third resistor R3 and the second end of the fourth resistor R4 are connected to the non-inverting input terminal of the first operational amplifier Amp1, and the first end of the fourth resistor R4 is grounded;

[0064] A first end of the fifth resistor R5 is connected to the bus midpoint potential end as a second input end of the first bus voltage detection circuit;

[0065] The second end of the fifth resistor R5 and the first end of the sixth resistor R6 are connected to the inverting input terminal of the first operational amplifier Amp1;

[0066] The second end of the sixth resistor R6 and the first end of the seventh resistor R7 are connected to the output end of the first operational amplifier Amp1;

[0067] The second end of the seventh resistor R7 and the first end of the third capacitor C3 are connected to the non-inverting input end of the first comparator Comp1, and the second end of the third capacitor C3 is grounded;

[0068] The inverting input terminal of the first comparator Comp1 is connected to the reference voltage output terminal;

[0069] An output terminal of the first comparator Comp1 is connected to a control terminal of the first switch Q1 .

[0070] Figure 4 The second bus voltage detection circuit provided in the embodiment of the present application is as follows: Figure 4 As shown, according to the above embodiment, this embodiment provides a specific solution, the second bus voltage detection circuit includes: an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a fourth capacitor C4, a second operational amplifier Amp2 and a second comparator Comp2;

[0071] A first end of the eighth resistor R8 is connected to the bus midpoint potential end as a first input end of the second bus voltage detection circuit;

[0072] The second end of the eighth resistor R8 and the second end of the ninth resistor R9 are connected to the non-inverting input terminal of the second operational amplifier Amp2, and the first end of the ninth resistor R9 is grounded;

[0073] A first end of the tenth resistor R10 is connected to the negative output end of the bus as a second input end of the second bus voltage detection circuit;

[0074] The second end of the tenth resistor R10 and the first end of the eleventh resistor R11 are connected to the inverting input terminal of the second operational amplifier Amp2;

[0075] The second end of the eleventh resistor R11 and the first end of the twelfth resistor R12 are connected to the output end of the second operational amplifier Amp2;

[0076] The second end of the twelfth resistor R12 and the first end of the fourth capacitor C4 are connected to the non-inverting input end of the second comparator Comp2, and the second end of the fourth capacitor C4 is grounded;

[0077] The inverting input terminal of the second comparator Comp2 is connected to the reference voltage output terminal;

[0078] An output terminal of the second comparator Comp2 is connected to a control terminal of the second switch Q2.

[0079] like Figure 3 As shown, the input end of the first bus voltage detection circuit is connected to the bus positive input end and the bus midpoint potential end, and the voltage signal of the upper half bus circuit enters the first operational amplifier Amp1 for differential sampling, and then transmits the signal to the first comparator Comp1. Figure 4 As shown, the input end of the second bus voltage detection circuit is connected to the bus midpoint potential end and the bus negative input end, and the voltage signal of the lower half bus circuit enters the second operational amplifier Amp2 for differential sampling, and then transmits the signal to the second comparator Comp2.

[0080] When the lower bus circuit fails and short-circuits, the upper bus circuit is over-voltaged at both ends. The first operational amplifier Amp1 transmits the collected voltage signal of the upper bus circuit to the first comparator Comp1. The first comparator Comp1 compares the signal representing the voltage of the upper bus circuit with the preset reference value Vref. When it is less than the preset reference value Vref of the reference voltage output end, the first comparator Comp1 outputs a low level, and the first switch Q1 is not turned on. When it is greater than the preset reference value Vref of the reference voltage output end, the first comparator Comp1 outputs a high level, and the first switch Q1 is turned on, the explosion-proof circuit is turned on, and the stored energy of the first capacitor C1 is discharged. When the upper bus circuit fails and short-circuits, the two ends of the lower bus circuit are overvoltage, and the second operational amplifier Amp2 transmits the collected voltage signal of the lower bus circuit to the second comparator Comp2. The second comparator Comp2 compares the signal representing the voltage of the lower bus circuit with the preset reference value Vref. When it is less than the preset reference value Vref of the reference voltage output end, the second comparator Comp2 outputs a low level, and the second switch Q2 is not turned on; when it is greater than the preset reference value Vref of the reference voltage output end, the second comparator Comp2 outputs a high level, and the second switch Q2 is turned on, the explosion-proof circuit is turned on, and the stored energy of the second capacitor C2 is discharged.

[0081] It can be seen that in this embodiment, the first bus voltage detection circuit and the second bus voltage detection circuit dynamically balance the bus midpoint potential end by detecting the voltage of the upper bus circuit and the lower bus circuit. When the upper bus circuit or the lower bus circuit fails and a short circuit occurs, the level of the first comparator Comp1 or the second comparator Comp2 will flip quickly, and the explosion-proof circuit will be controlled to quickly release the energy of the first capacitor C1 or the second capacitor C2, so that the voltage of the first capacitor C1 or the second capacitor C2 is lower than the rated voltage, thereby protecting the electrolytic capacitor and avoiding explosion and serious accidents.

[0082] This embodiment provides a specific solution, in which the first discharge element R1 and the second discharge element R2 are both power resistors.

[0083] Power resistors have a simple and stable physical structure. Compared with some complex electronic components, their working principle is mainly based on the basic physical properties of resistor materials, that is, converting electrical energy into heat energy and dissipating it through Ohm's law. This simple working method enables power resistors to operate stably and reliably within the normal working range, and is not easily affected by factors such as electromagnetic interference and temperature changes, resulting in performance mutations or failures. For example, in harsh industrial environments, such as those with strong electromagnetic noise or large temperature fluctuations, power resistors can still maintain their discharge function.

[0084] It can be understood that, in this embodiment, for the first discharge element R1 and the second discharge element R2, their rated power and resistance need to be calculated and determined according to the power level of the multi-level inverter circuit and the parameters of the first capacitor C1 and the second capacitor C2 in the upper and lower bus circuits to ensure that they can effectively discharge the discharge energy without being damaged when a short circuit fault occurs.

[0085] This embodiment provides a specific solution, in which the first switch Q1 and the second switch Q2 are both N-channel IGBT tubes.

[0086] The N-channel IGBT tube has the characteristics of high input impedance, fast response and high current carrying capacity. This means that it has low power requirements for the drive circuit, and only a small drive current is needed to control its conduction and shutdown. In the application scenario of explosion-proof circuits, it can be easily connected to the control signal source, and no complex, high-power drive circuit is required to provide the drive signal. For example, compared with bipolar transistors, the gate drive current of the IGBT tube can be several orders of magnitude smaller, which can simplify the design of the drive circuit and reduce costs. At the same time, since the N-channel IGBT tube is a voltage-controlled device, its state is controlled by applying an appropriate voltage between the gate and the emitter. This control method is more accurate and flexible than current-controlled devices. In the explosion-proof circuit, the on and off moments of the IGBT tube can be accurately controlled according to the signal fed back by the bus voltage detection circuit, which meets the fast response requirements of the bus capacitor overvoltage in this application, and the first capacitor C1 or the second capacitor C2 needs to discharge energy immediately.

[0087] According to the above embodiment, this embodiment provides a specific solution, further comprising: a controller;

[0088] The controller is connected to the bus midpoint potential terminal and is used to control the potential of the bus midpoint potential terminal to be in dynamic balance.

[0089] like Figure 5 As shown, in the present application, the controller is specifically used to: collect the first signal V in the first bus voltage detection circuit UP-OUT and the second signal V in the second bus voltage detection circuit LP-OUT , the first signal V UP-OUT The second signal V LP-OUT is a signal value reflecting the voltage across the second capacitor C2; calculate the first signal V UP-OUT and the second signal V LP-OUT The difference between the first signal V UP-OUT and the second signal V LP-OUTThe difference is input into the PI controller for proportional and integral operations to obtain a first arithmetic value; the first arithmetic value and the sinusoidal pulse width modulation duty cycle of the inverter loop are superimposed to obtain a second arithmetic value; and the potential of the bus midpoint potential end is adjusted according to the second arithmetic value.

[0090] It should be noted that the first signal V UP-OUT From the output terminal of the first operational amplifier, the second signal V LP-OUT from the output of the second operational amplifier.

[0091] The first bus voltage detection circuit and the second bus voltage detection circuit also need to transmit the detected upper bus circuit voltage signal and lower bus circuit voltage signal to the controller during normal operation for use by the DSP software control algorithm.

[0092] In a specific embodiment, the first signal V in the first bus voltage detection circuit is collected. UP-OUT and the second signal V in the second bus voltage detection circuit LP-OUT The controller is given so that the controller can use the DSP software control algorithm. The software algorithm adds midpoint potential balance control, calculates the difference between the upper and lower buses by sampling, and superimposes the PI controller and the sine wave pulse width modulation duty ratio SPWM DUTY of the inverter loop to obtain the actual duty ratio of the corresponding switch tube in the multi-level inverter circuit. In this way, the potential at the midpoint potential end of the bus can always maintain a small range of dynamic balance, and the voltage difference between the upper and lower buses can be controlled within a reasonable range. For example, when the total bus voltage is 1000V, the voltage difference between the upper and lower bus circuits is controlled to be between 20-30V.

[0093] According to the above embodiment, this embodiment provides a specific solution, which also includes a bus switch arranged on the bus input loop, which is used to disconnect the DC input of the bus when the voltage across the first capacitor C1 or the second capacitor C2 in the multi-level inverter circuit is over-voltage.

[0094] When the voltage across the first capacitor C1 or the second capacitor C2 is overvoltage, the explosion-proof circuit is turned on and directly connected to the upper bus circuit or the lower bus circuit. If the bus is still input at this time, it will be equivalent to short-circuiting the bus input terminal, causing great safety hazards. Therefore, it is very necessary to add a bus switch to the bus input loop in terms of circuit safety.

[0095] Finally, this embodiment provides an inverter, including the above-mentioned inverter circuit with capacitor explosion-proof.

[0096] The inverter circuit and inverter with capacitor explosion-proof provided by the present application are introduced in detail above. Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0097] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. An inverter circuit with capacitor explosion protection, including a multi-level inverter circuit, characterized in that: Also included is an explosion-proof circuit, the explosion-proof circuit comprising: a first discharge element, a second discharge element, a first switch, and a second switch; The first discharge element and the first switch are connected in series and connected between the bus positive input terminal and the bus midpoint potential terminal, and are used to turn on the first switch when the lower half bus circuit is short-circuited, so as to discharge the electric energy of the upper half bus circuit through the first discharge element; The second discharge element and the second switch are connected in series and connected between the bus negative input terminal and the bus midpoint potential terminal, and are used to turn on the second switch when the upper half bus circuit is short-circuited, so as to discharge the electric energy of the lower half bus circuit through the second discharge element.

2. The inverter circuit with capacitor explosion-proof according to claim 1, characterized in that: It also includes a first bus voltage detection circuit for detecting the voltage of the upper half bus circuit, and a second bus voltage detection circuit for detecting the voltage of the lower half bus circuit.

3. The inverter circuit with capacitor explosion-proof according to claim 2, characterized in that: The first bus voltage detection circuit includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor, a first operational amplifier and a first comparator; The first end of the third resistor is connected to the bus positive input end as the first input end of the first bus voltage detection circuit; The second end of the third resistor and the second end of the fourth resistor are connected to the non-inverting input terminal of the first operational amplifier, and the first end of the fourth resistor is grounded; The first end of the fifth resistor is connected to the bus midpoint potential end as the second input end of the first bus voltage detection circuit; The second end of the fifth resistor and the first end of the sixth resistor are connected to the inverting input terminal of the first operational amplifier; The second end of the sixth resistor and the first end of the seventh resistor are connected to the output end of the first operational amplifier; The second end of the seventh resistor and the first end of the third capacitor are connected to the non-inverting input terminal of the first comparator, and the second end of the third capacitor is grounded; The inverting input terminal of the first comparator is connected to the reference voltage output terminal; An output terminal of the first comparator is connected to a control terminal of the first switch.

4. The inverter circuit with capacitor explosion-proof according to claim 2, characterized in that: The second bus voltage detection circuit includes: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a fourth capacitor, a second operational amplifier and a second comparator; The first end of the eighth resistor is connected to the bus midpoint potential end as the first input end of the second bus voltage detection circuit; The second end of the eighth resistor and the second end of the ninth resistor are connected to the non-inverting input terminal of the second operational amplifier, and the first end of the ninth resistor is grounded; The first end of the tenth resistor is connected to the bus negative output end as the second input end of the second bus voltage detection circuit; The second end of the tenth resistor and the first end of the eleventh resistor are connected to the inverting input terminal of the second operational amplifier; The second end of the eleventh resistor and the first end of the twelfth resistor are connected to the output end of the second operational amplifier; The second end of the twelfth resistor and the first end of the fourth capacitor are connected to the non-inverting input terminal of the second comparator, and the second end of the fourth capacitor is grounded; The inverting input terminal of the second comparator is connected to the reference voltage output terminal; An output terminal of the second comparator is connected to a control terminal of the second switch.

5. The inverter circuit with capacitor explosion-proof according to claim 1, characterized in that: The first discharge element and the second discharge element are both power resistors.

6. The inverter circuit with capacitor explosion-proof according to claim 1, characterized in that: The first switch and the second switch are both N-channel IGBT tubes.

7. The inverter circuit with capacitor explosion protection according to any one of claims 1 to 6, characterized in that: Also includes: Controller; The controller is connected to the busbar midpoint potential end and is used to control the potential of the busbar midpoint potential end to be in dynamic balance.

8. The inverter circuit with capacitor explosion-proof according to claim 7, characterized in that: The controller is specifically used to: collect a first signal in the first bus voltage detection circuit and a second signal in the second bus voltage detection circuit, the first signal is a signal value reflecting the voltage across the first capacitor, and the second signal is a signal value reflecting the voltage across the second capacitor; calculate the difference between the first signal and the second signal; perform proportional and integral operations on the difference between the first signal and the second signal to obtain a first arithmetic value; superimpose the first arithmetic value and the sinusoidal pulse width modulation duty cycle of the inverter loop to obtain a second arithmetic value; and adjust the potential of the bus midpoint potential end according to the second arithmetic value.

9. The inverter circuit with capacitor explosion-proof according to claim 1, characterized in that: It also includes a bus switch arranged on the bus input loop, which is used to disconnect the DC input of the bus when the voltage across the first capacitor or the second capacitor in the multi-level inverter circuit is over-voltage.

10. An inverter, characterized in that: The invention comprises an inverter circuit with explosion-proof capacitor as claimed in any one of claims 1 to 9.

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