Design method of pipelined analog-to-digital converter and pipelined analog-to-digital converter

Abstract

This invention discloses a pipelined analog-to-digital converter (ADC) design method and the pipelined ADC thereof. The method includes the following steps: S1, the result of the second-stage quantization is multiplied by 1 / A and fed back to the minor bits of the first-stage DAC to regenerate the residual of the first stage; S2, the residual is amplified by a factor of A and used as the input of the second stage, which is then requantized again; S3, the signals quantized in the first stage and the second stage are combined by a combiner to obtain the final digital output signal. This invention significantly reduces the performance requirements of the first-stage quantizer and interstage amplifier by feeding back the result of the second-stage quantization to the lower bits of the first-stage DAC, then amplifying the first-stage residual, and finally requantizing it again in the second stage, thereby improving the linearity of the ADC. Simultaneously, the above process can be repeated multiple times, reducing the power consumption of the first-stage quantizer and interstage amplifier, thus reducing power consumption while maintaining the linearity of the pipelined ADC.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter design technology, and in particular to a pipelined analog-to-digital converter design method and the pipelined analog-to-digital converter thereof. Background Technology

[0002] Analog-to-digital converters (ADCs) are crucial devices that convert analog signals into digital signals and are widely used in modern electronic devices. Among them, pipelined ADCs are widely adopted in high-speed, high-precision data acquisition systems due to their ability to achieve high sampling rates and high resolutions. In a pipelined ADC, the input analog signal is quantized sequentially through multiple quantization stages, each of which includes a digital-to-analog converter (DAC) and a quantizer.

[0003] Existing pipelined ADCs typically consist of multiple identical quantization stages, each quantizing the input signal once. In practical applications, the number of bits in the first-stage quantizer determines the overall dynamic range and linearity of the ADC. However, increasing the number of bits in the first-stage quantizer significantly increases its accuracy requirements, leading to a significant increase in power consumption and area. To balance linearity and power consumption, current designs employ a smaller number of bits in the first-stage quantization stage, but this approach reduces the ADC's linearity.

[0004] This shows that existing pipelined ADC designs face a dilemma: using fewer first-stage quantization bits can reduce power consumption but also decrease the ADC's linearity; while using more first-stage quantization bits can improve the ADC's linearity but significantly increase power consumption.

[0005] Furthermore, existing designs typically require high performance from both the DAC and quantizer in each quantization stage, which increases design complexity and cost.

[0006] Therefore, existing pipelined ADC designs present a difficult trade-off between power consumption and linearity. Summary of the Invention

[0007] The technical problem to be solved by this invention is how to balance the conflict between linearity, power consumption and cost in pipelined ADCs.

[0008] In a first aspect, to address the aforementioned technical problems, the present invention provides a design method for a pipelined analog-to-digital converter, the method comprising the following steps:

[0009] S1. The result of the second-stage quantization is multiplied by 1 / A and fed back to the minor bits of the first-stage DAC to regenerate the residual of the first stage.

[0010] S2. The residual is amplified by A times and used as the input of the second stage, and the second stage is requantized again;

[0011] S3. The first-level quantized signal and the second-level quantized signal are combined by a combiner to form the final digital output signal.

[0012] Furthermore, S2 can reuse the interstage amplifier between the first stage and the second stage and the second-stage quantizer of the second stage.

[0013] Furthermore, the processes S1 and S2 can be repeated multiple times in sequence.

[0014] A second aspect of the present invention provides a pipelined analog-to-digital converter, which applies the design method of the pipelined analog-to-digital converter described above.

[0015] Furthermore, it includes at least a first-stage and a second-stage cascaded circuit, wherein the first stage includes a first-stage quantization circuit or a first-stage quantizer.

[0016] Furthermore, the first-stage quantization circuit includes a switch array, a capacitor array, a comparator, and a logic control module, wherein:

[0017] The input signal is connected to the negative input terminal of the comparator in sequence through the switch array, the capacitor array, and grounded. The output terminal of the comparator is connected to the input terminal of the logic control module. The output terminal of the logic control module outputs the first-stage quantized signal to the combiner, and the output terminal of the logic control module is connected to the switch array.

[0018] Furthermore, the input signal is quantized by the first-stage quantizer and output to the combiner.

[0019] Furthermore, the second stage includes a switch array, a capacitor array, a second-stage quantizer, and a multiplier, with an interstage amplifier positioned between the first and second stages. The input signal is sequentially connected to the input of the interstage amplifier via the switch array, the capacitor array, and the interstage amplifier. The output of the interstage amplifier is connected to the input of the second-stage quantizer, the output of the second-stage quantizer is connected to the input of the multiplier, and the output of the multiplier is connected to the switch array.

[0020] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0021] This invention significantly reduces the performance requirements of the first-stage quantizer and interstage amplifier by feeding the result of the second-stage quantization back to the lower bits of the first-stage DAC, then re-amplifying the first-stage residual, and then re-quantizing it again in the second stage. This improves the linearity of the ADC. At the same time, the above process can be repeated multiple times, reducing the power consumption of the first-stage quantizer and interstage amplifier. In other words, power consumption is reduced while ensuring the linearity of the pipelined ADC. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of the present invention;

[0024] Figure 2 This is a schematic diagram of the circuit principle disclosed in Embodiment 1 of the present invention;

[0025] Figure 3 This is a schematic diagram of the circuit principle disclosed in Embodiment 2 of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] This invention aims to resolve the conflict between the reduced ADC linearity due to a small number of quantization bits in the first stage and the significantly increased power consumption of the first stage in traditional pipelined ADC designs.

[0028] As is common knowledge in the field, the first-stage quantizer plays a crucial role in pipelined ADCs because it directly determines the dynamic range and linearity of subsequent quantization stages. If the first-stage quantizer has insufficient bits, it will be unable to provide enough resolution to support the high precision requirements of subsequent quantization stages, resulting in a degraded overall ADC performance.

[0029] The first aspect of this invention provides a design method for a pipelined analog-to-digital converter. (See also...) Figure 1 , the method comprises the following steps:

[0030] S1. The result of the second-stage quantization is multiplied by 1 / A and fed back to the minor bits of the first-stage DAC to regenerate the residual of the first stage.

[0031] S2. The residual is amplified by A times and used as the input for the second stage, which is then requantized.

[0032] S3. The signals after the first stage of quantization and the signals after the second stage of quantization are combined by a combiner to obtain the final digital output signal.

[0033] The second stage includes a second-stage quantizer, and an interstage amplifier is placed between the first and second stages. Step S2 reuses the interstage amplifier and the second-stage quantizer. This repetition not only makes full use of existing resources but also reduces error accumulation caused by multiple quantizations, thereby improving the ADC's performance. Simultaneously, processes S1 and S2 can be repeated sequentially multiple times. This significantly reduces the performance requirements on the first-stage quantizer and the interstage amplifier, thereby improving the ADC's linearity.

[0034] Those skilled in the art further explain that "minor bits" refer to the lower bits of the first-stage DAC, which are bits with smaller weights in the DAC. These bits have a relatively small impact on the final output, but are still important.

[0035] A second aspect of the present invention provides a specific structure for a pipelined analog-to-digital converter.

[0036] Example 1

[0037] Please see Figure 2 The pipelined analog-to-digital converter includes at least two cascaded circuits: a first stage and a second stage. The first stage includes a first-stage quantization circuit, and the second stage includes a switch array, a capacitor array, an interstage amplifier, a second-stage quantizer, and a multiplier.

[0038] First, the specific structure of the first level will be explained.

[0039] The first-stage quantization circuit includes a switch array, a capacitor array, a comparator, and a logic control module.

[0040] The input signal is connected to the negative input terminal of the comparator in sequence through the switch array and capacitor array. The positive input terminal of the comparator is grounded. The output terminal of the comparator is connected to the input terminal of the logic control module. The output terminal of the logic control module outputs the first-stage quantized signal to the combiner, and the output terminal of the logic control module is connected to the switch array.

[0041] Those skilled in the art further explain that the logic control module controls the opening and closing of corresponding switches in the switch network based on the received second-stage quantization result. These switches are connected to different bits of the first-stage DAC to achieve fine adjustment of the lower bits.

[0042] The first-stage DAC consists of capacitors C1 and C2. In this first-stage DAC, the capacitor array is the key component for analog signal conversion. Each capacitor corresponds to a specific weight, and different weight combinations can be achieved through switch control.

[0043] Next, the specific structure of the second level will be explained.

[0044] The input signal is connected to the input of the interstage amplifier in sequence through a switch array and a capacitor array. The output of the interstage amplifier is connected to the input of the second-stage quantizer. The output of the second-stage quantizer is connected to the input of the multiplier. The output of the multiplier is connected to the switch array.

[0045] Example 2

[0046] Please see Figure 3 The pipelined analog-to-digital converter includes at least two cascaded circuits: a first stage and a second stage. The first stage includes a first-stage quantizer, and the second stage includes a switch array, a capacitor array, an interstage amplifier, a second-stage quantizer, and a multiplier.

[0047] First, the specific structure of the first level will be explained.

[0048] The input signal is quantized by the first-stage quantizer and output to the combiner; at the same time, the output of the first-stage quantizer is connected to the switch array.

[0049] Next, the specific structure of the second level will be explained.

[0050] The input signal is connected to the input of the interstage amplifier in sequence through a switch array and a capacitor array. The output of the interstage amplifier is connected to the input of the second-stage quantizer. The output of the second-stage quantizer is connected to the input of the multiplier. The output of the multiplier is connected to the switch array.

[0051] In other schemes, there may also be a second stage followed by an interstage amplifier and a quantizer.

[0052] The present invention has the following beneficial effects:

[0053] 1. Improve linearity: By feeding the result of the second-stage quantization back to the lower bits of the first-stage DAC, then re-amplifying the residual, and repeating this process multiple times, the linearity of the ADC can be improved. This method significantly reduces the performance requirements of the first-stage quantizer and interstage amplifiers.

[0054] 2. Reduced power consumption: By reusing the interstage amplifier and the second-stage quantizer, the power consumption of the first-stage quantizer and the interstage amplifier is significantly reduced. Therefore, while maintaining linearity, power consumption is reduced, thereby improving energy efficiency.

[0055] 3. Reduced design costs: By lowering the performance requirements for the first-stage quantizer and interstage amplifiers, the design and manufacturing process is simplified, thereby reducing design costs. This has significant economic implications for mass production.

[0056] 4. Flexibility: The structure of the pipeline ADC of this invention can be flexibly adjusted, and different quantization levels and bit depths can be selected according to actual needs, thereby meeting the requirements of different application scenarios.

[0057] 5. Improved Signal-to-Noise Ratio: Because the pipeline ADC of this invention performs multiple quantizations, it can effectively reduce quantization noise, thereby improving the signal-to-noise ratio. This is of great significance for high-precision data acquisition systems.

[0058] This invention can be widely applied in fields such as analog-to-digital converter design, integrated circuit design, and signal processing technology.

[0059] Firstly, in the field of analog-to-digital converter design, by reusing the interstage amplifier and the second-stage quantizer, the performance requirements of the first-stage quantizer and the interstage amplifier are significantly reduced, thereby lowering the design cost. This novel structure is of great significance for improving the performance and reducing the cost of analog-to-digital converters.

[0060] Secondly, in the field of integrated circuit design, this invention provides a novel integrated circuit design approach. By optimizing the structure of a pipelined ADC, a balance between power consumption and linearity is achieved, which is of significant value for improving integrated circuit performance and reducing power consumption. With the development of integrated circuit technology, the demand for high-efficiency, low-power integrated circuits is increasing, and this technical solution is expected to be widely applied in the field of integrated circuit design.

[0061] Finally, in the field of signal processing technology, the novel pipelined ADC structure proposed in this technical solution can improve the accuracy and quality of signal processing, which is of great significance to the development of signal processing technology. With the widespread application of signal processing technology in various fields, such as communication, audio processing, and image processing, this technical solution is expected to find widespread application in the field of signal processing technology.

[0062] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A pipelined analog-to-digital converter, characterized in that, The pipelined analog-to-digital converter includes at least two cascaded stages, a first stage and a second stage, wherein it performs the following steps: S1. The signal quantized by the second-stage quantization circuit is multiplied by 1 / A and then fed back to the secondary bit of the DAC of the first-stage quantization circuit to regenerate the residual of the first-stage quantization circuit. S2, the residual is amplified by A times and used as the input of the second-stage quantization circuit, which then requantizes the data. S2 can reuse the interstage amplifier and the second-stage quantizer between the first-stage quantization circuit and the second-stage quantization circuit. The processes of S1 and S2 can be repeated multiple times. S3. The signals quantized by the first-stage quantization circuit and the signals quantized by the second-stage quantization circuit are combined by a combiner to form the final digital output signal.

2. The pipelined analog-to-digital converter according to claim 1, characterized in that, The first-stage quantization circuit includes the DAC and the first-stage quantizer; wherein: The DAC includes a switch array and a capacitor array; The first-stage quantizer includes a comparator and a logic control module; The input signal is connected to the negative input terminal of the comparator in sequence through the switch array, the capacitor array, and grounded. The output terminal of the comparator is connected to the input terminal of the logic control module. The output terminal of the logic control module outputs the first-stage quantized signal to the combiner, and the output terminal of the logic control module is connected to the switch array.

3. The pipelined analog-to-digital converter according to claim 2, characterized in that, The input signal is quantized by the first-stage quantizer and output to the combiner.

4. The pipelined analog-to-digital converter according to claim 2, characterized in that, The second-stage quantization circuit includes the DAC, the second-stage quantizer, and the multiplier; wherein: The multiplier is configured to multiply the signal quantized by the second-stage quantization circuit by 1 / A and then feed it back to the secondary bit of the DAC of the first-stage quantization circuit. An interstage amplifier is also provided between the first-stage quantization circuit and the second-stage quantization circuit; The input signal is connected to the input terminal of the interstage amplifier in sequence through the switch array, the capacitor array, the output terminal of the interstage amplifier, the input terminal of the second-stage quantizer, the output terminal of the second-stage quantizer, the input terminal of the multiplier, and the output terminal of the multiplier, which is connected to the switch array.

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