Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The manufacturing method comprises the following steps: forming a first transistor; forming a capacitor on the first transistor; wherein the capacitor comprises a first electrode, a dielectric layer and a second electrode; forming a second transistor on the capacitor; wherein the source electrode or the drain electrode of the first transistor is connected with the second electrode of the capacitor, and the grid electrode of the second transistor is connected with the second electrode of the capacitor.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] With the continuous improvement of semiconductor manufacturing technology, the process feature size is getting smaller and smaller, and the storage density of memory is getting higher and higher. However, with the improvement of the storage density of memory, the manufacturing process of memory is becoming more and more complicated.

[0003] Therefore, how to optimize the manufacturing process of memory becomes an urgent problem to be solved. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] forming a first transistor;

[0008] forming a capacitor on the first transistor; wherein the capacitor comprises a first electrode, a dielectric layer and a second electrode;

[0009] A second transistor is formed on the capacitor; wherein the source or drain of the first transistor is connected to the second electrode of the capacitor, and the gate of the second transistor is connected to the second electrode of the capacitor.

[0010] In some embodiments, the first transistor is a write transistor and the second transistor is a read transistor.

[0011] In some embodiments, forming the first transistor includes:

[0012] providing a first semiconductor layer;

[0013] Etching the first semiconductor layer to form a semiconductor column; the semiconductor column has two opposite ends and a channel region between the two ends in a direction perpendicular to the first semiconductor layer; the two opposite ends of the semiconductor column form a source or a drain respectively;

[0014] forming a first gate dielectric layer at least covering the sidewalls of the channel region of the semiconductor column;

[0015] A first gate layer is formed to cover at least a portion of the sidewall of the first gate dielectric layer.

[0016] In some embodiments, before forming a capacitor on the first transistor, the manufacturing method further includes:

[0017] A contact plug is formed on one end of the semiconductor column away from the first semiconductor layer; wherein the orthographic projection area of ​​the end of the contact plug away from the semiconductor column on the first semiconductor layer is larger than the orthographic projection area of ​​the end of the contact plug close to the semiconductor column on the first semiconductor layer; and the source or drain of the first transistor is connected to the second electrode through the contact plug.

[0018] In some embodiments, forming a capacitor on the first transistor includes:

[0019] A stacked structure is formed on the first transistor; the stacked structure comprises conductive layers and insulating layers stacked alternately; each conductive layer forms a sub-electrode, and a plurality of sub-electrodes together form a first electrode of the capacitor;

[0020] forming a capacitor hole penetrating the stacked structure and exposing the contact plug;

[0021] forming a dielectric layer covering the sidewalls of the capacitor hole;

[0022] A conductive material is filled in the capacitor hole to form a second electrode.

[0023] In some embodiments, forming a second transistor on the capacitor includes:

[0024] forming a first isolation layer, a source layer, and a second isolation layer in sequence on the capacitor;

[0025] forming a first sub-channel hole penetrating the second isolation layer and the source layer and exposing the first isolation layer;

[0026] forming a channel layer covering the sidewalls of the first sub-channel hole; the channel layer is connected to the source layer;

[0027] A second sub-channel hole is etched through the first sub-channel hole to penetrate the first isolation layer and expose the second electrode; wherein the first sub-channel hole and the second sub-channel hole are connected, and the first sub-channel hole and the second sub-channel hole together form a channel hole.

[0028] In some embodiments, after etching through the first sub-channel hole to form a second sub-channel hole penetrating the first isolation layer and exposing the second electrode, the manufacturing method further includes:

[0029] forming a second gate dielectric layer covering the sidewalls of the channel hole;

[0030] Filling a conductive material in the channel hole to form a second gate layer;

[0031] Part of the second gate dielectric layer and the second gate layer is removed, and a third isolation layer and a drain layer are sequentially formed in the first sub-channel hole; wherein the drain layer and the channel layer are connected; and the capacitor, the first transistor and the second transistor together form a first semiconductor structure.

[0032] In some embodiments, the manufacturing method further comprises:

[0033] Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer;

[0034] After forming the second transistor on the capacitor, the manufacturing method further includes:

[0035] The first semiconductor structure and the second semiconductor structure are bonded; wherein the second transistor is located between the capacitor and the peripheral circuit.

[0036] In some embodiments, after bonding the first semiconductor structure and the second semiconductor structure, the manufacturing method further includes:

[0037] Thinning the first semiconductor layer from the back side until an end of the semiconductor column away from the capacitor is exposed;

[0038] A bit line is formed, and a drain or a source of the first transistor is connected to the bit line.

[0039] In some embodiments, after forming the second transistor on the capacitor, the manufacturing method further includes:

[0040] The first semiconductor structure and the substrate are bonded; wherein the second transistor is located between the capacitor and the substrate.

[0041] In some embodiments, the manufacturing method further comprises:

[0042] Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer;

[0043] After bonding the first semiconductor structure and the substrate, the manufacturing method further includes:

[0044] Thinning the first semiconductor layer from the back side until an end of the semiconductor column away from the capacitor is exposed;

[0045] forming a bit line, wherein the drain or source of the first transistor is connected to the bit line;

[0046] The first semiconductor structure and the second semiconductor structure are bonded; wherein the first transistor is located between the capacitor and the peripheral circuit.

[0047] In some embodiments, the material of the channel region of the semiconductor pillar includes single crystal silicon; and / or,

[0048] The material of the channel layer includes indium gallium zinc oxide (IGZO); and / or,

[0049] The material of the dielectric layer includes ferroelectric material.

[0050] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising: a first semiconductor structure, the first semiconductor structure comprising:

[0051] A capacitor, the capacitor comprising a first electrode, a dielectric layer, and a second electrode;

[0052] a first transistor, wherein a source or a drain of the first transistor is connected to the second electrode; and a channel material of the first transistor comprises single crystal silicon;

[0053] A second transistor, wherein a gate of the second transistor is connected to the second electrode.

[0054] In some embodiments, the first transistor is a write transistor and the second transistor is a read transistor.

[0055] In some embodiments, the semiconductor device further comprises:

[0056] A second semiconductor structure bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; wherein the first transistor is located between the capacitor and the peripheral circuit; or, the second transistor is located between the capacitor and the peripheral circuit.

[0057] In some embodiments, the first semiconductor structure further comprises:

[0058] A stacked structure, comprising conductive layers and insulating layers stacked alternately; each of the conductive layers forms a sub-electrode, and a plurality of the sub-electrodes together form a first electrode of the capacitor;

[0059] The dielectric layer and the second electrode penetrate through the stacked structure, and the dielectric layer surrounds the second electrode.

[0060] In some embodiments, the first transistor comprises:

[0061] A semiconductor column extending in a stacking direction, wherein the semiconductor column has two opposite ends and a channel region between the two ends in the extending direction, and the two opposite ends of the semiconductor column respectively form a source or a drain; wherein the channel region comprises a channel material; and the drain or source of the first transistor is connected to a bit line;

[0062] A first gate dielectric layer at least covering the sidewalls of the channel region of the semiconductor column;

[0063] A first gate layer at least covers a portion of the sidewalls of the first gate dielectric layer.

[0064] In some embodiments, the first semiconductor structure further comprises:

[0065] A contact plug is located between the semiconductor column of the first transistor and the second electrode of the capacitor; wherein a contact area between the contact plug and the second electrode is greater than a contact area between the contact plug and the semiconductor column.

[0066] In some embodiments, the second transistor comprises:

[0067] A channel layer, a second gate dielectric layer and a second gate layer; the channel layer surrounds the second gate dielectric layer, and the second gate dielectric layer surrounds the second gate layer; wherein the channel layer has two opposite ends along the extension direction, and the two opposite ends of the channel layer form a source or a drain respectively; the second gate layer is connected to the second electrode.

[0068] In some embodiments, the end of the channel layer close to the capacitor forms a source, and the end of the channel layer away from the capacitor forms a drain; the second transistor further includes:

[0069] A source layer surrounding the channel layer; the source layer and the channel layer are connected;

[0070] A drain layer is located in the channel layer; the drain layer is connected to the channel layer.

[0071] In some embodiments, the material of the channel layer includes IGZO; and / or,

[0072] The material of the dielectric layer includes ferroelectric material.

[0073] In a third aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising:

[0074] The semiconductor device as described in the above technical solution; and

[0075] A controller is coupled to the semiconductor device, the controller being configured to control the semiconductor device.

[0076] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system. The manufacturing method includes: forming a first transistor; forming a capacitor on the first transistor; wherein the capacitor includes a first electrode, a dielectric layer, and a second electrode; forming a second transistor on the capacitor; wherein the source or drain of the first transistor is connected to the second electrode of the capacitor, and the gate of the second transistor is connected to the second electrode of the capacitor. Compared with the process of forming the capacitor first and then forming the first transistor, in the embodiments of the present disclosure, the first transistor is formed first and then the capacitor is formed, which can effectively reduce the damage to the capacitor caused by the high temperature annealing process in the process of forming the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided as an example;

[0078] Figure 2 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0079] FIG. 3A to FIG. 3F A schematic diagram of a cross-sectional structure of a semiconductor device during a manufacturing process provided by an embodiment of the present disclosure;

[0080] 4A to 4F A schematic cross-sectional structure diagram of another semiconductor device during the manufacturing process provided by an embodiment of the present disclosure;

[0081] Figure 5A A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0082] Figure 5B A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0083] Figure 6 A block diagram of a memory system provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0085] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0086] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0087] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0088] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0089] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0090] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0091] refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided as an example. Figure 1 As shown, the semiconductor device 100 includes second transistors 101 (such as Figure 1 The capacitor 102 and the first transistor 103 (shown as a dotted line box) Figure 1 As shown in the dashed box, the capacitor 102 includes a first electrode 104, a dielectric layer 105 and a second electrode 106; wherein the second electrode 106 of the capacitor 102 has two opposite ends arranged along the stacking direction, and the two ends of the second electrode 106 are respectively connected to the first transistor 103 and the second transistor 101.

[0092] Exemplarily, the process of forming the semiconductor device 100 may include the following steps: Figure 1 A capacitor 102 is formed on the front side of the substrate (not shown), and the capacitor 102 includes a first electrode 104, a dielectric layer 105, and a second electrode 106; wherein the dielectric layer 105 is located between the first electrode 104 and the second electrode 106, and the second electrode 106 has two opposite ends arranged in a direction perpendicular to the substrate; a first transistor 103 is formed on the capacitor 102, and one end of the first transistor 103 and the second electrode 106 are connected; the substrate is thinned from the back side until the other end of the second electrode 106 of the capacitor 102 is exposed; a second transistor 101 is formed, and the other end of the second transistor 101 and the second electrode 106 are connected. The direction perpendicular to the substrate is the stacking direction of the second transistor 101, the capacitor 102, and the first transistor 103.

[0093] It should be noted that the first transistor may include a semiconductor column extending in a direction perpendicular to the substrate (i.e., the stacking direction), and the semiconductor column has two opposite ends along the extending direction and a channel region between the two ends; wherein the two opposite ends along the extending direction of the semiconductor column may form a source or a drain, respectively. The process of forming the first transistor may include a high-temperature annealing treatment, so that the capacitor is formed first and then the first transistor is formed, and the high-temperature annealing treatment in the process of forming the first transistor may damage the capacitor.

[0094] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0095] refer to Figure 2 , Figure 2 The flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure is as follows. Figure 2 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0096] Step S201: forming a first transistor;

[0097] Step S202: forming a capacitor on the first transistor; wherein the capacitor comprises a first electrode, a dielectric layer and a second electrode;

[0098] Step S203: forming a second transistor on the capacitor; wherein the source or drain of the first transistor is connected to the second electrode of the capacitor, and the gate of the second transistor is connected to the second electrode of the capacitor.

[0099] In the embodiment of the present disclosure, the first transistor is formed first and the capacitor is formed later. The process of forming the first transistor may include a high-temperature annealing treatment. In this way, forming the first transistor first and then forming the capacitor can effectively reduce the damage to the capacitor caused by the high-temperature annealing treatment in the process of forming the first transistor, thereby reducing the thermal budget of the capacitor process and improving the performance of the capacitor.

[0100] In the embodiment of the present disclosure, the first transistor is a write transistor (Write Transistor), and the second transistor is a read transistor (Read Transistor).

[0101] Here, the first transistor may be a write transistor, and the second transistor may be a read transistor. Functions of the first transistor and the second transistor, such as reading or writing, may be determined according to a connection relationship between the first transistor, the second transistor, and the capacitor.

[0102] Exemplarily, the write transistor includes a gate, a source and a drain, the gate of the write transistor is connected to a write word line, the drain of the write transistor is connected to a second electrode of the capacitor, and the source of the write transistor is connected to a write bit line. The read transistor also includes a gate, a source and a drain, the gate of the read transistor is connected to a second electrode of the capacitor, the source of the read transistor is connected to a source line, and the drain of the read transistor is connected to a read bit line.

[0103] Before introducing the semiconductor device and the manufacturing method thereof provided by the embodiment of the present disclosure, various directions that may be involved in the embodiment of the present disclosure are first defined. The direction perpendicular to the first semiconductor layer is defined as the Z direction, and the X direction and the Y direction are defined in the plane perpendicular to the Z direction, and the X direction and the Y direction may intersect. In a specific embodiment, the X direction and the Y direction may be perpendicular to each other, so that the X direction, the Y direction and the Z direction may be perpendicular to each other.

[0104] refer to FIG. 3A to FIG. 3F , FIG. 3A to FIG. 3F A schematic diagram of a cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. FIG. 3A to FIG. 3F The manufacturing process of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0105] like Figure 3A As shown, in the embodiment of the present disclosure, step S201 includes:

[0106] Providing a first semiconductor layer 200;

[0107] The first semiconductor layer 200 is etched along a direction perpendicular to the first semiconductor layer 200 (ie, the Z direction) to form a semiconductor column 201 (eg, Figure 3A The semiconductor column 201 has two opposite ends and a channel region 202 located between the two ends in a direction perpendicular to the first semiconductor layer 200; the two opposite ends of the semiconductor column 201 respectively form a source 203 of the first transistor or a drain 204 of the first transistor; wherein the source 203 of the first transistor and the drain 204 of the first transistor can be formed by doping in subsequent process steps;

[0108] forming a first gate dielectric layer 205 at least covering the sidewalls of the channel region 202 of the semiconductor pillar 201;

[0109] A first gate layer 206 is formed to cover at least a portion of the sidewall of the first gate dielectric layer 205 .

[0110] Here, the first semiconductor layer may be a semiconductor substrate. The material of the first semiconductor layer may be, for example, silicon.

[0111] Exemplarily, the process of forming a semiconductor column may include the following steps: partially etching the first semiconductor layer along the Z direction to form a grid-shaped etching groove and a semiconductor column array. The semiconductor column array includes a plurality of semiconductor columns arranged in an array, and the height of the semiconductor column along the Z direction is less than the height of the first semiconductor layer along the Z direction. The row arrangement direction of the semiconductor column array may be along the X direction, and the column arrangement direction of the semiconductor column array may be along the Y direction. For ease of explanation, Figure 3A Only one semiconductor column is used for illustration. In fact, the embodiment of the present disclosure has no particular limitation on the number of semiconductor columns.

[0112] Here, the first semiconductor layer may be etched using, but not limited to, wet etching, dry etching, or a combination thereof, to form a semiconductor column. The etching depth is less than the height of the first semiconductor layer along the Z direction. In other words, the etching process does not penetrate the first semiconductor layer. Exemplarily, the first semiconductor layer may be etched using a process such as plasma dry etching to form a semiconductor column extending along the Z direction.

[0113] Here, the orthographic projection of the semiconductor column on the first semiconductor layer (ie, the XY plane) may be a rectangle, a circle, or other shapes. In fact, the embodiment of the present disclosure does not specifically limit the shape of the orthographic projection of the semiconductor column on the first semiconductor layer. For ease of explanation, Figure 3A The dotted circle in the middle indicates that the orthographic projection of the semiconductor column 201 on the first semiconductor layer (ie, the XY plane) is a circle. The first gate dielectric layer 205 surrounds the semiconductor column 201 , and the first gate layer 206 surrounds the first gate dielectric layer 205 . Figure 3A The first transistor 207 shown is a gate-all-around (GAA) transistor. In the embodiment of the present disclosure, the first transistor may also be a single-gate transistor, a double-gate transistor or a triple-gate transistor.

[0114] Here, the semiconductor column has two opposite ends and a channel region between the two ends in a direction perpendicular to the first semiconductor layer; wherein the two opposite ends of the semiconductor column form a source or a drain, respectively. Exemplarily, one end of the semiconductor column away from the first semiconductor layer can be doped to form a source or a drain; subsequently, the first semiconductor layer can be thinned on the back side to expose the other end of the semiconductor column, and after doping, a drain or a source can be formed. Figure 3A An example is given for description in which one end of the semiconductor pillar 201 away from the first semiconductor layer 200 forms the drain 204 of the first transistor.

[0115] Exemplarily, the process of forming a first gate dielectric layer and a first gate electrode layer may include the following steps: filling an insulating material in a mesh-shaped etching groove to form an insulating material layer, wherein the insulating material layer is located between any two adjacent semiconductor pillars; etching and removing a portion of the insulating material layer along the Z direction to expose the sidewalls of the channel region of the semiconductor pillar; depositing a first gate dielectric layer that at least covers the sidewalls of the channel region of the semiconductor pillar; continuing to deposit a first gate electrode layer that covers the first gate dielectric layer; wherein the first gate dielectric layer and the first gate electrode layer together form a first gate structure.

[0116] In the embodiment of the present disclosure, the process of forming the first gate dielectric layer and the first gate layer may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0117] Of course, after forming the grid-shaped etching grooves and the semiconductor pillar array, the semiconductor pillar sidewalls may be subjected to high temperature oxidation treatment to form the first gate dielectric layer. In fact, the disclosed embodiment has no special limitation on the process of forming the first gate dielectric layer and the first gate layer.

[0118] In the embodiment of the present disclosure, the material of the first gate dielectric layer may include but is not limited to oxide, and the material of the first gate layer may include but is not limited to metal, for example, tungsten.

[0119] In one embodiment, the material of the channel region 202 of the semiconductor pillar 201 includes single crystal silicon.

[0120] Here, compared with using polysilicon as the material of the channel region of the semiconductor column, using single crystal silicon as the material of the channel region of the semiconductor column has a smaller leakage current of the single crystal silicon material, and the first transistor can be completely turned off. Exemplarily, when the first transistor is a write transistor, during the read operation, the first transistor can be completely turned off to reduce the interference caused by the leakage of the first transistor to the read operation.

[0121] In the embodiment of the present disclosure, before step S202, the manufacturing method further includes:

[0122] A contact plug 208 is formed on one end of the semiconductor column 201 away from the first semiconductor layer 200; wherein the orthographic projection area of ​​the end of the contact plug 208 away from the semiconductor column 201 on the first semiconductor layer 200 (i.e., the XY plane) is larger than the orthographic projection area of ​​the end of the contact plug 208 close to the semiconductor column 201 on the first semiconductor layer 200; the source 203 of the first transistor or the drain 204 of the first transistor is connected to the second electrode through the contact plug 208.

[0123] Here, a contact plug is formed, and the contact area between the contact plug and the source or drain of the first transistor is smaller than the contact area between the contact plug and the second electrode of the capacitor. Compared with directly forming a capacitor on the first transistor, forming the capacitor after forming the contact plug on the first transistor can make it easier for the capacitor hole formed by etching to stop on the first transistor, and the contact area between the contact plug and the second electrode of the capacitor is increased, which can also reduce the contact resistance. Figure 3A The contact between the contact plug 208 and the drain 204 of the first transistor is taken as an example for description.

[0124] Exemplarily, the process of forming a contact plug may include the following steps: forming an insulating material layer on the first transistor; etching the insulating material layer to form a contact groove exposing the drain of the semiconductor column; wherein the contact groove appears to be wide at the top and narrow at the bottom in the cross-sectional structural schematic diagram; and filling the contact groove to form a contact plug.

[0125] In the embodiment of the present disclosure, the material of the contact plug may include a conductive material, such as metal or metal silicide.

[0126] In the embodiment of the present disclosure, step S202 includes:

[0127] A stacked structure 209 is formed on the first transistor 207; the stacked structure 209 includes conductive layers 210 and insulating layers 211 that are alternately stacked; each conductive layer 210 forms a sub-electrode 212, and the plurality of sub-electrodes 212 together form a first electrode 217 of the capacitor 216;

[0128] Forming a capacitor hole 213 penetrating the stacked structure 209 and exposing the contact plug 208;

[0129] forming a dielectric layer 215 covering the sidewall of the capacitor hole 213;

[0130] The capacitor hole 213 is filled with a conductive material to form a second electrode 218 .

[0131] like Figure 3B As shown, a stacked structure 209 is formed on the first transistor 207, and the stacked structure 209 includes alternately stacked conductive layers 210 and insulating layers 211; along the Z direction, the stacked structure 209 is etched to form a capacitor hole 213 that penetrates the stacked structure 209 and exposes the contact plug 208; wherein the sidewall of the capacitor hole 213 exposes the insulating layer 211 and the conductive layer 210; and a dielectric material layer 214 is formed to cover the bottom and sidewalls of the capacitor hole 213.

[0132] For ease of explanation, Figure 3BOnly two conductive layers 210 are shown, and two sub-electrodes 212 may be formed later, and the two sub-electrodes 212 together constitute the first electrode 217. In fact, the number and thickness of the conductive layer and the insulating layer in the embodiment of the present disclosure are not limited thereto. Those skilled in the art can set the appropriate number and thickness of the conductive layer and the insulating layer according to actual needs. In a specific embodiment, the material of the conductive layer may include but is not limited to a metal material, and the material of the insulating layer may include but is not limited to an oxide.

[0133] Combination Figure 3B and Figure 3C As shown, the dielectric material layer 214 covering the bottom of the capacitor hole 213 is removed to expose the contact plug 208 , and the remaining dielectric material layer forms a dielectric layer 215 ; and a conductive material is filled in the capacitor hole 213 to form a second electrode 218 .

[0134] For example, after the capacitor hole is filled with the conductive material, the conductive material layer may be planarized to expose the stacked structure. At this time, the remaining conductive material layer forms the second electrode, and the surface of the second electrode is substantially flush with the surface of the stacked structure.

[0135] In the embodiment of the present disclosure, the material of the dielectric layer may include ferroelectric material, so the capacitor may be a ferroelectric capacitor. In this way, the semiconductor device provided by the embodiment of the present disclosure includes a first transistor, a second transistor and a capacitor, forming a two-transistor-one-capacitor (2T1C) architecture. It should be noted that the laminated structure includes conductive layers and insulating layers alternately stacked, each conductive layer forms a sub-electrode, and a plurality of sub-electrodes together form the first electrode of the capacitor. In other words, the ferroelectric capacitor provided by the embodiment of the present disclosure may include a plurality of sub-capacitors, thereby increasing the storage capacity of the semiconductor device.

[0136] like Figure 3D As shown, in the embodiment of the present disclosure, step S203 includes:

[0137] A first isolation layer 219, a source layer 220 and a second isolation layer 221 are sequentially formed on the capacitor 216;

[0138] forming a first sub-channel hole 222 penetrating the second isolation layer 221 and the source layer 220 and exposing the first isolation layer 219;

[0139] A channel layer 223 is formed to cover the sidewall of the first sub-channel hole 222; the channel layer 223 is connected to the source layer 220;

[0140] A second sub-channel hole 225 is etched through the first sub-channel hole 222 to penetrate the first isolation layer 219 and expose the second electrode 218 ; wherein the first sub-channel hole 222 and the second sub-channel hole 225 are connected to form a channel hole 226 together.

[0141] Exemplarily, along the Z direction, the second isolation layer and the source layer are etched in sequence to form a first sub-channel hole; wherein the first sub-channel hole penetrates the second isolation layer and the source layer and exposes the first isolation layer; a channel material layer covering the bottom and side walls of the first sub-channel hole is formed; the channel material layer covering the bottom of the first sub-channel hole is removed, and the channel material layer covering the side walls of the first sub-channel hole is retained to form a channel layer; wherein the channel layer has two oppositely arranged ends along the Z direction, which can form a source or a drain, respectively.

[0142] Exemplarily, a second sub-channel hole penetrating the first isolation layer and exposing the second electrode is formed by etching along the Z direction through the first sub-channel hole; wherein the first sub-channel hole and the second sub-channel hole are connected to form a channel hole together.

[0143] Still Figure 3D As shown, in the embodiment of the present disclosure, after etching through the first sub-channel hole 222 to form a second sub-channel hole 225 penetrating the first isolation layer 219 and exposing the second electrode 218, the manufacturing method further includes:

[0144] forming a second gate dielectric layer 227 covering the sidewalls of the channel hole 226;

[0145] A conductive material is filled in the channel hole 226 to form a second gate layer 228; the second gate dielectric layer 227 is located between the channel layer 223 and the second gate layer 228;

[0146] Part of the second gate dielectric layer 227 and the second gate layer 228 is removed, and a third isolation layer 230 and a drain layer 231 are sequentially formed in the first sub-channel hole 222; wherein the drain layer 231 and the channel layer 223 are connected; the capacitor 216, the first transistor 207 and the second transistor 229 together form a first semiconductor structure 233.

[0147] Exemplarily, a second gate dielectric material layer covering the bottom and sidewalls of the channel hole is formed; the second gate dielectric material layer covering the bottom of the channel hole is removed, and the second gate dielectric material layer covering the sidewalls of the channel hole is retained to form a second gate dielectric layer; a conductive material is filled in the channel hole to form a second gate layer. At this time, the surface of the second gate dielectric layer, the surface of the second gate layer, the surface of the second isolation layer, and the surface of the channel layer are substantially flush. Along the Z direction, a portion of the second gate dielectric layer and the second gate layer are etched and removed. At this time, the surfaces of the second gate dielectric layer and the second gate layer are substantially flush, and the surfaces of the second gate dielectric layer and the second gate layer are lower than the surface of the channel layer. A third isolation layer and a drain layer can be sequentially formed in the first sub-channel hole, and the surface of the drain layer is substantially flush with the surface of the channel layer. Figure 3DIt is shown that the channel layer 223 surrounds the second gate layer 228 , and the second transistor 229 is a (Channel-All-Around, CAA) transistor.

[0148] For ease of explanation, Figure 3D The middle dashed box indicates that the channel hole 226 includes a first sub-channel hole 222 and a second sub-channel hole 225 that are connected; Figure 3D The dotted line box illustrates the relative position relationship among the channel layer 223 , the source layer 220 , and the drain layer 231 . Figure 3D The dotted line box indicates that the source layer 220 surrounds the channel layer 223, and the portion of the channel layer 223 in contact with the source layer 220 forms the source 224 of the second transistor (eg, Figure 3D Indicated by the dashed box in the middle); Figure 3D The dotted line box also indicates that the channel layer 223 surrounds the drain layer 231, and the portion of the channel layer 223 in contact with the drain layer 231 forms the drain 232 of the second transistor (eg, Figure 3D (shown in the dotted circle).

[0149] In the embodiment of the present disclosure, the material of the channel layer 223 may include Indium Gallium Zinc Oxide (IGZO).

[0150] Here, the material of the channel layer of the second transistor may include IGZO. Thus, the process of forming the second transistor does not include high-temperature annealing. Even if the capacitor is formed first and then the second transistor, the process of forming the second transistor will not damage the capacitor.

[0151] In the embodiment of the present disclosure, the material of the source layer and the drain layer may include a conductive material. The material of the first isolation layer, the second isolation layer and the third isolation layer may include but is not limited to oxides, such as silicon oxide. The material of the second gate dielectric layer may include but is not limited to oxides, and the material of the second gate layer may include but is not limited to metals, such as tungsten.

[0152] Compared with the ferroelectric random access memory (FerroelectricRAM, FeRAM) of 1T1C or multi-C architecture in the related technical solution, the ferroelectric effect of ferroelectric materials is used to realize data storage. Specifically, a certain electric field is applied to the ferroelectric crystal, and the central atom of the crystal moves under the action of the electric field and reaches a stable state; when the electric field is removed, the central atom of the crystal will still remain in its original position, so that the ferroelectric memory has non-volatile storage characteristics. In other words, the ferroelectric memory realizes the data storage function not through the charge stored on the capacitor, but through the central atom position of the ferroelectric crystal in the capacitor. The reading operation process is as follows: a certain electric field is applied to the capacitor. If the original position of the central atom of the crystal and the direction of the applied electric field make the central atom of the crystal the same as the position to be reached by the central atom of the crystal, then the central atom of the crystal will not move; if the opposite is true, then the central atom of the crystal will move. According to whether the central atom of the crystal moves, it can be judged whether the capacitor stores "1" or "0". During the reading operation, the position of the central atom of the crystal may move. In short, the reading operation in the ferroelectric random access memory is destructive, and a write-back operation is required after the reading operation.

[0153] In the disclosed embodiment, the drain of the first transistor (i.e., the write transistor) is connected to the second electrode of the capacitor, and the gate of the second transistor (i.e., the read transistor) is connected to the second electrode of the capacitor; wherein the connection node between the drain of the write transistor, the gate of the read transistor and the second electrode of the capacitor forms a floating node. During the write operation, a write voltage Vw is applied to the gate of the write transistor, so that the write transistor is turned on, and the voltage at the floating node is the write voltage Vw, so that it is in a certain storage state, thereby completing the write operation; during the read operation, the write transistor is turned off, and the input voltage Vin is applied to the first electrode of the capacitor, so that the voltage at the floating node is (Vin+Vw), and the output voltage Vout is applied to the source of the read transistor, and an output current is generated in the read transistor, and the magnitude of the output current is affected by the voltage at the floating node. That is to say, when the input voltage Vin remains unchanged, the write voltage Vw determines the output current. Therefore, the storage state can be judged according to the output current value.

[0154] The read operation in the semiconductor device provided by the present disclosure is non-destructive, and data is read by reading the output current value. However, in this read operation, the write transistor needs to be completely turned off, that is, this read operation has high requirements for the leakage of the write transistor. Therefore, using single crystal silicon as the channel region material of the semiconductor column of the write transistor can effectively reduce the leakage current.

[0155] In the embodiment of the present disclosure, the manufacturing method further includes:

[0156] Providing a second semiconductor structure 234, the second semiconductor structure 234 comprising a second semiconductor layer 235 and a peripheral circuit 236 located on the second semiconductor layer 235;

[0157] After forming the second transistor 229 on the capacitor 216, the manufacturing method further includes:

[0158] The first semiconductor structure 233 and the second semiconductor structure 234 are bonded; wherein the second transistor 229 is located between the capacitor 216 and the peripheral circuit 236 .

[0159] like Figure 3D As shown, the first semiconductor structure 233 and the second semiconductor structure 234 are bonded, that is, the second semiconductor structure 234 is located on the front side of the first semiconductor layer 200; wherein the second semiconductor structure 234 includes a second semiconductor layer 235 and a peripheral circuit 236 located on the second semiconductor layer 235, so that the second transistor 229 is located between the capacitor 216 and the peripheral circuit 236.

[0160] In the embodiment of the present disclosure, a memory cell array can be formed on the first semiconductor layer, the memory cell array includes a plurality of memory cells arranged in an array, the memory cell may include a first transistor, a second transistor and a capacitor, and a peripheral circuit can be formed on the second semiconductor layer; by bonding the first semiconductor structure and the second semiconductor structure, the memory cell array and the peripheral circuit can be integrated to reduce manufacturing costs.

[0161] In the embodiment of the present disclosure, after bonding the first semiconductor structure 233 and the second semiconductor structure 234, the manufacturing method further includes:

[0162] The first semiconductor layer 200 is thinned from the back side until an end of the semiconductor pillar 201 away from the capacitor 216 is exposed;

[0163] A bit line 238 is formed, and the drain 204 of the first transistor or the source 203 of the first transistor is connected to the bit line.

[0164] Combination Figure 3D and Figure 3E As shown, the bonded first semiconductor structure 233 and the second semiconductor structure 234 are turned over, and the first semiconductor layer 200 is thinned from the back until the end of the semiconductor pillar 201 away from the capacitor 216 is exposed. At this time, the end of the semiconductor pillar 201 away from the capacitor 216 can be doped to form the source 203 of the first transistor (such as Figure 3E shown in the dashed box).

[0165] In the embodiment of the present disclosure, the thinning process may be chemical mechanical polishing (CMP).

[0166] like Figure 3F As shown, a fourth isolation layer 237 can be formed on the semiconductor pillar 201, and a bit line groove that penetrates the fourth isolation layer 237 and exposes the source 203 of the first transistor is formed by etching along the stacking direction; a conductive material is filled in the bit line groove to form a bit line 238, wherein the source 203 of the first transistor and the bit line 238 are connected.

[0167] In the embodiment of the present disclosure, the material of the fourth isolation layer may be oxide, such as silicon oxide.

[0168] refer to 4A to 4F , 4A to 4F A schematic diagram of a cross-sectional structure of another semiconductor device during the manufacturing process provided by the embodiment of the present disclosure. 4A to 4F The manufacturing process of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0169] As mentioned earlier, FIG. 3A to FIG. 3F In the manufacturing process of the illustrated semiconductor device, after the first transistor, the capacitor and the second transistor of the first semiconductor structure are formed in sequence, the first semiconductor structure and the second semiconductor structure are bonded. At this time, the peripheral circuit of the second semiconductor structure is located on the front side of the first semiconductor layer, that is, the second transistor is located between the capacitor and the peripheral circuit. 4A to 4F In the manufacturing process of the illustrated semiconductor device, after the first transistor, the capacitor and the second transistor of the first semiconductor structure are formed in sequence, the first semiconductor structure and the second semiconductor structure are bonded. At this time, the peripheral circuit of the second semiconductor structure is located on the back side of the first semiconductor layer, that is, the first transistor is located between the capacitor and the peripheral circuit.

[0170] like Figure 4A As shown, step S201 includes: providing a first semiconductor layer 300;

[0171] The first semiconductor layer 300 is etched to form a semiconductor column 301 (eg Figure 4A The semiconductor column 301 has two opposite ends and a channel region 302 between the two ends in a direction perpendicular to the first semiconductor layer 300; the two opposite ends of the semiconductor column 301 respectively form a source 303 of the first transistor or a drain 304 of the first transistor;

[0172] forming a first gate dielectric layer 305 at least covering the sidewalls of the channel region 302 of the semiconductor pillar 301;

[0173] A first gate layer 306 is formed to cover at least a portion of the sidewall of the first gate dielectric layer 305 .

[0174] For ease of explanation, Figure 4AIt is taken as an example that one end of the semiconductor pillar 301 away from the first semiconductor layer 300 forms the drain 304 of the first transistor.

[0175] Still Figure 4A As shown, before step S202, the manufacturing method further includes:

[0176] A contact plug 308 is formed on one end of the semiconductor column 301 away from the first semiconductor layer 300; wherein the orthographic projection area of ​​the end of the contact plug 308 away from the semiconductor column 301 on the first semiconductor layer 300 is larger than the orthographic projection area of ​​the end of the contact plug 308 close to the semiconductor column 301 on the first semiconductor layer 300; the source 303 of the first transistor or the drain 304 of the first transistor is connected to the second electrode through the contact plug 308.

[0177] like Figure 4B and Figure 4C As shown, step S202 includes:

[0178] A stacked structure 309 is formed on the first transistor; the stacked structure 309 includes conductive layers 310 and insulating layers 311 that are alternately stacked; each conductive layer 310 forms a sub-electrode 312, and a plurality of sub-electrodes 312 together form a first electrode 317 of a capacitor 316;

[0179] A capacitor hole 313 is formed which penetrates the stacked structure 309 and exposes the contact plug 308;

[0180] Forming a dielectric material layer 314 covering the bottom and sidewalls of the capacitor hole 313;

[0181] Removing the dielectric material layer covering the bottom of the capacitor hole 313 to form a dielectric layer 315;

[0182] The capacitor hole 313 is filled with a conductive material to form a second electrode 318 .

[0183] like Figure 4D As shown, step S203 includes:

[0184] A first isolation layer 319, a source layer 320 and a second isolation layer 321 are sequentially formed on the capacitor 316;

[0185] forming a first sub-channel hole 322 penetrating the second isolation layer 321 and the source layer 320 and exposing the first isolation layer 319;

[0186] A channel layer 323 is formed to cover the sidewall of the first sub-channel hole 322; the channel layer 323 is connected to the source layer 320;

[0187] A second sub-channel hole 325 is etched through the first sub-channel hole 322 to penetrate the first isolation layer 319 and expose the second electrode 318 ; wherein the first sub-channel hole 322 and the second sub-channel hole 325 are connected to form a channel hole 326 together.

[0188] Still Figure 4D As shown, after etching through the first sub-channel hole 322 to form a second sub-channel hole 325 penetrating the first isolation layer 319 and exposing the second electrode 318, the manufacturing method further includes:

[0189] forming a second gate dielectric layer 327 covering the sidewalls of the channel hole 326;

[0190] Filling the channel hole 326 with a conductive material to form a second gate layer 328;

[0191] Part of the second gate dielectric layer 327 and the second gate layer 328 are removed, and a third isolation layer 330 and a drain layer 331 are sequentially formed in the first sub-channel hole 322; wherein the drain layer 331 and the channel layer 323 are connected, and the capacitor 316, the first transistor 307 and the second transistor 329 together form a first semiconductor structure 333.

[0192] For ease of explanation, Figure 4D The middle dashed box indicates that the channel hole 326 includes a first sub-channel hole 322 and a second sub-channel hole 325 that are connected; Figure 4D The dotted line box illustrates the relative position relationship among the channel layer 323 , the source layer 320 and the drain layer 331 . Figure 4D The dotted line box indicates that the source layer 320 surrounds the channel layer 323, and the portion of the channel layer 323 in contact with the source layer 320 forms the source 324 of the second transistor (eg, Figure 4D Indicated by the dashed box in the middle); Figure 4D The dotted line box also indicates that the channel layer 323 surrounds the drain layer 331, and the portion of the channel layer 323 in contact with the drain layer 331 forms the drain 332 of the second transistor (eg, Figure 4D (shown in the dotted circle).

[0193] In the embodiment of the present disclosure, after forming the second transistor 329 on the capacitor 316, the manufacturing method further includes:

[0194] The first semiconductor structure 333 and the substrate 339 are bonded; wherein the second transistor 329 is located between the capacitor 316 and the substrate 339 .

[0195] like Figure 4DAs shown, a bonding substrate 339 is bonded on the first semiconductor structure 333, and the second transistor 329 is located between the capacitor 316 and the substrate 339. The bonding substrate 339 is used to support the first semiconductor layer 300 when performing backside processing.

[0196] In the embodiment of the present disclosure, the manufacturing method further includes:

[0197] Providing a second semiconductor structure 334, the second semiconductor structure 334 includes a second semiconductor layer 335 and a peripheral circuit 336 located on the second semiconductor layer 335;

[0198] After bonding the first semiconductor structure 333 and the substrate 339, the manufacturing method further includes:

[0199] The first semiconductor layer 300 is thinned from the back side until an end of the semiconductor pillar 301 away from the capacitor 316 is exposed;

[0200] A bit line 338 is formed, and the drain 304 of the first transistor or the source 303 of the first transistor is connected to the bit line 338;

[0201] The first semiconductor structure 333 and the second semiconductor structure 334 are bonded; wherein the first transistor 307 is located between the capacitor 316 and the peripheral circuit 336 .

[0202] Combination Figure 4D and Figure 4E As shown, the bonded first semiconductor structure 333 and substrate 339 are turned over, and the substrate 339 is used as a support plate to thin the first semiconductor layer 300 from the back side until the end of the semiconductor column 301 away from the capacitor 316 is exposed. At this time, the end of the semiconductor column 301 away from the capacitor 316 can be doped to form the source 303 of the first transistor (such as Figure 4E shown in the dashed box).

[0203] like Figure 4F As shown, a fourth isolation layer 337 is formed on the semiconductor pillar 301, and a source electrode 303 of the first transistor is exposed by etching along the stacking direction to penetrate the fourth isolation layer 337 (as shown in FIG. Figure 4F A bit line groove is formed in the bit line groove (shown in the dashed box); a conductive material is filled in the bit line groove to form a bit line 338, wherein the source 303 of the first transistor is connected to the bit line 338.

[0204] Still Figure 4F As shown, the first semiconductor structure 333 and the second semiconductor structure 334 are bonded, and the second semiconductor structure 334 includes a second semiconductor layer 335 and a peripheral circuit 336 located on the second semiconductor layer 335 ; at this time, the first transistor 307 is located between the capacitor 316 and the peripheral circuit 336 .

[0205] refer to Figure 5A , Figure 5A A schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present disclosure. Figure 5A Corresponding to FIG. 3A to FIG. 3F The cross-sectional structure diagram of the formed semiconductor device is shown in FIG. 1 , that is, the second transistor is located between the capacitor and the peripheral circuit. Figure 5A As shown, the embodiment of the present disclosure provides a semiconductor device, the semiconductor device includes: a first semiconductor structure 233, the first semiconductor structure 233 includes:

[0206] Capacitor 216, capacitor 216 includes a first electrode 217, a dielectric layer 215 and a second electrode 218;

[0207] A first transistor 207, a source 203 of the first transistor or a drain 204 of the first transistor is connected to the second electrode 218; a channel material of the first transistor 207 includes single crystal silicon;

[0208] The second transistor 229, the gate of the second transistor (ie, Figure 5A The second gate layer 228 (shown in FIG. 1 ) is connected to the second electrode 218.

[0209] In the embodiment of the present disclosure, the first transistor 207 is a write transistor, and the second transistor 229 is a read transistor.

[0210] In the embodiment of the present disclosure, the semiconductor device further includes:

[0211] The second semiconductor structure 234 is bonded to the first semiconductor structure 233 , and the second semiconductor structure 234 includes a second semiconductor layer 235 and a peripheral circuit 236 located on the second semiconductor layer 235 ; the second transistor 229 is located between the capacitor 216 and the peripheral circuit 236 .

[0212] In the embodiment of the present disclosure, the first semiconductor structure 233 further includes:

[0213] The stacked structure 209 includes conductive layers 210 and insulating layers 211 stacked alternately; each conductive layer 210 forms a sub-electrode 212, and a plurality of sub-electrodes 212 together form a first electrode 217 of a capacitor 216;

[0214] The dielectric layer 215 and the second electrode 218 penetrate the stacked structure 209 , and the dielectric layer 215 surrounds the second electrode 218 .

[0215] In the embodiment of the present disclosure, the first transistor 207 includes:

[0216] The semiconductor pillars 201 extending along the stacking direction (eg Figure 5AThe semiconductor column 201 has two opposite ends and a channel region 202 between the two ends along the extension direction, and the two opposite ends of the semiconductor column 201 respectively form a source 203 of the first transistor or a drain 204 of the first transistor; wherein the channel region 202 includes a channel material; and the drain or source of the first transistor is connected to the bit line 238;

[0217] A first gate dielectric layer 205 at least covering the sidewalls of the channel region 202 of the semiconductor pillar 201;

[0218] A first gate layer 206 at least covers a portion of the sidewall of the first gate dielectric layer 205 .

[0219] For ease of explanation, Figure 5A The dotted line box indicates that the semiconductor column 201 has two opposite ends along the extension direction and a channel region 202 located between the two ends. The drain 204 of the first transistor (eg Figure 5A The source 203 of the first transistor (shown in the dashed circle) is in contact with the contact plug 208. Figure 5A The dotted circle (shown in the middle) contacts the bit line 238.

[0220] In the embodiment of the present disclosure, the first semiconductor structure 233 further includes:

[0221] The contact plug 208 is located between the semiconductor column 201 of the first transistor 207 and the second electrode 218 of the capacitor 216 ; wherein the contact area between the contact plug 208 and the second electrode 218 is greater than the contact area between the contact plug 208 and the semiconductor column 201 .

[0222] In the embodiment of the present disclosure, the second transistor 229 includes:

[0223] A channel layer 223, a second gate dielectric layer 227 and a second gate layer 228; the channel layer 223 surrounds the second gate dielectric layer 227, and the second gate dielectric layer 227 surrounds the second gate layer 228; wherein the channel layer 223 has two opposite ends along the extension direction, and the two opposite ends of the channel layer 223 respectively form the source 224 of the second transistor or the drain 232 of the second transistor; the second gate layer 228 is connected to the second electrode 218.

[0224] In the embodiment of the present disclosure, one end of the channel layer 223 close to the capacitor forms a source, and one end of the channel layer 223 away from the capacitor forms a drain; the second transistor 229 further includes:

[0225] A source layer 220 surrounding the channel layer 223; the source layer 220 and the channel layer 223 are connected;

[0226] The drain layer 231 is located in the channel layer 223 ; the drain layer 231 and the channel layer 223 are connected.

[0227] For ease of explanation, Figure 5A The dotted line box illustrates the relative position relationship among the channel layer 223 , the source layer 220 , and the drain layer 231 . Figure 5A The dotted line box indicates that the source layer 220 surrounds the channel layer 223, and the portion of the channel layer 223 in contact with the source layer 220 forms the source 224 of the second transistor (eg, Figure 5A Indicated by the dashed box in the middle); Figure 5A The dotted line box also indicates that the channel layer 223 surrounds the drain layer 231, and the portion of the channel layer 223 in contact with the drain layer 231 forms the drain 232 of the second transistor (eg, Figure 5A (shown in the dotted circle).

[0228] In the embodiment of the present disclosure, the material of the channel layer 223 includes IGZO; and / or,

[0229] The material of the dielectric layer 215 includes ferroelectric material.

[0230] refer to Figure 5B , Figure 5B A schematic diagram of the cross-sectional structure of another semiconductor device provided in an embodiment of the present disclosure. Figure 5B Corresponding to 4A to 4F The cross-sectional structure diagram of the formed semiconductor device is shown in FIG. 1 , that is, the second transistor is located between the capacitor and the peripheral circuit. Figure 5B As shown, the embodiment of the present disclosure provides a semiconductor device, the semiconductor device includes: a first semiconductor structure 333, the first semiconductor structure 333 includes:

[0231] Capacitor 316, capacitor 316 includes a first electrode 317, a dielectric layer 315 and a second electrode 318;

[0232] A first transistor 307, a source 303 of the first transistor or a drain 304 of the first transistor is connected to a second electrode 318; a channel material of the first transistor 307 includes single crystal silicon;

[0233] The second transistor 329 has a gate connected to the second electrode 318 .

[0234] In the embodiment of the present disclosure, the first transistor 307 is a write transistor, and the second transistor 329 is a read transistor.

[0235] In the embodiment of the present disclosure, the semiconductor device further includes:

[0236] The second semiconductor structure 334 is bonded to the first semiconductor structure 333 , and the second semiconductor structure 334 includes a second semiconductor layer 335 and a peripheral circuit 336 located on the second semiconductor layer 335 ; wherein the first transistor 307 is located between the capacitor 316 and the peripheral circuit 336 .

[0237] In the embodiment of the present disclosure, the first semiconductor structure 333 further includes:

[0238] The stacked structure 309 includes conductive layers 310 and insulating layers 311 stacked alternately; each conductive layer forms a sub-electrode 312, and the multiple sub-electrodes 312 together form a first electrode 317 of a capacitor 316;

[0239] The dielectric layer 315 and the second electrode 318 penetrate the stacked structure 309 , and the dielectric layer 315 surrounds the second electrode 318 .

[0240] In the embodiment of the present disclosure, the first transistor 307 includes:

[0241] A semiconductor column 301 extending in a stacking direction, wherein the semiconductor column 301 has two opposite ends and a channel region 302 located between the two ends in the extending direction, wherein the two opposite ends of the semiconductor column 301 respectively form a source 303 of a first transistor or a drain 304 of the first transistor; wherein the channel region comprises a channel material; and the drain 304 of the first transistor or the source 303 of the first transistor is connected to a bit line 338;

[0242] A first gate dielectric layer 305 at least covering the sidewalls of the channel region of the semiconductor pillar 301;

[0243] A first gate layer 306 at least covers a portion of the sidewall of the first gate dielectric layer 305 .

[0244] For ease of explanation, Figure 5B The dotted line box indicates that the semiconductor column 301 has two opposite ends along the extension direction and a channel region 302 located between the two ends. The drain 304 of the first transistor (eg Figure 5B The source 303 of the first transistor (shown in the dashed circle) is in contact with the contact plug 308. Figure 5B The dotted circle box shows that the PCB is in contact with the bit line 338.

[0245] In the embodiment of the present disclosure, the first semiconductor structure 333 further includes:

[0246] The contact plug 308 is located between the semiconductor column 301 of the first transistor 307 and the second electrode 318 of the capacitor 316 ; wherein the contact area between the contact plug 308 and the second electrode 318 is greater than the contact area between the contact plug 308 and the semiconductor column 301 .

[0247] In the embodiment of the present disclosure, the second transistor 329 includes:

[0248] A channel layer 323, a second gate dielectric layer 327 and a second gate layer 328; the channel layer 323 surrounds the second gate dielectric layer 327, and the second gate dielectric layer 327 surrounds the second gate layer 328; wherein the channel layer 323 has two opposite ends along the extension direction, and the two opposite ends of the channel layer 323 respectively form the source 324 of the second transistor or the drain 332 of the second transistor; the second gate layer 328 is connected to the second electrode 318.

[0249] In the embodiment of the present disclosure, one end of the channel layer 323 close to the capacitor 316 forms a source, and one end of the channel layer 323 away from the capacitor 316 forms a drain 332 of the second transistor; the second transistor 329 further includes:

[0250] A source layer 320 surrounding the channel layer 323; the source layer 320 and the channel layer 323 are connected;

[0251] The drain layer 331 is located in the channel layer 323 ; the drain layer 331 and the channel layer 323 are connected.

[0252] For ease of explanation, Figure 5B The dotted line box illustrates the relative position relationship among the channel layer 323 , the source layer 320 and the drain layer 331 . Figure 5B The dotted line box indicates that the source layer 320 surrounds the channel layer 323, and the portion of the channel layer 323 in contact with the source layer 320 forms the source 324 of the second transistor (eg, Figure 5B Indicated by the dashed box in the middle); Figure 5B The dotted line box also indicates that the channel layer 323 surrounds the drain layer 331, and the portion of the channel layer 323 in contact with the drain layer 331 forms the drain 332 of the second transistor (eg, Figure 5B (shown in the dotted circle).

[0253] In the embodiment of the present disclosure, the material of the channel layer 323 includes IGZO; and / or,

[0254] The material of the dielectric layer 315 includes ferroelectric material.

[0255] refer to Figure 6 , Figure 6 A block diagram of a memory system provided by an embodiment of the present disclosure. Figure 6 As shown, the embodiment of the present disclosure provides a memory system 400, and the memory system 400 includes:

[0256] The semiconductor device 401 in the above technical solution; and

[0257] A controller 402 is coupled to the semiconductor device 401 , and the controller 402 is configured to control the semiconductor device 401 .

[0258] In the embodiments of the present disclosure, the semiconductor device may be a memory; or may be a part of a memory, that is, the semiconductor device includes a memory cell array, and the memory cell array may form a memory together with a peripheral circuit.

[0259] Among them, the memory system can be integrated into various types of storage devices, for example, included in the same package (for example, Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the memory system can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0260] In some embodiments, the controller is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0261] In other embodiments, the controller is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0262] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system. The manufacturing method includes: forming a first transistor; forming a capacitor on the first transistor; wherein the capacitor includes a first electrode, a dielectric layer, and a second electrode; forming a second transistor on the capacitor; wherein the source or drain of the first transistor is connected to the second electrode of the capacitor, and the gate of the second transistor is connected to the second electrode of the capacitor. Compared with the process of forming the capacitor first and then forming the first transistor, in the embodiments of the present disclosure, the first transistor is formed first and then the capacitor is formed, which can effectively reduce the damage to the capacitor caused by the high temperature annealing process in the process of forming the first transistor.

[0263] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0264] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: forming a first transistor; forming a capacitor on the first transistor; wherein the capacitor comprises a first electrode, a dielectric layer and a second electrode; A second transistor is formed on the capacitor; wherein the source or drain of the first transistor is connected to the second electrode of the capacitor, and the gate of the second transistor is connected to the second electrode of the capacitor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first transistor is a write transistor, and the second transistor is a read transistor.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of the first transistor comprises: providing a first semiconductor layer; Etching the first semiconductor layer to form a semiconductor column; the semiconductor column has two opposite ends and a channel region between the two ends in a direction perpendicular to the first semiconductor layer; the two opposite ends of the semiconductor column form a source or a drain respectively; forming a first gate dielectric layer at least covering the sidewalls of the channel region of the semiconductor column; A first gate layer is formed to cover at least a portion of the sidewall of the first gate dielectric layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: Before forming a capacitor on the first transistor, the manufacturing method further includes: A contact plug is formed on one end of the semiconductor column away from the first semiconductor layer; wherein the orthographic projection area of ​​the end of the contact plug away from the semiconductor column on the first semiconductor layer is larger than the orthographic projection area of ​​the end of the contact plug close to the semiconductor column on the first semiconductor layer; and the source or drain of the first transistor is connected to the second electrode through the contact plug.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The forming a capacitor on the first transistor comprises: A stacked structure is formed on the first transistor; the stacked structure comprises conductive layers and insulating layers stacked alternately; each conductive layer forms a sub-electrode, and a plurality of sub-electrodes together form a first electrode of the capacitor; forming a capacitor hole penetrating the stacked structure and exposing the contact plug; forming a dielectric layer covering the sidewalls of the capacitor hole; A conductive material is filled in the capacitor hole to form a second electrode.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The forming of a second transistor on the capacitor comprises: forming a first isolation layer, a source layer, and a second isolation layer in sequence on the capacitor; forming a first sub-channel hole penetrating the second isolation layer and the source layer and exposing the first isolation layer; forming a channel layer covering the sidewalls of the first sub-channel hole; the channel layer is connected to the source layer; A second sub-channel hole is etched through the first sub-channel hole to penetrate the first isolation layer and expose the second electrode; wherein the first sub-channel hole and the second sub-channel hole are connected, and the first sub-channel hole and the second sub-channel hole together form a channel hole.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: After etching through the first sub-channel hole to form a second sub-channel hole penetrating the first isolation layer and exposing the second electrode, the manufacturing method further includes: forming a second gate dielectric layer covering the sidewalls of the channel hole; Filling a conductive material in the channel hole to form a second gate layer; Part of the second gate dielectric layer and the second gate layer is removed, and a third isolation layer and a drain layer are sequentially formed in the first sub-channel hole; wherein the drain layer and the channel layer are connected; and the capacitor, the first transistor and the second transistor together form a first semiconductor structure.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The manufacturing method further comprises: Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; After forming the second transistor on the capacitor, the manufacturing method further includes: The first semiconductor structure and the second semiconductor structure are bonded; wherein the second transistor is located between the capacitor and the peripheral circuit.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: After bonding the first semiconductor structure and the second semiconductor structure, the manufacturing method further includes: Thinning the first semiconductor layer from the back side until an end of the semiconductor column away from the capacitor is exposed; A bit line is formed, and a drain or a source of the first transistor is connected to the bit line.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: After forming the second transistor on the capacitor, the manufacturing method further includes: The first semiconductor structure and the substrate are bonded; wherein the second transistor is located between the capacitor and the substrate.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The manufacturing method further comprises: Providing a second semiconductor structure, the second semiconductor structure comprising a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; After bonding the first semiconductor structure and the substrate, the manufacturing method further includes: Thinning the first semiconductor layer from the back side until an end of the semiconductor column away from the capacitor is exposed; forming a bit line, wherein the drain or source of the first transistor is connected to the bit line; The first semiconductor structure and the second semiconductor structure are bonded; wherein the first transistor is located between the capacitor and the peripheral circuit.

12. The method for manufacturing a semiconductor device according to claim 6, wherein: The material of the channel region of the semiconductor column includes single crystal silicon; and / or, The material of the channel layer includes indium gallium zinc oxide (IGZO); and / or, The material of the dielectric layer includes ferroelectric material.

13. A semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor structure, wherein the first semiconductor structure comprises: A capacitor, the capacitor comprising a first electrode, a dielectric layer, and a second electrode; a first transistor, wherein a source or a drain of the first transistor is connected to the second electrode; and a channel material of the first transistor comprises single crystal silicon; A second transistor, wherein a gate of the second transistor is connected to the second electrode.

14. The semiconductor device according to claim 13, characterized in that The first transistor is a write transistor, and the second transistor is a read transistor.

15. The semiconductor device according to claim 13, wherein: The semiconductor device further comprises: A second semiconductor structure bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second semiconductor layer and a peripheral circuit located on the second semiconductor layer; wherein the first transistor is located between the capacitor and the peripheral circuit; or, the second transistor is located between the capacitor and the peripheral circuit.

16. The semiconductor device according to claim 13, wherein: The first semiconductor structure further comprises: A stacked structure, comprising conductive layers and insulating layers stacked alternately; each of the conductive layers forms a sub-electrode, and a plurality of the sub-electrodes together form a first electrode of the capacitor; The dielectric layer and the second electrode penetrate through the stacked structure, and the dielectric layer surrounds the second electrode.

17. The semiconductor device according to claim 16, characterized in that The first transistor comprises: A semiconductor column extending in a stacking direction, wherein the semiconductor column has two opposite ends and a channel region between the two ends in the extending direction, and the two opposite ends of the semiconductor column respectively form a source or a drain; wherein the channel region comprises a channel material; and the drain or source of the first transistor is connected to a bit line; A first gate dielectric layer at least covering the sidewalls of the channel region of the semiconductor column; A first gate layer at least covers a portion of the sidewalls of the first gate dielectric layer.

18. The semiconductor device according to claim 17, wherein: The first semiconductor structure further comprises: A contact plug is located between the semiconductor column of the first transistor and the second electrode of the capacitor; wherein a contact area between the contact plug and the second electrode is greater than a contact area between the contact plug and the semiconductor column.

19. The semiconductor device according to claim 18, characterized in that The second transistor comprises: A channel layer, a second gate dielectric layer and a second gate layer; the channel layer surrounds the second gate dielectric layer, and the second gate dielectric layer surrounds the second gate layer; wherein the channel layer has two opposite ends along the extension direction, and the two opposite ends of the channel layer form a source or a drain respectively; the second gate layer is connected to the second electrode.

20. The semiconductor device according to claim 19, characterized in that An end of the channel layer close to the capacitor forms a source, and an end of the channel layer away from the capacitor forms a drain; the second transistor further includes: A source layer surrounding the channel layer; the source layer and the channel layer are connected; A drain layer is located in the channel layer; the drain layer is connected to the channel layer.

21. The semiconductor device according to claim 19, characterized in that The material of the channel layer includes IGZO; and / or, The material of the dielectric layer includes ferroelectric material.

22. A memory system, characterized in that: The memory system comprises: The semiconductor device according to any one of claims 13 to 21; and A controller is coupled to the semiconductor device, the controller being configured to control the semiconductor device.

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