Storage unit, memory comprising storage unit and electronic equipment comprising storage unit

Abstract

The invention provides a storage unit and a memory and electronic equipment comprising the same. The storage unit comprises a read transistor and a write transistor; the reading transistor comprises a first grid electrode with a vertically extending first part and a horizontally extending second part, a first semiconductor layer surrounding the side wall of the first part, and a first electrode layer, a first insulating layer and a second electrode layer which surround the first semiconductor layer and are arranged from bottom to top along the vertical direction; the writing transistor comprises a second grid electrode, a second semiconductor layer, a third electrode layer, a third insulating layer and a fourth electrode layer, wherein the second grid electrode is provided with a third part extending vertically and a fourth part extending horizontally; the second semiconductor layer surrounds the side wall of the third part; the third electrode layer, the third insulating layer and the fourth electrode layer surround the second semiconductor layer and are arranged from bottom to top in the vertical direction; a first distance between the second portion and the second electrode layer is smaller than a second distance between the fourth portion and the fourth electrode layer in the vertical direction. According to the device architecture, the capacitance of the storage node is improved.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a storage unit and a memory and electronic device containing the same. Background Art

[0002] The conventional dynamic random access memory (DRAM) memory cell is based on a 1T1C structure of a transistor and a capacitor. The transistor controls the read and write operations of information while the capacitor stores charge information. Since the manufacturing process of the capacitor occupies an area, there are great process challenges in increasing the memory density, and memory cells without capacitors are increasingly attracting attention. Summary of the invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] In one aspect, an exemplary embodiment of the present application provides a memory cell including a read transistor and a write transistor located above the read transistor;

[0005] The read transistor includes a first gate having a first portion extending vertically and a second portion extending horizontally, a first semiconductor layer surrounding a sidewall of the first portion, and a first electrode layer, a first insulating layer, and a second electrode layer surrounding the first semiconductor layer and arranged from bottom to top along a vertical direction;

[0006] The write transistor includes a second gate having a third portion extending vertically and a fourth portion extending horizontally, a second semiconductor layer surrounding a side wall of the third portion, and a third electrode layer, a third insulating layer, and a fourth electrode layer surrounding the second semiconductor layer and arranged from bottom to top along the vertical direction;

[0007] The first gate is electrically connected to the third electrode layer;

[0008] A first distance exists between the second electrode layer and the second portion located above the second electrode layer in the vertical direction, and a second distance exists between the fourth electrode layer and the fourth portion located above the fourth electrode layer in the vertical direction, and the first distance is smaller than the second distance.

[0009] In an exemplary embodiment, the read transistor also includes a second insulating layer located between the second portion and the second electrode layer and extending horizontally, the upper surface of the second insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a fourth insulating layer located between the fourth portion and the fourth electrode layer and extending horizontally, the upper surface of the fourth insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

[0010] In an exemplary embodiment, the read transistor further includes a first gate insulating layer located between the first semiconductor layer and the first gate and isolating the first semiconductor layer from the first gate, and the write transistor further includes a second gate insulating layer located between the second semiconductor layer and the second gate and isolating the second semiconductor layer from the second gate.

[0011] In an exemplary embodiment, the read transistor also includes a horizontal extension portion of the first gate insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second portion and the lower surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second electrode layer; the write transistor also includes a horizontal extension portion of the second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension portion of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer.

[0012] In an exemplary embodiment, the read transistor also includes a horizontal extension portion of a first gate insulating layer and a second insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a horizontal extension portion of a second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension portion of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

[0013] In an exemplary embodiment, the read transistor also includes a second insulating layer, a second extension of the first semiconductor layer, and a horizontal extension of the first gate insulating layer, which are located between the second portion and the second electrode layer and arranged from bottom to top along the vertical direction, the upper surface of the horizontal extension of the first gate insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a fourth insulating layer, a fourth extension of the second semiconductor layer, and a horizontal extension of the second gate insulating layer, which are located between the fourth portion and the fourth electrode layer and arranged from bottom to top along the vertical direction, the upper surface of the horizontal extension of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

[0014] In an exemplary embodiment, the material used for the first gate insulating layer and the second gate insulating layer is selected from one of silicon oxide, aluminum oxide, hafnium oxide, titanium oxide and zirconium oxide; the material used for the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are selected from silicon oxide or silicon oxynitride; and the thickness of the horizontal extension portion of the first gate insulating layer is less than the thickness of the first insulating layer and less than the thickness of the second insulating layer, and the thickness of the horizontal extension portion of the second gate insulating layer is less than the thickness of the third insulating layer or the thickness of the fourth insulating layer.

[0015] In an exemplary embodiment, the third electrode layer is a portion of a third extension portion of the second semiconductor layer.

[0016] In another aspect, an exemplary embodiment of the present application provides a memory, comprising the above-mentioned storage unit. The memory may be, for example, a dynamic random access memory DRAM.

[0017] On the other hand, an exemplary embodiment of the present application provides an electronic device including the above-mentioned memory.

[0018] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0019] The two transistors in the 2T0C storage unit of the present application are arranged in an asymmetric structure, that is, the thickness of the insulating layer between the lateral extension portion of the gate of the read transistor and the read word line is smaller than or much smaller than the thickness of the insulating layer between the lateral extension portion of the gate of the write transistor and the write bit line. This not only greatly improves the storage node capacitance of the read transistor and improves the reading performance, but also does not affect the performance of the write transistor.

[0020] The storage unit of the present application can also be configured so that the thickness of the insulating layer between the lateral extension portion of the gate of the write transistor and the write bit line remains unchanged, while the insulating layer between the lateral extension portion of the gate of the read transistor and the read word line is removed, that is, the read transistor is designed to have a structure without an insulating layer (interlayer insulating layer) between the semiconductor channel layer and the adjacent connection line, which can maximize the storage node capacitance of the read transistor and improve the reading performance.

[0021] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0023] Figure 1A A schematic diagram of a longitudinal structure of a storage unit provided for an exemplary embodiment of the present application;

[0024] Figure 1B An equivalent circuit diagram of a memory cell provided for an exemplary embodiment of the present application;

[0025] Figure 1C A schematic diagram comparing the storage node charge amounts of a memory cell provided in an exemplary embodiment of the present application and a memory cell in the prior art;

[0026] Figure 2 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0027] Figure 3 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0028] Figure 4 A schematic diagram of the longitudinal structure of an exemplary intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0029] Figure 5A A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0030] Figure 5BA schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of another method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0031] Figure 6 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application; and

[0032] Figure 7 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0034] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0035] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the drawings.

[0036] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0037] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.

[0039] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may be replaced with "metal film" in some cases.

[0040] In the description of this application, a transistor refers to a component including at least three terminals: a gate, a drain, and a source. A transistor has a channel layer between a drain (drain terminal, a drain region, or a drain) and a source (source terminal, a source region, or a source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the area where the current mainly flows. In this application, the terms "channel layer" and "semiconductor layer" are interchangeable.

[0041] For storage cells without capacitors, 2T storage cells are currently mostly used. Usually, a storage cell contains two transistors, a read transistor and a write transistor, wherein the gate of the read transistor serves as a storage node, and the read transistor is controlled to be in an off or on state by storing different voltages corresponding to "1" and "0". According to the off and on states of the transistor, the stored information is determined to be "1" and "0". However, the applicant of the present application has found that the storage capacity of such storage nodes needs to be improved in order to further increase the sensing margin and improve the memory performance.

[0042] Therefore, an exemplary embodiment of the present application provides a memory cell, comprising a read transistor and a write transistor located above the read transistor; the read transistor comprises a first gate having a first portion extending vertically and a second portion extending horizontally, a first semiconductor layer surrounding the sidewall of the first portion, and a first electrode layer, a first insulating layer, and a second electrode layer surrounding the first semiconductor layer and arranged from bottom to top along a vertical direction; the write transistor comprises a second gate having a third portion extending vertically and a fourth portion extending horizontally, a second semiconductor layer surrounding the sidewall of the third portion, and a third electrode layer, a third insulating layer, and a fourth electrode layer surrounding the second semiconductor layer and arranged from bottom to top along the vertical direction; the first gate is electrically connected to the third electrode layer; the second electrode layer and the second portion located above the second electrode layer have a first distance in the vertical direction, the fourth electrode layer and the fourth portion located above the fourth electrode layer have a second distance in the vertical direction, and the first distance is less than the second distance.

[0043] As used in this application, "vertically extending" refers to extending along a vertical direction, which can be understood as a direction perpendicular to the substrate. Similarly, "horizontally extending" refers to extending along a horizontal direction, which can be understood as a direction parallel to the substrate.

[0044] As used in this application, the term "an integrated structure" may refer to the fact that there is no obvious boundary interface such as a fault or gap between A and B in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B are formed into a film layer using the same material and are simultaneously formed into a structure having a connection relationship through the same patterning process.

[0045] Figure 1A A schematic diagram of a longitudinal structure of a storage unit provided for an exemplary embodiment of the present application. Figure 1AAs shown, the present application provides a structure of an asymmetric 2TOC memory cell. The memory cell of the present application may include a read transistor 100 and a write transistor 200 located above the read transistor. The read transistor 100 may include a first gate 150 having a first portion 151 extending vertically and a second portion 152 extending horizontally, a first semiconductor layer 130 surrounding the sidewall of the first portion 151, and a first electrode layer 110, a first insulating layer 10, and a second electrode layer 120 surrounding the first semiconductor layer 130 and arranged from bottom to top along the vertical direction. The write transistor 200 may include a second gate 250 having a third portion 251 extending vertically and a fourth portion 252 extending horizontally, a second semiconductor layer 230 surrounding the sidewall of the third portion 251, and a third electrode layer 210, a third insulating layer 30, and a fourth electrode layer 220 surrounding the second semiconductor layer 230 and arranged from bottom to top along the vertical direction.

[0046] Figure 1A It is shown that both the first semiconductor layer 130 and the second semiconductor layer 230 are in the form of a ring channel, that is, the read transistor and the write transistor both adopt a ring channel structure.

[0047] Surrounding can be understood as partially or completely surrounding the first part 151 of the first gate 150 or the third part 251 of the second gate 250. In some embodiments, the surrounding can be completely surrounded as a whole, and the cross-section of the first semiconductor layer 130 or the second semiconductor layer 230 after surrounding can be a closed ring, and the ring shape is adapted to the outer contour shape of the cross-section of the gate. Exemplarily, the cross-section of the gate is, for example, a square structure. The interception direction of the cross section is intercepted along a direction perpendicular to the substrate. In some embodiments, the surrounding can be partially surrounded, and the cross-section after surrounding is not closed, but presents a ring shape. For example, the cross-section of the first semiconductor layer 130 or the second semiconductor layer 230 is a ring with an opening.

[0048] Figure 1A It is also shown that the third electrode layer 210 can be a part of the third extension portion 232 of the second semiconductor layer 230, so that the third electrode layer 210 can be an integral structure with the first gate 150, or the third electrode layer 210 can be electrically connected to the first gate 150. Therefore, the present application obtains a capacitor-free memory, such as a 2T0C DRAM memory, by interconnecting the gate of the read transistor with the source or drain of the write transistor.

[0049] Figure 1AIt is further shown that the read transistor 100 may further include a first gate insulating layer 140 located between the first semiconductor layer 130 and the first gate 150 and isolating the first semiconductor layer 130 from the first gate 150. The write transistor 200 may further include a second gate insulating layer 240 located between the second semiconductor layer 230 and the second gate 250 and isolating the second semiconductor layer 230 from the second gate 250.

[0050] Continue to refer Figure 1A The read transistor 100 may also include a second insulating layer 20 located between the second part 152 and the second electrode layer 120 and arranged from bottom to top along the vertical direction, a horizontally extending second extension portion 133 of the first semiconductor layer 130, and a horizontal extension portion 141 of the first gate insulating layer, wherein the upper surface of the horizontal extension portion 141 of the first gate insulating layer is in direct contact with the second part 152 and the lower surface of the second insulating layer 20 is in direct contact with the second electrode layer 120, that is, the second part 152 and the second electrode layer 120 include three layers in the vertical direction. The write transistor 200 may also include a fourth insulating layer 40 located between the fourth part 252 and the fourth electrode layer 220 and arranged from bottom to top along the vertical direction, a horizontally extending fourth extension portion 233 of the second semiconductor layer 230, and a horizontal extension portion 241 of the second gate insulating layer, wherein the upper surface of the horizontal extension portion 241 of the second gate insulating layer is in direct contact with the fourth part 252 and the lower surface of the fourth insulating layer 40 is in direct contact with the fourth electrode layer 220, that is, three layers are included between the fourth part 252 and the fourth electrode layer 220 in the vertical direction.

[0051] There is a first distance H1 between the second electrode layer 120 and the second portion 152 located on the second electrode layer 120 in the vertical direction, and there is a second distance H2 between the fourth electrode layer 220 and the fourth portion 252 located on the fourth electrode layer 220 in the vertical direction. The present application adjusts the thickness of the second insulating layer 20 of the read transistor and the thickness of the fourth insulating layer 40 of the write transistor so that the thickness of the second insulating layer 20 is less than or much less than the thickness of the fourth insulating layer 40, that is, the first distance H1 is less than or much less than the second distance H2, such as H1 is one-fifth, one-sixth, one-seventh, etc. of H2. The present application can not only improve the storage node capacitance of the read transistor and improve the reading performance through such a structural design, but also does not affect the performance of the write transistor.

[0052] As used in this application, the term "thickness" refers to a dimension of a film or a layer in a vertical direction, or refers to a total dimension of two or more films or layers in a vertical direction.

[0053] In an exemplary embodiment, the thickness of the fourth insulating layer 40 may be in a range of 50 nm to 200 nm, and the thickness of the second insulating layer 20 may be in a range of 0 to 10 nm.

[0054] In other exemplary embodiments, the read transistor 100 may further include a second insulating layer 20 located between the second portion 152 and the second electrode layer 120 and extending horizontally, the upper surface of the second insulating layer 20 being in direct contact with the second portion 152 and the lower surface of the second insulating layer 20 being in direct contact with the second electrode layer 120, that is, only the second insulating layer 20 is included between the second portion 152 and the second electrode layer 120, and the second insulating layer 20 may function as a gate insulating layer. The write transistor 200 may further include a fourth insulating layer 40 located between the fourth portion 252 and the fourth electrode layer 220 and extending horizontally, the upper surface of the fourth insulating layer 40 being in direct contact with the fourth portion 252 and the lower surface of the fourth insulating layer 40 being in direct contact with the fourth electrode layer 220, that is, only the fourth insulating layer 40 is included between the fourth portion 252 and the fourth electrode layer 220, and the fourth insulating layer 40 may also function as a gate insulating layer. The present application adjusts the thickness of the second insulating layer 20 of the read transistor and the thickness of the fourth insulating layer 40 of the write transistor so that the thickness of the second insulating layer 20 is smaller than or much smaller than the thickness of the fourth insulating layer 40.

[0055] In further other exemplary embodiments, the read transistor 100 may further include a horizontal extension portion 141 of the first gate insulating layer between the second portion 152 and the second electrode layer 120, the upper surface of the horizontal extension portion 141 of the first gate insulating layer directly contacts the second portion 152 and the lower surface of the horizontal extension portion 141 of the first gate insulating layer directly contacts the second electrode layer 120, that is, the second insulating layer 20 is not included between the second portion 152 and the second electrode layer 120. The write transistor 200 may further include a horizontal extension portion 241 of the second gate insulating layer and a fourth insulating layer 40 between the fourth portion 252 and the fourth electrode layer 220, the upper surface of the horizontal extension portion 241 of the second gate insulating layer directly contacts the fourth portion 252 and the lower surface of the fourth insulating layer 40 directly contacts the fourth electrode layer 220. The present application makes the thickness of the second insulating layer 20 be 0, that is, the read transistor does not include an insulating layer, so that the semiconductor layer / gate insulating layer of the read transistor is directly contacted and coupled with the source layer or drain layer (that is, the read word line) of the read transistor, thereby maximizing the capacitance of the storage node and enhancing the read performance of the device.

[0056] In an exemplary embodiment, the material used for the first gate insulating layer and the second gate insulating layer is selected from one of silicon oxide, aluminum oxide, hafnium oxide, titanium oxide and zirconium oxide; the material used for the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are selected from silicon oxide or silicon oxynitride; and the thickness of the horizontal extension portion of the first gate insulating layer is less than the thickness of the first insulating layer and less than the thickness of the second insulating layer, and the thickness of the horizontal extension portion of the second gate insulating layer is less than the thickness of the third insulating layer or the thickness of the fourth insulating layer.

[0057] In the present application, one of the first electrode and the second electrode in the read transistor can represent the source, and the other can represent the drain, and the position of the first electrode can be interchanged with the position of the second electrode. When determining which electrode is the source or the drain, it is related to the direction of current flow in the transistor and is not limited here. For example, the source can represent the electrode from which the current flows out, and the drain can represent the electrode into which the current flows. Similarly, one of the third electrode and the fourth electrode in the write transistor can represent the source, and the other can represent the drain, and the position of the third electrode can be interchanged with the position of the fourth electrode.

[0058] Figure 1B An equivalent circuit diagram of a memory cell provided for an exemplary embodiment of the present application. Figure 1B In the figure, SN represents a storage node, WWL, WBL, RWL, and RBL represent a write word line, a write bit line, a read word line, and a read bit line, respectively. The first electrode of the read transistor is connected to the read bit line RBL, and the second electrode is connected to the read word line RWL; the gate of the write transistor is connected to the write word line WWL, and the fourth electrode of the write transistor is connected to the write bit line WBL. The gate of the read transistor is connected to the third electrode of the write transistor, and the data "1" or "0" stored in the storage node is controlled to be turned on or off, and the data stored in the storage node is determined to be "1" or "0" according to the on and off state of the read transistor.

[0059] The applicant notes that, since the thickness of the semiconductor layer and the gate insulating layer is usually below 10 nm, the first distance H1 between the second electrode layer and the second portion of the gate (storage node) in the direction perpendicular to the substrate is usually determined by the thickness of the second insulating layer. The thickness of the second insulating layer of the read transistor can usually be in the range of 50 nm-200 nm.

[0060] However, in the exemplary embodiment of the present application, the thickness of the second insulating layer of the read transistor can be set to a range of 0-10 nm, which can greatly improve the storage capacity of the storage node.

[0061] refer to Figure 1C, which shows the simulation result comparison diagram of the capacitor storage capacity before and after the improvement of the storage unit structure of the present application. Figure 1C The results of the TCAD simulation test provided show that, compared with the case where the thickness of the second insulating layer of the read transistor (using oxide such as silicon oxide material as an example) is 50 nm, when the thickness of the second insulating layer of the read transistor (using oxide such as silicon oxide material as an example) of the exemplary embodiment of the present application is 0.1 nm, the storage node charge increases from approximately 1*10 -17 Increase to approximately 1*10 -15 , the charge increased nearly 100 times.

[0062] In the embodiment of the present application, the increase in the storage capacity Cs of the storage node also helps to increase the change ΔV of the signal on the read transistor bit line BL during the charge sharing phase. BL See the following formula to understand the relationship between Cs and ΔV BL relationship.

[0063]

[0064] According to the above formula, as Cs increases, the change ΔVBL of the bit line voltage of the read transistor that can be sensed during the data reading phase also increases, that is, the range of the sensing window becomes larger, and the signal can be identified more accurately.

[0065] The present application is directed to a vertical transistor stacking structure, thinning or removing the insulating layer between the read word line and the storage node, without increasing the footprint of the storage unit. On the contrary, while meeting the minimum capacitance requirement, the area of ​​the storage unit can be further reduced, thereby achieving further miniaturization of the device.

[0066] The technical solution of the present application is further explained below through the manufacturing process of the storage unit of the exemplary embodiment of the present application. The "patterning process" mentioned in the exemplary embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature manufacturing process in the relevant technology. The "photolithography process" mentioned in the exemplary embodiment includes coating of film layer, mask exposure and development, which is a mature manufacturing process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of the exemplary embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0067] In an exemplary embodiment, the manufacturing process of the storage unit may include:

[0068] S100: forming a first electrode layer, a first insulating layer, a second electrode layer and a second insulating layer that are horizontally extended and vertically stacked.

[0069] Exemplary steps may include: forming a first electrode layer 110 of the read transistor 100 in the substrate 1 by photolithography and metallization processes, and making the upper surfaces of the substrate 1 and the first electrode layer 110 flush by a planarization process, such as a chemical mechanical polishing (CMP) process; depositing a first insulating layer film on the first electrode layer 110 to form a first insulating layer 10; performing a metallization process to form a second electrode layer 120 of the read transistor 100 on the first insulating layer 10; and continuing to deposit a second insulating layer film on the second electrode layer 120 to form a second insulating layer 20, such as Figure 2 shown. Figure 2 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S100 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0070] In an exemplary embodiment, each insulating layer film may be deposited by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD), or the like.

[0071] In an exemplary embodiment, the substrate 1 may be made of an insulating material.

[0072] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of any one or more non-conductive materials selected from silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of an oxide insulating material, such as silicon dioxide (e.g., SiO2), which is convenient for large-area deposition.

[0073] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of the same or different insulating materials.

[0074] In an exemplary embodiment, the metallization process may adopt a direct etch metal process or a damascene process. In an exemplary embodiment, the metallization process may adopt a variety of metals, including but not limited to tungsten, molybdenum, aluminum, copper, titanium nitride, cobalt, nickel, ruthenium and platinum, or alloys thereof.

[0075] In an exemplary embodiment, the first electrode layer 110 may be a read bit line RBL, and the second electrode layer 120 may be a read word line RWL.

[0076] S200: forming a first through-hole structure.

[0077] An exemplary step may include: forming a first through-hole structure K1 in the structure formed in the above step by a photolithography process, wherein the first through-hole structure K1 vertically extends through the second insulating layer 20, the second electrode layer 120, and the first insulating layer 10 and terminates at a side of the first electrode layer 110 close to the first insulating layer 10, such as Figure 3 shown. Figure 3 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S200 ) of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application.

[0078] S300: forming a first semiconductor layer.

[0079] An exemplary step may include: depositing a semiconductor layer material film around the sidewall of the first through-hole structure K1, at the bottom of the first through-hole structure K1, and on the second insulating layer 20 to form a vertical portion 131 of the first semiconductor layer 130 extending around the sidewall of the first through-hole structure K1, and forming a first extension portion 132 of the first semiconductor layer 130 extending horizontally along the bottom of the first through-hole structure K1 and a second extension portion 133 extending horizontally along the second insulating layer 20, as shown in FIG. Figure 4 shown. Figure 4 A schematic diagram of the longitudinal structure of an exemplary intermediate product obtained in an intermediate step (ie, step S300 ) of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application.

[0080] In an exemplary embodiment, the first semiconductor layer 130 may be made of a metal oxide semiconductor material or a polycrystalline silicon material. In an exemplary embodiment, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the metal oxide semiconductor material has a slow corrosion rate in a weak acidic or weak alkaline solution. In an exemplary embodiment, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, and the like.

[0081] In an exemplary embodiment, when the first semiconductor layer 130 is made of IGZO metal oxide material, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, InGaO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn zO a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO and other materials. As long as the leakage current of the transistor can meet the requirements, it can be adjusted according to the actual situation.

[0082] In an exemplary embodiment, the first semiconductor layer 130 may not include the second extension portion 133 extending horizontally along the second insulating layer 20 , or the first semiconductor layer 130 may not include the first extension portion 132 extending horizontally along the bottom of the first through-hole structure K1 .

[0083] S400: forming a first gate.

[0084] An exemplary step may include: continuously depositing a dielectric film and a conductive film on the first semiconductor layer 130 to form a first gate insulating layer 140 and a first gate 150 (i.e., a storage node SN of the read transistor), wherein the first gate 150 includes a vertically extending first portion 151 and a horizontally extending second portion 152; and then photolithography and etching to remove excess film layers, i.e., forming a read transistor 100 having a vertical channel structure, such as Figure 5A shown. Figure 5A A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S400 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0085] In an exemplary embodiment, the first gate insulating layer 140 may be a dielectric layer with a high dielectric constant, i.e., a dielectric layer with K≥3.9. The dielectric layer with a high dielectric constant may be used as a gate oxide. The first gate insulating layer 140 may be any one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0086] In an exemplary embodiment, the first gate 150 may be made of ITO, P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0087] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition method.

[0088] refer to Figure 5AThe second portion 152 of the first gate 150 and the second electrode layer 120 may include a second insulating layer 20. The thickness of the second insulating layer 20 may be in the range of 0-10 nm. The third extension portion 232 of the first semiconductor layer 130 and the horizontal extension portion 141 of the first gate insulating layer 140 may also be included between the second portion 152 of the first gate 150 and the second electrode layer 120.

[0089] Figure 5B A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (i.e., step S400) of another method for manufacturing a storage unit provided in an exemplary embodiment of the present application. Figure 5B , the second insulating layer 20 is no longer included between the second portion 152 of the first gate 150 and the second electrode layer 120 , that is, the thickness of the second insulating layer is 0. That is, the semiconductor layer 130 is in direct contact with the second electrode layer 120 .

[0090] The present application can maximize the capacitance of the storage node and improve the reading rate by directly contacting and coupling the semiconductor layer of the read transistor with the source or drain (read word line) of the read transistor. In addition, by directly contacting the semiconductor layer of the read transistor with the read word line, a dielectric layer is saved, that is, the process steps are reduced, the process efficiency is improved, and the production process cost is reduced.

[0091] S500: forming a fourth electrode layer and a second through-hole structure of the write transistor.

[0092] Exemplary steps may include: depositing a third insulating layer film to form a third insulating layer 30, so that the total thickness of the insulating layer reaches the device contact area requirement; then performing a metallization process to form a fourth electrode layer 220 of the write transistor 200 on the third insulating layer 30; continuing to deposit a fourth insulating layer film to form a fourth insulating layer 40; and performing a photolithography process to form a second through-hole structure K2, wherein the second through-hole structure K2 passes through the fourth insulating layer 40, the fourth electrode layer 220, and the third insulating layer 30 and terminates at the first gate 150 of the read transistor 100, such as Figure 6 shown. Figure 6 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S500 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0093] In an exemplary embodiment, the third insulating layer 30 and the fourth insulating layer 40 may be made of any one or more non-conductive materials of silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the third insulating layer 30 and the fourth insulating layer 40 may be made of an oxide insulating material, such as silicon dioxide (e.g., SiO2), which is convenient for large-area deposition.

[0094] In an exemplary embodiment, the third insulating layer 30 and the fourth insulating layer 40 may be made of the same or different insulating materials.

[0095] The metallization process can be as described in the above steps.

[0096] In an exemplary embodiment, the fourth electrode layer 220 may be a write bit line WBL.

[0097] S600: forming a second gate.

[0098] Exemplary steps may include depositing a semiconductor layer material film around the sidewall of the second through-hole structure K2, at the bottom of the second through-hole structure K2, and on the fourth insulating layer 40 to form a vertical portion 231 of the second semiconductor layer 230 extending around the sidewall of the second through-hole structure K2, and forming a third extension portion 232 of the second semiconductor layer 230 extending horizontally along the bottom of the second through-hole structure K2 and a fourth extension portion 233 extending horizontally along the fourth insulating layer 40; continuing to deposit a dielectric layer film and a conductive film on the second conductor layer 230 to form a second gate insulating layer 240 and a second gate 250, the second gate 250 including a third portion 251 extending vertically and a fourth portion 252 extending horizontally; then photolithography and etching to remove excess film layers, i.e., forming a write transistor 200 with a vertical channel structure, such as Figure 7 shown. Figure 7 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S600 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0099] refer to Figure 7 , a fourth insulating layer 40 may be included between the fourth portion 252 of the second gate 250 and the fourth electrode layer 220. The thickness of the fourth insulating layer 40 may be in the range of 50-200 nm. A fourth extension portion 233 of the second semiconductor layer 230 and a horizontal extension portion 241 of the second gate insulating layer 240 may also be included between the fourth portion 252 of the second gate 250 and the fourth electrode layer 220.

[0100] In the present application, the thickness of the second insulating layer 20 between the second portion 152 of the first gate 150 of the read transistor and the second electrode layer 120 is smaller than or much smaller than the thickness of the fourth insulating layer 40 between the fourth portion 252 of the second gate 250 of the write transistor and the fourth electrode layer 220, that is, the first distance H1 is smaller than or much smaller than the second distance H2, such as H1 is one fifth, one sixth, one seventh, etc. of H2. This design can not only greatly improve the storage node capacitance of the read transistor and improve the reading performance, but also does not affect the performance of the write transistor.

[0101] In an exemplary embodiment, the region of the second semiconductor layer 230 coupled to the second portion 152 of the first gate 150 is the third electrode layer 210 of the write transistor 200. Therefore, the first gate 150 of the read transistor 100 is electrically connected or coupled to the third electrode layer 210 of the write transistor 200.

[0102] In an exemplary embodiment, the second gate 250 of the write transistor 200 may be a write word line WWL.

[0103] In an exemplary embodiment, the second gate insulating layer 240 may be a dielectric layer with a high dielectric constant, i.e., a dielectric layer with K≥3.9. The dielectric layer with a high dielectric constant may be used as a gate oxide. The second gate insulating layer 240 may be any one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0104] In an exemplary embodiment, the second gate 250 may be made of P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0105] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition method.

[0106] S700: Metallization process is used to form connections at each end.

[0107] The exemplary embodiment of the present application further provides a memory, comprising the storage unit provided by the exemplary embodiment of the present application as above. The memory may be, for example, a DRAM.

[0108] An exemplary embodiment of the present application further provides an electronic device, comprising the above-mentioned memory.

[0109] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0110] Although the embodiments disclosed in this application are as above, the contents are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A storage unit, characterized in that: comprising a read transistor and a write transistor located above the read transistor; The read transistor includes a first gate having a first portion extending vertically and a second portion extending horizontally, a first semiconductor layer surrounding a sidewall of the first portion, and a first electrode layer, a first insulating layer, and a second electrode layer surrounding the first semiconductor layer and arranged from bottom to top along a vertical direction; The write transistor includes a second gate having a third portion extending vertically and a fourth portion extending horizontally, a second semiconductor layer surrounding a side wall of the third portion, and a third electrode layer, a third insulating layer, and a fourth electrode layer surrounding the second semiconductor layer and arranged from bottom to top along the vertical direction; The first gate is electrically connected to the third electrode layer; A first distance exists between the second electrode layer and the second portion located above the second electrode layer in the vertical direction, and a second distance exists between the fourth electrode layer and the fourth portion located above the fourth electrode layer in the vertical direction, and the first distance is smaller than the second distance.

2. The storage unit according to claim 1, characterized in that The read transistor also includes a second insulating layer located between the second portion and the second electrode layer and extending horizontally, wherein the upper surface of the second insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a fourth insulating layer located between the fourth portion and the fourth electrode layer and extending horizontally, wherein the upper surface of the fourth insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

3. The storage unit according to claim 1, characterized in that The read transistor further includes a first gate insulating layer located between the first semiconductor layer and the first gate and isolating the first semiconductor layer from the first gate, and the write transistor further includes a second gate insulating layer located between the second semiconductor layer and the second gate and isolating the second semiconductor layer from the second gate.

4. The storage unit according to claim 3, characterized in that The read transistor also includes a horizontal extension portion of the first gate insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second portion and the lower surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second electrode layer; the write transistor also includes a horizontal extension portion of the second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension portion of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer.

5. The storage unit according to claim 3, characterized in that: The read transistor also includes a horizontal extension portion of a first gate insulating layer and a second insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a horizontal extension portion of a second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension portion of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

6. The storage unit according to claim 3, characterized in that: The read transistor also includes a second insulating layer, a second extension of the first semiconductor layer, and a horizontal extension of the first gate insulating layer, which are located between the second part and the second electrode layer and arranged from bottom to top along the vertical direction, wherein the upper surface of the horizontal extension of the first gate insulating layer is in direct contact with the second part and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a fourth insulating layer, a fourth extension of the second semiconductor layer, and a horizontal extension of the second gate insulating layer, which are located between the fourth part and the fourth electrode layer and arranged from bottom to top along the vertical direction, wherein the upper surface of the horizontal extension of the second gate insulating layer is in direct contact with the fourth part and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

7. The storage unit according to any one of claims 4 to 6, characterized in that: The material used for the first gate insulating layer and the second gate insulating layer is selected from one of silicon oxide, aluminum oxide, hafnium oxide, titanium oxide and zirconium oxide; the material used for the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer is selected from silicon oxide or silicon oxynitride; and the thickness of the horizontal extension portion of the first gate insulating layer is less than the thickness of the first insulating layer and less than the thickness of the second insulating layer, and the thickness of the horizontal extension portion of the second gate insulating layer is less than the thickness of the third insulating layer or the thickness of the fourth insulating layer.

8. The storage unit according to claim 1, characterized in that The third electrode layer is a portion of a third extension portion of the second semiconductor layer.

9. A memory, characterized in that: Comprising a storage unit according to any one of claims 1-8.

10. An electronic device, characterized in that: Comprising a memory according to claim 9.

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