Memory cell structure

Abstract

The invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conduction region, and a second conduction region. The capacitor has a storage electrode, wherein the capacitor is located above the transistor and the storage electrode is electrically coupled to the second conduction region of the transistor. The capacitor includes a capacitor perimeter, and the transistor is located within the capacitor perimeter. Therefore, compared with the prior art, the memory cell structure has the advantages of more compact structure, smaller area, lower leakage current, higher capacitance value and the like.

Description

[0001] The filing date of the original application is June 4, 2021, the application number is 202110625681.0, and the name of the invention is "Memory Cell Structure". Technical Field

[0002] The present invention relates to a storage unit structure, and in particular to a storage unit structure having the advantages of a more compact structure, a smaller area, a lower leakage current, a higher capacitance value, etc. Background Art

[0003] In the prior art, one of the most important volatile-memory integrated circuits is a dynamic random access memory (DRAM) using a 1T1C memory cell. The dynamic random access memory not only provides the best cost-performance function and serves as a main memory and / or buffer memory for computing and communication applications, but also serves as the best driving force for maintaining Moore's Law by shrinking the minimum feature size on silicon wafers (from a few microns to about twenty nanometers (nm)) through micro-scaling manufacturing process technology. Recently, logic technology that continues to use embedded static random access memory (SRAM) as its micro-scaling manufacturing process driver claims to have achieved the most advanced technology node of the manufacturing process close to 5 nanometers. In contrast, the claimed optimal technology node of the dynamic random access memory is still above 10 to 12 nanometers. The main problem is that it is difficult to further shrink the structure of the 1T1C memory cell even by very aggressive design rules, wherein the very aggressive design rules are used to shrink the access transistor (i.e., 1T) and the three-dimensional (3D) storage capacitor (i.e., 1C) in the 1T1C memory cell, and the three-dimensional storage capacitor is, for example, a stacked capacitor above a portion of the access transistor and above the isolation region, or is, for example, a very deep trench capacitor located below the access transistor.

[0004] The well-known difficulties faced in scaling down the 1T1C memory cell despite the huge investment and R&D in technology, design and equipment are described in detail. Some examples of the well-known difficulties are listed below: (1) The structure of the access transistor suffers from the inevitable and more serious leakage current problem, thereby reducing the storage function of the 1T1C memory cell (e.g., reducing the refresh time of the dynamic random access memory); (2) The complexity of the geometry and surface morphology of the layout of the word line, bit line and storage capacitor and the connection between the word line, the bit line, the storage capacitor and the gate, source and drain of the access transistor become worse and worse when scaling down the dynamic random access memory; (3) The trench capacitor suffers from the problem of too large aspect ratio of the depth of the trench capacitor to the opening size, and the manufacturing process of the trench capacitor is almost stopped at the 14 nanometer node process; (4) The stack capacitor suffers from worse surface morphology, and after the active area of ​​the access transistor is twisted from 20 degrees to more than 50 degrees, there is almost no space left as the contact space between the storage electrode of the storage capacitor and the source of the access transistor. In addition, the allowable space for the bit line to contact the drain of the access transistor is getting smaller and smaller, but the self-alignment feature must be maintained with difficulty; (5) Unless a high dielectric constant (high-k) insulator material can be found to obtain a higher storage capacitor capacitance value, the worsening leakage current problem of the access transistor will require increasing the capacitance value of the stacked capacitor and continuing to increase the height of the stacked capacitor to obtain a larger capacitance area; (6) Because there is no technological breakthrough to solve the above difficulties under the increasingly demanding conditions of higher density / capacity and performance, all the growing demands for better reliability, quality and resilience of the dynamic random access memory chip are becoming increasingly difficult to meet, etc.

[0005] However, there is no technical breakthrough in the prior art to solve the above difficulties, so how to design a new structure of the 1T1C memory cell to solve the above difficulties has become an important issue for designers of the 1T1C memory cell. Summary of the invention

[0006] An embodiment of the present invention provides a method for manufacturing a semiconductor component. The method includes preparing a semiconductor substrate having an original surface; forming a group of active regions based on the semiconductor substrate, and forming a shallow trench isolation region between two active regions of the group of active regions; forming a first interconnection structure in the shallow trench isolation region, wherein the first interconnection structure is located below the original surface; forming a gate region of a transistor located in a first active region of the two active regions, and forming a second interconnection structure across the two active regions and the shallow trench isolation region, wherein the gate region is connected to the second interconnection structure, wherein the second interconnection structure is located at a bottom of the shallow trench isolation region and is not aligned with a bottom of the gate region; and forming a capacitor having a storage electrode, wherein the capacitor covers the transistor.

[0007] In one embodiment of the present invention, the second interconnect structure is located at the bottom of the shallow trench isolation region and is higher than the bottom of the gate region.

[0008] In one embodiment of the present invention, before forming the first interconnect structure in the shallow trench isolation region, the method further includes: forming a set of asymmetric spacer layers between the two active regions.

[0009] In one embodiment of the present invention, before forming the capacitor, a bridge contact is formed in the first active region to electrically couple the first interconnect structure, and the bridge contact is located below the original surface; and a first conductive region and a second conductive region of the transistor are formed in the first active region.

[0010] In one embodiment of the present invention, the step of forming the bridge contact includes generating a first hole within the first active region; forming a first isolation layer on the surface of the first hole; removing a spacer layer in the set of asymmetric spacer layers to expose a side wall of the first interconnect structure; and forming a conductive plug in the first hole to electrically couple the side wall of the first interconnect structure, wherein the conductive plug can be metal or doped semiconductor.

[0011] In one embodiment of the present invention, the semiconductor substrate is a silicon substrate, and the step of forming the bridge contact further includes removing a portion of the first isolation layer located on the surface of the first hole to expose the silicon material of the silicon substrate; selectively growing a doped silicon layer based on the exposed silicon material, wherein the doped silicon layer contacts the conductive plug, and the bridge contact includes the conductive plug and the doped silicon layer; and forming a second isolation layer located on the doped silicon layer.

[0012] In one embodiment of the present invention, the first isolation layer on the surface of the first hole is a thermally generated oxide layer, and the removed spacer layer is made of a material different from the oxide layer.

[0013] In one embodiment of the present invention, the bridge contact comprises metal or doped semiconductor.

[0014] In one embodiment of the present invention, the method further includes forming a second hole on one side of the second conductive region of the transistor and forming an isolation pin in the second hole; wherein the bridge contact electrically couples the first interconnect structure to the first conductive region of the transistor; wherein the step of forming the capacitor includes forming the storage electrode electrically coupled to the second conductive region of the transistor, wherein the storage electrode includes a first protruding region located above the first conductive region of the transistor, a second protruding region located above the second conductive region of the transistor, and a connecting region; wherein the second conductive region is electrically connected to the second protruding region, and the connecting region is located above the gate structure of the transistor and laterally connects the first protruding region and the second protruding region; forming an insulating layer above the storage electrode; and forming a pair of electrodes above the insulating layer, wherein the pair of electrodes covers the first protruding region, the second protruding region, and the connecting region of the storage electrode.

[0015] In an embodiment of the present invention, the semiconductor device is a dynamic random access memory cell, and the transistor is an access transistor of the dynamic random access memory cell.

[0016] Another embodiment of the present invention provides a semiconductor component. The semiconductor component includes a semiconductor substrate, a group of active regions, a shallow trench isolation region, a first interconnection structure, a gate region of a transistor, and a second interconnection structure. The semiconductor substrate has an original surface. The group of active regions is located in the semiconductor substrate, and the shallow trench isolation region is between two active regions of the group of active regions. The first interconnection structure is located in the shallow trench isolation region, wherein the first interconnection structure is located below the original surface. The gate region is located in a first active region of the two active regions. The gate region is connected to the second interconnection structure.

[0017] In one embodiment of the present invention, the first interconnect structure is located between a set of asymmetric spacer layers, and the second interconnect structure spans the two active regions and the shallow trench isolation region, wherein the second interconnect structure is located at a bottom of the shallow trench isolation region and is not aligned with a bottom of the gate region.

[0018] In one embodiment of the present invention, it further includes a capacitor, wherein the capacitor covers the transistor, the second interconnect structure is a word line, the first interconnect structure is a bit line, the semiconductor memory is a dynamic random access memory unit, and the transistor is an access transistor of the dynamic random access memory unit.

[0019] In one embodiment of the present invention, the semiconductor component further includes a bridge contact located in the first active region electrically coupled to the first interconnect structure, the bridge contact being located below the original surface; and a second conductive region and a second conductive region of the transistor in the first active region.

[0020] In one embodiment of the present invention, the semiconductor component further includes a first hole in the first active region; a first isolation layer on the surface of the first hole; and a conductive plug in the first hole electrically coupled to a side wall of the first interconnect structure, and the conductive plug can be metal or doped semiconductor.

[0021] In one embodiment of the present invention, the semiconductor device further comprises a doped silicon layer and a second isolation layer, wherein the doped silicon layer contacts the conductive plug, the bridge contact comprises the conductive plug and the doped silicon layer, and the second isolation layer is located on the doped silicon layer.

[0022] In one embodiment of the present invention, the semiconductor component further comprises a second hole and an isolation plug. The second hole is located at one side of the second conductive region of the transistor. The isolation plug is located in the second hole; wherein the bridge contact electrically couples the first interconnect structure to the first conductive region of the transistor.

[0023] In one embodiment of the present invention, the capacitor includes a storage electrode electrically coupled to the second conductive region of the transistor, wherein the storage electrode includes a first protruding region located above the first conductive region of the transistor, a second protruding region located above the second conductive region of the transistor, and a connection region; wherein the second conductive region is electrically connected to the second protruding region, and the connection region is located above the gate structure of the transistor and laterally connects the first protruding region and the second protruding region; an insulating layer is above the storage electrode; and a pair of electrodes are above the insulating layer, wherein the pair of electrodes cover the first protruding region, the second protruding region, and the connection region of the storage electrode.

[0024] In one embodiment of the present invention, the bridge contact comprises metal or doped semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A The invention is a flow chart of a method for manufacturing a dynamic random access memory storage cell (1T1Ccell) array disclosed in an embodiment of the invention.

[0026] Figure 1B-1J Yes Description Figure 1A Schematic diagram of .

[0027] Figure 2 It is a schematic diagram illustrating a top view and a cross-sectional view along the X direction after depositing a pad nitride layer and a pad oxide layer and forming a shallow trench isolation.

[0028] Figure 3 is a schematic diagram illustrating deposition and etching back of a first nitride layer to form a first nitride spacer layer, and deposition of a spin-on dielectric layer and a photoresist layer.

[0029] Figure 4 Schematic diagram of etching away the upper edge first nitride spacer layer and the spin-on dielectric layer not covered by the photoresist layer.

[0030] Figure 5 It is a schematic diagram illustrating the stripping of the photoresist layer and the spin-coating of the dielectric, and the formation of the first oxide layer.

[0031] Figure 6 is a schematic diagram illustrating a metal layer deposited in a trench and planarized by the chemical mechanical planarization technique.

[0032] Figure 7 is a schematic diagram illustrating deposition of a photoresist layer.

[0033] Figure 8 is a schematic diagram illustrating etching of the metal layer corresponding to the end of the active region.

[0034] Fig. 9 is a schematic diagram illustrating the removal of the photoresist layer and etching back the metal layer to form a bit line under the silicon surface.

[0035] Fig.10 is a schematic diagram illustrating deposition of a second oxide layer in the trench.

[0036] Fig.11 The invention is a schematic diagram for explaining depositing a third oxide layer, a second nitride layer, and a photoresist layer, and then removing unnecessary portions of the third oxide layer, the second nitride layer, and the photoresist layer.

[0037] Fig.12 is a schematic diagram illustrating the removal of a photoresist layer, a pad nitride layer, and a pad oxide layer.

[0038] Fig.13 The diagram is a schematic diagram illustrating forming a U-shaped groove, forming a high dielectric constant insulating layer as a gate dielectric layer of an access transistor, and depositing and etching back a gate material to form a word line and a gate structure of the access transistor.

[0039] Fig.14 is a schematic diagram illustrating depositing a third nitride layer and a fourth oxide layer, and then etching back or planarizing the third nitride layer and the fourth oxide layer.

[0040] Fig.15is a schematic diagram illustrating etching away the second nitride layer and the third oxide layer.

[0041] Fig.16 The diagram is a schematic diagram illustrating the removal of the pad nitride layer, etching back the second oxide layer, and depositing and etching the fourth nitride layer, the fifth oxide layer, and the first polysilicon layer.

[0042] Fig.17 is a schematic diagram illustrating the deposition and planarization of a spin-on dielectric, etching of the upper half of a first polysilicon layer, and the deposition and planarization of a first oxide cap layer.

[0043] Fig.18 is a schematic diagram illustrating the removal of the spin-on dielectric and then the deposition of the fifth nitride layer.

[0044] Fig.19 is a schematic diagram illustrating the steps of depositing a spin-on dielectric layer, depositing a photoresist, and removing the spin-on dielectric layer corresponding to the source.

[0045] Fig. 20 is a schematic diagram illustrating etching away the exposed fifth nitride layer and the pad oxide layer located at the center of the source region, and digging out the silicon material at the center of the source region to generate a hole.

[0046] Fig.21 is a schematic diagram illustrating the thermal generation of the seventh oxide layer in the hole.

[0047] Fig. 22 is a schematic diagram illustrating the deposition and etch-back of a spin-on dielectric layer.

[0048] Fig.23 It is a schematic diagram illustrating depositing photoresist to cover the area corresponding to the source and exposing the area reserved for the drain, and then removing the exposed spin-on dielectric layer, the exposed fifth nitride layer, the exposed pad oxide layer, and removing the silicon material corresponding to the horizontal silicon surface to produce a hole.

[0049] Fig.24 is a schematic diagram illustrating removing the photoresist and then thermally growing the eighth oxide layer to produce an eighth oxide spacer layer.

[0050] Fig.25 It is a schematic diagram illustrating a cross-sectional view of the dynamic random access memory storage cell array along the Y2 direction.

[0051] Fig.26 is a schematic diagram illustrating the first nitride spacer layer at the lower edge of the etching hole.

[0052] Fig. 27 is a schematic diagram illustrating the removal of the fifth nitride layer.

[0053] Fig.28is a schematic diagram illustrating the deposition and etching back of a metal layer to leave a tungsten plug in a hole, and the deposition and etching of a sixth nitride layer.

[0054] Fig.29 is a schematic diagram illustrating etching back the upper half of the tungsten plug below the horizontal silicon surface.

[0055] Fig.30 is a schematic diagram illustrating the connection of the tungsten plug to the UGBL.

[0056] Fig.31 is a schematic diagram illustrating the removal of the upper half of the eighth oxide layer.

[0057] Fig.32 It is a schematic diagram illustrating the lateral growth of an n+ in-situ doped silicon layer to form an n+ silicon drain ring.

[0058] Fig.33 is a schematic diagram illustrating the local thermal generation of a ninth oxide layer on an n+ silicon drain ring.

[0059] Fig.34 It is a schematic diagram for explaining etching back the ninth oxide layer, and depositing and etching back the polysilicon layer-a.

[0060] Fig.35 is a schematic diagram illustrating the removal of the sixth nitride spacer layer, and the deposition and etching back of the polysilicon layer-b.

[0061] Fig.36 is a schematic diagram illustrating the removal of all spin-on dielectric layers and the fifth nitride layer.

[0062] Fig.37 is a schematic diagram illustrating a top view of a dynamic random access memory cell (HCoT cell) array.

[0063] Fig.38 is a schematic diagram illustrating deposition of a metal layer and etching back a portion of the metal layer to form a tungsten buffer wall.

[0064] Fig.39 The diagram is a schematic diagram illustrating etching away the first oxide cap layer, the first polysilicon spacer layer, and the pad oxide layer to expose a horizontal silicon surface corresponding to the source and the drain.

[0065] Fig.40 It is a schematic diagram explaining the formation of a source electrode and a drain electrode.

[0066] Figure 40-1 is a schematic diagram illustrating the formation of an n+ lightly doped drain (NLDD) for connecting a source electrode or a drain electrode to a channel by a rapid thermal annealing (RTA) step.

[0067] Fig.41 Schematic diagram illustrating etching of the fifth oxide spacer layer, and thermal generation and etching of oxide layer-a.

[0068] Fig.42 It is a schematic diagram explaining the formation of a source electrode and a drain electrode.

[0069] Fig.43 is a schematic diagram illustrating the deposition and etching back of a first spin-on dielectric layer.

[0070] Fig.44 is a schematic diagram illustrating etching away the tungsten buffer wall.

[0071] Fig.45 is a schematic diagram illustrating deposition of a nitride layer-a and etching of the nitride layer-a by the anisotropic etching technique.

[0072] Fig.46 is a schematic diagram illustrating the removal of polysilicon layer-a and polysilicon layer-b, and etching of a portion of the bottom of the drain electrode.

[0073] Fig.47 is a schematic diagram illustrating the thermally generated oxide layer -bb.

[0074] Fig.48 is a schematic diagram illustrating the removal of the nitride layer-a spacer layer and the first spin-on dielectric layer.

[0075] Fig.49 is a schematic diagram illustrating the formation of a first high dielectric constant insulating layer.

[0076] Fig.50 is a schematic diagram illustrating the deposition and etching back of metal layers.

[0077] Fig.51 is a schematic diagram illustrating removing the first high dielectric constant insulating layer above the fourth oxide layer and then etching away the fourth oxide layer.

[0078] Fig.52 2 is a schematic diagram illustrating the removal of an upper half of the third nitride layer and an upper half of the fourth nitride spacer layer.

[0079] Fig.53 is a schematic diagram illustrating the laterally grown source electrode and drain electrode LGS-2D.

[0080] Fig.54 is a schematic diagram illustrating the deposition of a nitride layer-cc and the exposure of a drain electrode, a source electrode, and the nitride layer-cc by the chemical mechanical planarization technique.

[0081] Fig.55is a schematic diagram illustrating the removal of the first metal counter electrode plate and the wall.

[0082] Fig.56 FIG. 1 is a schematic diagram illustrating the formation of a twin-tower storage electrode for the H-type storage capacitor by using the exposed drain electrode and source electrode as seeds.

[0083] Fig.57 is a schematic diagram illustrating thermally generated oxide layer-d and anisotropically etched oxide layer-d.

[0084] Fig.58 It is a schematic diagram illustrating the lateral and vertical growth of n+ in-situ heavily doped silicon material.

[0085] Fig.59 is a schematic diagram illustrating the removal of the oxide layer-d spacer layer.

[0086] Fig.60 is a schematic diagram illustrating removing the first high dielectric constant insulating layer and forming the second high dielectric constant insulating layer.

[0087] Fig.61 is a schematic diagram illustrating depositing a metal layer and planarizing the metal layer using the chemical mechanical planarization technique.

[0088] Fig.62 is a schematic diagram illustrating etching back the second metal counter electrode plate and wall and etching away the second high dielectric constant insulating layer on top of the double-tower-shaped storage electrode.

[0089] Fig.63 It is a schematic diagram illustrating the use of the exposed silicon material on the top of the twin-tower storage electrode as a seed crystal to generate a higher n+ in-situ heavily doped silicon tower to serve as the twin-tower storage electrode of the H-type storage capacitor, etching the second high dielectric constant insulating layer, and forming a third high dielectric constant insulating layer.

[0090] Fig.64 is a schematic diagram illustrating the formation of a photoresist.

[0091] Fig.65 is a schematic diagram illustrating etching away the third high dielectric constant insulating layer on the exposed edge regions of the second metal counter electrode plate and the wall.

[0092] Fig.66 is a schematic diagram illustrating the removal of photoresist.

[0093] Fig.67 is a schematic diagram illustrating the deposition of a metal layer to complete the electrode plate of the H-type storage capacitor.

[0094] Fig.68 is a schematic diagram illustrating the structure of the HCoT unit disclosed in the present invention.

[0095] Fig.69 is a schematic diagram illustrating a simplified top view of the HCoT unit.

[0096] The reference numerals are described as follows:

[0097] 202 substrate

[0098] 204 Pad Oxide Layer

[0099] 206 pad nitride layer

[0100] 208, HSS-1 / 2, HSS-1 / 3, HSS horizontal silicon surface

[0101] 210 Groove

[0102] 214 Oxide layer

[0103] 304, 1702, 1902, 2202 Spin-on dielectrics

[0104] 306, 702, 1106, photoresist layer

[0105] 502 First Oxide Layer

[0106] 504 First Oxide / STI Layer

[0107] 602, 2802, 3802, 5002, 6102, 6702 metal layer

[0108] 902、UGBL Under-silicon bit line

[0109] 1002, CVD-STI-Oxide2 Second oxide layer

[0110] 1102 Third Oxide Layer

[0111] 1104 Second Nitride Layer

[0112] 1302 U-shaped channel

[0113] 1304 High dielectric constant insulation layer

[0114] 1306 Gate Material

[0115] 1402 Third nitride layer

[0116] 1404 Fourth Oxide Layer

[0117] 1602 Fourth Nitride Layer

[0118] 1604 Fifth Oxide Layer

[0119] 1606 First polysilicon layer

[0120] 1704 First Oxide Cap Layer

[0121] 1802 Fifth Nitride Layer

[0122] 1904, 2302, 6402 Photoresist

[0123] 2102 Seventh Oxide Layer

[0124] 2402 Eighth Oxide Layer

[0125] 2802 Tungsten Latch

[0126] 2804 Sixth nitride layer

[0127] 3202 n+ in-situ doped silicon layer

[0128] 3302 Ninth Oxide Layer

[0129] 3402 Polysilicon layer-a

[0130] 3502 polysilicon layer-b

[0131] 4012 n+ lightly doped drain

[0132] 4102 Oxide layer-a

[0133] 4302 First Spin-On Dielectric

[0134] 4502 Nitride layer-a

[0135] 4702 Oxide layer-bb

[0136] 4902 The first high dielectric constant insulating layer

[0137] 5402 Nitride layer-cc

[0138] 5702 Oxide-d

[0139] 6002 Second highest dielectric constant insulating layer

[0140] 6301 n+ in-situ heavily doped silicon tower

[0141] 6302 The third highest dielectric constant insulating layer

[0142] AQ1, AQ2, AQ3 access transistors

[0143] Drain-1 First drain

[0144] Drain-2 Second drain EH-1D, EH-2D, EH-1+2D, LGS-2D drain electrode

[0145] EH-1S, EH-2S, EH-1+2S, LGS-2S source electrode

[0146] Hole-1 / 2, Hole-1 / 3

[0147] LGS-2D-Tower Drain Electrode Tower

[0148] LGS-2S-Tower Source Electrode Tower

[0149] LGS-2DS Connecting Silicon Layer

[0150] oxide-7plug seventh oxide plug

[0151] SHAR Seed silicon surface area for source and drain Source-1 First source

[0152] STI Shallow Trench Isolation

[0153] Source-3 The third source

[0154] Tungsten plug

[0155] Wordline-1 First wordline

[0156] Wordline-2 Second wordline

[0157] Wordline-3 The third wordline

[0158] WBW Tungsten Buffer Wall

[0159] Steps 10-55, 102-202 DETAILED DESCRIPTION

[0160] Please refer to Figures 1A-1F , Figure 1A 1 is a flow chart of a method for manufacturing a dynamic random access memory storage cell (HCoT cell) array disclosed in one embodiment of the present invention, wherein the HCoT cell is a 1T1C memory cell, and the detailed steps of the manufacturing method are as follows:

[0161] Step 10: Start;

[0162] Step 15: Based on a substrate (eg, a p-type silicon substrate), define an active region of the dynamic random access memory cell array and form shallow trench isolation (STI);

[0163] Step 20: forming an asymmetric spacer layer along the sidewall of the active region;

[0164] Step 25: forming a silicon subsurface conductive line (eg, a bit line) between the asymmetric spacer layers and below the horizontal surface of the substrate;

[0165] Step 30: forming word lines and gate structures of access transistors of the dynamic random access memory cell array;

[0166] Step 35: Defining the access transistor drain of the dynamic random access memory cell array

[0167] (i.e., the first conduction region) and the source (i.e., the second conduction region);

[0168] Step 40: forming a connection between the subsurface conductive line of the silicon and the drain of the access transistor;

[0169] Step 45: forming a drain and a source of the access transistor;

[0170] Step 50: forming a capacitor tower above the access transistor;

[0171] Step 55: End.

[0172] Please refer to Figure 1B and Figure 2 , step 15 comprises:

[0173] Step 102: depositing a pad oxide layer 204 and a pad nitride layer 206 on a horizontal silicon surface 208 (ie, the horizontal surface) of a substrate 202;

[0174] Step 104: Define an active region of the DRAM cell array and remove substrate material (eg, silicon material) corresponding to the horizontal silicon surface 208 outside the active region.

[0175] To produce a groove 210;

[0176] Step 106 : Deposit and etch back an oxide layer 214 in the trench 210 to form the shallow trench isolation (STI) below the horizontal silicon surface 208 .

[0177] Please refer to Figure 1C and Figure 3-5 , step 20 comprises:

[0178] Step 108: Deposit and etch back the first nitride layer to form a first nitride spacer ( Figure 3 );

[0179] Step 110: Deposit spin-on dielectrics (SOD) 304 in the trench 210 and planarize the surface of the trench 210 by chemical mechanical polishing (CMP). Figure 3 );

[0180] Step 112: Deposit a photoresist layer 306 over the spin-on dielectric 304 and the pad nitride layer 206 ( Figure 3 );

[0181] Step 114: Etch away the upper edge first nitride spacer layer and the spin-on dielectric 304 that are not covered by the photoresist layer 306 ( Figure 4 );

[0182] Step 116: Strip the photoresist layer 306 and the spin-on dielectric 304, and grow (eg, thermally grow) the first oxide layer 502 ( Figure 5 ).

[0183] Please refer to Figure 1D and Figure 6-10 , step 25 comprises:

[0184] Step 118: Deposit a metal layer 602 in the trench 210 and planarize it by the chemical mechanical planarization technique ( Figure 6 );

[0185] Step 120: Deposit and pattern a photoresist layer 702 ( Figure 7 );

[0186] Step 122: Etch the metal layer 602 corresponding to the end of the active region to form a plurality of conductive lines ( Figure 8 ); Step 124: remove the photoresist layer 702 and etch back the metal layer 602 (the plurality of conductive lines) to form an underground bit line (UGBL) 902 or an underground conductive line ( Fig. 9 ); Step 126: Deposit a second oxide layer 1002 in the trench 210 and planarize it by the chemical mechanical planarization technique ( Fig.10 ).

[0187] Please refer to Figure 1E and Figure 11-15 Step 30 comprises:

[0188] Step 128: deposit a third oxide layer 1102, a second nitride layer 1104, and a patterned photoresist layer 1106, and then etch away unnecessary portions of the third oxide layer 1102 and the second nitride layer 1104 ( Fig.11 );

[0189] Step 130: Remove the patterned photoresist layer 1106, the pad nitride layer 206, and the pad oxide layer 204, and expose the horizontal silicon surface 208 ( Fig.12 );

[0190] Step 132: Etching the horizontal silicon surface 208 to form a U-shaped groove, forming a high-k insulating layer 1304 in the U-shaped groove, and depositing and etching back a gate material 1306 (e.g., tungsten) to form the word line and gate structure of the access transistor ( Fig.13 ), wherein the access transistor may be referred to as a U-type transistor;

[0191] Step 134: deposit and etch back the third nitride layer 1402, then deposit the fourth oxide layer 1404, and then etch back or planarize the fourth oxide layer 1404 ( Fig.14 );

[0192] Step 136: Etch away the second nitride layer 1104 and the third oxide layer 1102 ( Fig.15 ).

[0193] Please refer to Figure 1F and Figure 16-22 Step 35 comprises:

[0194] Step 138: remove the pad nitride layer 206 , and etch back the second oxide layer 1002 to the top of the pad oxide layer 204 ;

[0195] Step 140: depositing and anisotropically etching the fourth nitride layer 1602,

[0196] The fifth oxide layer 1604 and the first polysilicon layer 1606 ( Fig.16 );

[0197] Step 142: Deposit and planarize the spin-on dielectric 1702 by the chemical mechanical planarization technique,

[0198] The upper half of the first polysilicon layer 1606 is etched, and the first oxide cap layer 1704 is deposited and planarized by the chemical mechanical planarization technique ( Fig.17 );

[0199] Step 144: Remove the spin-on dielectric 1702 and then deposit the fifth nitride layer 1802 ( Fig.18 );

[0200] Step 146: Deposit and planarize the spin-on dielectric 1902 by the chemical mechanical planarization technique,

[0201] Deposit photoresist 1904 and then etch back the spin-on dielectric 1902 to be removed ( Fig.19 ); Step 148: Etch away the exposed fifth nitride layer 1802, the pad oxide layer 204, and the silicon material corresponding to the horizontal silicon surface HSS-1 / 3 to produce a hole hole-1 / 3 ( Fig. 20 );

[0202] Step 150: Remove the photoresist 1904 and thermally generate the seventh oxide layer 2102 ( Fig.21 );

[0203] Step 152: Deposit a spin-on dielectric 2202 on the seventh oxide layer 2102, and then etch back the spin-on dielectric 2202 ( Fig. 22 ).

[0204] Please refer to Figure 1G and Figure 23-33 , step 40 comprises:

[0205] Step 154: deposit photoresist 2302, remove the exposed spin-on dielectric 1902, the exposed fifth nitride layer 1802 and the exposed pad oxide layer 204, and then dig and remove the silicon material corresponding to the horizontal silicon surface HSS-1 / 2 to produce a hole hole-1 / 2 ( Fig.23 );

[0206] Step 156: Remove the photoresist 2302 and thermally generate the eighth oxide layer 2402 ( Fig.24 and Fig.25 );

[0207] Step 158: Remove the first nitride spacer layer at the lower edge to expose the sidewall of the bit line 902 (UGBL) under the silicon surface, and remove the fifth nitride layer 1802 ( Fig.26 and Fig. 27 ); Step 160: depositing a metal layer 2802 in the hole hole-1 / 2 to contact the sidewall of the silicon surface lower bit line 902 (UGBL), and then depositing and etching back a sixth nitride layer 2804 to create a sixth nitride spacer ( Fig.28 );

[0208] Step 162: Etch back the upper half of the metal layer 2802 ( Fig.29 and Fig.30 );

[0209] Step 164: Etch back the upper half of the eighth oxide layer 2402 to expose the silicon material corresponding to the hole hole-1 / 2 ( Fig.31 );

[0210] Step 166: Laterally grow an n+ in-situ doped silicon layer 3202 based on the exposed silicon material to contact the drain and the tungsten plug ( Fig.32 );

[0211] Step 168: Thermally generate a ninth oxide layer 3302 on the n+ in-situ doped silicon layer 3202 ( Fig.33 ).

[0212] Please refer to Figure 1H and Figure 34-42 , step 45 comprises:

[0213] Step 170: Etch back the ninth oxide layer 3302, and deposit and etch back the polysilicon layer-a 3402 ( Fig.34 ); Step 171: removing the sixth nitride spacer layer, and depositing and etching back the polysilicon layer-b 3502 ( Fig.35 );

[0214] Step 172: Remove all spin-on dielectric layers (ie, spin-on dielectric 1902 and spin-on dielectric 2202) and the fifth nitride layer 1802 ( Fig.36 );

[0215] Step 173: Deposit and etch back a metal layer (eg, tungsten) 3802 ( Fig.38 );

[0216] Step 174: Etch away the first oxide cap layer 1704, the first polysilicon spacer layer, and the pad oxide layer 204 ( Fig.39 );

[0217] Step 175: Generate a source electrode EH-1S and a drain electrode EH-1D by the selective epitaxial growth technique ( Fig.40 );

[0218] Step 176: Etching away the fifth oxide spacer layer, and thermally generating and etching the oxide layer-a

[0219] 4102( Fig.41 );

[0220] Step 177: Generate source electrode EH-2S and drain electrode EH-2D by using the exposed silicon surface of source electrode EH-1S and drain electrode EH-1D and the selective epitaxial growth technique, respectively. Fig.42 ).

[0221] Please refer to Fig. 1I , 1J and Figure 43-67 , step 50 comprises:

[0222] Step 178: Deposit and etch back the first spin-on dielectric 4302 ( Fig.43 );

[0223] Step 179: Etch away the tungsten buffer wall ( Fig.44 );

[0224] Step 180: Deposition and etching of nitride layer-a 4502 ( Fig.45 );

[0225] Step 181: Remove the polysilicon layer-a 3402 and the polysilicon layer-b 3502, and etch the bottom portion of the drain electrode EH-1D by the isotropic etching technique ( Fig.46 );

[0226] Step 182: Thermally generated oxide layer - bb 4702 ( Fig.47 );

[0227] Step 183: Remove the nitride layer-a spacer layer and the first spin-on dielectric 4302 by the isotropic etching technique ( Fig.48 );

[0228] Step 184: Form a first high dielectric constant insulating layer 4902 ( Fig.49 );

[0229] Step 185: Deposit and etch back the metal layer 5002 to produce the first metal counter electrode plate and wall

[0230] (metal-counter-electrode-plate&wall-1,MCEPW-1)( Fig.50 );

[0231] Step 186: Remove the first high dielectric constant insulating layer 4902 above the fourth oxide layer 1404 and etch away the fourth oxide layer 1404 ( Fig.51 );

[0232] Step 187: Etching the third nitride layer 1402 and the fourth nitride spacer layer ( Fig.52 );

[0233] Step 188: Laterally grow n+ in-situ doped silicon material ( Fig.53 );

[0234] Step 189: Deposition of nitride layer -cc 5402 ( Fig.54 );

[0235] Step 190: Remove the first metal counter electrode plate and wall ( Fig.55 );

[0236] Step 191: Using the exposed drain electrode LGS-2D and source electrode LGS-2S as seed crystals,

[0237] The selective epitaxial growth technique is performed to create a twin-tower-like

[0238] Storage electrode ( Fig.56 );

[0239] Step 192: Heat generation and etching of the oxide layer-d 5702 using the anisotropic etching technique, and removal of the nitride layer-cc 5402 ( Fig.57 );

[0240] Step 193: Using the selective epitaxial growth technique, n+ in-situ heavily doped silicon is grown laterally and vertically from the exposed silicon regions of the drain electrode LGS-2D and the source electrode LGS-2S.

[0241] (heavily n+in-situ-doped silicon) materials Fig.58 );

[0242] Step 194: Remove the oxide layer-d spacer layer ( Fig.59 );

[0243] Step 195: Remove the first high dielectric constant insulating layer 4902 and form a second high dielectric constant insulating layer 6002 ( Fig.60 );

[0244] Step 196: Deposit a metal layer (eg, tungsten) 6102, and then planarize the metal layer 6102 using the chemical mechanical planarization technique ( Fig.61 );

[0245] Step 197: Etch back the second metal counter electrode plate and the wall, and then etch away the second high dielectric constant insulating layer 6002 ( Fig.62 );

[0246] Step 198: Generate a higher n+ in-situ heavily doped silicon tower 6301, etch the second high dielectric constant insulating layer 6002, and form a third high dielectric constant insulating layer 6302 ( Fig.63 );

[0247] Step 199: Forming photoresist 6402 ( Fig.64 );

[0248] Step 200: Etch away the third high dielectric constant insulating layer 6302 ( Fig.65 );

[0249] Step 201: Remove the photoresist 6402 ( Fig.66 );

[0250] Step 202: Deposit and etch back the metal layer 6702 to complete the HCoT unit ( Fig.67 ).

[0251] Possible materials for the metal layer used in the above-mentioned manufacturing method (e.g. Figure 6 In the metal material used for the bit line under the silicon surface, Fig.13 In the present invention, the electrodes (source electrode and drain electrode), and / or the counter electrode of the H-type storage capacitor, etc.) used for the word line can be tungsten. However, due to the sensitivity of tungsten materials to oxides or oxidation processes, it is best that the tungsten material can be covered by another titanium nitride layer or a suitable layer. Because those skilled in the art should be aware of the characteristics of the tungsten material, the present invention does not describe the detailed protection process of the tungsten material, but assumes that the metal layers including the tungsten material are well treated to avoid any oxidation reaction directly thereon. Of course, there are some suitable metal layers that can still be applied to the bit lines and the word lines under the silicon surface, without being limited to a specific type of metal material that is not suitable for insertion integration processes.

[0252] The above manufacturing method is described in detail as follows. The above manufacturing method starts with a p-type silicon wafer (i.e., a p-type substrate 202). In step 102, as Figure 2 As shown in (a), a pad oxide layer 204 is formed above a horizontal silicon surface 208 (if the substrate is a silicon substrate), and then a pad nitride layer 206 is deposited above the pad oxide layer 204, wherein the horizontal silicon surface 208 is also referred to as HSS (horizontal silicon surface) or OSS (original silicon surface), and the subsequent drawings are described using the horizontal silicon surface 208 or HSS as an example.

[0253] In step 104, the active region of the DRAM memory cell array may be defined by photolithographic mask technique, wherein Figure 2 As shown in (a), since the active region of the dynamic random access memory cell array corresponds to the pad oxide layer 204 and the pad nitride layer 206, the horizontal silicon surface 208 outside the active region pattern will be exposed accordingly. Since the horizontal silicon surface 208 outside the active region pattern is exposed, the silicon material corresponding to the horizontal silicon surface 208 outside the active region pattern can be removed by anisotropic etching technique to produce a trench (or channel) 210, wherein, for example, the trench 210 can reach a depth of 250 nanometers (nm) below the horizontal silicon surface 208.

[0254] In step 106, an oxide layer 214 is deposited to fill the trench 210, and then the oxide layer 214 is etched back to form the shallow trench isolation below the horizontal silicon surface 208 in the trench 210. In addition, Figure 2 (b) corresponds to Figure 2 (a) is a top view, where Figure 2 (a) is along the Figure 2 (b) is a cross-sectional view of the cutting line in the X direction. Figure 2 As shown in (a), for example, the shallow trench isolation has a thickness of about 50 nanometers, and if the trench 210 below the horizontal silicon surface 208 has a depth of 250 nanometers, the top of the shallow trench isolation is about 200 nanometers deep from the horizontal silicon surface 208.

[0255] In step 108, if Figure 3 As shown in (a), the first nitride layer is deposited and the first nitride layer is etched back using the anisotropic etching technique to form the first nitride spacer along the two edges (i.e., the upper edge and the lower edge) of the trench 210. In step 110, as shown in Figure 3 As shown in (a), a spin-on dielectric 304 is deposited on the shallow trench isolation in the trench 210 to fill the trench 210. The spin-on dielectric 304 is then planarized by the chemical mechanical planarization technique to make the top of the spin-on dielectric 304 flush with the top of the pad nitride layer 206.

[0256] In step 112, if Figure 3 As shown in (a), the first nitride spacer at the lower edge of the first nitride spacer along the lower edge of the groove 210 is protected by the photoresist layer 306 using the photolithography mask technology, but the first nitride spacer at the upper edge of the first nitride spacer along the upper edge of the groove 210 is not protected by the photoresist layer 306. That is to say, after the photoresist layer 306 is deposited on the spin-on dielectric 304 and the pad nitride layer 206, because the photoresist layer 306 on the first nitride spacer at the upper edge is removed but the photoresist layer 306 on the first nitride spacer at the lower edge is retained, the first nitride spacer at the lower edge can be retained but the first nitride spacer at the upper edge will be removed. In addition, Figure 3 (b) corresponds to Figure 3 (a) is a top view, where Figure 3 (a) is along the Figure 3 (b) is a cross-sectional view of the cutting line in the Y direction shown in FIG. Figure 4 As shown, the upper edge first nitride spacer layer and the spin-on dielectric 304 not covered by the photoresist layer 306 may be etched away by an etching process.

[0257] In step 116, if Figure 5 As shown, the photoresist layer 306 and the spin-on dielectric 304 are stripped, wherein the spin-on dielectric 304 has a much higher etching rate than the thermally generated oxide layer and the deposited oxide layer. Then the first oxide layer 502 is thermally generated to form a first oxide spacer, wherein the first oxide spacer covers the upper edge of the trench 210, the first oxide layer 502 does not grow beyond the pad nitride layer 206, and only a very thin oxide layer (referred to as the first oxide / STI layer 504) is formed above the shallow trench isolation. Figure 5 As shown, step 116 results in an asymmetric spacer (i.e., the first nitride spacer at the lower edge and the first oxide spacer) being formed at two symmetrical edges of the trench 210 (i.e., the upper edge and the lower edge of the trench 210). For example, the thickness of the first oxide spacer is 4 nanometers and the thickness of the first nitride spacer at the lower edge is 3 nanometers. On the other hand, the asymmetric spacer is also formed along the sidewall of the active region. The asymmetric spacer (i.e., Figure 5 The structure of the present invention and the above-mentioned related steps are the first main technical features of the present invention, which are called asymmetric spacers on twosymmetricaledges of a trench or a canal (ASoSE).

[0258] In step 118, if Figure 6 As shown, a metal layer 602 (or a conductive material that needs to withstand subsequent process conditions) is deposited to fill the trench 210 and is planarized by the chemical mechanical planarization technique so that the top of the metal layer 602 is flush with the top of the pad nitride layer 206 (as shown in FIG. Figure 6 In addition, in one embodiment of the present invention, the metal layer 602 may be tungsten (abbreviated as W).

[0259] In step 120, if Figure 7 As shown, a photoresist layer 702 is deposited to cover the first nitride spacer and the first oxide spacer at the lower edge, but expose two edges of the first nitride spacer and the first oxide spacer at the lower edge corresponding to the ends of the active region.

[0260] In step 122, if Figure 8 As shown, the metal layer 602 corresponding to the end of the active region is etched until the top of the first oxide / STI layer 504 is exposed to separate the plurality of conductive lines (ie, the metal layer 602 ).

[0261] In step 124, if Fig. 9As shown in (a), after removing the photoresist layer 702, the metal layer 602 in the trench 210 is etched back to a reasonable thickness to form a subsurface silicon bit line (or subsurface silicon conductive line) 902, wherein the top of the subsurface silicon bit line 902 is much lower than the horizontal silicon surface 208 (for example, the thickness of the subsurface silicon bit line 902 is about 40 nanometers). In addition, as shown in FIG. Fig. 9 As shown in (a), the bit line 902 under the silicon surface is located on the top of the shallow trench isolation and the two side walls of the bit line 902 under the silicon surface are respectively restricted by the asymmetric spacer layer (that is, the first nitride spacer layer at the lower edge and the first oxide spacer layer). In addition, Fig. 9 (a) is along the Fig. 9 (b) is a cross-sectional view taken along the cutting line in the Y direction.

[0262] In step 126, if Fig.10 (Along as Fig. 9 As shown in (b) of the cross-sectional view of the cutting line in the Y direction, the second oxide layer 1002 (also called CVD-STI-oxide2) needs to have a sufficient thickness to fill the trench 210 above the bit line 902 under the silicon surface, and then the second oxide layer 1002 is polished by the chemical mechanical planarization technology to retain a portion of the second oxide layer 1002, wherein the top of the retained portion of the second oxide layer 1002 is flush with the top of the pad nitride layer 206, and covers the lower edge first nitride spacer and the first oxide spacer. Fig.10 As shown, step 126 can make the silicon surface bit line 902 (that is, the interconnection wire) embedded in all insulators (that is, the isolation region) in the trench 210 and confined by all the insulators (later the silicon surface bit line 902 will be connected to the drain of the access transistor of the dynamic random access memory storage cell array), wherein Fig.10 The structure shown is called Under Silicon Bit Line Surrounded by Insulator, and the Under Silicon Bit Line (UGBL) is the second main technical feature of the present invention.

[0263] The following description will introduce how to simultaneously form the access transistors and word lines of the dynamic random access memory storage cell (1T1C cell) array by a self-alignment method and form all related gate structures of the word lines connecting the access transistors. In this way, the gate structures of the access transistors and word lines of the dynamic random access memory storage cell (1T1C cell) array will be connected into a single metal (e.g., tungsten (W)).

[0264] In step 128, if Fig.11As shown in (a), firstly, a third oxide layer 1102, a second nitride layer 1104, and a patterned photoresist layer 1106 are deposited. Then, unnecessary portions of the third oxide layer 1102 and the second nitride layer 1104 are removed by etching technology. In addition, a transistor / word line pattern can be defined by a composite layer composed of the third oxide layer 1102 and the second nitride layer 1104, wherein the composite layer composed of the third oxide layer 1102 and the second nitride layer 1104 is composed of a plurality of strip-shaped third oxide layers 1102 and the second nitride layer 1104 in a direction perpendicular to the active region. Therefore, as shown in FIG. Fig.11 (a) and Fig.11 As shown in (b), longitudinal (the Y direction) stripes (composed of the third oxide layer 1102 and the second nitride layer 1104) for defining the access transistor and the word line, and a cross-point square for defining the active region will be formed, wherein the active region is the cross-point square located between the two longitudinal stripes, and Fig.11 (a) is along the Fig.11 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0265] like Fig.11 (b) Fig.11 The top view shown in (b) shows a fabric-like checkerboard pattern with longitudinal stripes of the third oxide layer 1102 and the second nitride layer 1104 located above the pad nitride layer 206 and the pad oxide layer 204, and also shows the fabric-like checkerboard pattern in the horizontal direction (i.e., Fig.11 (b) in the X direction) of the active region and the shallow trench isolation. Fig.11 As shown in (b), the active region allows the access transistor to be made by a self-alignment technique. This fabric-like checkerboard pattern of the self-aligned structure for making the gate structure of the access transistor and the word line in one process step is the third main technical feature of the present invention.

[0266] In step 130, if Fig.12 As shown in (a), the photoresist layer 1106 is retained to etch away the pad nitride layer 206, but the pad oxide layer 204 is retained, and Fig.12 As shown in (b), the photoresist layer 1106 and the pad oxide layer 204 are removed. As a result, the horizontal silicon surface 208 (i.e., HSS) is exposed as shown in FIG. Fig.12(b) The cross-point square area shown in FIG. 1 , wherein the cross-point square area corresponds to the active area (located at Fig.11 (a) and Fig.11 (b) The intersection point is shown as a square).

[0267] In step 132, if Fig.13 As shown in FIG. 1 , the horizontal silicon surface 208 exposed in the square area of ​​the intersection is etched by the anisotropic etching technology to form a groove (e.g., the U-shaped groove), wherein the U-shaped groove is used to form the U-shaped channel 1302 of the access transistor, and the vertical depth of the U-shaped groove starting from the horizontal silicon surface 208 can reach about 60 nanometers, that is, Fig.13 As shown, the U-shaped channel 1302 is located below the horizontal silicon surface 208. Because the U-shaped groove of the access transistor is exposed, the U-shaped channel 1302 in the U-shaped groove can be doped with a properly designed concentration of boron (p-type dopant) to achieve channel doping, wherein the channel doping is to enable the access transistor to have a desired threshold voltage after a high-k metal-gate structure is subsequently formed. A high-k dielectric insulating layer 1304 is then formed at the bottom and sidewalls of the U-shaped groove, wherein the high-k dielectric insulating layer 1304 serves as the gate dielectric layer of the access transistor, wherein as shown in FIG. Fig.13 As shown, the tops of both edges of the high dielectric constant insulating layer 1304 are above the horizontal silicon surface 208. Then, a gate material 1306 suitable for the word line conductivity and capable of achieving the targeted work-function performance of the access transistor is selected so that the access transistor has a lower threshold voltage (the purpose of selecting the gate material 1306 is to reduce the boosted word line voltage as much as possible but still provide sufficient driving force to complete the sufficient charge amount for restoring the capacitor (1C), and on the other hand, to facilitate faster charge transfer for signal detection).

[0268] The gate material 1306 is sufficient to fill the U-shaped groove (such as Fig.13). Then, the gate material 1306 is etched back to generate a longitudinal (the Y direction) word line sandwiched between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104). For example, the gate material 1306 can be tungsten (W) used to form the high dielectric constant metal-gate structure, wherein if the U-shaped channel 1302 has a suitable doping concentration, the high dielectric constant metal-gate structure can allow the access transistor to have a desired lower threshold voltage.

[0269] The access transistor (hereinafter referred to as U-shaped transistor) with a U-shaped channel 1302 disclosed in the present invention is different from the recessed transistor commonly used in the buried word line design disclosed in the prior art. The body of the U-shaped transistor is limited by the second oxide layer 1002 (i.e., CVD-STI-Oxide2) on both sides along the Y direction (i.e., the channel width direction), and the channel length of the U-shaped transistor includes the depth of the side of the U-shaped channel 1302 corresponding to the drain of the U-shaped transistor, the length of the bottom of the U-shaped channel 1302, and the depth of the side of the U-shaped channel 1302 corresponding to the source of the U-shaped transistor. For example, if the vertical depth of the U-shaped groove is 60 nanometers and the opening of the U-shaped groove along the X direction (i.e., the channel length direction) is 7 nanometers, the total length of the U-shaped channel 1302 of the U-shaped transistor can reach about 127 nanometers. In contrast, the channel length of the embedded transistor must be more dependent on the depth to which the gate material of the embedded transistor is embedded and the depth to which the source and drain junctions of the embedded transistor are formed.

[0270] Due to the structural differences between the U-shaped transistor and the embedded transistor, the channel length of the U-shaped channel 1302 can be better controlled (especially when the channel length of the U-shaped channel 1302 does not need to depend on the height of the gate structure of the U-shaped transistor). In addition, because the horizontal silicon surface 208 is fixed, the doping concentration distribution of the drain and source of the U-shaped transistor has less device-design-parameter variation and is more controllable, which will be described in more detail later on how to complete the drain and source of the U-shaped transistor. In addition, in the longitudinal direction, the gate structure and the word line of the U-shaped transistor are formed simultaneously by self-alignment between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104), which is a way to prevent the word line from being located below the horizontal silicon surface 208, wherein the word line that is not located below the horizontal silicon surface 208 has design and performance parameters that are quite different from those of the buried word line commonly used in the prior art. In addition, as Fig.13 As shown, the height of the word line (that is, the gate material 1306) is designed to be lower than the height of the composite layer (composed of the third oxide layer 1102 and the second nitride layer 1104) by etching back. In addition, the structural design that the gate structure of the U-type transistor is self-alignedly connected to the word line is the fourth main technical feature of the present invention.

[0271] In step 134, if Fig.14 As shown, a third nitride layer 1402 (i.e., a dielectric cap) is deposited, and then a fourth oxide layer 1404 is deposited, wherein the third nitride layer 1402 and the fourth oxide layer 1404 are stacked together so that their total thickness is sufficient to fill the gap between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104). Then, the fourth oxide layer 1404 is etched back (or polished) so that the top of the fourth oxide layer 1404 is flush with the top of the second nitride layer 1104, thereby forming a composite layer composed of the fourth oxide layer 1404 and the third nitride layer 1402 directly above the word line (i.e., the gate material 1306).

[0272] In step 136, if Fig.15 As shown, the second nitride layer 1104 is etched away by the anisotropic etching technique, and the fourth oxide layer 1404 / third nitride layer 1402 on the word line is retained. Then the third oxide layer 1102 is also etched away by the anisotropic etching technique to expose the pad nitride layer 206. The gate structure (e.g., the fourth oxide layer 1404 / third nitride layer 1402 / gate material 1306) simultaneously implements the gate structure of the U-shaped transistor in the U-shaped groove and the word line in the longitudinal direction (that is, the Y direction).

[0273] In step 138, if Fig.16 As shown, the pad nitride layer 206 is removed to leave the pad oxide layer 204. The second oxide layer 1002 (ie, CVD-STI-oxide2) is etched back to make the top of the second oxide layer 1002 flush with the top of the pad oxide layer 204.

[0274] In step 140, if Fig.16 As shown, a fourth nitride layer 1602 is deposited and etched by the anisotropic etching technique to generate a fourth nitride spacer with a carefully designed thickness. A fifth oxide layer 1604 is then deposited and etched by the anisotropic etching technique to generate a fifth oxide spacer. A first polysilicon layer 1606 is then deposited (wherein the first polysilicon layer 1606 is intrinsic and undoped) as shown. Fig.16 The first polysilicon layer 1606 is then etched by the anisotropic etching technique to create a first polysilicon spacer to form surrounding word lines (e.g., first word line wordline-1, second word line wordline-2, third word line wordline-3). Therefore, in summary, the first polysilicon spacer is outside the fifth nitride spacer, the fifth oxide spacer is outside the fourth nitride spacer, and all of the above spacers surround and are along the gate structure (e.g., fourth oxide layer 1404 / third nitride layer 1402 / gate material 1306).

[0275] like Fig.16, as shown in 17, in order to conveniently and clearly describe the dynamic random access memory storage cell array having the word lines and the bit lines, the word line located in the center is marked as the first word line wordline-1 (corresponding to the access transistor AQ1), the word line adjacent to the left of the first word line wordline-1 is marked as the second word line wordline-2 (corresponding to the access transistor AQ2 adjacent to the left of the access transistor AQ1), and the pad oxide layer 204 still covers the area between the first word line wordline-1 and the second word line wordline-2 as the drain to reserve the first drain Drain-1 of the access transistor AQ1 and the second drain drain-2 of the access transistor AQ2. The word line adjacent to the right of the first word line wordline-1 is marked as the third word line wordline-3 (corresponding to the access transistor AQ3 adjacent to the right of the access transistor AQ1), and the pad oxide layer 204 still covers the area between the first word line wordline-1 and the third word line wordline-3 as the source to reserve the first source source-1 of the access transistor AQ1 and the third source source-3 of the access transistor AQ3.

[0276] In step 142, if Fig.17 As shown, a spin-on dielectric 1702 is deposited, wherein the thickness of the spin-on dielectric 1702 is sufficient to fill the gaps (corresponding to the region serving as the drain and the region serving as the source) between the above-mentioned word lines (the first word line wordline-1, the second word line wordline-2, and the third word line wordline-3), and then the spin-on dielectric 1702 is polished by the chemical mechanical planarization technique so that the top of the spin-on dielectric 1702 is flush with the top of the fourth oxide layer 1404. Then, the upper half of the first polysilicon layer 1606 is etched by the anisotropic etching technique. Then, a first oxide cap layer 1704 is deposited to fill the gap above the top of the first polysilicon spacer layer, and then the first oxide cap layer 1704 is planarized by the chemical mechanical planarization technique so that the top of the first oxide cap layer 1704 is flush with the top of the fourth oxide layer 1404.

[0277] In step 144, if Fig.18 As shown, the spin-on dielectric 1702 is etched away, wherein the spin-on dielectric 1702 has a much higher etching rate than the thermally generated oxide layer and the deposited oxide layer, so when the spin-on dielectric 1702 is etched away, the thermally generated oxide layer and the deposited oxide layer can still remain in good condition. Then the fifth nitride layer 1802 is deposited as shown in FIG. Fig.18 over the entire surface shown.

[0278] In step 146, if Fig.19As shown, a spin-on dielectric 1902 is deposited, wherein the thickness of the spin-on dielectric 1902 is sufficient to fill the gaps between the above-mentioned word lines (the first word line wordline-1, the second word line wordline-2, and the third word line wordline-3), and then the spin-on dielectric 1902 is polished by the chemical mechanical planarization technology to make the top of the spin-on dielectric 1902 flush with the top of the fifth nitride layer 1802. Then, a photoresist 1904 is deposited on the flush surface to cover the spin-on dielectric 1902 corresponding to the drain (the first drain drain-1 and the second drain drain-2), and to expose the spin-on dielectric 1902 corresponding to the source (the first source source-1 and the third source source-3) for subsequent processing. Then, the fifth nitride layer 1802 surrounding the word lines (the first word line wordline-1, the second word line wordline-2, and the third word line wordline-3) can be used as a self-alignment mask to remove the spin-on dielectric 1902 corresponding to the source (the first source source-1 and the third source source-3). After the desired pattern has been transferred to the spin-on dielectric 1902, all unnecessary photoresist is removed, thereby making the spin-on dielectric 1902 planar (such as Fig.19 shown).

[0279] In step 148, if Fig. 20 As shown, the exposed fifth nitride layer 1802 and the pad oxide layer 204 at the center of the source region between the two word lines (the first word line wordline-1 and the third word line wordline-3) are etched away to expose the horizontal silicon surface 208. Because the exposed horizontal silicon surface 208 is located between the first source source-1 of the access transistor AQ1 and the third source source-3 of the access transistor AQ3, the horizontal silicon surface 208 between the first source source-1 and the third source source-3 is called the horizontal silicon surface HSS-1 / 3. Fig. 20As shown, the horizontal silicon surface HSS-1 / 2 between the first word line wordline-1 and the second word line wordline-2 is a region serving as the first drain drain-1 (i.e., the drain of the access transistor AQ1) and the second drain drain-2 (i.e., the drain of the access transistor AQ2), and is also a region vertically connecting the access transistors AQ1 and AQ2 to the bit line 902 below the silicon surface. In addition, to the right of the first word line wordline-1, the horizontal silicon surface HSS-1 / 3 between the first word line wordline-1 and the third word line wordline-3 is a region serving as the first source source-1 (i.e., the source of the access transistor AQ1) and the third source source-3 (i.e., the source of the access transistor AQ3), but because the first source source-1 and the third source source-3 will be connected to the unit storage nodes CSN1 and CSN3 (not shown in FIG. 1 ), respectively. Fig. 20 ), so the first source source-1 and the third source source-3 must be separated and cannot be connected.

[0280] In addition, in summary, the photolithography mask technology is used to cover the horizontal silicon surface HSS-1 / 2, but the mask used in the photolithography mask technology is not a critical mask, and its function is only to separate the process of processing the horizontal silicon surface HSS-1 / 3 from the process of processing the horizontal silicon surface HSS-1 / 2. As described above, the thickness of the deposited spin-on dielectric 1902 must be sufficient to form a smooth surface morphology, and then the photoresist 1904 is deposited as a mask material to protect the spin-on dielectric 1902 covering the drain but expose the source. In addition, the spin-on dielectric 1902 is used because the spin-on dielectric 1902 has a high etching rate and can be removed without damaging other existing materials, and the spin-on dielectric 1902 can resist other thermal processes except photoresist.

[0281] like Fig. 20 As shown, the silicon material below the horizontal silicon surface HSS-1 / 3 (corresponding to the center of the source region) is excavated by the anisotropic etching to generate a hole hole-1 / 3, wherein two opposite sides of the hole hole-1 / 3 (not shown in FIG. Fig. 20 ) is surrounded by the first nitride spacer layer and the first oxide spacer layer at the lower edge and the other two pairs of sides of the hole hole-1 / 3 are surrounded by the substrate 202.

[0282] In step 150, if Fig.21As shown, the photoresist 1904 is removed, and the seventh oxide layer 2102 is thermally generated to fill the hole hole-1 / 3, wherein because no oxide will grow on the fifth nitride layer 1802, the seventh oxide layer 2102 will only partially grow on the top of the first oxide cap layer 1704 that is not covered by the fifth nitride layer 1802. In addition, the seventh oxide layer 2102 filling the hole hole-1 / 3 is called a seventh oxide plug (oxide-7 plug), wherein the seventh oxide plug has a smooth surface, and its height is flush with the top of the pad oxide layer 204.

[0283] In step 152, if Fig. 22 As shown, a spin-coated dielectric 2202 is deposited, wherein the spin-coated dielectric 2202 must be thick enough to fill the vacancy above the top of the seventh oxide layer 2102 in the hole hole-1 / 3, and then the top material of the spin-coated dielectric 2202 is removed by the chemical mechanical planarization technology until the top of the spin-coated dielectric 2202 is flush with the top of the fifth nitride layer 1802.

[0284] In step 154, if Fig.23 As shown, the deposited photoresist 2302 covers the area corresponding to the source and exposes the area reserved for the drain, wherein the mask used in step 154 ​​is not a critical mask, and its function is only to separate the process of processing the horizontal silicon surface HSS-1 / 3 from the process of processing the horizontal silicon surface HSS-1 / 2. Then the exposed spin-on dielectric 1902, the exposed fifth nitride layer 1802, and the exposed pad oxide layer 204 are removed to expose the horizontal silicon surface (that is, the horizontal silicon surface HSS-1 / 2). Then, the silicon material corresponding to the horizontal silicon surface HSS-1 / 2 is excavated and removed by the anisotropic etching technology to produce a hole hole-1 / 2, wherein two pairs of sides of the hole hole-1 / 2 are surrounded by the substrate 202, and the third side of the hole hole-1 / 2 (not shown) Fig.23 ) is surrounded by the first nitride spacer layer at the lower edge, and the fourth side of the hole hole-1 / 2 (not shown in FIG. Fig.23 ) is surrounded by the first oxide spacer layer, and the third side and the fourth side of the hole hole-1 / 2 are further surrounded by the second oxide layer 1002 (ie, CVD-STI-oxide2, not shown in FIG. Fig.23 ) at the external limit.

[0285] In step 156, if Fig.24As shown, the photoresist 2302 is removed, and then the eighth oxide layer 2402 is thermally generated to produce an eighth oxide spacer, wherein among the four sidewalls of the hole hole-1 / 2, except for the third sidewall which is covered by the first nitride spacer at the lower edge, the eighth oxide spacer covers the remaining three sidewalls of the four sidewalls of the hole hole-1 / 2 and the bottom of the hole hole-1 / 2. In addition, the eighth oxide layer 2402 is partially grown on the top of the first oxide cap layer 1704. Fig.25 is a schematic diagram illustrating a cross-sectional view of the dynamic random access memory cell array along the Y2 direction, wherein the Y2 direction extends along the center of the hole Hole-1 / 2 and is perpendicular to the X direction. Fig.25 As shown, the active region is sandwiched between the second oxide layer 1002 (CVD-STI-Oxide 2), the under-silicon bit line 902 (UGBL), the first oxide spacer, and the lower edge first nitride spacer.

[0286] In step 158, if Fig.26 , 27 As shown, the first nitride spacer layer at the lower edge on the third sidewall in the hole hole-1 / 2 is removed by the isotropic etching technique, and the fifth nitride layer 1802 (as shown in FIG. Fig. 27 As shown, because the first nitride spacer layer at the lower edge is very thin, the isotropic etching technology will not damage other structures above the horizontal silicon surface 208, and will not remove the eighth oxide layer 2402 in the hole Hole-1 / 2).

[0287] In step 160, if Fig.28 As shown, a metal layer (e.g., tungsten) 2802 is deposited, wherein the thickness of the metal layer 2802 is sufficient to fill the hole hole-1 / 2, and then the metal layer 2802 on the horizontal silicon surface 208 is etched back by the isotropic etching technique to leave a tungsten plug in the hole hole-1 / 2. Fig.28 As shown, the tungsten plug is connected to the silicon surface lower bit line 902 (UGBL) through the opening on the third sidewall of the hole hole-1 / 2, wherein the third sidewall of the hole hole-1 / 2 is originally covered by the first nitride spacer at the lower edge. Then, a sixth nitride layer 2804 is deposited and etched by the anisotropic etching technology to create the sixth nitride spacer, wherein the sixth nitride spacer surrounds the first polysilicon spacer corresponding to the drain.

[0288] In step 162, if Fig.29 As shown, the upper half of the tungsten plug below the horizontal silicon surface 208 is etched back, wherein as shown in FIG. Fig.30 As shown, in the hole Hole-1 / 2, the tungsten plug is connected to the sidewall of the lower silicon bit line 902 (UGBL) through the sidewall thereof.

[0289] In step 164, if Fig.31 As shown, an appropriate amount of the upper half of the eighth oxide layer 2402 is removed by the anisotropic etching technology, resulting in the height of the eighth oxide spacer being lower than the height of the tungsten plug. Fig.31 As shown, portions of the first oxide cap layer 1704 may also be etched away.

[0290] In step 166, if Fig.32 As shown, an n+ in-situ doped silicon layer 3202 is laterally grown from two exposed silicon edges (adjacent to and above the eighth oxide layer 2402 and the tungsten plug) by the selective epitaxial growth (SEG) technology, resulting in a necklace-type conductive n+ silicon drain (called an n+ silicon drain-collar) connected to the horizontal silicon surface 208 on both sides of the hole hole-1 / 2, which can serve as the first drain drain-1 of the access transistor AQ1 and the second drain drain-2 of the access transistor AQ2, respectively, and can also serve as a conductive bridge (that is, a bridge contact) between the bit line 902 (UGBL) under the silicon surface and the access transistors AQ1 and AQ2.

[0291] In step 168, if Fig.33 As shown, a ninth oxide layer 3302 with a well-designed thickness is locally thermally generated on the n+ silicon drain ring to cover the horizontal silicon surface HSS-1 / 2 (and the ninth oxide layer 3302 may cover the first oxide cap layer 1704). The above connection method for forming the conductive bridge between the silicon surface under bit line 902 (UGBL) and the first drain drain-1 (or the second drain drain-2) is the sixth main technical feature of the present invention, wherein the first drain drain-1 and the second drain drain-2 are oxide-capped n+ drains.

[0292] In step 170, if Fig.34 As shown, the portion of the ninth oxide layer 3302 covering the n+ silicon drain ring is etched back to make the thickness of the ninth oxide layer 3302 the same as the height of the pad oxide layer 204, and the ninth oxide layer 3302 covering the first oxide cap layer 1704 is etched away. Then, a polysilicon layer-a 3402 is deposited in the vacancy above the ninth oxide layer 3302 and the polysilicon layer-a 3402 is etched back.

[0293] In step 171, if Fig.35 As shown, the sixth nitride spacer (sixth nitride layer 2804) is removed by the anisotropic etching technique. Polysilicon layer-b 3502 is deposited. Then, the polysilicon layer-b 3502 is etched back by the anisotropic etching technique so that the polysilicon layer-b 3502 can fill the vacancy after the sixth nitride spacer is removed (wherein the vacancy after the sixth nitride spacer is removed is adjacent to the polysilicon layer-a 3402), and the thickness of the polysilicon layer-b 3502 is almost the same as the thickness of the polysilicon layer-a 3402.

[0294] In step 172, if Fig.36 As shown, all the spin-on dielectric layers (ie, spin-on dielectric 1902 and spin-on dielectric 2202) and the fifth nitride layer 1802 are removed by the isotropic etching technique. In addition, Fig.37 is a schematic diagram illustrating a top view of the dynamic random access memory storage cell (HCoT cell) array, wherein Fig.37 In particular, the geometric arrangement of the word lines (first word line wordline-1, second word line wordline-2, third word line wordline-3), the under-silicon bit line (UGBL), the sources of access transistors AQ1 and AQ3 (first source source-1 and third source source-3), and the drains of access transistors AQ1 and AQ2 (first drain drain-1 and second drain drain-2) are shown.

[0295] In step 173, if Fig.38 As shown, a metal layer (eg, tungsten) 3802 is deposited and a portion of the metal layer 3802 is etched back to form tungsten buffer walls (W-Buffer-Walls, WBW).

[0296] In step 174, if Fig.39 As shown, the first oxide cap layer 1704 above the first polysilicon spacer is removed. Then, the first polysilicon spacer and the pad oxide layer 204 below the first polysilicon spacer are etched away. In this way, the horizontal silicon surfaces 208 corresponding to the source and the drain are exposed (referred to as the seeding HSS area for source and drain regions, SHAR) respectively.

[0297] In step 175, if Fig.40As shown, the source electrode EH-1S and the drain electrode EH-1D are respectively generated in the vertical direction above the horizontal silicon surface 208 by using the seed silicon surface area for the source and the drain as a seed using the selective epitaxial growth technology, wherein the source electrode EH-1S and the drain electrode EH-1D can be gradually generated well by using the seed silicon surface area for the source and the drain as a seed, so the source electrode EH-1S and the drain electrode EH-1D can be pure silicon material instead of polycrystalline or amorphous silicon material, and the left side wall and the right side wall of the source electrode EH-1S and the drain electrode EH-1D along the X direction are respectively surrounded by the tungsten buffer wall and the fifth oxide spacer. Although the other two side walls along the Y direction are open, the second oxide layer 1002 (CVD-STI-oxide2) cannot provide a seed function for growing selective epitaxial silicon. Therefore, the growth of selective epitaxial silicon should result in some lateral overgrowth of pure silicon material stopping at the edge of the second oxide layer 1002 (CVD-STI-oxide2) and not causing the connection of adjacent electrodes. In addition, after the source electrode EH-1S and the drain electrode EH-1D are generated, a rapid thermal annealing (RTA) step can be selectively used to form an n+ lightly doped drain (NLDD) 4012 for connecting the source electrode EH-1S (or the drain electrode EH-1D) to the U-shaped channel 1302.

[0298] The new process design for completing the source electrode EH-1S and the drain electrode EH-1D is described as follows:

[0299] (1) When the source electrode EH-1S and the drain electrode EH-1D are grown by using the seed silicon surface region (SHAR) for source and drain as a seed and utilizing the selective epitaxial growth technique, it is important to design a suitable n+ in-situ doping concentration (in-situ doping concentration) during the silicon growth process to achieve an appropriate interface conductance of the channel region of the access transistor (wherein the interface conductance includes the conductance of the horizontal silicon surface 208 directly below the gate dielectric layer (high dielectric constant insulating layer 1304), the conductance of the horizontal silicon surface 208 below the fourth nitride spacer / the fifth oxide spacer, and the conductance of the horizontal silicon surface 208 below the source electrode EH-1S or the conductive electrode EH-1D) to achieve low leakage current, in particular, gate induced drain leakage (GIDL), drain induced barrier lowering (DIBL), sub-threshold leakage due to the short-channel effect), and junction leakages, etc.

[0300] (2) Fig.40 As shown, the source electrode EH-1S and the drain electrode EH-1D grow to a specific height, wherein the height of the source electrode EH-1S and the drain electrode EH-1D is lower than the final height of the EH-1+2 electrode (that is, the source electrode EH-1+2S and the drain electrode EH-1+2D subsequently generated in step 177). In step 176, as shown in FIG. Fig.41As shown, the fifth oxide spacer is first etched away by the isotropic etching technique to leave a seam between the fourth nitride spacer and the drain electrode EH-1D (between the fourth nitride spacer and the source electrode EH-1S). The oxide layer-a 4102 is thermally generated to cover the other three side walls and the top (called oxide-a-cap layer) except the fourth side wall of the drain electrode EH-1D (or the source electrode EH-1S), wherein the fourth side wall of the drain electrode EH-1D (or the source electrode EH-1S) is limited by the tungsten buffer wall. The purpose of performing such a fine stepped source electrode formation process as described below is to ensure that the top of the source electrode EH-1S (or the top of the drain electrode EH-1D) has a high-performance silicon oxide interface due to the thermally generated oxide layer-a 4102 having a very high-quality silicon dioxide to silicon electrode bond (wherein the amorphous or low-quality silicon material derived from the selective epitaxial growth process may undoubtedly reduce the quality of the silicon source electrode and thus cause a large number of defects that may increase the leakage current when the access transistor is turned off instead of reducing the carrier mobility (resulting in the inability to transmit sufficient on-current when the access transistor is turned on). Then, the capping portion of the oxide layer-a 4102 is etched by the anisotropic etching technology to leave a portion of the oxide layer-a 4102, which exists between the fourth nitride spacer source electrode EH-1S (or between the fourth nitride spacer and the drain electrode EH-1D).

[0301] (3) In step 177, if Fig.42 As shown, a second selective epitaxial growth is performed by using the exposed silicon surface of the source electrode EH-1S and the drain electrode EH-1D as high-quality silicon seeds to generate the source electrode EH-2S and the drain electrode EH-2D respectively. In the process of performing the second selective epitaxial growth, in order to prepare for the low-impedance connection between the source electrode EH-2S (or the drain electrode EH-2D) and the signal electrode of the stacked storage capacitor (SSC) to be manufactured later, a well-designed n+ in-situ heavy doping concentration (heavier in-situ n+doping concentration) can be achieved in the source electrode EH-2S and the drain electrode EH-2D. In addition, the combination of the source electrode EH-1S and the source electrode EH-2S is called the source electrode EH-1+2S (similarly, the combination of the drain electrode EH-1D and the drain electrode EH-2D is called the drain electrode EH-1+2D). In addition, taking the source electrode EH-1+2S as an example, as Fig.42As shown, the upper half of the source electrode EH-1+2S (that is, the source electrode EH-2S) has some high-quality features, such as the n+ doped silicon material of one sidewall of the source electrode EH-2S directly adjacent to the fourth nitride spacer, a sidewall in the opposite direction of the sidewall of the source electrode EH-2S adjacent to the tungsten buffer wall, and the remaining two sidewalls of the source electrode EH-2S open along the word line in the Y direction. In addition, the height of the source electrode EH-1+2S (or the drain electrode EH-1+2D) is well designed to be lower than the height of the fourth nitride spacer.

[0302] In step 178, if Fig.43 As shown, a first spin-on dielectric 4302 is deposited on top of the drain electrode EH-2D and the source electrode EH-2S, respectively, and the first spin-on dielectric 4302 is etched back.

[0303] In step 179, if Fig.44 As shown, the tungsten buffer wall is etched away on the entire wafer surface.

[0304] In step 180, if Fig.45 As shown, a nitride layer-a 4502 is deposited, and the nitride layer-a 4502 is etched by the anisotropic etching technique to form the nitride layer-a spacer surrounding all side walls of the source electrode EH-1+2S and the drain electrode EH-1+2D. Fig.45 As shown, the nitride layer-a spacer layer surrounding the source electrode EH-1+2S (drain electrode EH-1+2D) stands on top of the polysilicon layer-a 3402 and the polysilicon layer-b 3502 acting like a mattress, but on the side of the source electrode EH-1+2S (drain electrode EH-1+2D), there is no polysilicon layer-a 3402 and polysilicon layer-b 3502 acting like a mattress.

[0305] In step 181, if Fig.46As shown, the polysilicon layer-a 3402 is first removed by the anisotropic etching technique (at this time, the remaining silicon regions (such as the drain electrode EH-2D and the source electrode EH-2S) can be well protected by the first spin-on dielectric 4302 and the nitride layer-a spacer). Then, after the polysilicon layer-b 3502 is etched away by the isotropic etching technique, since a seam (or vacancy) can be formed by the removal of the polysilicon layer-a 3402 and the polysilicon layer-b 3502, the isotropic etching technique can be used to etch away a portion of the bottom of the drain electrode EH-1D. It is noteworthy that (1) due to the high-quality silicon bonding force, the remaining bottom of the drain electrode EH-1D can still maintain the strength for supporting the upper half of the drain electrode EH-1D, and (2) because the nitride-a spacer surrounding the EH-1+2 electrode has feet standing on the top of the second oxide layer 1002 (i.e., CVD-STI-oxide2), and the strong glue of the nitride-a spacer due to chemical bonds, the nitride-a spacer is not completely suspended. The ultimate goal of creating this novel process design is to expose the horizontal silicon surface 208 located below the drain electrode EH-1D.

[0306] In step 182, if Fig.47 As shown in Fig.46 A thermal oxidation process is performed to generate a high-quality oxide layer-bb 4702 by a thermochemical reaction between silicon and silicon dioxide on the exposed horizontal silicon surface 208, thereby resulting in an oxide isolation layer (oxide layer-bb 4702) that well isolates the drain from the bottom of the drain electrode EH-1+2D, wherein the drain electrode EH-1+2D can be used as part of the signal electrode of the storage capacitor.

[0307] In step 183, if Fig.48 As shown, the nitride layer-a spacer and the first spin-on dielectric 4302 corresponding to the EH-1+2 electrodes (that is, the source electrode EH-1+2S and the drain electrode EH-1+2D) are removed by the isotropic etching technology. Then, in step 184, as shown in FIG. Fig.49 As shown, a first high dielectric constant insulating layer 4902 is formed.

[0308] In step 185, if Fig.50As shown, a metal layer (e.g., tungsten) 5002 is deposited and etched back so that the height of the residual metal layer 5002 with a well-designed thickness is slightly higher than the height of the EH-1+2 electrodes (that is, the source electrode EH-1+2S and the drain electrode EH-1+2D), but is approximately equal to the height of the fourth nitride spacer. At this time, the metal layer 5002 that is prevalent on the surface of the wafer is called the first metal counter-electrode plate and wall (metal-counter-electrode-plate&wall-1, MCEPW-1). The first metal counter-electrode plate and wall covers a portion of the high-K-cap-1 of the first high dielectric constant insulating layer 4902 above the EH-1+2 electrodes, and may cover the fourth oxide layer 1404 in the composite layer (composed of the fourth oxide layer 1404 and the third nitride layer 1402) and the top of the fourth nitride spacer.

[0309] In step 186, if Fig.51 As shown, the first high dielectric constant insulating layer 4902 above the fourth oxide layer 1404 is removed by the anisotropic etching technology, and then the fourth oxide layer 1404 (the top layer of the composite layer composed of the fourth oxide layer 1404 and the third nitride layer 1402) is etched away without damaging the high-K-cap-1 of the first high dielectric constant insulating layer 4902 covered by the first metal counter electrode plate and wall (MCEPW-1) and the first high dielectric constant insulating layer 4902. Therefore, there is a canal-like groove above the composite layer (composed of the fourth oxide layer 1404 and the third nitride layer 1402), and the fourth nitride spacer is provided on both sides of the composite layer, wherein the height of the upper half of the fourth nitride spacer is higher than the thickness of the third nitride layer 1402 and stands like a fence but is exposed in the direction facing the canal-like groove.

[0310] In step 187, if Fig.52 As shown, the upper half of the third nitride layer 1402 having a well-designed thickness above the composite layer is removed by the isotropic etching technology, and the upper half of the fourth nitride spacer is also removed by the isotropic etching technology so that the top of the remaining portion of the fourth nitride spacer is flush with the top of the remaining portion of the third nitride layer 1402. In addition, after the fourth nitride spacer loses its upper half due to the isotropic etching technology, the height of the fourth nitride spacer becomes lower, resulting in the upper half of the silicon sidewalls of the EH-2 electrodes (that is, the source electrode EH-2S and the drain electrode EH-2D) facing the fourth nitride spacer being exposed.

[0311] In step 188, if Fig.53As shown, the n+ in-situ doped silicon material is grown laterally above the third nitride layer 1402 through the silicon sidewall exposed in the direction of the word line (that is, the direction facing the fourth nitride spacer mentioned above) through the EH-2 electrode (that is, the source electrode EH-2S and the drain electrode EH-2D) using the selective epitaxial growth technology. With the first word line wordline-1 as a reference, the source electrode EH-1+2S and the drain electrode EH-1+2D are respectively on both sides of the first word line wordline-1. By controlling the growth time, the epitaxial silicon (called the source electrode LGS-2S) grown laterally from the source electrode EH-2S and the epitaxial silicon (called the drain electrode LGS-2D) grown laterally from the drain electrode EH-2D are not allowed to contact the center above the first word line wordline-1, and instead, there is a carefully designed gap in the horizontal space (or vacancy).

[0312] In step 189, if Fig.54 As shown, a high-quality nitride layer-cc 5402 is deposited and the chemical mechanical planarization technique is used to expose the drain electrode LGS-2D and the source electrode LGS-2S, wherein there is a nitride-cc isolation layer (that is, nitride layer-cc 5402) between the drain electrode LGS-2D and the source electrode LGS-2S, which can completely separate the drain electrode LGS-2D and the source electrode LGS-2S. At the same time, the first metal counter electrode plate and the upper half of the wall and the first high dielectric constant insulating layer 4902 are removed by either the chemical mechanical planarization technique or etching, and the height of the remaining part of the first metal counter electrode plate and the wall and the first high dielectric constant insulating layer 4902 is flush with the height of the drain electrode LGS-2D and the height of the source electrode LGS-2S, respectively.

[0313] In step 190, if Fig.55 As shown, the first metal counter electrode plate and wall (ie, metal layer 5002) are removed.

[0314] In step 191, if Fig.56As shown, by using the exposed drain electrode LGS-2D and the source electrode LGS-2S as seeds (referred to as SBSES-D and SBSES-S, respectively, where SBSES is the abbreviation of Seeding Base for Growing Storage-Electrode Skyscraper), the selective epitaxial growth technology is performed to create a twin-tower storage electrode for the H-type storage capacitor, and the following description will show how to complete the twin-tower storage electrode of the H-type storage capacitor (the twin-tower storage electrode has two electrode towers: the one above the drain is called the drain electrode tower LGS-2D-Tower, and the one above the source is called the source electrode tower LGS-2S-Tower).

[0315] In step 192, if Fig.57 As shown, the oxide layer-d 5702 is thermally generated and the oxide layer-d 5702 on the top of the drain electrode tower LGS-2D-Tower and the source electrode tower LGD-2S-Tower is removed by the anisotropic etching technology to form the oxide layer-d spacer. Then the nitride layer-cc 5402 is removed by the isotropic etching technology to expose the sides of the drain electrode LGS-2D and the source electrode respectively.

[0316] In step 193, if Fig.58 As shown, the selective epitaxial growth technique is used to laterally grow n+ heavily in-situ-doped silicon material from the exposed silicon regions of the drain electrode LGS-2D and the source electrode LGS-2S until a connecting silicon layer LGS-2DS is formed. Fig.58 As shown, the selective epitaxial growth technology is also used to vertically grow n+ in-situ heavily doped silicon material from the top of the drain electrode tower LGS-2D-Tower and the source electrode tower LGD-2S-Tower. Fig.58 As shown, the horizontal connection region (including the connecting silicon layer LGS-2DS) connects a vertical protruding region of an H-shaped capacitor (for example, the drain electrode EH-1+2D) and another vertical protruding region of the H-shaped storage capacitor (for example, the source electrode EH-1+2S), wherein the horizontal connection region does not have to be coupled to the middle of the two vertical protruding regions of the H-shaped storage capacitor, that is, the horizontal connection region can be coupled to the higher or lower region of the two vertical protruding regions of the H-shaped storage capacitor.

[0317] In step 194, if Fig.59 As shown, the oxide layer-d spacer layer is then removed. In step 195, as Fig.60As shown, the first high dielectric constant insulating layer 4902 is removed by the isotropic etching technology and a second high dielectric constant insulating layer 6002 is formed around the double-tower-shaped storage electrode.

[0318] In step 196, if Fig.61 As shown, a metal layer (e.g., tungsten) 6102 is deposited (wherein the metal layer 6102 is the second metal counter electrode plate and wall (MCEPW-2)), and then the metal layer 6102 is etched back or the metal layer 6102 is planarized using the chemical mechanical planarization technique to produce a flat surface. Fig.61 As shown, the H-type storage capacitor included in the dynamic random access memory storage cell (HCoT cell) has the double tower storage electrode (also called double tower H-type storage electrode), wherein the second high dielectric constant layer 6002 completely covers the double tower storage electrode from the outside, and the second high dielectric constant layer 6002 is completely covered by the second metal electrode plate and wall (that is, metal layer 6102) biased at a constant voltage level (e.g., half-VCC). Fig.61 As shown, the H-type storage capacitor surrounds the access transistor AQ1 like a saddle tightly clamping the access transistor AQ1 and has a fully extended surface area of ​​the double-tower storage electrode, wherein the fully extended surface area ranges from the horizontal silicon surface 208 at the bottom of the source electrode EH-1S of the access transistor AQ1, to the top of the source electrode tower LGD-2S-Tower and all surface areas surrounding the source electrode tower LGD-2S-Tower, to the top of the drain electrode tower LGS-2D-Tower and all surface areas surrounding the drain electrode tower LGS-2D-Tower, and until it drops to the top of the oxide layer-bb 4702 located at the bottom of the drain electrode EH-1 of the access transistor AQ1. The four sidewall surfaces surrounding the source electrode tower LGD-2S-Tower and the drain electrode tower LGS-2D-Tower are almost all used to produce an almost maximum dielectric area to maximize the capacitance value of the H-type storage capacitor.

[0319] In addition, if the height of the source electrode tower LGD-2S-Tower and the drain electrode tower LGS-2D-Tower must be further extended, Figure 62 to Figure 67 The steps shown in the figure are used to further increase the capacitance value of the H-type storage capacitor. Figure 62 to Figure 67 After several steps, the horizontal connection region between the two vertical protruding regions of the H-type storage capacitor may include a plurality of horizontal sub-connection regions, wherein each of the plurality of horizontal sub-connection regions may connect the two vertical protruding regions of the H-type storage capacitor.

[0320] In step 197, if Fig.62 As shown, the second metal counter electrode plate and the wall are etched back to make their height lower than the height of the twin-tower storage electrode. Then, the second high dielectric constant insulating layer 6002 on the top of the twin-tower storage electrode is etched away by the anisotropic etching technique, leaving only the second high dielectric constant insulating layer 6002 surrounding the twin-tower storage electrode.

[0321] In step 198, if Fig.63 As shown, by using the exposed silicon material on the top of the double tower storage electrode as a seed, the selective epitaxial growth technology is used to generate a higher n+ in-situ heavily doped silicon tower 6301 to serve as the double tower storage electrode of the H-type storage capacitor. Then, the second high dielectric constant insulating layer 6002 is etched by the isotropic etching technology, and a third high dielectric constant insulating layer 6302 is formed to cover all side walls and the top of the n+ in-situ doped silicon tower 6301 to block any electrical connection path or leakage current mechanism that may be from the n+ in-situ doped silicon tower 6301 to the second metal electrode plate and wall.

[0322] In step 199, if Fig.64 As shown, a photoresist 6402 is formed to cover all memory cell array regions except for the edge regions where the second metal counter electrode plate and the wall are exposed. In step 200, as Fig.65 As shown, the third high dielectric constant insulating layer 6302 on the edge area of ​​the second metal electrode plate and the wall exposed is then etched away. In step 201, as Fig.66 As shown, the photoresist 6402 is then removed.

[0323] In step 202, if Fig.67 As shown, a metal (e.g., tungsten W) layer 6702 is deposited and etched back, wherein the metal layer 6702 wraps the sidewalls of all n+ in-situ heavily doped silicon towers 6301 and other valley-like regions on the horizontal silicon surface 208 into a flat plateau, and is referred to as the third metal counter electrode plate and wall (MCEPW-3). The third metal counter electrode plate and wall plus the existing second metal counter electrode plate and wall (MCEPW-2) can not only be used as a counter electrode plate of the H-type storage capacitor biased at a constant voltage level (e.g., half-VCC), but can also be used as a metal shielding plate to achieve better heat dissipation like a metal heat sink, and because the electric field can be more evenly distributed and shielded on the counter electrode plate, the noise of the gate structure of the word line and the access transistor can be further reduced or the noise resistance of the gate structure of the word line and the access transistor can be improved. Fig.67A novel DRAM memory cell (HCoT cell) having an H-type storage capacitor that can clamp the access transistor is shown, wherein the H-type storage capacitor has a maximized capacitance storage area because the H-type storage capacitor has the dual-tower storage electrode. Fig.68 is a schematic diagram illustrating the structure of the HCoT unit disclosed in the present invention.

[0324] Fig.69 is a schematic diagram illustrating a simplified top view of the HCoT cell (1T1C storage cell), wherein Fig.69 Particular attention is paid to the dual-tower storage electrode, and the bottom of the dual-tower storage electrode can be connected and transmitted downward to the source electrode of the access transistor. The cell area of ​​the HCoT cell has a rectangular shape, the H-type storage capacitor includes a capacitor periphery also having a rectangular shape, and the access transistor is located within the capacitor periphery. Except for the isolation tolerance required by the cell area to divide adjacent storage electrodes, the area of ​​the H-type storage capacitor is almost as large as the area of ​​the cell area. As far as the common knowledge in the art is concerned, the H-type storage capacitor disclosed in the present invention should be the most effective design with respect to the ratio between the planar area of ​​the storage capacitor and the planar area of ​​the 1T1C cell.

[0325] In summary, the present invention discloses a new structure of a dynamic random access memory storage cell (the HCoT cell), which not only reduces the size of the dynamic random access memory storage cell, but also improves the signal-to-noise ratio during the operation of the dynamic random access memory. Because the H-type storage capacitor is located above the access transistor and largely covers the access transistor, and has a vertical and horizontal self-alignment technology for arranging and connecting the geometric shapes of the basic microstructures in the dynamic random access memory storage cell, the new structure (the structure of the HCoT cell) can retain the advantages of at least 4 to 10 square units even when the minimum feature size λ is much smaller than 10 nanometers, wherein the area of ​​the H-type storage capacitor can account for 50% to 70% of the area of ​​the HCoT cell.

[0326] In addition, the metal electrode of the H-type storage capacitor in the new structure provides an effective way for heat dissipation, so the temperature of the dynamic random access memory cell can be correspondingly reduced during operation, and then the lower temperature will simultaneously reduce thermal / operational noise and leakage current of the H-type storage capacitor. In addition, the metal electrode further surrounds the word line passing through the access transistor, and the combination of the surrounded word line and the silicon surface under-bit line (UGBL) located below the silicon surface can effectively shield the cross-coupling noise between different word lines / bit lines. In this way, the problematic pattern sensitivity issue that occurs when the dynamic random access memory cell array disclosed in the prior art is operated can be greatly reduced.

[0327] Additionally, a well-designed transistor structure may also reduce gate induced drain leakage (GIDL) current, and the combination of the reduced GIDL current and the reduced current derived from lower operating temperature may further improve the signal-to-noise ratio and enable the use of smaller storage capacitors in the HCoT cell structure without negatively affecting the reliability of the stored data.

[0328] In addition, the subsilicon bit line (UGBL) disclosed in the present invention can flexibly reduce the parasitic resistance and parasitic capacitance of the subsilicon bit line, so the signal sensitivity of the storage capacitor and the subsilicon bit line during charge sharing can be improved, thereby improving the operating speed of the structure of the HCoT unit.

[0329] In summary, Fig.68 is a schematic diagram illustrating the structure of the HCoT unit disclosed in the present invention, wherein Fig.68 correspond Fig.67 Compared with the structure of the DRAM memory cell array disclosed in the prior art, when the minimum feature size λ is less than 10 nanometers, the structure of the HCoT cell shows the following advantages that can help the memory cell size to achieve about 4 to 10 square units (or 4 to 10λ 2) functions: (1) the dual tower storage electrode of the H-type storage capacitor surrounds the access transistor; (2) the electrode plates (the second metal electrode plates and walls and the third metal electrode plates and walls) surround the access transistor and cover the entire dynamic random access memory cell array; (3) the silicon surface bit line is located below the horizontal silicon surface to simplify the surface morphology of the dynamic random access memory cell array; (4) the self-aligned source electrode has an adjustable conductivity to the channel edge to minimize the leakage current of the HCoT cell; (5) the self-aligned dual tower storage electrode extends from the source and rides on top of the access transistor, like a saddle with a self-aligned capacitor tower; (6) most of the HCoT cells can be extended with reliable materials and process steps with sufficient reliability and quality; (7) for most of the dynamic random access memory cells disclosed in the prior art, the shape of the HCoT cell is like a rectangle (L (length) x W (width)), so except that some distance must be reserved to isolate the storage electrodes between adjacent storage capacitors of different storage cells, the HCoT cell has the maximum storage capacitance expansion capability on the rectangle (L x W); (8) As described in the above embodiments, by using the various technologies and methods disclosed in the present invention, the height of the double-tower storage electrode can be gradually established, and the double-tower storage electrode can have the desired good straight tower shape; in addition, in the storage cell (the HCoT cell) area that is further reduced due to component scaling requirements, the ratio of increasing the height of the storage cell (the HCoT cell) to expand the surface area of ​​the H-type storage capacitor to the plane area occupied by the storage cell (the HCoT cell) is effectively improved; (9) Creating multiple storage electrodes with protruding shapes and connected as storage nodes of the H-type storage capacitor can expand its storage area, resulting in a large capacitance value in the limited and reduced plane area occupied by the HCoT cell.

[0330] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor component, characterized in that Include: preparing a semiconductor substrate having an original surface; Forming a group of active regions based on the semiconductor substrate, and forming a shallow trench isolation region between two active regions of the group of active regions; forming a first interconnect structure in the shallow trench isolation region, wherein the first interconnect structure is located below the original surface; A gate region of a transistor is formed in a first active region of the two active regions, and a second interconnect structure is formed across the two active regions and the shallow trench isolation region, the gate region is connected to the second interconnect structure, wherein the second interconnect structure is located at a bottom of the shallow trench isolation region and is not aligned with a bottom of the gate region; as well as A capacitor having a storage electrode is formed, wherein the capacitor covers the transistor.

2. The method according to claim 1, characterized in that The second interconnect structure is located at the bottom of the shallow trench isolation region and is higher than the bottom of the gate region.

3. The method according to claim 1, characterized in that Before forming the first interconnect structure in the shallow trench isolation region, the method further includes: forming a set of asymmetric spacer layers between the two active regions.

4. The method according to claim 3, characterized in that Before forming the capacitor, the method further comprises: forming a bridge contact in the first active region to electrically couple the first interconnect structure, wherein the bridge contact is located below the original surface; and A first conductive region and a second conductive region of the transistor are formed in the first active region.

5. The method according to claim 4, characterized in that The steps of forming the bridge contact include: Producing a first hole in the first active region; forming a first isolation layer on the surface of the first hole; removing a spacer layer in the set of asymmetric spacer layers to expose a sidewall of the first interconnect structure; and A conductive plug is formed in the first hole to electrically couple the sidewall of the first interconnect structure. The conductive plug can be made of metal or doped semiconductor.

6. The method according to claim 5, characterized in that The semiconductor substrate is a silicon substrate, and the step of forming the bridge contact further comprises: removing a portion of the first isolation layer located on a surface of the first hole to expose the silicon material of the silicon substrate; Selectively growing a doped silicon layer based on the exposed silicon material, wherein the doped silicon layer contacts the conductive plug, and the bridge contact includes the conductive plug and the doped silicon layer; and A second isolation layer is formed on the doped silicon layer. 7 . The method of claim 6 , wherein the first isolation layer on the surface of the first hole is a thermally generated oxide layer, and the removed isolation layer is made of a material different from the oxide layer.

8. The method according to claim 4, characterized in that The bridge contact includes metal or doped semiconductor.

9. The method according to claim 8, characterized in that Also includes: A second hole is formed on one side of the second conductive region of the transistor, and an isolation plug is formed in the second hole; wherein the bridge contact electrically couples the first interconnect structure to the first conductive region of the transistor; The step of forming the capacitor comprises: forming the storage electrode electrically coupled to the second conductive region of the transistor, wherein the storage electrode comprises a first protruding region located above the first conductive region of the transistor, a second protruding region located above the second conductive region of the transistor, and a connecting region; wherein the second conductive region is electrically connected to the second protruding region, and the connecting region is located above the gate structure of the transistor and laterally connects the first protruding region and the second protruding region; forming an insulating layer on the storage electrode; as well as A pair of electrodes is formed on the insulating layer, wherein the pair of electrodes covers the first protruding region, the second protruding region, and the connecting region of the storage electrode.

10. The method according to claim 9, characterized in that The semiconductor device is a dynamic random access memory cell, and the transistor is an access transistor of the dynamic random access memory cell.

11. A semiconductor component, characterized in that Include: a semiconductor substrate having a pristine surface; a set of active regions in the semiconductor substrate, and a shallow trench isolation region between two active regions of the set of active regions; a first interconnect structure in the shallow trench isolation region, wherein the first interconnect structure is below the original surface; A gate region of a transistor is located in a first active region of the two active regions; and A second interconnect structure, wherein the gate region is connected to the second interconnect structure.

12. The semiconductor device according to claim 11, characterized in that The first interconnect structure is located between a group of asymmetric spacer layers, and the second interconnect structure spans the two active regions and the shallow trench isolation region, wherein the second interconnect structure is located at a bottom of the shallow trench isolation region and is not aligned with a bottom of the gate region.

13. The semiconductor device according to claim 12, characterized in that It further includes a capacitor, wherein the capacitor covers the transistor, the second interconnect structure is a word line, the first interconnect structure is a bit line, the semiconductor memory is a dynamic random access memory unit, and the transistor is an access transistor of the dynamic random access memory unit.

14. The semiconductor device according to claim 12, characterized in that Also includes: A bridge contact located in the first active region is electrically coupled to the first interconnect structure, the bridge contact being located below the original surface; and A first conductive region and a second conductive region of the transistor are within the first active region.

15. The semiconductor device according to claim 14, characterized in that Also includes: a first hole in the first active region; a first isolation layer on the surface of the first hole; as well as A conductive plug in the first hole is electrically coupled to a side wall of the first interconnect structure, and the conductive plug can be metal or doped semiconductor.

16. The semiconductor device according to claim 15, characterized in that Also includes: a doped silicon layer, wherein the doped silicon layer contacts the conductive plug, and the bridge contact includes the conductive plug and the doped silicon layer; and A second isolation layer is located on the doped silicon layer.

17. The semiconductor device according to claim 16, characterized in that Also includes: A second hole is located at one side of the second conductive region of the transistor; An isolation pin is located in the second hole; wherein the bridge contact electrically couples the first interconnect structure to the first conductive region of the transistor.

18. The semiconductor device according to claim 17, characterized in that The capacitor comprises: a storage electrode electrically coupled to the second conductive region of the transistor, wherein the storage electrode comprises a first protruding region located above the first conductive region of the transistor, a second protruding region located above the second conductive region of the transistor, and a connecting region; wherein the second conductive region is electrically connected to the second protruding region, and the connecting region is located above the gate structure of the transistor and laterally connects the first protruding region and the second protruding region; an insulating layer on the storage electrode; as well as A pair of electrodes is on the insulating layer, wherein the pair of electrodes covers the first protruding region, the second protruding region, and the connecting region of the storage electrode.

19. The semiconductor device according to claim 14, characterized in that The bridge contact includes metal or doped semiconductor.

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