Antifuse type one-time programmable memory and related bias control method

Abstract

A one-time-programmable (OTP) memory with a reverse fuse and a related bias control method are disclosed. The OTP memory includes a first memory cell. The first memory cell includes a reverse fuse transistor. The reverse fuse transistor includes a first nanowire, a first gate structure, a first drain / source structure, and a second drain / source structure. The first nanowire is surrounded by the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer, and a first gate layer. The first drain / source structure is electrically connected to a first end of the first nanowire. The second drain / source structure is electrically connected to a second end of the first nanowire.

Description

Technical Field

[0001] This invention relates to a non-volatile memory and its control method, and more particularly to an antifuse type one-time programmable memory and its associated bias control method. Background Technology

[0002] As is well known, antifuse-type one-time programming memory (OTP memory) is a type of non-volatile memory. Before programming, an antifuse-type OTP memory cell is in a high-resistance state. After programming, it becomes a low-resistance state. Once programmed, the stored data in an antifuse-type OTP memory cell cannot be modified.

[0003] Generally, antifuse OTP memories include peripheral circuitry and an array structure. Both the peripheral circuitry and the array structure are designed on a semiconductor substrate. The array structure includes multiple memory cells, each containing a storage transistor. Additionally, the peripheral circuitry includes control circuitry and power circuitry. The control circuitry controls the power circuitry to provide appropriate bias voltage to selected memory cells in the array structure and performs programming or reading operations on those cells. For example, the power circuitry might be a charge pump.

[0004] Due to the continuous evolution of semiconductor manufacturing processes, transistors have shifted from early planar structures to FinFETs (Fin Field-Effect Transistors). More advanced manufacturing processes have enabled the production of even smaller Gate-All-Around (GAA) transistors. GAA transistors are small in size. Furthermore, because the channel region of a GAA transistor is surrounded by the gate, it possesses excellent gate control capabilities and low source / drain current, and is gradually replacing traditional transistors. Summary of the Invention

[0005] This invention relates to an antifuse type programmable memory (AMP) having a first memory cell, the first memory cell comprising: a P-type semiconductor substrate; a P-type well region located on a surface of the P-type semiconductor substrate; an N-type region formed within the P-type semiconductor substrate and located below the P-type well region, wherein the P-type semiconductor substrate below the N-type region and the P-type well region are not in contact with each other through the N-type region, and the P-type well region is an isolated P-type well region; a first nanowire; a first gate structure including a first spacer wall, a second spacer wall, a first gate dielectric layer, and a first gate layer; wherein the first gate dielectric layer surrounds a central region of the first nanowire, and the first gate... A first gate dielectric layer surrounds the first gate layer, which is electrically connected to a first word line. A first end of the first nanowire is surrounded by the first spacer wall, and a second end of the first nanowire is surrounded by the second spacer wall. The first and second spacers are located above the P-type well region. A first drain / source structure is located above the P-type well region, electrically contacting the first end of the first nanowire, and electrically connected to a first word line. A second drain / source structure is located above the P-type well region and electrically contacting the second end of the first nanowire. The first nanowire, the first gate structure, the first drain / source structure, and the second drain / source structure form a first select transistor. A second nanowire is also included. A second gate structure includes a third spacer, a fourth spacer, a second gate dielectric layer, and a second gate layer; wherein the second gate dielectric layer surrounds a central region of the second nanowire, the second gate layer surrounds the second gate dielectric layer, the second gate layer is electrically connected to a first antifuse control line, a first end of the second nanowire is surrounded by the third spacer, a second end of the second nanowire is surrounded by the fourth spacer, and the third and fourth spacers are located above the P-type well region; a third drain / source structure is located above the P-type well region and electrically contacts the first end of the second nanowire, wherein the third drain / source structure is coupled to the second drain / source structure; and a fourth A drain / source structure is located above the P-type well region and electrically contacts the second end of the second nanowire. The second nanowire, the second gate structure, the third drain / source structure, and the fourth drain / source structure form a first antifuse transistor. During a programming operation, the P-type well region receives a negative programming voltage, the N-type region receives a first voltage, and the P-type semiconductor substrate receives a second voltage. There is a reverse bias between the P-type well region and the N-type region. The reverse bias or a zero bias is also present between the P-type semiconductor substrate and the N-type region. The first voltage is greater than or equal to a ground voltage, the second voltage is greater than or equal to the negative programming voltage, and the second voltage is less than or equal to the first voltage.

[0006] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0007] Figure 1A , Figure 1B and Figure 1C This is a perspective view, a cross-sectional view along the dotted line ab, and a top view of the GAA transistor of the present invention;

[0008] Figure 2A and Figure 2B These are perspective and top views of the two GAA transistors of the present invention;

[0009] Figure 3A , Figure 3B and Figure 3C The images show a top view, a cross-sectional view along the cd dashed line, and a cross-sectional view along the ef dashed line of the array structure of the antifuse type programmable memory according to the first embodiment of the present invention.

[0010] Figure 3D The bias representation of the programming and reading operations of the OTP memory in the first embodiment of the present invention is shown.

[0011] Figure 4A , Figure 4B and Figure 4C The images show a top view, a cross-sectional view along the dashed line gh, and a cross-sectional view along the dashed line ij of the array structure of the antifuse type one-time programmable memory according to the second embodiment of the present invention.

[0012] Figure 4D The bias representation of the programming and reading operations of the OTP memory in the second embodiment of the present invention is shown.

[0013] Figure 5A and Figure 5B This is a top view of the array structure of the antifuse type one-time programmable memory according to the third embodiment of the present invention, and a bias table; and

[0014] Figure 6A and Figure 6B This is a top view of the array structure of the antifuse type one-time programmable memory according to the fourth embodiment of the present invention, and a bias table.

[0015] Symbol Explanation

[0016] 110,123,124,125,126,215,217,221,222,245,247,251,252,265,267,271,272,285,287,291,292,315,317,321,322,345,347,351,352,365,367,371,372,385,387,391,392,403,404 413,414,423,424,433,434,443,444,453,454,463,464,473,474,483,484,493,494,503,504,513,514,523,524,533,534,543,544,553,554,563,564,573,574,583,584,593,594: Gate dielectric layer

[0017] 120: Gate structure

[0018] 128,229,259,279,299,329,359,379,399,407,417,427,437,447,457,467,477,487,497: Gate layer

[0019] 130,140,150,160,211,212,214,216,241,242,244,246,261,262,264,266,281,282,284,286,311,312,314,316,341,342,344,346,361,362,364,366,381,382,384,386,401,402,4 11,412,421,422,431,432,441,442,451,452,461,462,471,472,481,482,491,492,501,502,511,512,521,522,531,532,541,542,551,552,561,562,571,572,581,582,591,592: Nanowires

[0020] 132,136,182,186,231,232,233,234,235,236,237,238,239,331,332,333,334,335,336,337,338,339,408,409,419,429,439,449,459,469,479,489,499,508,509,519,529,539,549,559,569,579,589,599: Drain / Source Structure

[0021] 172,174,226,227,256,257,276,277,296,297,326,327,356,357,376,377,396,397,405,406,415,416,425,426,435,436,445,446,455,456,465,466,475,476,485,486,495,496: Spare wall Detailed Implementation

[0022] This invention proposes an antifuse-type OTP memory and its associated bias control method. The antifuse-type OTP memory is fabricated using GAA transistors. For example, the peripheral circuitry and array structure of the antifuse-type OTP memory are composed of GAA transistors and fabricated on a semiconductor substrate.

[0023] Generally, GAA transistors have small size and low voltage rating, for example, 2.5V. Therefore, using GAA transistors to fabricate antifuse OTP memory will encounter some problems.

[0024] For example, antifuse OTP memory requires a high voltage difference, such as 5V, to be supplied to the storage transistor in the selected memory cell during programming. This storage transistor is a GAA transistor. In other words, during programming, the power supply circuit provides a high voltage difference to both sides of the gate dielectric layer of the storage transistor. When the voltage difference exceeds the voltage stress that the gate dielectric layer can withstand, the gate dielectric layer will rupture, causing the memory cell to exhibit a low resistance storage state. For example, a charge pump is designed in the power supply circuit to receive the supply voltage (V). DD It generates a 5V output voltage for programming operations. The supply voltage V... DD ≥0.4V and supply voltage V DD Less than or equal to 1.6V.

[0025] Generally, because GAA transistors cannot withstand excessively high voltage stress, if a single power supply circuit directly outputs 5V, the GAA transistor in the charge pump will not be able to withstand this voltage stress, causing the charge pump to fail and malfunction. Therefore, OTP memory requires multiple power supply circuits to generate multiple voltages, and combining these voltages to create a sufficiently large voltage difference for programming.

[0026] To address the aforementioned requirements, this invention proposes an antifuse-type OTP memory and its associated bias control method. The antifuse-type OTP memory includes multiple power supply circuits, one providing a positive voltage and the other providing a negative voltage. The magnitude of the voltage provided by each power supply circuit is less than the withstand voltage of the GAA transistor, thus ensuring normal operation of the power supply circuits. Furthermore, the positive and negative voltages provided by the two power supply circuits can be used as a large voltage difference for programming operations.

[0027] Please refer to Figure 1A , Figure 1B and Figure 1C The diagram shows a perspective view, a cross-sectional view along the dashed line ab, and a top view of the GAA transistor of the present invention. The GAA transistor of the present invention can form a memory cell and an array structure of an OTP memory.

[0028] like Figure 1A and Figure 1B As shown, an insulating structure STI, such as a shallow trench isolation (STI), is formed on the surface of the P-type well region PW of a P-type semiconductor substrate P_sub. Furthermore, a gate structure 120 is formed on the surface of the P-type well region PW and the insulating structure STI, and nanowires 130 and 140 pass through the gate structure 120. That is, nanowires 130 and 140 are surrounded and supported by the gate structure 120. Nanowires 130 and 140 can be rectangular nanowires or cylindrical nanowires. Additionally, two drain / source structures 132 and 136 are electrically contacted with nanowires 130 and 140, and nanowires 130 and 140 pass through the two drain / source structures 132 and 136. Alternatively, nanowires 130 and 140 do not pass through the two drain / source structures 132 and 136; only the two ends of nanowires 130 and 140 are electrically connected to the two drain / source structures 132 and 136, respectively. Basically, the two drain / source structures 132 and 136, the gate structure 120, and the nanowires 130 and 140 constitute a GAA transistor.

[0029] It is worth noting that the number of nanowires in a GAA transistor is not limited to only two. For example, a GAA transistor can have only one nanowire or more than two. Furthermore, as... Figure 1A and Figure 1BAs shown, an N-type region is formed within the P-type semiconductor substrate P_sub and located below the P-type well region PW. This N-type region can be a deep N-well (DNW) or an N-buried layer (NBL). Furthermore, the P-type semiconductor substrate P_sub and the P-type well region PW are isolated by the N-type region, ensuring that they do not contact each other. In other words, the P-type well region PW is an isolated P-well.

[0030] like Figure 1B As shown, gate structure 120 is located above the P-type well region PW and the insulating structure STI. Gate structure 120 includes: two spacers 172 and 174, three gate dielectric layers 110, 123, and 124, and a gate layer 128. The two spacers 172 and 174 are located above the P-type well region PW. Furthermore, the two spacers 172 and 174 and the gate dielectric layers 110, 123, and 124 are electrical insulators. Gate dielectric layer 110 contacts the surfaces of the P-type well region PW and the insulating structure STI. Gate dielectric layer 123 surrounds the central region of nanowire 130, and gate dielectric layer 124 surrounds the central region of nanowire 140. Gate dielectric layer 110 contacts the first side surfaces of spacers 172 and 174. Gate layer 128 covers gate dielectric layers 110, 123, and 124. Furthermore, spacers 172 and 174 are formed above the P-type well region (PW) and the surface of the insulating structure (STI). The first ends of nanowires 130 and 140 are surrounded and supported by spacer 172. The second ends of nanowires 130 and 140 are surrounded and supported by spacer 174. Furthermore, the nanowires 130 and 140 surrounded by the gate structure 120 constitute the nanowire channel region of the GAA transistor.

[0031] Furthermore, the drain / source structures 132 and 136 are located above the P-type well region (PW) and the insulating structure (STI). Drain / source structure 132 contacts the second side surface of spacer wall 172, and drain / source structure 136 contacts the second side surface of spacer wall 174. Drain / source structure 132 is electrically contacted at the first end of nanowires 130 and 140, and drain / source structure 136 is electrically contacted at the second end of nanowires 130 and 140. In one embodiment, drain / source structures 132 and 136 have the same doping type as nanowires 130 and 140. For example, drain / source structures 132 and 136, as well as nanowires 130 and 140, are all n-type or p-type doped structures.

[0032] Therefore, as Figure 1B As shown, the GAA transistor includes: a gate structure 120, nanowires 130 and 140, and drain / source structures 132 and 136. In addition, the gate structure 120 includes at least two spacer walls 172 and 174, gate dielectric layers 123 and 124, and a gate layer 128.

[0033] Please refer to Figure 2A and Figure 2B The diagram shows a perspective view and a top view of the two GAA transistors of the present invention. Compared to Figure 1A and Figure 1C Furthermore, an additional GAA transistor is added. Both GAA transistors have identical structures and share spacers 172 and 174 and gate layer 128. The structure of the newly added GAA transistor is briefly described below.

[0034] The newly added GAA transistor includes two drain / source structures 182 and 186, a gate structure, and nanowires 150 and 160. The gate structure of the new GAA transistor includes spacers 172 and 174, gate dielectric layers 125 and 126, and a gate layer 128. Gate dielectric layer 125 surrounds the middle region of nanowire 150, and gate dielectric layer 126 surrounds the middle region of nanowire 160. Gate layer 128 covers gate dielectric layers 125 and 126. The first end of nanowires 150 and 160 is surrounded and supported by spacers 172. The second end of nanowires 150 and 160 is surrounded and supported by spacers 174. Furthermore, drain / source structure 182 is electrically contacted at the first end of nanowires 150 and 160, and another drain / source structure 186 is electrically contacted at the second end of nanowires 150 and 160.

[0035] exist Figure 2A In this design, two GAA transistors are fabricated on a P-type semiconductor substrate P_sub. Drain / source structures 132 and 182 are not electrically connected, and drain / source structures 136 and 186 are also not electrically connected. Furthermore, the two GAA transistors share spacers 172 and 174 and a gate layer 128. Of course, those skilled in the art can fabricate more GAA transistors on the P-type semiconductor substrate P_sub, sharing spacers 172 and 174 and a gate layer 128.

[0036] Please refer to Figure 3A , Figure 3B and Figure 3C The diagram shows a top view, a cross-sectional view along the cd dashed line, and a cross-sectional view along the ef dashed line of the array structure of the antifuse type one-time programmable memory according to the first embodiment of the present invention.

[0037] The array structure comprises four memory cells, Cell1 to Cell4, forming a 2×2 array structure, with each of Cell1 to Cell4 having a similar structure. Furthermore, the array structure is designed above the P-type well region PW in the P-type semiconductor substrate P_sub. An N-type region is formed within the P-type semiconductor substrate P_sub and located below the P-type well region PW. The N-type region can be a deep N-type well region (DNW) or an N-type buried layer (NBL). Additionally, the P-type semiconductor substrate P_sub and the P-type well region PW are isolated by the N-type region.

[0038] The array structure is connected to at least bit lines BL1 and BL2, word lines WL1 and WL2, and antifuse control lines AF1 and AF2. Each memory cell (Cell1 to Cell4) in the array structure includes at least three GAA transistors. The structure of each GAA transistor is the same as... Figure 1A The GAA transistor shown.

[0039] The first memory cell Cell1 includes: a selection transistor M SEL1 Switching transistor M SW1 With antifuse transistor M AF1 Select transistor M SEL1 via switching transistor M SW1 Coupled to antifuse transistor M AF1 Among them, the antifuse transistor M AF1 As a storage transistor.

[0040] Select transistor M SEL1 The system includes: a drain / source structure 233, a drain / source structure 234, a gate structure, and nanowires 261 and 262. The gate structure includes: two spacers 276 and 277, gate dielectric layers 271 and 272, and a gate layer 279. Gate dielectric layer 271 surrounds the middle region of nanowire 261, gate dielectric layer 272 surrounds the middle region of nanowire 262, and gate layer 279 surrounds gate dielectric layers 271 and 272. The first ends of nanowires 261 and 262 are surrounded by spacers 276, and the second ends of nanowires 261 and 262 are surrounded by spacers 277. The nanowires 261 and 262 surrounded by the gate structure constitute the selection transistor M. SEL1 The nanowire channel region is further defined. Furthermore, two drain / source structures 233 and 234 are located on either side of the gate structure. Drain / source structure 233 is electrically contacted at the first end of nanowires 261 and 262, and drain / source structure 234 is electrically contacted at the second end of nanowires 261 and 262. Moreover, drain / source structure 234 is electrically connected to bit line BL1, and gate layer 279 is electrically connected to word line WL1.

[0041] Switching transistor M SW1The system includes: a drain / source structure 232, a drain / source structure 233, a gate structure, and nanowires 241 and 242. The gate structure includes: two spacers 256 and 257, gate dielectric layers 251 and 252, and a gate layer 259. Gate dielectric layer 251 surrounds the middle region of nanowire 241, gate dielectric layer 252 surrounds the middle region of nanowire 242, and gate layer 259 surrounds gate dielectric layers 251 and 252. The first ends of nanowires 241 and 242 are surrounded by spacers 256, and the second ends of nanowires 241 and 242 are surrounded by spacers 257. The nanowires 241 and 242 surrounded by the gate structure constitute a switching transistor M. SW1 The nanowire channel region. Furthermore, two drain / source structures 232 and 233 are located on either side of the gate structure. Drain / source structure 232 is electrically contacted at the first end of nanowires 241 and 242, and drain / source structure 233 is electrically contacted at the second end of nanowires 241 and 242. Furthermore, the gate layer 259 is electrically connected to the word line WL1.

[0042] antifuse transistor M AF1 The system includes: a drain / source structure 231, a drain / source structure 232, a gate structure, and nanowires 211 and 212. The gate structure includes: two spacers 226 and 227, gate dielectric layers 221 and 222, and a gate layer 229. Gate dielectric layer 221 surrounds the middle region of nanowire 211, gate dielectric layer 222 surrounds the middle region of nanowire 212, and gate layer 229 surrounds gate dielectric layers 221 and 222. The first ends of nanowires 221 and 222 are surrounded by spacers 226, and the second ends of nanowires 221 and 222 are surrounded by spacers 227. The nanowires 221 and 222 surrounded by the gate structure constitute an antifuse transistor M. AF1 The nanowire channel region. Furthermore, two drain / source structures 231 and 232 are located on either side of the gate structure. Drain / source structure 231 is electrically contacted at the first end of nanowires 211 and 212, and drain / source structure 232 is electrically contacted at the second end of nanowires 211 and 212. Furthermore, the gate layer 229 is electrically connected to the antifuse control line AF1.

[0043] Additionally, in the first memory cell Cell1, transistor M is selected. SEL1 With switching transistor M SW1 Shared drain / source structure 233, switching transistor M SW1 With antifuse transistor M AF1 Shared drain / source structure 232. Drain / source structure 233 switches transistor M via a switching transistor. SW1Coupled to drain / source structure 232. Furthermore, the drain / source structures 231, 232, and 233 in the first memory cell Cell1 have the same doping type as the nanowires 211, 212, 241, 242, 261, and 262. For example, the drain / source structures 231, 232, and 233, as well as the nanowires 211, 212, 241, 242, 261, and 262, are all n-type or p-type doped structures.

[0044] The second memory cell Cell2 includes: a selection transistor M SEL2 Switching transistor M SW2 With antifuse transistor M AF2 Among them, the antifuse transistor M AF2 As a storage transistor.

[0045] Select transistor M SEL2 It includes: drain / source structure 234, drain / source structure 235, a gate structure, and nanowires 361 and 362. The gate structure includes: two spacer walls 376 and 377, gate dielectric layers 371 and 372, and a gate layer 379. Furthermore, drain / source structure 234 is electrically connected to bit line BL1, and gate layer 379 is electrically connected to word line WL2.

[0046] Switching transistor M SW2 It includes: drain / source structure 235, drain / source structure 236, a gate structure, and nanowires 341 and 342. The gate structure includes: two spacer walls 356 and 357, gate dielectric layers 351 and 352, and a gate layer 359. Furthermore, the gate layer 359 is electrically connected to the word line WL2.

[0047] antifuse transistor M AF2 It includes: drain / source structure 236, drain / source structure 237, a gate structure, and nanowires 311 and 312. The gate structure includes: two spacer walls 326 and 327, gate dielectric layers 321 and 322, and a gate layer 329. Furthermore, the gate layer 329 is electrically connected to the antifuse control line AF2.

[0048] Additionally, in the second storage cell Cell2, transistor M is selected. SEL2 With switching transistor M SW2 Shared drain / source structure 235, switching transistor M SW2 With antifuse transistor M AF2 Shared drain / source structure 236. Furthermore, the drain / source structures 235, 236, and 237 in the second memory cell Cell2 have the same doping morphology as the nanowires 311, 312, 341, 342, 361, and 362.

[0049] The third memory cell, Cell3, includes: a selection transistor M. SEL3Switching transistor M SW3 With antifuse transistor M AF3 Among them, the antifuse transistor M AF3 As a storage transistor.

[0050] Select transistor M SEL3 This includes: drain / source structure 333, drain / source structure 334, a gate structure, and nanowires 264 and 266. The gate structure includes: two spacers 276 and 277, gate dielectric layers 265 and 267, and a gate layer 279. Furthermore, drain / source structure 334 is electrically connected to bit line BL2, and gate layer 279 is electrically connected to word line WL1. The selection transistor M of the third memory cell Cell3... SEL3 With the selection transistor M of the first memory cell Cell1 SEL1 They share spacer walls 276 and 277 with gate layer 279.

[0051] Switching transistor M SW3 This includes: drain / source structure 332, drain / source structure 333, a gate structure, and nanowires 244 and 246. The gate structure includes: two spacers 256 and 257, gate dielectric layers 245 and 247, and a gate layer 259. Furthermore, the gate layer 259 is electrically connected to the word line WL1. The switching transistor M of the third memory cell Cell3... SW3 The switching transistor M of the first memory cell Cell1 SW1 They share spacer walls 256 and 257 with gate layer 259.

[0052] antifuse transistor M AF3 This includes: drain / source structure 331, drain / source structure 332, a gate structure, and nanowires 214 and 216. The gate structure includes: two spacers 226 and 227, gate dielectric layers 215 and 217, and a gate layer 229. Furthermore, the gate layer 229 is electrically connected to the antifuse control line AF1. The antifuse transistor M of the third memory cell Cell3... AF3 With the antifuse transistor M of the first memory cell Cell1 AF1 They share spacer walls 226 and 227 with gate layer 229.

[0053] Additionally, in the third memory cell Cell3, transistor M is selected. SEL3 With switching transistor M SW3 Shared drain / source structure 333, switching transistor M SW3 With antifuse transistor M AF3 Shared drain / source structure 332. Furthermore, the drain / source structures 331, 332, and 333 in the third memory cell Cell3 have the same doping morphology as the nanowires 214, 216, 244, 246, 264, and 266.

[0054] The fourth memory cell, Cell4, includes: a selection transistor M. SEL4 Switching transistor M SW4 With antifuse transistor M AF4 Among them, the antifuse transistor M AF4 As a storage transistor.

[0055] Select transistor M SEL4 This includes: drain / source structure 334, drain / source structure 335, a gate structure, and nanowires 364 and 366. The gate structure includes: two spacers 376 and 377, gate dielectric layers 365 and 367, and a gate layer 379. Furthermore, the drain / source structure 334 is electrically connected to bit line BL2, and the gate layer 379 is electrically connected to word line WL2. The selection transistor M of the fourth memory cell Cell4... SEL4 With the selection transistor M of the second memory cell Cell2 SEL2 They share spacer walls 376 and 377 with gate layer 379.

[0056] Switching transistor M SW4 This includes: drain / source structure 335, drain / source structure 336, a gate structure, and nanowires 344 and 346. The gate structure includes: two spacers 356 and 357, gate dielectric layers 345 and 347, and a gate layer 359. Furthermore, the gate layer 359 is electrically connected to the word line WL2. The switching transistor M of the fourth memory cell Cell4... SW4 The switching transistor M of the second memory cell Cell2 SW2 They share spacer walls 356 and 357 with gate layer 359.

[0057] antifuse transistor M AF4 This includes: drain / source structure 336, drain / source structure 337, a gate structure, and nanowires 314 and 316. The gate structure includes: two spacers 326 and 327, gate dielectric layers 315 and 317, and a gate layer 329. Furthermore, the gate layer 329 is electrically connected to the antifuse control line AF2. The antifuse transistor M of the fourth memory cell Cell4... AF4 With the antifuse transistor M of the second memory cell Cell2 AF2 They share spacer walls 326 and 327 with gate layer 329.

[0058] Additionally, in the fourth memory cell, Cell4, transistor M is selected. SEL4 With switching transistor M SW4 Shared drain / source structure 335, switching transistor M SW4 With antifuse transistor M AF4Shared drain / source structure 336. Furthermore, the drain / source structures 335, 336, and 337 in the fourth memory cell Cell4 have the same doping morphology as the nanowires 314, 316, 344, 346, 364, and 366.

[0059] Additionally, to prevent significant leakage during array operation, a dummy transistor can be added to the peripheral memory cells of the array. For example... Figure 3A , Figure 3B and Figure 3C As shown, each of the four memory cells Cell1 to Cell4 contains a dummy transistor M. DUMMY1 ~M DUMMY4 .

[0060] In the first memory cell Cell1, the dummy transistor M DUMMY1 It includes: drain / source structure 238, drain / source structure 231, a gate structure, and nanowires 281 and 282. The gate structure includes: two spacer walls 296 and 297, a gate dielectric layer 291 and 292, and a gate layer 299.

[0061] In the second memory cell Cell2, the dummy transistor M DUMMY2 It includes: drain / source structure 237, drain / source structure 239, a gate structure, and nanowires 381 and 382. The gate structure includes: two spacer walls 396 and 397, gate dielectric layers 391 and 392, and a gate layer 399.

[0062] In the third memory cell Cell3, the dummy transistor M DUMMY3 It includes: drain / source structure 338, drain / source structure 331, a gate structure, and nanowires 284 and 286. The gate structure includes: two spacer walls 296 and 297, gate dielectric layers 285 and 287, and a gate layer 299.

[0063] In the fourth memory cell, Cell4, the dummy transistor M DUMMY4 This includes: drain / source structure 337, drain / source structure 339, a gate structure, and nanowires 384 and 386. The gate structure includes: two spacers 396 and 397, gate dielectric layers 385 and 387, and a gate layer 399. Additionally, four dummy transistors M... DUMMY1 ~M DUMMY4 The gate layers 229 and 339 are connected to the dummy gate control line Gd, and the four M... DUMMY1 ~M DUMMY4 The drain / source structures 238, 239, 338, and 339 are floating.

[0064] Please refer to Figure 3D The diagram illustrates the bias representation of the programming and reading operations of the OTP memory according to the first embodiment of the present invention.

[0065] In the programming action (PGM) and reading action (READ) described below, the first memory cell Cell1 is the selected memory cell, and the other memory cells Cell2 to Cell4 are unselected memory cells.

[0066] According to a first embodiment of the present invention, when the array structure performs a programming operation (PGM), the array structure receives a negative programming voltage (-V). BB To prevent negative programming voltage (-V) BB This affects other peripheral circuits in the OTP memory. The array structure is designed on the P-type well region PW, and the P-type semiconductor substrate P_sub and the P-type well region PW are isolated by the N-type region (N_region), so that the P-type well region PW becomes an isolated P-type well region.

[0067] Furthermore, during programming (PGM), the P-type well region PW receives a negative programming voltage (-V). BB The N-type region (N_region) receives a first voltage V1, and the P-type semiconductor substrate P_sub receives a second voltage V2. The negative programming voltage (-V...) BB ) less than or equal to -1V, and negative programming voltage (-V BB The first voltage V1 is greater than or equal to -2.5V and less than or equal to 1.6V. Therefore, there is a reverse bias between the N-region and the P-type well region PW. Additionally, the second voltage V2 is greater than or equal to the negative programming voltage (-V). BB The second voltage V2 is less than or equal to the first voltage V1. Therefore, there is either a reverse bias between the N-type region and the P-type semiconductor substrate P_sub, or no voltage difference between the N-type region and the P-type semiconductor substrate P_sub, i.e., zero bias.

[0068] like Figure 3D As shown, during programming action (PGM), word line WL1 receives the third voltage V3, and word line WL2 receives the negative programming voltage (-V). BBTherefore, word line WL1 is the selected word line, and word line WL2 is the non-selected word line. The third voltage V3 can be considered as the on voltage; the third voltage V3 is greater than or equal to -1V, and the first voltage V1 is less than or equal to the power supply voltage V. DD Additionally, the negative programming voltage (-V) BB This can be considered as the off voltage.

[0069] Furthermore, bit line BL1 receives the negative programming voltage (-V) BB Bit line BL2 receives the third voltage V3. Antifuse control line AF1 receives the positive programming voltage V. PP The antifuse control line AF2 receives the fourth voltage V4. The programming voltage V... PP Greater than or equal to 1V, programming voltage V PP Less than or equal to 2.5V. The fourth voltage V4 is greater than or equal to the negative programming voltage (-V). BB The fourth voltage V4 is less than or equal to 0V.

[0070] In the first memory cell Cell1 (selected memory cell) of the array structure, word line WL1 receives the third voltage V3, so transistor M is selected. SEL1 With switching transistor M SW1 Turn on. Therefore, via the selection transistor M SEL1 With switching transistor M SW1 The negative programming voltage (-V) of bit line BL1 BB ) Passed to antifuse transistor M AF1 Furthermore, because the antifuse control line AF1 receives the positive programming voltage V... PP Therefore, the antifuse transistor M AF1 The total voltage stress borne by the gate dielectric layers 221 and 222 is the total program voltage. The total program voltage is approximately equal to the positive program voltage (V). PP Subtract the negative programming voltage (-V) BB ), that is (V PP +V BB Therefore, one of the gate dielectric layers 221 and 222 is broken, causing the storage state of the first memory cell Cell1 to change from an unruptured state to a ruptured state.

[0071] In the second memory cell (Cell2, the non-selected memory cell) of the array structure, word line WL2 receives a negative programming voltage (shutdown voltage), so transistor M is selected. SEL2 With switching transistor M SW2Turn off. Therefore, the antifuse transistor M AF2 Since the gate dielectric layers 321 and 322 are not subjected to voltage stress, the gate dielectric layers 321 and 322 are not broken, thus maintaining the storage state of the second memory cell Cell2 in an unbroken state.

[0072] In the third memory cell (Cell3, the non-selected memory cell) of the array structure, word line WL1 receives the third voltage V3, and bit line BL2 also receives the third voltage V3. Therefore, the selection transistor M... SEL3 With switching transistor M SW3 Turn off. Antifuse transistor M AF3 Since the gate dielectric layers 215 and 217 are not subjected to voltage stress, the gate dielectric layers 215 and 217 are not broken, thus maintaining the storage state of the third memory cell Cell3 in an unbroken state.

[0073] In the fourth memory cell (Cell4, a non-selected memory cell) of the array structure, word line WL2 receives a negative programming voltage (-V). BB Furthermore, bit line BL2 receives the third voltage V3. Therefore, transistor M is selected. SEL4 With switching transistor M SW4 Turn off. Antifuse transistor M AF4 Since the gate dielectric layers 315 and 317 are not subjected to voltage stress, the gate dielectric layers 315 and 317 are not broken, thus maintaining the storage state of the fourth memory cell Cell4 in an unbroken state.

[0074] Additionally, during programming (PGM), the voltage received by the gate control line Gd is less than or equal to the negative programming voltage (-V). BB Therefore, it can be ensured that the four dummy transistors M DUMMY1 ~M DUMMY4 When turned off, leakage current will not occur.

[0075] According to a first embodiment of the present invention, during a read operation, the P-type well region PW receives a ground voltage (0V), the N-type region (N_region) receives a first voltage V1, and the P-type semiconductor substrate P_sub receives a second voltage V2. Therefore, there is either a reverse bias between the N-type region (N_region) and the P-type well region PW, or no voltage difference between them, i.e., zero bias. Similarly, there is either a reverse bias between the N-type region (N_region) and the P-type semiconductor substrate P_sub, or no voltage difference between them, i.e., zero bias.

[0076] like Figure 3D As shown, during the READ operation, word line WL1 receives the supply voltage V. DD Word line WL2 receives the ground voltage (0V). Therefore, word line WL1 is the selected word line, and word line WL2 is the unselected word line. The supply voltage V... DD The voltage at ground level (0V) can be considered as the on voltage, while the ground voltage can be considered as the off voltage.

[0077] Furthermore, bit line BL1 receives the ground voltage (0V), and bit line BL2 receives the supply voltage V. DD The antifuse control line AF1 receives and reads the voltage V. READ The antifuse control line AF2 receives and reads the voltage V. READ Among them, the voltage V is read. READ Greater than or equal to 0.4V, read voltage V READ Less than or equal to 1.6V.

[0078] In the first memory cell (selected memory cell) of the array structure, word line WL1 receives the supply voltage V. DD Therefore, transistor M is selected. SEL1 With switching transistor M SW1 Turn on. A read current is generated between the antifuse control line AF1 and the bit line BL1, and the magnitude of the read current is determined by the storage state of the first memory cell Cell1. For example, when the first memory cell Cell1 is in a broken state, the read current of the first memory cell Cell1 is relatively large, such as 2mA. When the first memory cell Cell1 is in a broken-but-not-broken state, the read current of the first memory cell Cell1 is very small (almost zero). Therefore, the storage state of the first memory cell Cell1 can be determined according to the magnitude of the read current.

[0079] In the second memory cell (Cell2, a non-selected memory cell) of the array structure, word line WL2 receives ground voltage (0V), so transistor M is selected. SEL2 With switching transistor M SW2 Turn off. No read current can be generated between the antifuse control line AF2 and the bit line BL1.

[0080] In the third memory cell (Cell3, a non-selected memory cell) of the array structure, word line WL1 receives the supply voltage V. DD Bit line BL2 receives the supply voltage V DD Therefore, transistor M is selected. SEL3 With switching transistor M SW3 Turn off. No read current can be generated between the antifuse control line AF1 and the bit line BL2.

[0081] In the fourth memory cell (Cell4, a non-selected memory cell) of the array structure, word line WL2 receives ground voltage (0V), so transistor M is selected. SEL4 With switching transistor M SW4 Turn off. No read current can be generated between the antifuse control line AF2 and the bit line BL2.

[0082] Additionally, during the READ operation, the gate control line Gd receives a ground voltage (0V). Therefore, it is possible to ensure the four dummy transistors M... DUMMY1 ~M DUMMY4 When turned off, no leakage current is generated.

[0083] Please refer to Figure 4A , Figure 4B and Figure 4C The diagram shows a top view, a cross-sectional view along the dashed line gh, and a cross-sectional view along the dashed line ij of the array structure of the antifuse type one-time programmable memory according to the second embodiment of the present invention.

[0084] The array structure comprises four memory cells, Cell1 to Cell4, forming a 2×2 array structure, with each of Cell1 to Cell4 having a similar structure. Furthermore, the array structure is designed above the P-type well region PW in the P-type semiconductor substrate P_sub. Additionally, an N-type region is formed within the P-type semiconductor substrate P_sub and located below the P-type well region PW. This N-type region can be a deep N-well (DNW) or an N-buried layer (NBL). Furthermore, the P-type semiconductor substrate P_sub and the P-type well region PW are isolated by the N-type region.

[0085] According to a second embodiment of the present invention, the array structure is at least connected to bit lines BL1 and BL2, word lines WL1 and WL2, and antifuse control lines AF1 and AF2. Each memory cell Cell1 to Cell4 in the array structure includes at least five GAA transistors. The structure of each GAA transistor is the same as... Figure 1A The GAA transistor shown.

[0086] The first memory cell Cell1 includes: a selection transistor M SEL11 Switching transistor M SW11 Anti-fuse transistor M AF1 Switching transistor M SW12 With selection transistor M SEL12 Among them, the antifuse transistor M AF1 As a storage transistor.

[0087] Select transistor M SEL11 The system includes: a drain / source structure 408, a drain / source structure 409, a gate structure, and nanowires 401 and 402. The gate structure includes: two spacers 405 and 406, gate dielectric layers 403 and 404, and a gate layer 407. Gate dielectric layer 403 surrounds the middle region of nanowire 401, gate dielectric layer 404 surrounds the middle region of nanowire 402, and gate layer 407 surrounds gate dielectric layers 403 and 404. The first ends of nanowires 401 and 402 are surrounded by spacers 405, and the second ends of nanowires 401 and 402 are surrounded by spacers 406. The nanowires 401 and 402 surrounded by the gate structure constitute the selection transistor M. SEL11The nanowire channel region is further defined. Furthermore, two drain / source structures 408 and 409 are located on either side of the gate structure. Drain / source structure 408 is electrically contacted at the first end of nanowires 401 and 402, and drain / source structure 409 is electrically contacted at the second end of nanowires 401 and 402. Moreover, drain / source structure 408 is electrically connected to bit line BL1, and gate layer 407 is electrically connected to word line WL1.

[0088] Switching transistor M SW11 The system includes: a drain / source structure 409, a drain / source structure 419, a gate structure, and nanowires 411 and 412. The gate structure includes: two spacers 415 and 416, gate dielectric layers 413 and 414, and a gate layer 417. Gate dielectric layer 413 surrounds the middle region of nanowire 411, gate dielectric layer 414 surrounds the middle region of nanowire 412, and gate layer 417 surrounds gate dielectric layers 413 and 414. The first ends of nanowires 411 and 412 are surrounded by spacers 415, and the second ends of nanowires 411 and 412 are surrounded by spacers 416. The nanowires 411 and 412 surrounded by the gate structure constitute a switching transistor M. SW11 The nanowire channel region. Furthermore, two drain / source structures 409 and 419 are located on either side of the gate structure. Drain / source structure 409 is electrically contacted at the first end of nanowires 411 and 412, and drain / source structure 419 is electrically contacted at the second end of nanowires 411 and 412. Furthermore, the gate layer 417 is electrically connected to the word line WL1.

[0089] antifuse transistor M AF1 The system includes: a drain / source structure 419, a drain / source structure 429, a gate structure, and nanowires 421 and 422. The gate structure includes: two spacers 425 and 426, gate dielectric layers 423 and 424, and a gate layer 427. Gate dielectric layer 423 surrounds the middle region of nanowire 421, gate dielectric layer 424 surrounds the middle region of nanowire 422, and gate layer 427 surrounds gate dielectric layers 423 and 424. The first ends of nanowires 421 and 422 are surrounded by spacers 425, and the second ends of nanowires 421 and 422 are surrounded by spacers 426. The nanowires 421 and 422 surrounded by the gate structure constitute an antifuse transistor M. AF1 The nanowire channel region. Furthermore, two drain / source structures 419 and 429 are located on either side of the gate structure. Drain / source structure 419 is electrically contacted at the first end of nanowires 421 and 422, and drain / source structure 429 is electrically contacted at the second end of nanowires 421 and 422. Furthermore, the gate layer 427 is electrically connected to the antifuse control line AF1.

[0090] Switching transistor M SW12The system includes: a drain / source structure 429, a drain / source structure 439, a gate structure, and nanowires 431 and 432. The gate structure includes: two spacers 435 and 436, gate dielectric layers 433 and 434, and a gate layer 437. Gate dielectric layer 433 surrounds the middle region of nanowire 431, gate dielectric layer 434 surrounds the middle region of nanowire 432, and gate layer 437 surrounds gate dielectric layers 433 and 434. The first ends of nanowires 431 and 432 are surrounded by spacers 435, and the second ends of nanowires 431 and 432 are surrounded by spacers 436. The nanowires 431 and 432 surrounded by the gate structure constitute a switching transistor M. SW12 The nanowire channel region. Furthermore, two drain / source structures 429 and 439 are located on either side of the gate structure. Drain / source structure 429 is electrically contacted at the first end of nanowires 431 and 432, and drain / source structure 439 is electrically contacted at the second end of nanowires 431 and 432. Furthermore, the gate layer 437 is electrically connected to the word line WL1.

[0091] Select transistor M SEL12 The system includes: a drain / source structure 439, a drain / source structure 449, a gate structure, and nanowires 441 and 442. The gate structure includes: two spacers 445 and 446, gate dielectric layers 443 and 444, and a gate layer 447. Gate dielectric layer 443 surrounds the middle region of nanowire 441, gate dielectric layer 444 surrounds the middle region of nanowire 442, and gate layer 447 surrounds gate dielectric layers 443 and 444. The first ends of nanowires 441 and 442 are surrounded by spacers 445, and the second ends of nanowires 441 and 442 are surrounded by spacers 446. The nanowires 441 and 442 surrounded by the gate structure constitute the selection transistor M. SEL12 The nanowire channel region is further defined. Furthermore, two drain / source structures 439 and 449 are located on either side of the gate structure. Drain / source structure 439 is electrically contacted at the first ends of nanowires 441 and 442, and drain / source structure 449 is electrically contacted at the second ends of nanowires 441 and 442. Moreover, drain / source structure 449 is electrically connected to bit line BL1, and gate layer 447 is electrically connected to word line WL1.

[0092] Additionally, in the first memory cell Cell1, transistor M is selected. SEL11 With switching transistor M SW11 Shared drain / source structure 409, switching transistor M SW11 With antifuse transistor M AF1 Shared drain / source structure 419, antifuse transistor M AF1 With switching transistor M SW12 Shared drain / source structure 429, switching transistor M SW12 With selection transistor M SEL12Shared drain / source structure 439. Furthermore, the drain / source structures 408, 409, 419, 429, 439, and 449 in the first memory cell Cell1 have the same doping morphology as the nanowires 401, 402, 411, 412, 421, 422, 431, 432, 441, and 442.

[0093] The second memory cell Cell2 includes: a selection transistor M SEL21 Switching transistor M SW21 Anti-fuse transistor M AF2 Switching transistor M SW22 With selection transistor M SEL22 Among them, the antifuse transistor M AF2 As a storage transistor.

[0094] Select transistor M SEL21 It includes: a drain / source structure 449, a drain / source structure 459, a gate structure, and nanowires 451 and 452. The gate structure includes: two spacer walls 455 and 456, gate dielectric layers 453 and 454, and a gate layer 457. Furthermore, the gate layer 457 is electrically connected to the word line WL2.

[0095] Switching transistor M SW21 It includes: drain / source structure 459, drain / source structure 469, a gate structure, and nanowires 461 and 462. The gate structure includes: two spacers 465 and 466, gate dielectric layers 463 and 464, and a gate layer 467. Furthermore, the gate layer 467 is electrically connected to the word line WL2.

[0096] antifuse transistor M AF2 This includes: a drain / source structure 469, a drain / source structure 479, a gate structure, and nanowires 471 and 472. The gate structure includes: two spacers 475 and 476, gate dielectric layers 473 and 474, and a gate layer 477. Furthermore, the gate layer 477 is electrically connected to the antifuse control line AF2.

[0097] Switching transistor M SW22 It includes: drain / source structure 479, drain / source structure 489, a gate structure, and nanowires 481 and 482. The gate structure includes: two spacers 485 and 486, gate dielectric layers 483 and 484, and a gate layer 487. Furthermore, the gate layer 487 is electrically connected to the word line WL2.

[0098] Select transistor M SEL22It includes: a drain / source structure 489, a drain / source structure 499, a gate structure, and nanowires 491 and 492. The gate structure includes: two spacers 495 and 496, gate dielectric layers 493 and 494, and a gate layer 497. Furthermore, the drain / source structure 499 is electrically connected to the bit line BL1, and the gate layer 497 is electrically connected to the word line WL2.

[0099] Additionally, in the second storage cell Cell2, transistor M is selected. SEL21 With switching transistor M SW21 Shared drain / source structure 459, switching transistor M SW21 With antifuse transistor M AF2 Shared drain / source structure 469, antifuse transistor M AF2 With switching transistor M SW22 Shared drain / source structure 479, switching transistor M SW22 With selection transistor M SEL22 Shared drain / source structure 489. Furthermore, the drain / source structures 449, 459, 469, 479, 489, and 499 in the second memory cell Cell2 have the same doping morphology as the nanowires 451, 452, 461, 462, 471, 472, 481, 482, 491, and 492.

[0100] The third memory cell, Cell3, includes: a selection transistor M. SEL31 Switching transistor M SW31 Anti-fuse transistor M AF3 Switching transistor M SW32 With selection transistor M SEL32 Among them, the antifuse transistor M AF3 As a storage transistor.

[0101] Select transistor M SEL31 Includes: drain / source structure 508, drain / source structure 509, a gate structure, and nanowires 501 and 502. The gate structure includes: two spacers 405 and 406, gate dielectric layers 503 and 504, and a gate layer 407. The selection transistor M for the third memory cell Cell3... SEL31 With the selection transistor M of the first memory cell Cell1 SEL11 They share spacer walls 405 and 406 with gate layer 407.

[0102] Switching transistor M SW31 Includes: drain / source structure 509, drain / source structure 519, a gate structure, nanowires 511 and 512. The gate structure includes: two spacer walls 415 and 416, gate dielectric layers 513 and 514, and a gate layer 417. The switching transistor M of the third memory cell Cell3... SW31The switching transistor M of the first memory cell Cell1 SW11 They share spacer walls 415 and 416 with gate layer 417.

[0103] antifuse transistor M AF3 Includes: drain / source structure 519, drain / source structure 529, a gate structure, nanowires 521 and 522. The gate structure includes: two spacers 425 and 426, gate dielectric layers 523 and 524, and a gate layer 427. The antifuse transistor M of the third memory cell Cell3... AF3 With the antifuse transistor M of the first memory cell Cell1 AF1 They share spacer walls 425 and 426 with gate layer 427.

[0104] Switching transistor M SW32 Includes: drain / source structure 529, drain / source structure 539, a gate structure, nanowires 531 and 532. The gate structure includes: two spacer walls 435 and 436, gate dielectric layers 533 and 534, and a gate layer 437. The switching transistor M of the third memory cell Cell3... SW32 The switching transistor M of the first memory cell Cell1 SW12 They share spacer walls 435 and 436 with gate layer 437.

[0105] Select transistor M SEL32 Includes: drain / source structure 539, drain / source structure 549, a gate structure, nanowires 541 and 542. The gate structure includes: two spacers 445 and 446, gate dielectric layers 543 and 544, and a gate layer 447. The selection transistor M for the third memory cell Cell3... SEL32 With the selection transistor M of the first memory cell Cell1 SEL12 They share spacer walls 445 and 446 with gate layer 447.

[0106] Additionally, in the third memory cell Cell3, transistor M is selected. SEL31 With switching transistor M SW31 Shared drain / source structure 509, switching transistor M SW31 With antifuse transistor M AF3 Shared drain / source structure 519, antifuse transistor M AF3 With switching transistor M SW32 Shared drain / source structure 529, switching transistor M SW32 With selection transistor M SEL32Shared drain / source structure 539. Furthermore, the drain / source structures 508, 509, 519, 529, 539, and 549 in the third memory cell Cell3 have the same doping morphology as the nanowires 501, 502, 511, 512, 521, 522, 531, 532, 541, and 542.

[0107] The fourth memory cell, Cell4, includes: a selection transistor M. SEL41 Switching transistor M SW41 Anti-fuse transistor M AF4 Switching transistor M SW42 With selection transistor M SEL42 Among them, the antifuse transistor M AF4 As a storage transistor.

[0108] Select transistor M SEL41 Includes: drain / source structure 549, drain / source structure 559, a gate structure, nanowires 551 and 552. The gate structure includes: two spacers 455 and 456, gate dielectric layers 553 and 554, and a gate layer 457. The selection transistor M of the fourth memory cell Cell4. SEL41 With the selection transistor M of the second memory cell Cell2 SEL21 They share spacer walls 455 and 456 with gate layer 457.

[0109] Switching transistor M SW41 This includes: drain / source structure 559, drain / source structure 569, a gate structure, and nanowires 561 and 562. The gate structure includes: two spacers 465 and 466, gate dielectric layers 563 and 564, and a gate layer 467. The switching transistor M of the fourth memory cell Cell4... SW41 The switching transistor M of the second memory cell Cell2 SW21 They share spacer walls 465 and 466 with gate layer 467.

[0110] antifuse transistor M AF4 Includes: drain / source structure 569, drain / source structure 579, a gate structure, nanowires 571 and 572. The gate structure includes: two spacers 475 and 476, gate dielectric layers 573 and 574, and a gate layer 477. The fourth memory cell, Cell4, contains an antifuse transistor M. AF4 With the antifuse transistor M of the second memory cell Cell2 AF2 They share spacer walls 475 and 476 with gate layer 477.

[0111] Switching transistor M SW42This includes: drain / source structure 579, drain / source structure 589, a gate structure, and nanowires 581 and 582. The gate structure includes: two spacers 485 and 486, gate dielectric layers 583 and 584, and a gate layer 487. The switching transistor M of the fourth memory cell Cell4... SW42 The switching transistor M of the second memory cell Cell2 SW22 They share spacer walls 485 and 486 with gate layer 487.

[0112] Select transistor M SEL42 Includes: drain / source structure 589, drain / source structure 599, a gate structure, nanowires 591 and 592. The gate structure includes: two spacer walls 495 and 496, gate dielectric layers 593 and 594, and a gate layer 497. The selection transistor M of the fourth memory cell Cell4. SEL42 With the selection transistor M of the second memory cell Cell2 SEL22 They share spacer walls 495 and 496 with gate layer 497.

[0113] Additionally, in the fourth memory cell, Cell4, transistor M is selected. SEL41 With switching transistor M SW41 Shared drain / source structure 559, switching transistor M SW41 With antifuse transistor M AF4 Shared drain / source structure 569, antifuse transistor M AF4 With switching transistor M SW42 Shared drain / source structure 579, switching transistor M SW42 With selection transistor M SEL42 Shared drain / source structure 589. Furthermore, the drain / source structures 549, 559, 569, 579, 589, and 599 in the fourth memory cell Cell4 have the same doping morphology as the nanowires 551, 552, 561, 562, 571, 572, 581, 582, 591, and 592.

[0114] Similar to the array structure in the first embodiment, in order to prevent large leakage during the operation of the array structure, a dummy transistor (not shown) can be added to the peripheral memory cell of the array structure.

[0115] Please refer to Figure 4D The diagram illustrates the bias representation of the programming and reading operations of the OTP memory according to the second embodiment of the present invention.

[0116] In the following description of programming actions (PGM) and reading actions (READ), the first storage unit Cell1 is used as the selected storage unit, and the other storage units Cell2 to Cell4 are used as non-selected storage units.

[0117] According to a second embodiment of the present invention, when the array structure performs programming (PGM), the P-type well region PW receives a negative programming voltage (-V). BB The N-type region (N_region) receives a first voltage V1, and the P-type semiconductor substrate P_sub receives a second voltage V2. The negative programming voltage (-V...) BB ) less than or equal to -1V, and negative programming voltage (-V BB The voltage V1 is greater than or equal to -2.5V. The first voltage V1 is greater than or equal to 0V and less than or equal to 1.6V. Additionally, the second voltage V2 is greater than or equal to the negative programming voltage (-V). BB And the second voltage V2 is less than or equal to the first voltage V1.

[0118] like Figure 4D As shown, during programming action (PGM), word line WL1 receives the third voltage V3, and word line WL2 receives the negative programming voltage (-V). BB Therefore, word line WL1 is the selected word line, and word line WL2 is the non-selected word line. The third voltage V3 can be considered as the on voltage; the third voltage V3 is greater than or equal to -1V, and the first voltage V1 is less than or equal to the power supply voltage V. DD Additionally, the negative programming voltage (-V) BB This can be considered as the off voltage.

[0119] Furthermore, bit line BL1 receives the negative programming voltage (-V) BB Bit line BL2 receives the third voltage V3. Antifuse control line AF1 receives the positive programming voltage V. PP The antifuse control line AF2 receives the fourth voltage V4. The programming voltage V... PP Greater than or equal to 1V, programming voltage V PP Less than or equal to 2.5V. The fourth voltage V4 is greater than or equal to the negative programming voltage (-V). BB The fourth voltage V4 is less than or equal to 0V.

[0120] In the first memory cell Cell1 (selected memory cell) of the array structure, word line WL1 receives the third voltage V3, so transistor M is selected. SEL11 Select transistor M SEL12 Switching transistor M SW11 With switching transistor M SW12 Turn on. Therefore, via the selection transistor M SEL11 With switching transistor M SW11 and via the selection transistor M SEL12 With switching transistor M SW12The negative programming voltage (-V) of bit line BL1 BB ) Passed to antifuse transistor M AF1 Furthermore, because the antifuse control line AF1 receives the positive programming voltage V... PP Therefore, the antifuse transistor M AF1 The total voltage stress borne by the gate dielectric layers 423 and 424 is the total program voltage, which is approximately equal to the positive program voltage (V). PP Subtract the negative programming voltage (-V) BB ), that is (V PP +V BB This causes one of the gate dielectric layers 423 and 424 to break, thus changing the storage state of the first memory cell Cell1 from an unbroken state to a broken state.

[0121] In the second memory cell (Cell2, the non-selected memory cell) of the array structure, word line WL2 receives a negative programming voltage (shutdown voltage), so transistor M is selected. SEL21 Select transistor M SEL22 Switching transistor M SW21 With switching transistor M SW22 (turn off). Therefore, the antifuse transistor M AF2 Since the gate dielectric layers 473 and 474 are not subjected to voltage stress, the gate dielectric layers 473 and 474 are not broken, thus maintaining the storage state of the second memory cell Cell2 in an unbroken state.

[0122] In the third memory cell (Cell3, the non-selected memory cell) of the array structure, word line WL1 receives the third voltage V3, and bit line BL2 also receives the third voltage V3. Therefore, the selection transistor M... SEL31 Select transistor M SEL32 Switching transistor M SW31 With switching transistor M SW32 Turn off. Antifuse transistor M AF3 Since the gate dielectric layers 523 and 524 are not subjected to voltage stress, the gate dielectric layers 523 and 524 are not broken, thus maintaining the storage state of the third memory cell Cell3 in an unbroken state.

[0123] In the fourth memory cell (Cell4, a non-selected memory cell) of the array structure, word line WL2 receives a negative programming voltage (-V). BB Furthermore, bit line BL2 receives the third voltage V3. Therefore, transistor M is selected. SEL41 Select transistor M SEL42 Switching transistor M SW41 With switching transistor MSW42 Turn off. Antifuse transistor M AF4 Since the gate dielectric layers 573 and 574 are not subjected to voltage stress, the gate dielectric layers 573 and 574 are not broken, thus maintaining the storage state of the fourth memory cell Cell4 in an unbroken state.

[0124] According to a second embodiment of the present invention, during the programming operation (READ), the P-type well region PW receives a ground voltage (0V), the N-type region (N_region) receives a first voltage V1, and the P-type semiconductor substrate P_sub receives a second voltage V2.

[0125] like Figure 4D As shown, during the READ operation, word line WL1 receives the supply voltage V. DD Word line WL2 receives the ground voltage (0V). Therefore, word line WL1 is the selected word line, and word line WL2 is the unselected word line. The supply voltage V... DD The voltage at ground level (0V) can be considered as the on voltage, while the ground voltage can be considered as the off voltage.

[0126] Furthermore, bit line BL1 receives the ground voltage (0V), and bit line BL2 receives the supply voltage V. DD The antifuse control line AF1 receives and reads the voltage V. READ The antifuse control line AF2 receives and reads the voltage V. READ Among them, the voltage V is read. READ Greater than or equal to 0.4V, read voltage V READ Less than or equal to 1.6V.

[0127] In the first memory cell (selected memory cell) of the array structure, word line WL1 receives the supply voltage V. DD Therefore, transistor M is selected. SEL11 Select transistor M SEL12 Switching transistor M SW11 With switching transistor M SW12 Turning on. A read current is generated between the antifuse control line AF1 and the bit line BL1, and the magnitude of the read current is determined by the storage state of the first memory cell Cell1. For example, when the first memory cell Cell1 is in a broken state, the read current of the first memory cell Cell1 is relatively large, such as 2mA. When the first memory cell Cell1 is in a broken-but-not-broken state, the read current of the first memory cell Cell1 is very small (almost zero). Therefore, the storage state of the first memory cell Cell1 can be determined according to the magnitude of the read current.

[0128] In the second memory cell (Cell2, a non-selected memory cell) of the array structure, word line WL2 receives ground voltage (0V), so transistor M is selected. SEL21 Select transistor M SEL22 Switching transistor M SW21 With switching transistor M SW22 Turn off. No read current can be generated between the antifuse control line AF2 and the bit line BL1.

[0129] In the third memory cell (Cell3, a non-selected memory cell) of the array structure, word line WL1 receives the supply voltage V. DD Bit line BL2 receives the supply voltage V DD Therefore, transistor M is selected. SEL31 Select transistor M SEL32 Switching transistor M SW31 With switching transistor M SW32 Turn off. No read current can be generated between the antifuse control line AF1 and the bit line BL2.

[0130] In the fourth memory cell (Cell4, a non-selected memory cell) of the array structure, word line WL2 receives ground voltage (0V), so transistor M is selected. SEL41 Select transistor M SEL42 Switching transistor M SW41 With switching transistor M SW42 Turn off. No read current can be generated between the antifuse control line AF2 and the bit line BL2.

[0131] Furthermore, to save on the layout area of ​​the antifuse-type OTP memory, the bias voltage of the array structure in the first and second embodiments can be modified. For example, the positive programming voltage V... PP It can be supplied by voltage V DD To replace it. That is to say, during the programming operation, the total programming voltage is approximately (V). DD +V BB This can also cause the gate dielectric layer of the antifuse transistor in a selected memory cell to break. Because antifuse OTP memories do not have a power supply circuit designed to generate a positive programming voltage V... PP Therefore, the layout area of ​​antifuse type OTP memory can be reduced.

[0132] Furthermore, the connection lines in the array structures of the first and second embodiments can be modified according to actual needs.

[0133] Please refer to Figure 5A and Figure 5BThe diagram shows a top view of the array structure of an antifuse type one-time programmable memory according to a third embodiment of the present invention, along with a bias table. The difference from the first embodiment lies in the array structure of the third embodiment, where the switching transistor M... SW1 M SW3 M SW2 M SW4 The corresponding word lines WL1 and WL2 are not connected. The following only describes the differences between the third embodiment and the first embodiment; the rest will not be repeated.

[0134] like Figure 5A As shown, in the first memory cell Cell1 and the third memory cell Cell3, the selection transistor M is connected. SEL1 M SEL3 The conducting line of gate layer 279 serves as word line WL1 and is connected to the switching transistor M. SW1 M SW3 The wires of gate layer 259 serve as following lines (FL), and word line WL1 is not connected to the following line FL. Similarly, in the second memory cell Cell2 and the fourth memory cell Cell4, the connection is made to the select transistor M. SEL2 M SEL4 The wires of gate layer 379 serve as word line WL2 and are connected to the switching transistor M. SW2 M SW4 The wires of gate layer 359 serve as follower lines FL, and word lines WL2 and follower lines FL are not interconnected. According to a third embodiment of the present invention, it is connected to the switching transistor M. SW1 M SW3 The wires of gate layer 259 are connected to the switching transistor M. SW2 M SW4 The wires of the gate layer 359 are interconnected and serve as follower lines FL.

[0135] like Figure 5B As shown, during the programming action (PGM), the follower line FL receives the following voltage V. FL Following voltage V FL Greater than or equal to 0V, and following voltage V FL Less than or equal to 1.5V. Follows voltage V FL This allows the switching transistor M to... SW1 M SW2 M SW3 M SW4It remains in the conducting state, also known as the on state. Similarly, during the programming action (PGM), the first memory cell, Cell1, is the selected memory cell, and its storage state can be changed to the broken state. The other memory cells, Cells 2 through 4, are not selected memory cells, and their storage states do not change.

[0136] like Figure 5B As shown, during the READ operation, the follower line FL receives the supply voltage V. DD V DD This allows the switching transistor M to... SW1 M SW2 M SW3 M SW4 It remains in the conducting state. Similarly, during a read operation, the first memory cell, Cell1, can generate read current, while the other memory cells, Cell2 to Cell4, cannot generate read current.

[0137] Please refer to Figure 6A and Figure 6B The diagram shows a top view of the array structure of an antifuse type one-time programmable memory according to a fourth embodiment of the present invention, along with a bias table. The difference from the second embodiment lies in the array structure of the fourth embodiment, where the switching transistor M... SW11 M SW12 M SW21 M SW22 M SW31 M SW32 M SW41 M SW42 The corresponding word lines WL1 and WL2 are not connected. The following only describes the differences between the fourth and second embodiments; the rest will not be repeated.

[0138] like Figure 6A As shown, in the first memory cell Cell1 and the third memory cell Cell3, the selection transistor M is connected. SEL11 M SEL12 M SEL31 M SEL32 The conducting lines of gate layers 407 and 447 serve as word line WL1, connecting to the switching transistor M. SW11 M SW12 M SW31 M SW32 The wires on gate layers 417 and 437 serve as follower lines FL, and word line WL1 is not connected to follower line FL. Similarly, in the second memory cell Cell2 and the fourth memory cell Cell4, the connection is made to the select transistor M. SEL21 MSEL22 M SEL41 M SEL42 The wires on gate layers 457 and 497 serve as word line WL2, connecting to the switching transistor M. SW21 M SW22 M SW41 M SW42 The wires of gate layers 467 and 487 serve as follower lines FL, and word line WL2 is not connected to follower line FL. According to the fourth embodiment of the present invention, it is connected to the switching transistor M. SW11 M SW12 M SW31 M SW32 The wires of gate layers 417 and 437 are connected to the switching transistor M. SW21 M SW22 M SW41 M SW42 The wires of gate layers 467 and 487 are interconnected and serve as follower lines FL.

[0139] like Figure 6B As shown, during the programming operation (PGM), the follower line FL receives the follower voltage V. FL Following voltage V FL This allows the switching transistor M to... SW11 M SW12 M SW21 M SW22 M SW31 M SW32 M SW41 M SW42 It remains in the conducting state. Similarly, during the programming action (PGM), the first memory cell, Cell1, is the selected memory cell, and its storage state can be changed to the broken state. The other memory cells, Cells 2 through 4, are not selected memory cells, and their storage states do not change.

[0140] like Figure 6B As shown, during the READ operation, the follower line FL receives the supply voltage V. DD V DD This allows the switching transistor M to... SW11 M SW12 M SW21 M SW22 M SW31 M SW32 M SW41 M SW42It remains in the conducting state. Similarly, during a read operation, the first memory cell, Cell1, can generate read current, while the other memory cells, Cell2 to Cell4, cannot generate read current.

[0141] In summary, this invention proposes an antifuse type OTP programmable memory and its related bias control method. In the four embodiments described above, using the bias control table disclosed in this invention, any memory cell in the array structure can be selected as the chosen memory cell during programming (PGM) and reading (READ) operations, and programming or reading operations can be performed on the selected memory cell. Furthermore, this invention utilizes a positive programming voltage (V... PP ) and negative programming voltage (-V BB The combined voltages form the total programming voltage. The voltage stress of this total programming voltage can cause the gate dielectric layer of the antifuse transistor in the selected memory cell to crack, thus successfully completing the programming operation. Furthermore, because the power supply circuit of this invention supplies negative programming voltages (-V... BB ) and positive programming voltage (V PP Therefore, all GAA transistors in an antifuse type OTP memory can operate normally in the safe operating area (SOA) without causing damage to the GAA transistors.

[0142] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. An antifuse type programmable memory having a first storage cell, the first storage cell comprising: P-type semiconductor substrate; The P-type well region is located on the surface of the P-type semiconductor substrate; An N-type region is formed within the P-type semiconductor substrate and located below the P-type well region. The N-type region ensures that the P-type semiconductor substrate below the N-type region and the P-type well region are not in contact with each other, and the P-type well region is an isolated P-type well region. First nanowire; A first gate structure includes a first spacer wall, a second spacer wall, a first gate dielectric layer, and a first gate layer; wherein the first gate dielectric layer surrounds the middle region of the first nanowire, the first gate layer surrounds the first gate dielectric layer, the first gate layer is electrically connected to a first word line, a first end of the first nanowire is surrounded by the first spacer wall, a second end of the first nanowire is surrounded by the second spacer wall, and the first spacer wall and the second spacer wall are located above the P-type well region; The first drain / source structure is located above the P-type well region, electrically contacts the first end of the first nanowire, and is electrically connected to the first nanowire. The second drain / source structure is located above the P-type well region and is electrically contacted at the second end of the first nanowire; wherein the first nanowire, the first gate structure, the first drain / source structure and the second drain / source structure form a first selection transistor; Second nanowire; The second gate structure includes a third spacer wall, a fourth spacer wall, a second gate dielectric layer, and a second gate layer; wherein the second gate dielectric layer surrounds the middle region of the second nanowire, the second gate layer surrounds the second gate dielectric layer, the second gate layer is electrically connected to a first antifuse control line, the first end of the second nanowire is surrounded by the third spacer wall, the second end of the second nanowire is surrounded by the fourth spacer wall, and the third spacer wall and the fourth spacer wall are located above the P-type well region; A third drain / source structure is located above the P-type well region and is electrically contacted at the first end of the second nanowire, wherein the third drain / source structure is coupled to the second drain / source structure. A fourth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the second nanowire, wherein the second nanowire, the second gate structure, the third drain / source structure and the fourth drain / source structure form a first antifuse transistor; The third nanowire, wherein the fourth drain / source structure is electrically contacted at the first end of the third nanowire; The third gate structure includes a fifth spacer, a sixth spacer, a third gate dielectric layer, and a third gate layer; wherein the third gate dielectric layer surrounds the middle region of the third nanowire, the third gate layer surrounds the third gate dielectric layer, the third gate layer is electrically connected to a dummy gate control line, a first end of the third nanowire is surrounded by the fifth spacer, a second end of the third nanowire is surrounded by the sixth spacer, and the fifth and sixth spacers are located above the P-type well region; and The fifth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the third nanowire, wherein the third nanowire, the third gate structure, the fourth drain / source structure and the fifth drain / source structure form a dummy transistor; During programming, the P-type well region receives a negative programming voltage, the N-type region receives a first voltage, the P-type semiconductor substrate receives a second voltage, and the dummy gate control line receives a third voltage; the P-type well region and the N-type region are reverse biased; the third voltage is less than or equal to the negative programming voltage, and the P-type semiconductor substrate and the N-type region are either reverse biased or zero biased; Wherein, the first voltage is greater than or equal to the ground voltage, the second voltage is greater than or equal to the negative programming voltage, and the second voltage is less than or equal to the first voltage.

2. The antifuse type one-time programmable memory as described in claim 1, wherein the N-type region is a deep N-type well region or an N-type buried layer.

3. The antifuse type one-time programmable memory as claimed in claim 1, wherein during a read operation, the P-type well region receives the ground voltage, the N-type region receives the first voltage, and the P-type semiconductor substrate receives the second voltage; the P-type well region and the N-type region are subject to either a reverse bias or a zero bias; and the P-type semiconductor substrate and the N-type region are subject to either a reverse bias or a zero bias.

4. The antifuse type programmable memory as claimed in claim 1, wherein the third drain / source structure is coupled to the second drain / source structure via a first switching transistor, and the gate of the first switching transistor is electrically connected to a first wire.

5. The antifuse type one-time programmable memory as claimed in claim 4, wherein during the programming operation, the first bit line receives the negative programming voltage, the first antifuse control line receives the positive programming voltage, the first select transistor and the first switch transistor are turned on, the total voltage stress on both sides of the first gate dielectric layer of the first antifuse transistor is the total programming voltage, and the total programming voltage is equal to the positive programming voltage minus the negative programming voltage, causing the first gate dielectric layer to break, and the first memory cell changes from an unbroken state to a broken state.

6. The antifuse type one-time programmable memory as described in claim 4, further comprising: The second storage unit includes: A fourth nanowire, wherein the first drain / source structure is electrically contacted at a first end of the fourth nanowire; The fourth gate structure includes a seventh spacer wall, an eighth spacer wall, a fourth gate dielectric layer, and a fourth gate layer; wherein the fourth gate dielectric layer surrounds the middle region of the fourth nanowire, the fourth gate layer surrounds the fourth gate dielectric layer, the fourth gate layer is electrically connected to the second word line, the first end of the fourth nanowire is surrounded by the seventh spacer wall, the second end of the fourth nanowire is surrounded by the eighth spacer wall, and the seventh spacer wall and the eighth spacer wall are located above the P-type well region; The fifth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the fourth nanowire; wherein the fourth nanowire, the fourth gate structure, the first drain / source structure and the fifth drain / source structure form a second selection transistor; A fifth nanowire, wherein the fifth drain / source structure is electrically contacted at the first end of the fifth nanowire; The fifth gate structure includes a ninth spacer, a tenth spacer, a fifth gate dielectric layer, and a fifth gate layer; wherein the fifth gate dielectric layer surrounds the middle region of the fifth nanowire, the fifth gate layer surrounds the fifth gate dielectric layer, the fifth gate layer is electrically connected to a second wire, the first end of the fifth nanowire is surrounded by the ninth spacer, the second end of the fifth nanowire is surrounded by the tenth spacer, and the ninth and tenth spacers are located above the P-type well region; The sixth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the fifth nanowire; wherein the fifth nanowire, the fifth gate structure, the fifth drain / source structure and the sixth drain / source structure form a second switching transistor; A sixth nanowire, wherein the sixth drain / source structure is electrically contacted at the first end of the sixth nanowire; The sixth gate structure includes an eleventh spacer wall, a twelfth spacer wall, a sixth gate dielectric layer, and a sixth gate layer; wherein the sixth gate dielectric layer surrounds the central region of the sixth nanowire, the sixth gate layer surrounds the sixth gate dielectric layer, the sixth gate layer is electrically connected to a second antifuse control line, the first end of the sixth nanowire is surrounded by the eleventh spacer wall, the second end of the sixth nanowire is surrounded by the twelfth spacer wall, and the eleventh and twelfth spacer walls are located above the P-type well region; and The seventh drain / source structure is located above the P-type well region and is electrically contacted at the second end of the sixth nanowire; wherein the sixth nanowire, the sixth gate structure, the sixth drain / source structure and the seventh drain / source structure form a second antifuse transistor.

7. An antifuse type one-time programmable memory has a first memory cell, a second memory cell, and a third memory cell, wherein the first memory cell includes: P-type semiconductor substrate; The P-type well region is located on the surface of the P-type semiconductor substrate; An N-type region is formed within the P-type semiconductor substrate and located below the P-type well region. The N-type region ensures that the P-type semiconductor substrate below the N-type region and the P-type well region are not in contact with each other, and the P-type well region is an isolated P-type well region. First nanowire; A first gate structure includes a first spacer wall, a second spacer wall, a first gate dielectric layer, and a first gate layer; wherein the first gate dielectric layer surrounds the middle region of the first nanowire, the first gate layer surrounds the first gate dielectric layer, the first gate layer is electrically connected to a first word line, a first end of the first nanowire is surrounded by the first spacer wall, a second end of the first nanowire is surrounded by the second spacer wall, and the first spacer wall and the second spacer wall are located above the P-type well region; The first drain / source structure is located above the P-type well region, electrically contacts the first end of the first nanowire, and is electrically connected to the first nanowire. The second drain / source structure is located above the P-type well region and is electrically contacted at the second end of the first nanowire; wherein the first nanowire, the first gate structure, the first drain / source structure and the second drain / source structure form a first selection transistor; Second nanowire; The second gate structure includes a third spacer wall, a fourth spacer wall, a second gate dielectric layer, and a second gate layer; wherein the second gate dielectric layer surrounds the middle region of the second nanowire, the second gate layer surrounds the second gate dielectric layer, the second gate layer is electrically connected to a first antifuse control line, the first end of the second nanowire is surrounded by the third spacer wall, the second end of the second nanowire is surrounded by the fourth spacer wall, and the third spacer wall and the fourth spacer wall are located above the P-type well region; A third drain / source structure is located above the P-type well region and is electrically contacted at the first end of the second nanowire, wherein the third drain / source structure is coupled to the second drain / source structure. A fourth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the second nanowire, wherein the second nanowire, the second gate structure, the third drain / source structure and the fourth drain / source structure form a first antifuse transistor; A third nanowire, wherein the second drain / source structure is electrically contacted at a first end of the third nanowire, and the third drain / source structure is electrically contacted at a second end of the third nanowire; and The third gate structure includes a fifth spacer, a sixth spacer, a third gate dielectric layer, and a third gate layer; wherein the third gate dielectric layer surrounds the middle region of the third nanowire, the third gate layer surrounds the third gate dielectric layer, the third gate layer is electrically connected to a first wire, the first end of the third nanowire is surrounded by the fifth spacer, the second end of the third nanowire is surrounded by the sixth spacer, and the fifth spacer and the sixth spacer are located above the P-type well region, wherein the third nanowire, the third gate structure, the second drain / source structure, and the third drain / source structure form a first switching transistor; The second storage unit includes: A fourth nanowire, wherein the first drain / source structure is electrically contacted at a first end of the fourth nanowire; The fourth gate structure includes a seventh spacer wall, an eighth spacer wall, a fourth gate dielectric layer, and a fourth gate layer; wherein the fourth gate dielectric layer surrounds the middle region of the fourth nanowire, the fourth gate layer surrounds the fourth gate dielectric layer, the fourth gate layer is electrically connected to the second word line, the first end of the fourth nanowire is surrounded by the seventh spacer wall, the second end of the fourth nanowire is surrounded by the eighth spacer wall, and the seventh spacer wall and the eighth spacer wall are located above the P-type well region; The fifth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the fourth nanowire; wherein the fourth nanowire, the fourth gate structure, the first drain / source structure and the fifth drain / source structure form a second selection transistor; A fifth nanowire, wherein the fifth drain / source structure is electrically contacted at the first end of the fifth nanowire; The fifth gate structure includes a ninth spacer, a tenth spacer, a fifth gate dielectric layer, and a fifth gate layer; wherein the fifth gate dielectric layer surrounds the middle region of the fifth nanowire, the fifth gate layer surrounds the fifth gate dielectric layer, the fifth gate layer is electrically connected to a second wire, the first end of the fifth nanowire is surrounded by the ninth spacer, the second end of the fifth nanowire is surrounded by the tenth spacer, and the ninth and tenth spacers are located above the P-type well region; The sixth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the fifth nanowire; wherein the fifth nanowire, the fifth gate structure, the fifth drain / source structure and the sixth drain / source structure form a second switching transistor; A sixth nanowire, wherein the sixth drain / source structure is electrically contacted at the first end of the sixth nanowire; The sixth gate structure includes an eleventh spacer wall, a twelfth spacer wall, a sixth gate dielectric layer, and a sixth gate layer; wherein the sixth gate dielectric layer surrounds the central region of the sixth nanowire, the sixth gate layer surrounds the sixth gate dielectric layer, the sixth gate layer is electrically connected to a second antifuse control line, the first end of the sixth nanowire is surrounded by the eleventh spacer wall, the second end of the sixth nanowire is surrounded by the twelfth spacer wall, and the eleventh and twelfth spacer walls are located above the P-type well region; and The seventh drain / source structure is located above the P-type well region and is electrically contacted at the second end of the sixth nanowire; wherein the sixth nanowire, the sixth gate structure, the sixth drain / source structure and the seventh drain / source structure form a second antifuse transistor; The third storage unit includes: The seventh nanowire; The seventh gate structure includes the first spacer wall, the second spacer wall, the seventh gate dielectric layer, and the first gate layer; wherein the seventh gate dielectric layer surrounds the middle region of the seventh nanowire, the first gate layer surrounds the seventh gate dielectric layer, the first end of the seventh nanowire is surrounded by the first spacer wall, and the second end of the seventh nanowire is surrounded by the second spacer wall. The eighth drain / source structure is located above the P-type well region, electrically contacts the first end of the seventh nanowire, and is electrically connected to the second bit line; A ninth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the seventh nanowire; wherein the seventh nanowire, the seventh gate structure, the eighth drain / source structure, and the ninth drain / source structure form a third selection transistor; The eighth nanowire, wherein the ninth drain / source structure is electrically contacted at the first end of the eighth nanowire; The eighth gate structure includes the fifth spacer, the sixth spacer, the eighth gate dielectric layer and the third gate layer; wherein the eighth gate dielectric layer surrounds the middle region of the eighth nanowire, the third gate layer surrounds the eighth gate dielectric layer, the first end of the eighth nanowire is surrounded by the fifth spacer, and the second end of the eighth nanowire is surrounded by the sixth spacer. The tenth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the eighth nanowire; wherein the eighth nanowire, the eighth gate structure, the ninth drain / source structure and the tenth drain / source structure form a third switching transistor; A ninth nanowire, wherein the tenth drain / source structure is electrically contacted at the first end of the ninth nanowire; A ninth gate structure includes the third spacer wall, the fourth spacer wall, a ninth gate dielectric layer, and the second gate layer; wherein the ninth gate dielectric layer surrounds the middle region of the ninth nanowire, the second gate layer surrounds the ninth gate dielectric layer, the first end of the ninth nanowire is surrounded by the third spacer wall, and the second end of the ninth nanowire is surrounded by the fourth spacer wall; and The eleventh drain / source structure is located above the P-type well region and is electrically contacted at the second end of the ninth nanowire; wherein the ninth nanowire, the ninth gate structure, the tenth drain / source structure and the eleventh drain / source structure form a third antifuse transistor; During programming, the P-type well region receives a negative programming voltage, the N-type region receives a first voltage, and the P-type semiconductor substrate receives a second voltage; the P-type well region and the N-type region are reverse biased; and the P-type semiconductor substrate and the N-type region are either reverse biased or zero biased. Wherein, the first voltage is greater than or equal to the ground voltage, the second voltage is greater than or equal to the negative programming voltage, and the second voltage is less than or equal to the first voltage.

8. The antifuse type one-time programmable memory as claimed in claim 7, wherein the first wire is connected to the first word line, and the second wire is connected to the second word line.

9. The antifuse type one-time programmable memory as claimed in claim 8, wherein during the programming operation, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first antifuse control line receives a positive programming voltage, the second antifuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage; the third voltage is less than or equal to the supply voltage, and the third voltage is greater than or equal to -1V; the fourth voltage is greater than or equal to the negative programming voltage, and the fourth voltage is less than or equal to the ground voltage; and during the read operation, the third memory cell is a non-selected memory cell, and the second bit line receives the supply voltage.

10. The antifuse type one-time programmable memory as claimed in claim 7, wherein the first wire and the second wire are respectively used as follower lines.

11. The antifuse type one-time programmable memory as claimed in claim 10, wherein during the programming operation, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first antifuse control line receives a positive programming voltage, the second antifuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage, and the follower line receives a follower voltage; the third voltage is less than or equal to the supply voltage and greater than or equal to -1V; the fourth voltage is greater than or equal to the negative programming voltage and less than or equal to the ground voltage; and the supply voltage is greater than or equal to 0.4V and less than or equal to 1.6V; the follower voltage is greater than or equal to the ground voltage and less than or equal to 1.5V.

12. An antifuse type programmable memory has a first storage cell, the first storage cell comprising: P-type semiconductor substrate; The P-type well region is located on the surface of the P-type semiconductor substrate; An N-type region is formed within the P-type semiconductor substrate and located below the P-type well region. The N-type region ensures that the P-type semiconductor substrate below the N-type region and the P-type well region are not in contact with each other, and the P-type well region is an isolated P-type well region. First nanowire; A first gate structure includes a first spacer wall, a second spacer wall, a first gate dielectric layer, and a first gate layer; wherein the first gate dielectric layer surrounds the middle region of the first nanowire, the first gate layer surrounds the first gate dielectric layer, the first gate layer is electrically connected to a first word line, a first end of the first nanowire is surrounded by the first spacer wall, a second end of the first nanowire is surrounded by the second spacer wall, and the first spacer wall and the second spacer wall are located above the P-type well region; The first drain / source structure is located above the P-type well region, electrically contacts the first end of the first nanowire, and is electrically connected to the first nanowire. The second drain / source structure is located above the P-type well region and is electrically contacted at the second end of the first nanowire; wherein the first nanowire, the first gate structure, the first drain / source structure and the second drain / source structure form a first selection transistor; Second nanowire; The second gate structure includes a third spacer wall, a fourth spacer wall, a second gate dielectric layer, and a second gate layer; wherein the second gate dielectric layer surrounds the middle region of the second nanowire, the second gate layer surrounds the second gate dielectric layer, the second gate layer is electrically connected to a first antifuse control line, the first end of the second nanowire is surrounded by the third spacer wall, the second end of the second nanowire is surrounded by the fourth spacer wall, and the third spacer wall and the fourth spacer wall are located above the P-type well region; A third drain / source structure is located above the P-type well region and is electrically contacted at the first end of the second nanowire, wherein the third drain / source structure is coupled to the second drain / source structure. A fourth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the second nanowire, wherein the second nanowire, the second gate structure, the third drain / source structure and the fourth drain / source structure form a first antifuse transistor; The third nanowire, wherein the second drain / source structure is electrically contacted at the first end of the third nanowire, and the third drain / source structure is electrically contacted at the second end of the third nanowire; The third gate structure includes a fifth spacer, a sixth spacer, a third gate dielectric layer, and a third gate layer; wherein the third gate dielectric layer surrounds the middle region of the third nanowire, the third gate layer surrounds the third gate dielectric layer, the third gate layer is electrically connected to a first wire, the first end of the third nanowire is surrounded by the fifth spacer, the second end of the third nanowire is surrounded by the sixth spacer, and the fifth spacer and the sixth spacer are located above the P-type well region, wherein the third nanowire, the third gate structure, the second drain / source structure, and the third drain / source structure form a first switching transistor; A fourth nanowire, wherein the fourth drain / source structure is electrically contacted at the first end of the fourth nanowire; The fourth gate structure includes a seventh spacer wall, an eighth spacer wall, a fourth gate dielectric layer, and a fourth gate layer; wherein the fourth gate dielectric layer surrounds the middle region of the fourth nanowire, the fourth gate layer surrounds the fourth gate dielectric layer, the fourth gate layer is electrically connected to the first wire, the first end of the fourth nanowire is surrounded by the seventh spacer wall, the second end of the fourth nanowire is surrounded by the eighth spacer wall, and the seventh spacer wall and the eighth spacer wall are located above the P-type well region; The fifth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the fourth nanowire; wherein the fourth nanowire, the fourth gate structure, the fourth drain / source structure and the fifth drain / source structure form a second switching transistor; A fifth nanowire, wherein the fifth drain / source structure is electrically contacted at the first end of the fifth nanowire; The fifth gate structure includes a ninth spacer, a tenth spacer, a fifth gate dielectric layer, and a fifth gate layer; wherein the fifth gate dielectric layer surrounds the central region of the fifth nanowire, the fifth gate layer surrounds the fifth gate dielectric layer, the fifth gate layer is electrically connected to the first word line, the first end of the fifth nanowire is surrounded by the ninth spacer, the second end of the fifth nanowire is surrounded by the tenth spacer, and the ninth and tenth spacers are located above the P-type well region; and The sixth drain / source structure is located above the P-type well region, electrically contacts the second end of the fifth nanowire, and is electrically connected to the first line; wherein the fifth nanowire, the fifth gate structure, the fifth drain / source structure, and the sixth drain / source structure form a second selection transistor; During programming, the P-type well region receives a negative programming voltage, the N-type region receives a first voltage, and the P-type semiconductor substrate receives a second voltage; the P-type well region and the N-type region are reverse biased; and the P-type semiconductor substrate and the N-type region are either reverse biased or zero biased. Wherein, the first voltage is greater than or equal to the ground voltage, the second voltage is greater than or equal to the negative programming voltage, and the second voltage is less than or equal to the first voltage.

13. The antifuse type one-time programmable memory of claim 12, further comprising a second storage unit, the second storage unit comprising: A sixth nanowire, wherein the first drain / source structure is electrically contacted at a first end of the sixth nanowire; The sixth gate structure includes an eleventh spacer wall, a twelfth spacer wall, a sixth gate dielectric layer, and a sixth gate layer; wherein the sixth gate dielectric layer surrounds the middle region of the sixth nanowire, the sixth gate layer surrounds the sixth gate dielectric layer, the sixth gate layer is electrically connected to the second word line, the first end of the sixth nanowire is surrounded by the eleventh spacer wall, the second end of the sixth nanowire is surrounded by the twelfth spacer wall, and the eleventh spacer wall and the twelfth spacer wall are located above the P-type well region; A seventh drain / source structure is located above the P-type well region and is electrically contacted at the second end of the sixth nanowire; wherein the sixth nanowire, the sixth gate structure, the first drain / source structure, and the seventh drain / source structure form a third selection transistor; A seventh nanowire, wherein the seventh drain / source structure is electrically contacted at the first end of the seventh nanowire; The seventh gate structure includes a thirteenth spacer, a fourteenth spacer, a seventh gate dielectric layer, and a seventh gate layer; wherein the seventh gate dielectric layer surrounds the middle region of the seventh nanowire, the seventh gate layer surrounds the seventh gate dielectric layer, the seventh gate layer is electrically connected to a second wire, the first end of the seventh nanowire is surrounded by the thirteenth spacer, the second end of the seventh nanowire is surrounded by the fourteenth spacer, and the thirteenth and fourteenth spacers are located above the P-type well region; The eighth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the seventh nanowire; wherein the seventh nanowire, the seventh gate structure, the seventh drain / source structure and the eighth drain / source structure form a third switching transistor; The eighth nanowire, wherein the eighth drain / source structure is electrically contacted at the first end of the eighth nanowire; The eighth gate structure includes a fifteenth spacer wall, a sixteenth spacer wall, an eighth gate dielectric layer, and an eighth gate layer; wherein the eighth gate dielectric layer surrounds the middle region of the eighth nanowire, the eighth gate layer surrounds the eighth gate dielectric layer, the eighth gate layer is electrically connected to the second antifuse control line, the first end of the eighth nanowire is surrounded by the fifteenth spacer wall, the second end of the eighth nanowire is surrounded by the sixteenth spacer wall, and the fifteenth spacer wall and the sixteenth spacer wall are located above the P-type well region; The ninth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the eighth nanowire; wherein the eighth nanowire, the eighth gate structure, the eighth drain / source structure and the ninth drain / source structure form a second antifuse transistor; A ninth nanowire, wherein the ninth drain / source structure is electrically contacted at the first end of the ninth nanowire; The ninth gate structure includes a seventeenth spacer, an eighteenth spacer, a ninth gate dielectric layer, and a ninth gate layer; wherein the ninth gate dielectric layer surrounds the middle region of the ninth nanowire, the ninth gate layer surrounds the ninth gate dielectric layer, the ninth gate layer is electrically connected to the second wire, the first end of the ninth nanowire is surrounded by the seventeenth spacer, the second end of the ninth nanowire is surrounded by the eighteenth spacer, and the seventeenth and eighteenth spacers are located above the P-type well region; The tenth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the ninth nanowire; wherein the ninth nanowire, the ninth gate structure, the ninth drain / source structure and the tenth drain / source structure form a fourth switching transistor; A tenth nanowire, wherein the tenth drain / source structure is electrically contacted at the first end of the tenth nanowire; A tenth gate structure includes a nineteenth spacer, a twentieth spacer, a tenth gate dielectric layer, and a tenth gate layer; wherein the tenth gate dielectric layer surrounds the central region of the tenth nanowire, the tenth gate layer surrounds the tenth gate dielectric layer, the tenth gate layer is electrically connected to the second word line, the first end of the tenth nanowire is surrounded by the nineteenth spacer, the second end of the tenth nanowire is surrounded by the twentieth spacer, and the nineteenth and twentieth spacers are located above the P-type well region; and The eleventh drain / source structure is located above the P-type well region, electrically contacts the second end of the tenth nanowire, and is electrically connected to the first line; wherein the tenth nanowire, the tenth gate structure, the tenth drain / source structure and the eleventh drain / source structure form the fourth selection transistor.

14. The antifuse type one-time programmable memory as claimed in claim 13, further comprising a third storage unit, the third storage unit comprising: Eleventh nanowire; The eleventh gate structure includes the first spacer wall, the second spacer wall, the eleventh gate dielectric layer and the first gate layer; wherein the eleventh gate dielectric layer surrounds the middle region of the eleventh nanowire, the first gate layer surrounds the eleventh gate dielectric layer, the first end of the eleventh nanowire is surrounded by the first spacer wall, and the second end of the eleventh nanowire is surrounded by the second spacer wall. The twelfth drain / source structure is located above the P-type well region, electrically contacts the first end of the eleventh nanowire, and is electrically connected to the second bit line; The thirteenth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the eleventh nanowire; wherein the eleventh nanowire, the eleventh gate structure, the twelfth drain / source structure and the thirteenth drain / source structure form the fifth selection transistor; The twelfth nanowire, wherein the thirteenth drain / source structure is electrically contacted at a first end of the twelfth nanowire; The twelfth gate structure includes the fifth spacer, the sixth spacer, the twelfth gate dielectric layer, and the third gate layer; wherein the twelfth gate dielectric layer surrounds the middle region of the twelfth nanowire, the third gate layer surrounds the twelfth gate dielectric layer, the first end of the twelfth nanowire is surrounded by the fifth spacer, and the second end of the twelfth nanowire is surrounded by the sixth spacer. The fourteenth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the twelfth nanowire; wherein the twelfth nanowire, the twelfth gate structure, the thirteenth drain / source structure and the fourteenth drain / source structure form the fifth switching transistor; The thirteenth nanowire, wherein the fourteenth drain / source structure is electrically contacted at the first end of the thirteenth nanowire; The thirteenth gate structure includes the third spacer, the fourth spacer, the thirteenth gate dielectric layer and the second gate layer; wherein the thirteenth gate dielectric layer surrounds the middle region of the thirteenth nanowire, the second gate layer surrounds the thirteenth gate dielectric layer, the first end of the thirteenth nanowire is surrounded by the third spacer, and the second end of the thirteenth nanowire is surrounded by the fourth spacer. The fifteenth drain / source structure is located above the P-type well region and is electrically contacted to the second end of the thirteenth nanowire; wherein the thirteenth nanowire, the thirteenth gate structure, the fourteenth drain / source structure and the fifteenth drain / source structure form a third antifuse transistor; The fourteenth nanowire, wherein the fifteenth drain / source structure is electrically contacted at the first end of the fourteenth nanowire; The fourteenth gate structure includes the seventh spacer wall, the eighth spacer wall, the fourteenth gate dielectric layer and the fourth gate layer; wherein the fourteenth gate dielectric layer surrounds the middle region of the fourteenth nanowire, the fourth gate layer surrounds the fourteenth gate dielectric layer, the first end of the fourteenth nanowire is surrounded by the seventh spacer wall, and the second end of the fourteenth nanowire is surrounded by the eighth spacer wall. The sixteenth drain / source structure is located above the P-type well region and is electrically contacted to the second end of the fourteenth nanowire; wherein the fourteenth nanowire, the fourteenth gate structure, the fifteenth drain / source structure and the sixteenth drain / source structure form a sixth switching transistor; The fifteenth nanowire, wherein the sixteenth drain / source structure is electrically contacted at the first end of the fifteenth nanowire; The fifteenth gate structure includes the ninth spacer wall, the tenth spacer wall, the fifteenth gate dielectric layer, and the fifth gate layer; wherein the fifteenth gate dielectric layer surrounds the middle region of the fifteenth nanowire, the fifth gate layer surrounds the fifteenth gate dielectric layer, the first end of the fifteenth nanowire is surrounded by the ninth spacer wall, and the second end of the fifteenth nanowire is surrounded by the tenth spacer wall; and The seventeenth drain / source structure is located above the P-type well region, electrically contacts the second end of the fifteenth nanoline, and is electrically connected to the second bit line; wherein the fifteenth nanoline, the fifteenth gate structure, the sixteenth drain / source structure, and the seventeenth drain / source structure form the sixth selection transistor.

15. The antifuse type programmable memory of claim 14, wherein the first wire is connected to the first word line and the second wire is connected to the second word line.

16. The antifuse type one-time programmable memory as claimed in claim 15, wherein during the programming operation, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first antifuse control line receives a positive programming voltage, the second antifuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage; the third voltage is less than or equal to the supply voltage, and the third voltage is greater than or equal to -1V; The fourth voltage is greater than or equal to the negative programming voltage, and the fourth voltage is less than or equal to the ground voltage; Furthermore, the supply voltage is greater than or equal to 0.4V and less than or equal to 1.6V.

17. The antifuse type one-time programmable memory as claimed in claim 14, wherein the first wire and the second wire are respectively used as follower lines.

18. The antifuse-type one-time programmable memory of claim 17, wherein during the programming operation, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first antifuse control line receives a positive programming voltage, the second antifuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage, and the follower line receives a follower voltage; the third voltage is less than or equal to the supply voltage and greater than or equal to -1V; the fourth voltage is greater than or equal to the negative programming voltage and less than or equal to the ground voltage; and the supply voltage is greater than or equal to 0.4V and less than or equal to 1.6V; the follower voltage is greater than or equal to the ground voltage and less than or equal to 1.5V.

19. An antifuse type programmable memory has a first storage cell and a second storage cell, wherein the first storage cell includes: P-type semiconductor substrate; The P-type well region is located on the surface of the P-type semiconductor substrate; An N-type region is formed within the P-type semiconductor substrate and located below the P-type well region. The N-type region ensures that the P-type semiconductor substrate below the N-type region and the P-type well region are not in contact with each other, and the P-type well region is an isolated P-type well region. First nanowire; A first gate structure includes a first spacer wall, a second spacer wall, a first gate dielectric layer, and a first gate layer; wherein the first gate dielectric layer surrounds the middle region of the first nanowire, the first gate layer surrounds the first gate dielectric layer, the first gate layer is electrically connected to a first word line, a first end of the first nanowire is surrounded by the first spacer wall, a second end of the first nanowire is surrounded by the second spacer wall, and the first spacer wall and the second spacer wall are located above the P-type well region; The first drain / source structure is located above the P-type well region, electrically contacts the first end of the first nanowire, and is electrically connected to the first nanowire. The second drain / source structure is located above the P-type well region and is electrically contacted at the second end of the first nanowire; wherein the first nanowire, the first gate structure, the first drain / source structure and the second drain / source structure form a first selection transistor; Second nanowire; The second gate structure includes a third spacer wall, a fourth spacer wall, a second gate dielectric layer, and a second gate layer; wherein the second gate dielectric layer surrounds the middle region of the second nanowire, the second gate layer surrounds the second gate dielectric layer, the second gate layer is electrically connected to a first antifuse control line, the first end of the second nanowire is surrounded by the third spacer wall, the second end of the second nanowire is surrounded by the fourth spacer wall, and the third spacer wall and the fourth spacer wall are located above the P-type well region; A third drain / source structure is located above the P-type well region and is electrically contacted at the first end of the second nanowire, wherein the third drain / source structure is coupled to the second drain / source structure. A fourth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the second nanowire, wherein the second nanowire, the second gate structure, the third drain / source structure and the fourth drain / source structure form a first antifuse transistor; A third nanowire, wherein the second drain / source structure is electrically contacted at a first end of the third nanowire, and the third drain / source structure is electrically contacted at a second end of the third nanowire; and The third gate structure includes a fifth spacer, a sixth spacer, a third gate dielectric layer, and a third gate layer; wherein the third gate dielectric layer surrounds the middle region of the third nanowire, the third gate layer surrounds the third gate dielectric layer, the third gate layer is electrically connected to a first wire, the first end of the third nanowire is surrounded by the fifth spacer, the second end of the third nanowire is surrounded by the sixth spacer, and the fifth spacer and the sixth spacer are located above the P-type well region, wherein the third nanowire, the third gate structure, the second drain / source structure, and the third drain / source structure form a first switching transistor; The second storage unit includes: A fourth nanowire, wherein the first drain / source structure is electrically contacted at a first end of the fourth nanowire; The fourth gate structure includes a seventh spacer wall, an eighth spacer wall, a fourth gate dielectric layer, and a fourth gate layer; wherein the fourth gate dielectric layer surrounds the middle region of the fourth nanowire, the fourth gate layer surrounds the fourth gate dielectric layer, the fourth gate layer is electrically connected to the second word line, the first end of the fourth nanowire is surrounded by the seventh spacer wall, the second end of the fourth nanowire is surrounded by the eighth spacer wall, and the seventh spacer wall and the eighth spacer wall are located above the P-type well region; The fifth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the fourth nanowire; wherein the fourth nanowire, the fourth gate structure, the first drain / source structure and the fifth drain / source structure form a second selection transistor; A fifth nanowire, wherein the fifth drain / source structure is electrically contacted at the first end of the fifth nanowire; The fifth gate structure includes a ninth spacer, a tenth spacer, a fifth gate dielectric layer, and a fifth gate layer; wherein the fifth gate dielectric layer surrounds the middle region of the fifth nanowire, the fifth gate layer surrounds the fifth gate dielectric layer, the fifth gate layer is electrically connected to a second wire, the first end of the fifth nanowire is surrounded by the ninth spacer, the second end of the fifth nanowire is surrounded by the tenth spacer, and the ninth and tenth spacers are located above the P-type well region; The sixth drain / source structure is located above the P-type well region and is electrically contacted at the second end of the fifth nanowire; wherein the fifth nanowire, the fifth gate structure, the fifth drain / source structure and the sixth drain / source structure form a second switching transistor; A sixth nanowire, wherein the sixth drain / source structure is electrically contacted at the first end of the sixth nanowire; The sixth gate structure includes an eleventh spacer wall, a twelfth spacer wall, a sixth gate dielectric layer, and a sixth gate layer; wherein the sixth gate dielectric layer surrounds the central region of the sixth nanowire, the sixth gate layer surrounds the sixth gate dielectric layer, the sixth gate layer is electrically connected to a second antifuse control line, the first end of the sixth nanowire is surrounded by the eleventh spacer wall, the second end of the sixth nanowire is surrounded by the twelfth spacer wall, and the eleventh and twelfth spacer walls are located above the P-type well region; and The seventh drain / source structure is located above the P-type well region and is electrically contacted at the second end of the sixth nanowire; wherein the sixth nanowire, the sixth gate structure, the sixth drain / source structure and the seventh drain / source structure form a second antifuse transistor; During programming, the P-type well region receives a negative programming voltage, the N-type region receives a first voltage, and the P-type semiconductor substrate receives a second voltage; the P-type well region and the N-type region are reverse biased; and the P-type semiconductor substrate and the N-type region are either reverse biased or zero biased. Wherein, the first voltage is greater than or equal to the ground voltage, the second voltage is greater than or equal to the negative programming voltage, and the second voltage is less than or equal to the first voltage; The first wire is connected to the first word line, and the second wire is connected to the second word line.

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