Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. According to one embodiment, a semiconductor device includes: a first film including a plurality of electrode layers and a plurality of insulating layers alternately provided in a first direction; and a plurality of first semiconductor layers provided in the first film via a charge storage layer and extending in the first direction. The device is further provided with: a first wiring that is provided within the first film and extends in the first direction; and a second semiconductor layer provided so as to be in contact with the plurality of first semiconductor layers and the first wiring in the first direction of the first film. The second semiconductor layer has a first surface on the side of the first semiconductor layer and the first wiring and a second surface on the opposite side of the first semiconductor layer and the first wiring. The first surface and the second surface are surfaces having recesses and projections across a region of the first semiconductor layer in the first direction and a region of the first wiring in the first direction.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of June 5, 2019, application number 201910486286.1, and invention name “Semiconductor device and manufacturing method thereof”.

[0003] Citation of Related Applications

[0004] This application is based upon and claims the benefit of priority based on prior Japanese Patent Application No. 2019-050310, filed on March 18, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0005] Various embodiments described herein generally relate to a semiconductor device and a method of manufacturing the same. Background Art

[0006] There is a need for a method of electrically connecting a channel semiconductor layer and wiring such as a source wiring layer in a preferred form in a three-dimensional memory. Summary of the invention

[0007] Embodiments of the present invention provide a semiconductor device capable of electrically connecting a channel semiconductor layer and wiring in a preferred form, and a method for manufacturing the same.

[0008] According to a semiconductor device of an embodiment, the semiconductor device comprises: a first film including a plurality of electrode layers and a plurality of insulating layers alternately arranged in a first direction; and a plurality of first semiconductor layers, which are arranged in the first film with a charge storage layer interposed therebetween and extend in the first direction. The device further comprises: a first wiring arranged in the first film and extending in the first direction; and a second semiconductor layer arranged in contact with the plurality of first semiconductor layers and the first wiring in the first direction of the first film. The second semiconductor layer comprises a first surface on the side of the first semiconductor layer and the first wiring and a second surface on the opposite side of the first semiconductor layer and the first wiring. The first surface and the second surface comprise a surface having a concave-convex surface throughout a region of the first semiconductor layer in the first direction and a region of the first wiring in the first direction.

[0009] According to the above configuration, it is possible to provide a semiconductor device capable of electrically connecting a channel semiconductor layer and wiring in a preferred form and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0011] Figure 2 It is a cross-sectional view showing the structure of the columnar portion according to the first embodiment.

[0012] Figure 3 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 4 This is a cross-sectional view (1 / 3) showing details of the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 5 It is a cross-sectional view (2 / 3) showing details of the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 6 It is a cross-sectional view (3 / 3) showing details of the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 7 It is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0017] Figure 8 It is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment.

[0018] Fig. 9 It is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, a plurality of embodiments will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar parts.

[0020] In addition, the embodiments of the present invention will be described below with reference to the accompanying drawings. Figures 1 to 9 In the present invention, the same or similar components are denoted by the same symbols, and repeated descriptions are omitted.

[0021] (First embodiment) Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device is a three-dimensional memory formed by bonding an array chip 1 and a circuit chip 2. The circuit chip 2 is an example of a first chip. The array chip 1 is an example of a second chip.

[0022] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, a semiconductor layer 12 on the memory cell array 11, a back gate insulating film 13 on the semiconductor layer 12, and a back gate electrode 14 on the back gate insulating film 13. The back gate electrode 14 is used for electric field control of the semiconductor layer 12 in the same manner as the selection gate SG described below. Details of the semiconductor layer 12, the back gate insulating film 13, and the back gate electrode 14 will be described below. The array chip 1 also includes an interlayer insulating film 15 under the memory cell array 11 and an insulating film 16 under the interlayer insulating film 15. The insulating film 16 is, for example, a silicon oxide film.

[0023] The circuit chip 2 is provided under the array chip 1. The circuit chip 2 includes an insulating film 17 under the insulating film 16, an interlayer insulating film 18 under the insulating film 17, and a substrate 19 under the interlayer insulating film 18. The insulating film 17 is, for example, a silicon oxide film. The substrate 19 is, for example, a semiconductor substrate such as a silicon substrate.

[0024] Figure 1 The X direction and the Y direction parallel to the surface of the substrate 19 and perpendicular to each other, and the Z direction perpendicular to the surface of the substrate 19 are shown. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the gravity direction. The +Z direction or the -Z direction is an example of the first direction.

[0025] The array chip 1 includes a plurality of word lines WL and select gates SG as electrode layers in the memory cell array 11 . Figure 1 FIG. 2 shows a step structure portion 21 of the memory cell array 11. The array chip 1 further includes the back gate electrode 14 as an electrode layer outside the memory cell array 11. Figure 1 As shown, each word line WL is electrically connected to the word line wiring layer 23 via a contact plug 22, the back gate electrode 14 is electrically connected to the back gate wiring layer 25 via a contact plug 24, and the selection gate SG is electrically connected to the selection gate wiring layer 27 via a contact plug 26. The columnar portion CL that passes through the word line WL and the selection gate SG is electrically connected to the bit line BL via a plug 28, and is electrically connected to the semiconductor layer 12. In addition, the details of the word line WL, the columnar portion CL, etc. will be described below.

[0026] The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 disposed on a substrate 19 through a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed in the substrate 19. The circuit chip 2 also includes a plurality of plugs 33 disposed on the source diffusion layer or the drain diffusion layer of the transistors 31, a wiring layer 34 disposed on the plugs 33 and including a plurality of wirings, and a wiring layer 35 disposed on the wiring layer 34 and including a plurality of wirings. The circuit chip 2 also includes a plurality of through-hole plugs 36 disposed on the wiring layer 35, and a plurality of metal pads 37 disposed on the through-hole plugs 36 in the insulating film 17. The circuit chip 2 functions as a control circuit (logic circuit) for controlling the array chip 1. The metal pad 37 is an example of a first pad.

[0027] The array chip 1 includes a plurality of metal pads 41 disposed on the metal pads 37 in the insulating film 16, a plurality of through-hole plugs 42 disposed on the metal pads 41, and a wiring layer 43 disposed on these through-hole plugs 42 and including a plurality of wirings. Each word line WL or each bit line BL is electrically connected to a corresponding wiring in the wiring layer 43. The array chip 1 also includes a wiring layer 44 disposed on the wiring layer 43 and including a plurality of wirings, a wiring layer 45 disposed on the wiring layer 44 and including a plurality of wirings, and a through-hole plug 46 disposed on the wiring layer 45. The array chip 1 also includes a metal pad 47 disposed on the through-hole plug 46, and a passivation film 48 covering the metal pad 47 or the back gate electrode 14. The passivation film 48 is, for example, a silicon oxide film, and has an opening P that exposes the upper surface of the metal pad 47. The metal pad 47 is Figure 1 The external connection pad of the semiconductor device can be connected to the mounting substrate or other devices via solder balls, metal bumps, wires, etc. The metal pad 41 is an example of a second pad.

[0028] Figure 2 It is a cross-sectional view showing the structure of the columnar portion CL according to the first embodiment.

[0029] like Figure 2 As shown, the memory cell array 11 has an interlayer insulating film 15 ( Figure 1 ), the stacked film 58 includes a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked in the Z direction. The word lines WL are, for example, W (tungsten) layers. The insulating layers 51 are, for example, silicon oxide films. The stacked film 58 is an example of the first film, and the word lines WL are an example of the electrode layer.

[0030] The columnar portion CL includes a memory insulating film 57 extending in the Z direction, a channel semiconductor layer 55, and a core insulating film 56. The memory insulating film 57 includes a blocking insulating film 52, a charge storage layer 53, and a tunnel insulating film 54. The charge storage layer 53 is, for example, a silicon nitride film, and the interlayer blocking insulating film 52 is formed on the side of the stacked film 58. The channel semiconductor layer 55 is, for example, a polysilicon layer, and the interlayer tunnel insulating film 54 is formed on the side of the charge storage layer 53. The blocking insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films. The channel semiconductor layer 55 is an example of a first semiconductor layer. The charge storage layer 53 may be a layer other than an insulating film as long as it can store charges.

[0031] Figure 3 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0032] Figure 3 The array wafer W1 includes a plurality of array chips 1 and the circuit wafer W2 includes a plurality of circuit chips 2. The array wafer W1 does not include the semiconductor layer 12, the back gate insulating film 13, and the back gate electrode 14, but includes a substrate 20 on the memory cell array 11.

[0033] First, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure, thereby bonding the insulating film 16 to the insulating film 17 . Next, the array wafer W1 and the circuit wafer W2 are annealed at 400° C., thereby bonding the metal pad 41 to the metal pad 37 .

[0034] Then, the substrate 20 is removed by CMP (Chemical Mechanical Polishing) or wet etching, and the substrate 19 is thinned by CMP or wet etching, and then the array wafer W1 and the circuit wafer W2 are cut into multiple chips. Figure 1 In addition, the semiconductor layer 12, the back gate insulating film 13, the back gate electrode 14, the metal pad 47 and the passivation film 48 are formed on the memory cell array 11 or on the via plug 46 after removing the substrate 20, for example.

[0035] In addition, in this embodiment, the array wafer W1 and the circuit wafer W2 are bonded together, but the array wafers W1 may be bonded together instead. Figures 1 to 3 The content or references in the above text Figures 4 to 9 The content described below can also be applied to the bonding of array wafers W1 to each other.

[0036] in addition, Figure 1Although the boundary surfaces between the insulating film 16 and the insulating film 17 or the boundary surfaces between the metal pad 41 and the metal pad 37 are shown, these boundary surfaces are usually not observed after the annealing. However, the positions of these boundary surfaces can be estimated by, for example, detecting the inclination of the side surface of the metal pad 41 or the side surface of the metal pad 37 or the positional offset between the side surface of the metal pad 41 and the metal pad 37.

[0037] exist Figure 1 or Figure 3 In the embodiment, the insulating film 16 is formed on the lower surface of the interlayer insulating film 15, but the insulating film 16 may be included in the interlayer insulating film 15 and integrated. Figure 1 or Figure 3 In the embodiment, the insulating film 17 is formed on the upper surface of the interlayer insulating film 18 , but the insulating film 17 may be included in the interlayer insulating film 18 and integrated therewith.

[0038] Figures 4 to 6 It is a cross-sectional view showing details of the method for manufacturing the semiconductor device according to the first embodiment.

[0039] Figure 4 and Figure 3 Similarly, the array wafer W1 is shown before being bonded to the circuit wafer W2. Figure 3 The array wafer W1 represents the Figure 4 The upper and lower parts of the array wafer W1 are inverted. That is, Figure 4 It shows the array wafer W1 before inversion. Figure 3 It shows the array wafer W1 after being inverted.

[0040] In this embodiment, an etching stop insulating film 103 is formed on the substrate 20, and a build-up film 58 ( Figure 4 The etching stop insulating film 103 is, for example, a high-k insulating film (high dielectric constant insulating film). The high-k insulating film is, for example, an insulating film containing a rare earth element. The stacked film 58 is formed in a manner that alternately includes a plurality of word lines WL and a plurality of insulating layers 51 .

[0041] Next, a plurality of holes and slits are formed through the stacked film 58 and the etching stop insulating film 103 by etching, and the memory insulating film 57, the channel semiconductor layer 55 and the core insulating film 56 are sequentially formed in these holes, and the source insulating film 101 and the source wiring layer 102 are sequentially formed in the slits. Figure 4 As a result, a plurality of columnar portions CL extending in the Z direction and a source wiring layer 102 are formed in the stacked film 58 and the etching stop insulating film 103. The source insulating film 101 is, for example, a silicon oxide film, and the source wiring layer 102 is, for example, a polysilicon layer or a metal layer. The source wiring layer 102 is an example of a first wiring.

[0042] If over-etching of the substrate 20 occurs when forming the holes or slits, the holes or slits may protrude from the build-up film 58 (and the etching stop insulating film 103 ) into the substrate 20 . Figure 4 An example of such overetching is shown. Thus, each channel semiconductor layer 55 includes a protruding portion P1 protruding from the laminated film 58 into the substrate 20, and the source wiring layer 102 includes a protruding portion P2 protruding from the laminated film 58 into the substrate 20. The protruding portion P1 is an example of the first portion, and the protruding portion P2 is an example of the second portion. Since the overetching amount of the substrate 20 is uneven depending on the hole or the slit, the heights (lengths in the Z direction) of the protruding portions P1 and P2 are different from each other.

[0043] In addition, a replacement step may be adopted when forming the stacked film 58. In this case, a plurality of sacrificial layers and a plurality of insulating layers 51 are alternately formed on the etching stop insulating film 103, and a plurality of columnar portions CL and a source wiring layer 102 are formed in these sacrificial layers, the insulating layers 51, and the etching stop insulating film 103. Then, the sacrificial layers are removed to form a plurality of cavities between the insulating layers 51, and a plurality of word lines WL are buried in these cavities. Thus, a stacked film 58 alternately including a plurality of word lines WL and a plurality of insulating layers 51 is formed, and a plurality of columnar portions CL and a source wiring layer 102 are formed in the stacked film 58.

[0044] Next, the array wafer W1 and the circuit wafer W2 are bonded together (see Figure 3 ), implementation Figure 5 and Figure 6 In the implementation Figure 5 and Figure 6 In the step of , the array wafer W1 is actually held in such a manner that the bottom of the columnar portion CL is located at the top. Figure 5 and Figure 6 The bottom of the columnar portion CL is shown in the figure at the bottom for easy comparison. Figure 4 Therefore, the implementation Figure 5 and Figure 6 In the step of , it is necessary to note that the bottom of the columnar portion CL is actually located at the upper part rather than the lower part, and the etching stop insulating film 103 is actually located at the upper surface of the stacked film 58 rather than the lower surface. In addition, for this reason, it is necessary to note that Figure 5 and Figure 6 The arrow in the Z direction is Figure 4 Different, the illustration shows it facing up and down on the paper.

[0045] exist Figure 5In the process, the substrate 20 is removed by wet etching or dry etching the etching stop insulating film 103 used as a stopper film. Wet etching is performed, for example, using an aqueous hydrofluoric acid solution or an alkaline aqueous solution. Dry etching is performed, for example, using a gas containing fluorine or chlorine. When the memory insulating film 57 is subsequently etched, an aqueous hydrofluoric acid solution, phosphoric acid, or a gas containing fluorine or chlorine is also used. Therefore, the etching stop insulating film 103 is preferably formed of a material that is not etched or not easily etched by such a liquid or gas. In addition, the etching stop insulating film 103 of the present embodiment is also used in order to have a function of gate controlling the carrier concentration of the semiconductor layer 12 to be formed later. Therefore, the etching stop insulating film 103 of the present embodiment is ideally made of a high-k insulating film (Zr represents zirconium, and Hf represents hafnium) such as a ZrO film or an HfO film. Continuous Figure 5 The etching is continued until the memory insulating film 57 or the source insulating film 101 covering the protruding portions P1 and P2 is removed. As a result, the surfaces of the protruding portions P1 and P2 are exposed.

[0046] Next, the semiconductor layer 12 ( Figure 6 ). As a result, the semiconductor layer 12 is formed on the surface of the stacked film 58 via the etching stop insulating film 103. In addition, the semiconductor layer 12 is formed in contact with the protruding portions P1 and P2, and is thus electrically connected to the channel semiconductor layer 55 and the source wiring layer 102. The semiconductor layer 12 is an example of a second semiconductor layer. The semiconductor layer 12 is, for example, a p-type polycrystalline silicon layer having a thickness of 10 nm or less. The semiconductor layer 12 may also be an n-type polycrystalline silicon layer.

[0047] Next, a back gate insulating film 13 is formed on the surface of the semiconductor layer 12, and a back gate electrode 14 ( Figure 6 ). As a result, the etching stop insulating film 103, the semiconductor layer 12, the back gate insulating film 13 and the back gate electrode 14 are sequentially stacked on the surface of the stacked film 58. The back gate insulating film 13 is an example of a first insulating film, and the back gate electrode 14 is an example of a first electrode. The back gate insulating film 13 is, for example, a silicon oxide film. The back gate electrode 14 is, for example, a metal layer.

[0048] So, in Figure 5 and Figure 6 In the step of removing the substrate 20, the semiconductor layer 12, the back gate insulating film 13 and the back gate electrode 14 are formed. As a result, the protrusions P1 and P2 protrude from the stacked film 58 into the semiconductor layer 12, the back gate insulating film 13 and the back gate electrode 14. Then, the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips to form Figure 1 semiconductor device. Figure 6 and Figure 1 Similarly, the structure of the semiconductor device according to the first embodiment is shown.

[0049] Below, refer to Figure 6 The semiconductor device according to this embodiment will be described in more detail.

[0050] In a conventional three-dimensional memory, when a columnar portion including a memory insulating film, a channel semiconductor layer, and a core insulating film is formed in sequence on a substrate, an opening is sometimes formed at the bottom of the memory insulating film, and a channel main layer is buried in the opening. As a result, the channel semiconductor layer is electrically connected to the substrate via the channel main layer. Furthermore, the source wiring layer is also electrically connected to the substrate. As a result, the channel semiconductor layer and the source wiring layer are electrically connected to each other. However, if the depths of the multiple holes for burying the multiple columnar portions are uneven, the three-dimensional memory may not operate normally. The reason is that it is not easy for carrier electrons to reach the channel semiconductor layer in which the channel main layer is located at a deeper position in the channel semiconductor layer of these columnar portions.

[0051] Therefore, in this embodiment, the substrate 20 is removed, and the memory insulating film 57 covering the protruding portions P1 and P2 is removed, so that the surfaces of the protruding portions P1 and P2 are exposed ( Figure 5 Then, a semiconductor layer 12 is formed on the surface exposed by the protruding portions P1 and P2 ( Figure 6 ). Thus, the channel semiconductor layer 55 and the source wiring layer 102 of each columnar portion (memory string) CL are electrically connected to each other through the semiconductor layer 12. The semiconductor layer 12 of this embodiment is a silicon thin film having a thickness of 10 nm or less.

[0052] The semiconductor layer 12 is covered by a back gate insulating film 13 and a back gate electrode 14, which constitute a MOS (Metal-Oxide-Semiconductor) structure. Similarly, the semiconductor layer 12, the etching stop insulating film 103 and the word line WL located closest to the etching stop insulating film 103 also constitute another MOS structure. In this embodiment, a carrier path is formed in the channel semiconductor layer 55 and in the semiconductor layer 12 through the back gate electrode 14 and the word line WL and connected to the source wiring layer 102. In this way, the preferred operation of the three-dimensional memory can be achieved. In addition, the word line WL located closest to the etching stop insulating film 103 functions as a selection line rather than a word line WL, but since it is formed of the same material as other word lines WL, it is expressed as "word line WL" for convenience.

[0053] In this case, the thickness of the semiconductor layer 12 is preferably 10 nm or less as described above. The reason for this is that the back gate electrode 14 is ensured to enter the space between the protruding portions P1, and the thickness of the inversion layer generated in the semiconductor layer 12 is several nm. If the semiconductor layer 12 is thicker, the charge storage layer or the inversion layer may be interrupted in the Z direction, causing the cell current to decrease.

[0054] In addition, it is desirable to make the semiconductor layer 12 into a p-type diffusion layer in order to provide holes to the channel semiconductor layer 55 when deleting data in the memory cell. When the semiconductor layer 12 is made into an n-type diffusion layer, an operation called GIDL (Gate Induced Drain Leakage) deletion is required to generate holes at the gate edge of the selection gate SG, for example.

[0055] The channel semiconductor layer 55 preferably contains impurity atoms. For example, by providing a p-type high-concentration diffusion layer at the bottom (eg, the protruding portion P1) in the channel semiconductor layer 55, the above discontinuity can be suppressed.

[0056] The semiconductor layer 12 also preferably contains impurity atoms. Therefore, the semiconductor layer 12 also contains p-type impurities. This can more effectively suppress the above-mentioned discontinuity.

[0057] In addition, in the present embodiment, there is a case where the wiring layers 34, 35, 43, 44, 45 or the metal pads 37, 41, 47 are set as Cu (copper) layers. In this case, in order to avoid the thermal influence on the Cu layer, it is difficult to perform heat treatment to make the channel semiconductor layer 55 or the semiconductor layer 12 into a p-type diffusion layer. In this case, the heat treatment of the p-type diffusion layer can be performed by laser heating or microwave heating to avoid the thermal influence on the Cu layer while performing the heat treatment. Thus, a high-quality polycrystalline silicon layer can be formed as a p-type diffusion layer. Examples of the heat treatment are heat treatment for diffusing p-type impurities (such as III group elements such as boron, aluminum, and indium) in the semiconductor layer or heat treatment for crystallizing a semiconductor layer formed in an amorphous state at a low temperature. The heat treatment can also be a very short time heating treatment such as heating with a heat lamp.

[0058] Next, refer to Figure 1 The contact plug (gate line, gate contact plug) 24 between the back gate electrode 14 and the back gate wiring layer 25 will be described.

[0059] The gate line 24 is formed in the interlayer insulating film 15 and is located in the stacked film 58 ( Figure 2 ) outside. The gate line 24 is, for example, a polysilicon layer or a metal layer. The gate line 24 extends in the Z direction and penetrates the etching stop insulating film 103 ( Figure 4) and in contact with the back gate electrode 14. The gate line 24 is an example of a second wiring. The gate line 24 of this embodiment is similar to the columnar portion CL or the source wiring layer 102 through Figure 4 steps to form.

[0060] As described above, in this embodiment, after the array wafer W1 and the circuit wafer W2 are bonded together, Figure 5 and Figure 6 Steps. Figure 5 In the step of removing the substrate 20, the memory insulating film 57 or the source insulating film 101 covering the protruding portions P1 and P2 is removed. Figure 6 In the step, a semiconductor layer 12 is formed on the surface of the etching stop insulating film 103 and the protruding portions P1 and P2, a back gate insulating film 13 is formed on the surface of the semiconductor layer 12, and a back gate electrode 14 is formed on the surface of the back gate insulating film 13.

[0061] At this time, the semiconductor layer 12 and the back gate insulating film 13 are formed in a manner not to cover the gate line 24. Alternatively, after the semiconductor layer 12 and / or the back gate insulating film 13 are formed on the surface of the gate line 24, before the back gate electrode 14 is formed, the semiconductor layer 12 and / or the back gate insulating film 13 are removed from the surface of the gate line 24. As a result, the back gate electrode 14 is formed on the surface of the gate line 24 in a manner in contact with the gate line 24. Thus, the back gate electrode 14 can function as a part of the MOS structure and be electrically connected to the gate line 24.

[0062] In this embodiment, the array wafer W1 and the circuit wafer W2 are bonded together to electrically connect the gate line 24 in the array wafer W1 and the logic circuit (CMOS (Complementary Metal Oxide Semiconductor) circuit) in the circuit wafer W2. Figure 6 In the step of , the back gate electrode 14 is electrically connected to the circuit wafer W2 via the gate line 24. The back gate electrode 14 of this embodiment can also be connected to the circuit wafer W2. Figure 1 The metal pads 48 are formed of the same metal layer.

[0063] As described above, the semiconductor device of this embodiment includes semiconductor layer 12 provided on the bottom surface side of stacked film 58 so as to be in contact with channel semiconductor layer 55 and source wiring layer 102. Thus, according to this embodiment, channel semiconductor layer 102 and source wiring layer 102 can be electrically connected in a preferred form.

[0064] For example, according to this embodiment, by forming an electron layer in the semiconductor layer 12 using the electric field control of the double gate of the selection gate SG and the back gate electrode 106, multiple channel semiconductor layers 102 with different depths of the protruding part P1 can be electrically connected to the source wiring layer 102 through the same semiconductor layer 12.

[0065] In addition, when an opening is formed at the bottom of the memory insulating film and the channel main body layer is buried in the opening, an opening defect may occur in the opening. On the other hand, according to this embodiment, by removing the memory insulating film 57 covering the protruding portion P1, the occurrence of such an opening defect can be avoided. In addition, the opening at the bottom of the memory insulating film is not easy to form when the stacked film is thick, while the memory insulating film 57 covering the protruding portion P1 is easy to remove even when the stacked film 58 is thick. Therefore, this structure of the present embodiment has the advantage of being easy to implement even when the stacked film 58 is thick.

[0066] (Second embodiment) Figure 7 It is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0067] This embodiment Figure 7 Compared with the first embodiment Figure 6 However, in this embodiment, the back gate insulating film 13 and the back gate electrode 14 are not formed on the surface of the semiconductor layer 12. In addition, the semiconductor layer 12 of the first embodiment is formed to be thin, while the semiconductor layer 12 of this embodiment is formed to be thick. In addition, in this embodiment, a metal layer 104 is formed on the surface of the semiconductor layer 12. The metal layer 104 is, for example, a low resistance layer such as an aluminum layer.

[0068] The semiconductor layer 12 has a first surface on the channel semiconductor layer 55 and the source wiring layer 102 side and a second surface on the opposite side to the channel semiconductor layer 55 and the source wiring layer 102. Figure 7 In the figure, the first surface is the surface of the semiconductor layer 12 in the −Z direction, and the second surface is the surface of the semiconductor layer 12 in the +Z direction.

[0069] The first surface and the second surface of the present embodiment have unevenness due to the influence of the protruding parts P1 and P2 in the same manner as in the first embodiment. Specifically, the first surface and the second surface of the present embodiment are surfaces having unevenness in the region of the +Z direction of the semiconductor layer 55 and the region of the +Z direction of the source wiring layer 102. However, the thickness of the semiconductor layer 12 is also substantially constant in these regions. The above also holds true for the metal layer 104, and also holds true when other layers are formed on the surface of the semiconductor layer 12 instead of the metal layer 104 (for example, the back gate insulating film 13 or the back gate electrode 14 of the first embodiment).

[0070] In addition, it is considered that the unevenness of the second surface is relaxed as the semiconductor layer 12 becomes thicker. In other words, the shape of the second surface is closer to a flat shape as the semiconductor layer 12 is thicker. When the unevenness of the second surface of the semiconductor layer 12 is relaxed, the unevenness of both surfaces of the metal layer 104 is also relaxed.

[0071] The structure of this embodiment can be used, for example, in the following case: the three-dimensional memory can be properly operated without the back gate electrode 14. For example, the structure of this embodiment is used when both the channel semiconductor layer 55 and the semiconductor layer 12 are made into n-type diffusion layers. In addition, according to this embodiment, by forming the metal layer 104 on the surface of the semiconductor layer 12, long-distance transmission of current can be easily performed.

[0072] (Third embodiment) Figure 8 It is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment.

[0073] This embodiment Figure 8 Compared with the second embodiment Figure 7 However, the channel semiconductor layer 55 and the source wiring layer 102 of this embodiment do not protrude from the stacked film 58 into the semiconductor layer 12, that is, they do not have the protruding portions P1 and P2. This structure can be achieved, for example, by continuing CMP or wet etching when removing the substrate 20 until the protruding portions P1 and P2 disappear.

[0074] The semiconductor layer 12 has a first surface on the channel semiconductor layer 55 and the source wiring layer 102 side and a second surface on the opposite side to the channel semiconductor layer 55 and the source wiring layer 102. Figure 8 In the figure, the first surface is the surface of the semiconductor layer 12 in the −Z direction, and the second surface is the surface of the semiconductor layer 12 in the +Z direction.

[0075] The first surface and the second surface of the present embodiment are not affected by the protruding portions P1 and P2, and therefore have no unevenness. Specifically, the first surface and the second surface of the present embodiment are flat surfaces over the region in the +Z direction of the semiconductor layer 55 and the region in the +Z direction of the source wiring layer 102. The thickness of the semiconductor layer 12 is substantially constant in these regions. The above also holds true for the metal layer 104, and also holds true when other layers are formed on the surface of the semiconductor layer 12 instead of the metal layer 104.

[0076] According to this embodiment, by removing the protruding portions P1 and P2, the unevenness of the cell current in the plurality of columnar portions CL can be reduced. On the other hand, according to the second embodiment, by increasing the contact area between the channel semiconductor layer 55 and the semiconductor layer 12 or the contact area between the source wiring layer 102 and the semiconductor layer 12, the interruption can be more effectively suppressed.

[0077] In addition, the semiconductor device of the present embodiment may further include a back gate insulating film 13 and a back gate electrode 14 similarly to the first embodiment.

[0078] (Fourth embodiment) Fig. 9 It is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment.

[0079] This embodiment Fig. 9 Compared with the third embodiment Figure 8 Corresponding. The channel semiconductor layer 55 and the source wiring layer 102 of this embodiment do not protrude from the stacked film 58 into the semiconductor layer 12, similarly to the second embodiment, that is, they do not have protruding portions P1 and P2. However, the surface (bottom surface) of the channel semiconductor layer 55 and the source wiring layer 102 of this embodiment is recessed relative to the surface (bottom surface) of the etching stop insulating film 103. Symbols P3 and P4 respectively represent the protruding portions of the semiconductor layer 12 relative to the channel semiconductor layer 55 and the source wiring layer 102. Such a structure is generated, for example, due to a recess caused by CMP or over-etching caused by wet etching when the substrate 20 is removed.

[0080] The semiconductor layer 12 has a first surface on the channel semiconductor layer 55 and the source wiring layer 102 side and a second surface on the opposite side to the channel semiconductor layer 55 and the source wiring layer 102. Fig. 9 In the figure, the first surface is the surface of the semiconductor layer 12 in the −Z direction, and the second surface is the surface of the semiconductor layer 12 in the +Z direction.

[0081] The first surface and the second surface of the present embodiment have concavities and convexities due to the influence of the protruding portions P3 and P4. Specifically, the first surface and the second surface of the present embodiment are surfaces having concavities and convexities throughout the region in the +Z direction of the semiconductor layer 55 and the region in the +Z direction of the source wiring layer 102. However, the thickness of the semiconductor layer 12 is also substantially constant in these regions. The above also holds true for the metal layer 104, and also holds true when other layers are formed on the surface of the semiconductor layer 12 instead of the metal layer 104.

[0082] In addition, it is considered that the unevenness of the second surface is relaxed as the semiconductor layer 12 becomes thicker. In other words, the shape of the second surface is closer to a flat shape as the semiconductor layer 12 is thicker. When the unevenness of the second surface of the semiconductor layer 12 is relaxed, the unevenness of both surfaces of the metal layer 104 is also relaxed.

[0083] According to the present embodiment, by removing the protruding portions P1 and P2 , it is possible to reduce the variation in the cell current in the plurality of columnar portions CL, similarly to the third embodiment.

[0084] In addition, the semiconductor device of the present embodiment may further include a back gate insulating film 13 and a back gate electrode 14 similarly to the first embodiment.

[0085] Several embodiments have been described above, but these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices and methods described in this specification may be implemented in various other ways. In addition, various omissions, substitutions, and changes may be made to the methods of the devices and methods described in this specification without departing from the scope of the invention. The attached claims and their equivalents are intended to include such methods or variations that are included in the scope or spirit of the invention.

Claims

1. A semiconductor device comprising: A first film including a plurality of electrode layers and a plurality of insulating layers alternately arranged in a first direction; A first semiconductor layer, disposed in the first film through a charge storage layer, and extending in the first direction; as well as a second semiconductor layer provided in contact with one end of the first semiconductor layer in the first direction and extending in a second direction intersecting the first direction; and The second semiconductor layer has a first surface on the first semiconductor layer side and a second surface on the opposite side to the first semiconductor layer; The first semiconductor layer has a first protruding portion protruding from the first film, and the first surface and the second surface are surfaces having concavities and convexities corresponding to the first protruding portion throughout a region of the first semiconductor layer in the first direction. 2 . The semiconductor device according to claim 1 , further comprising a first insulating film provided on a surface of the second semiconductor layer in the first direction of the first film. 3 . The semiconductor device according to claim 2 , further comprising a first electrode provided on a surface of the first insulating film in the first direction of the first film.

4. The semiconductor device according to claim 1, further comprising: a layer provided in the first film, extending in the first direction, and including a semiconductor or a metal; and One end of the layer including a semiconductor or a metal in the first direction is in contact with the second semiconductor layer. 5 . The semiconductor device according to claim 3 , further comprising a wiring provided outside the first film and extending in the first direction, wherein the first electrode is provided on a surface of the first insulating film and is provided in contact with the wiring. 6 . The semiconductor device according to claim 1 , wherein the second semiconductor layer is an n-type semiconductor layer. The semiconductor device according to claim 6 , wherein the second semiconductor layer is a polysilicon layer. 8 . The semiconductor device according to claim 4 , wherein the layer including a semiconductor or a metal is a polysilicon layer.

9. A semiconductor device according to claim 1, wherein the first protruding portion of the first semiconductor layer protrudes from the first film into the second semiconductor layer, the second semiconductor layer is arranged in a manner of being in contact with the first protruding portion of the first semiconductor layer, and the second surface having the concave and convex surface includes: a portion extending in the first direction, and a portion extending in the second direction.

10. A semiconductor device comprising: a first chip having a first pad; and a second chip having a second pad provided on the first pad; and The second chip comprises: A first film including a plurality of electrode layers and a plurality of insulating layers alternately arranged in a first direction; A first semiconductor layer, disposed in the first film through a charge storage layer, and extending in the first direction; as well as a second semiconductor layer provided in contact with one end of the first semiconductor layer in the first direction and extending in a second direction intersecting the first direction; and The second semiconductor layer has a first surface on the first semiconductor layer side and a second surface on the opposite side to the first semiconductor layer; The first semiconductor layer has a first protruding portion protruding from the first film, and the first surface and the second surface are surfaces having concavities and convexities corresponding to the first protruding portion throughout a region of the first semiconductor layer in the first direction.

11. A method for manufacturing a semiconductor device, comprising: forming a first film including a plurality of first layers and a plurality of insulating layers alternately arranged in a first direction on a first substrate, A first semiconductor layer extending in the first direction is formed in the first film via a charge storage layer. removing the first substrate to expose the first semiconductor layer so as to protrude from the first film, and forming a second semiconductor layer so as to be in contact with one end of the protruding first semiconductor layer in the first direction, and A thickness of a first protruding portion of the first semiconductor layer protruding from the first film in the first direction is thicker than a thickness of the second semiconductor layer in the first direction. 12 . The method for manufacturing a semiconductor device according to claim 11 , wherein the thickness of the second semiconductor layer is 10 nm or less.

13. The method for manufacturing a semiconductor device according to claim 11, further comprising forming the following layer: a layer provided in the first film, extending in the first direction, and including a semiconductor or a metal; and One end of the layer including a semiconductor or a metal in the first direction is in contact with the second semiconductor layer. 14 . The method for manufacturing a semiconductor device according to claim 11 , wherein the second semiconductor layer is an n-type semiconductor layer. 15 . The method for manufacturing a semiconductor device according to claim 14 , wherein the second semiconductor layer is a polysilicon layer. 16 . The method for manufacturing a semiconductor device according to claim 13 , wherein the layer containing a semiconductor or a metal is a polysilicon layer.

17. The method for manufacturing a semiconductor device according to claim 11, comprising: The surface of the second semiconductor layer opposite to the surface in contact with the first semiconductor layer is a surface having projections and depressions corresponding to the first protruding portion.

18. The method for manufacturing a semiconductor device according to claim 11, further comprising: preparing a second substrate on which a circuit is formed, The first substrate is removed after the first substrate and the second substrate are bonded together.

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