Storage unit, manufacturing method thereof, memory and electronic equipment

Abstract

According to the storage unit, the manufacturing method thereof, the memory and the electronic equipment, when the Helmholtz free energy of the metal element in the introduced first doping layer is lower than the Helmholtz free energy of the metal element in the ferroelectric layer, the dielectric layer can display the ferroelectric performance through the introduction of the first doping layer; when the Helmholtz free energy of the metal element in the introduced second doping layer is not lower than the Helmholtz free energy of the metal element in the ferroelectric layer, captured and accumulated electrons can be dredged through introduction of the second doping layer, and aggregation and accumulation of the electrons in the dielectric layer are avoided. Therefore, breakdown of the dielectric layer caused by electron aggregation and accumulation is avoided, and the reliability of the dielectric layer and even the storage unit is improved when the ferroelectric storage unit is obtained.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage unit, a manufacturing method thereof, a memory and an electronic device. Background Art

[0002] Ferroelectric memory has the advantages of low read and write voltage, low power consumption, small device size, high read and write speed, good cycle performance, good radiation resistance and non-volatility, and is expected to be used to build a new generation of non-volatile memory. Compared with traditional ferroelectric materials, hafnium-based ferroelectric materials not only have superior miniaturization characteristics, but also can overcome the technical difficulties and bottlenecks such as incompatibility between traditional ferroelectric materials and complementary metal oxide semiconductor (CMOS) processes, difficulty in miniaturization, and difficulty in achieving high-density integration. Therefore, hafnium-based ferroelectric devices are expected to become the core unit of future new ferroelectric memories.

[0003] However, in the storage layer of the hafnium-based ferroelectric memory, in order to enable the hafnium oxide material to exhibit ferroelectricity, oxygen vacancies are generally introduced into the hafnium oxide. If there are a large number of oxygen vacancies, the oxygen vacancies can capture accumulated electrons, introduce a built-in electric field, produce a pinning effect on the electric domain in a certain polarization direction, and may even cause the storage layer to be broken down, resulting in poor reliability of the hafnium-based ferroelectric memory. Summary of the invention

[0004] The present application provides a storage unit, a manufacturing method thereof, a storage unit and an electronic device, which are used to improve the reliability of a hafnium-based ferroelectric storage unit and improve the performance of the ferroelectric storage unit.

[0005] In the first aspect, the embodiment of the present application provides a storage unit, which may include: a first conductive layer, a functional layer, and a dielectric layer disposed between the first conductive layer and the functional layer; the dielectric layer may include: a stacked ferroelectric layer, a first doped layer, and a second doped layer. The material used to make the ferroelectric layer may include, but is not limited to, a hafnium oxide material. A pure hafnium oxide material is unlikely to have ferroelectricity. When the first doped layer is introduced, and the Helmholtz free energy of the metal element in the first doped layer is lower than the Helmholtz free energy of the metal element in the ferroelectric layer, it means that the metal in the first doped layer requires less energy to move, which makes it easier to generate defects in the dielectric layer, thereby generating more oxygen vacancies. The oxygen vacancies can cause the hafnium oxide to exhibit ferroelectricity, thereby forming a ferroelectric layer. However, due to the deep defect energy level of oxygen vacancies, more oxygen vacancies can capture and accumulate electrons, introduce a built-in electric field, produce a pinning effect on the electric domain of a certain polarization direction, and may even cause the dielectric layer to be broken down. Therefore, when the second doping layer is introduced and the Helmholtz free energy of the metal element in the second doping layer is not lower than the Helmholtz free energy of the metal element in the ferroelectric layer, it means that the metal in the second doping layer requires higher energy when moving, and fewer defects are generated in the dielectric layer and the defect energy level is shallow. These defects with shallow energy levels can guide the captured and accumulated electrons, avoid the aggregation and accumulation of electrons in the dielectric layer, and thus avoid the problem of dielectric layer breakdown caused by electron aggregation and accumulation. Therefore, by introducing the first doping layer and the second doping layer with different functions, not only can the ferroelectric layer be obtained, but also the reliability of the dielectric layer and even the storage unit can be improved.

[0006] It should be understood that the material for making the ferroelectric layer may include not only hafnium oxide material, but also other materials with similar properties to hafnium oxide material, which is not limited here. The hafnium oxide material property means that it is difficult for a pure hafnium oxide material to exhibit ferroelectricity, but when oxygen vacancies or a first doping layer are introduced, hafnium oxide can exhibit ferroelectricity.

[0007] For the introduced first doping layer and the second doping layer: the first doping layer can be provided with multiple layers, and a ferroelectric layer is provided between two adjacent first doping layers, the second doping layer can also be provided with multiple layers, and a ferroelectric layer is also provided between two adjacent second doping layers, and a ferroelectric layer is provided between the first doping layer and the second doping layer, so that the first doping layer and the second doping layer can be spaced apart by the ferroelectric layer, and each first doping layer and each second doping layer can also be spaced apart by the ferroelectric layer, so as to achieve uniform ferroelectric distribution in the dielectric layer. When the ferroelectric layer also has multiple layers, the ferroelectric layer, the first doping layer and the second doping layer can be stacked alternately or non-alternatingly, as long as ferroelectric layers are provided between different first doping layers, between different second doping layers, and between the first doping layer and the second doping layer. The specific stacking method of the ferroelectric layer, the first doping layer and the second doping layer can be designed according to actual needs and is not limited here.

[0008] Exemplarily, in addition to meeting the requirements of Helmholtz free energy, the metal elements in the first doping layer may also meet the following requirements: the difference between the atomic radius of the metal elements in the first doping layer and the metal elements in the ferroelectric layer is not less than a threshold value, that is, the difference between the atomic radius of the metal elements in the first doping layer and the metal elements in the ferroelectric layer is relatively large, so that when the metal in the first doping layer is introduced, the lattice distortion of the material in the ferroelectric layer is relatively large, which has a greater impact on the crystallization of the material in the ferroelectric layer, thereby being more conducive to the formation of the ferroelectric layer. Or the valence state of the metal elements in the first doping layer is lower than the valence state of the metal elements in the ferroelectric layer, so that the stability of the metal in the first doping layer and oxygen combination is relatively low, and it is easy to introduce more oxygen vacancies, which also has a greater impact on the crystallization of the material in the ferroelectric layer, thereby being more conducive to the formation of the ferroelectric layer. Or the difference between the atomic radius of the metal elements in the first doping layer and the metal elements in the ferroelectric layer is not less than a threshold value, and the valence state of the metal elements in the first doping layer is lower than the valence state of the metal elements in the ferroelectric layer, so that the formation of the ferroelectric layer can be promoted from two perspectives: causing the lattice distortion of the material in the ferroelectric layer and introducing oxygen vacancies. At this time, the metal element in the first doping layer may include, but is not limited to, at least one of lanthanum, cerium, molybdenum, zirconium, silicon, gadolinium, yttrium, etc. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is lower than the valence state of the metal element in the ferroelectric layer, it can be considered that the metal meets the requirement that the valence state is lower than the valence state of the metal element in the ferroelectric layer.

[0009] Moreover, taking the example of the ferroelectric layer made of hafnium oxide material, the hafnium oxide material has multiple phase structures, among which the most common are T phase, O phase and M phase. The ferroelectric phase is a type of O phase. During the heat treatment process, hafnium oxide can form a T phase as the temperature rises, and then transform into an O phase or an M phase during the cooling process. When a metal element is included in the first doping layer, the metal element can cause the hafnium oxide to be stable in the O phase and exhibit ferroelectricity to form a ferroelectric layer. Alternatively, when the first doping layer includes multiple metal elements, some of these metal elements (referred to as Class A metal elements) are used to promote the hafnium oxide to stabilize in the O phase and exhibit ferroelectricity to form a ferroelectric layer, so the role of the Class A metal elements includes promoting the formation of the ferroelectric layer, and another part of these metal elements (referred to as Class B metal elements) are used to promote the hafnium oxide to form the T phase, so as to reduce the heat treatment temperature and the thermal budget required for crystallization, so the role of the Class B metal elements includes reducing the heat treatment temperature required in the formation of the ferroelectric layer, so that the ferroelectric layer can be obtained and the reliability of the dielectric layer can be improved, and the thermal budget when the ferroelectric layer is formed can also be reduced. Among them, the Class A metal elements may include but are not limited to: at least one of lanthanum, cerium, molybdenum, etc., and the Class B metal elements may include but are not limited to: at least one of zirconium, silicon, gadolinium, yttrium, etc.

[0010] Similarly, in addition to meeting the requirements of Helmholtz free energy, the metal elements in the second doping layer can also meet the following requirements: the difference between the atomic radius of the metal elements in the second doping layer and the metal elements in the ferroelectric layer is less than the threshold value, that is, the atomic radius of the metal elements in the second doping layer and the metal elements in the ferroelectric layer are close, so that when the metal in the second doping layer is introduced, the lattice distortion of the material in the ferroelectric layer is small, the crystallization of the material in the ferroelectric layer is less affected, and the defect energy level generated is shallow, which can guide the accumulated electrons to avoid the aggregation of electrons. Or the valence state of the metal elements in the second doping layer is not lower than the valence state of the metal elements in the ferroelectric layer, so that the metal in the second doping layer is relatively stable in combination with oxygen, it is difficult to introduce oxygen vacancies or the introduced oxygen vacancies are less, and the defect energy level generated is shallow, which can guide the accumulated electrons to avoid the aggregation of electrons. Or the difference between the atomic radius of the metal elements in the second doping layer and the metal elements in the ferroelectric layer is less than the threshold value, and the valence state of the metal elements in the second doping layer is not lower than the valence state of the metal elements in the ferroelectric layer. At this time, the metal element in the second doping layer may include, but is not limited to, at least one of titanium and niobium. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is not lower than the valence state of the metal element in the ferroelectric layer, it can be considered that the metal meets the requirement that the valence state is not lower than the valence state of the metal element in the ferroelectric layer.

[0011] The threshold value can be set according to factors such as the storage window and reliability requirements of the storage unit, for example, the threshold value can be set to 10 pm, which is not limited here. It should be understood that within the storage window of the storage unit, the polarization state of the ferroelectric is strong and remains unchanged, and outside the storage window, the polarization state is weak or flipped, so the storage window of the storage unit has a higher storage capacity, and information can be stably recorded to achieve data storage.

[0012] The storage unit may include a transistor and a storage capacitor. When the dielectric layer is applied to the storage capacitor, the functional layer may be used as the second conductive layer in the storage capacitor. The first conductive layer and the second conductive layer are disposed on both sides of the dielectric layer to form a storage capacitor. The storage window of the dielectric layer in the storage capacitor affects the storage performance of the storage capacitor, and further affects the performance of the storage unit. By introducing the first doped layer, a ferroelectric layer may be obtained to obtain a sufficient storage window, thereby realizing data storage; and by introducing the second doped layer, the reliability of the dielectric layer may be improved, thereby improving the reliability of the dielectric layer without losing the storage window.

[0013] When the dielectric layer is applied to a transistor, the functional layer can serve as the channel of the transistor, and correspondingly the first conductive layer can serve as the gate of the transistor. The dielectric layer serves as the gate insulating layer of the transistor to isolate the channel and the gate to avoid short circuit between the channel and the gate. Thus, when the dielectric layer has better reliability, the reliability and performance of the transistor will also be improved.

[0014] Moreover, taking the storage capacitor as an example, when the storage capacitor is arranged on the substrate, the first conductive layer, the dielectric layer and the functional layer can be stacked in a direction perpendicular to the substrate surface, and the dielectric layer is arranged between the first conductive layer and the functional layer. In this case, the storage capacitor can be regarded as a storage capacitor with a two-dimensional structure. Alternatively, the functional layer and the insulating layer can be alternately stacked in a direction perpendicular to the substrate surface to form a stacked structure, and then a through hole is dug in the stacked structure, and the through hole penetrates the stacked structure along the stacking direction, and then the dielectric layer and the first conductive layer are filled in the through hole in sequence, and the dielectric layer is arranged between the stacked structure and the first conductive layer. In this case, the stacking direction of the ferroelectric layer, the first doped layer and the second doped layer is perpendicular to the extension direction of the through hole. In this case, the storage capacitor formed can be regarded as a storage capacitor with a three-dimensional structure. For transistors, similar to storage capacitors, transistors with a two-dimensional structure or transistors with a three-dimensional structure can also be made, which will not be described in detail here.

[0015] Exemplarily, the material of the first conductive layer may include any material with conductive function, such as but not limited to: metal, metal oxide, and conductive organic matter, etc., which can be selected according to actual needs and are not limited here. When the functional layer is used as the second conductive layer, the material of the functional layer can be the same as or different from the material of the first conductive layer, which can be selected according to actual needs and are not limited here. When the functional layer is used as a transistor, it can be made of semiconductor material, which can be selected according to actual needs and are not limited here.

[0016] Of course, the first conductive layer and the functional layer as the second conductive layer can both be referred to as conductive film layers. For example, a film layer with auxiliary functions can be provided between the conductive film layer and the dielectric layer, such as but not limited to an adhesion layer or an interface passivation layer, etc. When an adhesion layer is provided, the adhesion between the dielectric layer and the conductive film layer can be increased by the adhesion layer, so as to avoid the conductive film layer and the dielectric layer from falling off and separating during the use of the storage unit, thereby further improving the reliability of the storage unit. Among them, the adhesive layer can be made of a material selected according to the material of the conductive film layer, and any material that can play an adhesion role can be used to make the adhesive layer. When an interface passivation layer is provided, the element diffusion between the dielectric layer and the conductive film layer can be suppressed by the interface passivation layer, so as to avoid the functional degradation of the conductive film layer and the dielectric layer, thereby improving the ferroelectricity of the dielectric layer and improving the reliability of the storage unit. Among them, the interface passivation layer can also be made of a material selected according to the material of the conductive film layer, and any material that can play an interface passivation role can be used to make the interface passivation layer.

[0017] In the second aspect, the embodiment of the present application further provides a method for manufacturing a memory cell. The memory cell manufactured by the manufacturing method can be the memory cell described in the first aspect and any possible embodiment of the first aspect. The manufacturing method can include: forming a functional layer; stacking a ferroelectric layer, a first doping layer, and a second doping layer on the functional layer, so that the ferroelectric layer, the first doping layer, and the second doping layer constitute a dielectric layer, the Helmholtz free energy of the metal element in the first doping layer is lower than the Helmholtz free energy of the metal element in the ferroelectric layer; the Helmholtz free energy of the metal element in the second doping layer is not lower than the Helmholtz free energy of the metal element in the ferroelectric layer; forming a first conductive layer on the dielectric layer. In this way, the introduction of the first doping layer can help the dielectric layer to exhibit ferroelectric properties, and the introduction of the second doping layer can guide the captured and accumulated electrons to avoid the aggregation and accumulation of electrons in the dielectric layer, thereby avoiding the problem of the dielectric layer being broken down due to the aggregation and accumulation of electrons, thereby improving the reliability of the dielectric layer and even the memory cell when the ferroelectric memory cell is obtained.

[0018] Exemplarily, stacking a ferroelectric layer, a first doping layer, and a second doping layer on the functional layer may include: stacking an initial film layer, a first doping layer, and a second doping layer on the functional layer, and then heat-treating the initial film layer, the first doping layer, and the second doping layer so that the initial film layer is transformed into a ferroelectric layer, thereby forming a dielectric layer on the functional layer. In other words, when forming the dielectric layer, a physical vapor deposition method or a chemical vapor deposition method may be used to form a stacked initial film layer, a first doping layer, and a second doping layer; and heat-treating the initial film layer, the first doping layer, and the second doping layer so that the initial film layer is transformed into a ferroelectric layer. Among them, taking the atomic layer deposition method as an example, since the thickness of the film layer obtained by each deposition of the atomic layer deposition method is limited, in order to obtain a film layer of a target thickness, it can be deposited continuously for multiple times. For example, when the initial film layer is deposited by the atomic layer deposition method, taking the use of hafnium oxide to make the initial film layer as an example, the hafnium oxide layer can be deposited continuously for multiple times so that the thickness of the hafnium oxide layer deposited continuously for multiple times reaches the target thickness, thereby obtaining the initial film layer. Furthermore, the first doping layer and the second doping layer are used to promote the formation of the ferroelectric layer and improve the reliability of the ferroelectric layer, so the thickness of the first doping layer and the second doping layer does not need to be set thick, and can be deposited once by atomic layer deposition. After stacking multiple ferroelectric layers, the first doping layer and the second doping layer, a dielectric layer of target thickness can be obtained.

[0019] Taking the initial film layer made of hafnium oxide as an example, the heat treatment process may include: first heating the initial film layer, the first doped layer and the second doped layer to a first preset temperature, so that the hafnium oxide forms a T phase during the heating process, and then cooling the initial film layer, the first doped layer and the second doped layer to a second preset temperature, so that the hafnium oxide is converted from the T phase to the O phase during the cooling process and stabilized in the O phase, so that the hafnium oxide exhibits ferroelectricity, and the initial film layer after heat treatment can be converted into a ferroelectric layer. It should be understood that the first preset temperature is higher than the second preset temperature, and the selection of the first preset temperature and the second preset temperature can be set according to factors such as the formation temperature of the T phase and the O phase, and is not limited here.

[0020] Of course, the heat treatment process is not limited to being performed before forming the first conductive layer, but can also be performed after forming the first conductive layer. In this case, the method for manufacturing the memory cell can specifically include: forming a functional layer; forming an initial dielectric layer in contact with the functional layer, the initial dielectric layer including: an initial film layer, a first doping layer and a second doping layer stacked; forming the first conductive layer on the initial dielectric layer; performing heat treatment to convert the initial film layer into a ferroelectric layer, thereby forming a dielectric layer. The heat treatment process can refer to the heat treatment process in the above content, and will not be described in detail here.

[0021] For example, when the dielectric layer is applied to the storage capacitor and the storage capacitor is a three-dimensional structure, the forming of the functional layer may include: forming alternating functional layers and insulating layers. The insulating layer may be made of any material that can play an insulating role, and is not limited here.

[0022] Among them, since the principle of solving the problem of the storage unit manufactured by this manufacturing method is similar to the principle of solving the problem of the aforementioned storage unit, the technical effects of this manufacturing method can refer to the embodiments and technical effects of the aforementioned storage unit, and the repeated parts will not be repeated.

[0023] In a third aspect, an embodiment of the present application further provides a memory, which may include: a storage array and a controller coupled to the storage array, the storage array including a plurality of storage units as described in the first aspect and any possible implementation of the first aspect, the plurality of storage units being deployed in an array manner; a storage array for storing data; a controller for writing data to the storage array or reading data from the storage array. In this way, on the basis of improving the reliability of the storage unit, the reliability of the memory is also improved, thereby improving the performance of the memory. Since the principle of solving the problem by the memory is similar to the principle of solving the problem by the aforementioned storage unit, the embodiments and technical effects of the memory can refer to the embodiments and technical effects of the aforementioned storage unit, and the repeated parts will not be repeated.

[0024] Exemplarily, when the storage cell includes a transistor and at least one storage capacitor, the memory may further include: a word line, a bit line, and at least one control line. When each storage cell in the storage array is deployed in an array manner, the storage cells in the same row can be connected to the same word line, and the storage cells in different rows are connected to different word lines, so that different word lines can control the conduction and disconnection of transistors in storage cells in different rows. The storage cells in the same column can be connected to the same bit line, and the storage cells in different columns are connected to different bit lines, so that different bit lines can provide voltages to storage cells in different rows. Each control line is respectively connected to the second end of each storage capacitor of each storage cell, that is, each storage cell is connected to each control line, and the number of control lines set is the same as the number of storage capacitors set in the storage cell, and is set one by one. Thus, each storage cell can be accurately controlled through the word line and the bit line, and the accurate writing and reading of data can be achieved under the action of the voltage provided by each control line.

[0025] In a fourth aspect, an embodiment of the present application further provides an electronic device, which may include: a circuit board, and a memory as described in the second aspect and any possible implementation of the second aspect, wherein the memory is disposed on the circuit board. In this way, on the basis of improving the reliability of the memory, the reliability of the electronic device is also improved, thereby improving the performance of the electronic device. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned memory, the embodiments and technical effects of the electronic device can refer to the embodiments and technical effects of the aforementioned memory, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of the structure of a storage capacitor in a storage unit provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of the structure of a storage capacitor in another storage unit provided in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of the principles provided for the embodiments of the present application;

[0031] Figure 6 A schematic diagram of the structure of a transistor in a memory cell provided in an embodiment of the present application;

[0032] Figure 7 A schematic diagram of the structure of a storage capacitor in another storage unit provided in an embodiment of the present application;

[0033] Figure 8 A manufacturing flow chart of a storage unit provided in an embodiment of the present application;

[0034] Fig. 9 A flowchart of manufacturing another storage unit provided in an embodiment of the present application;

[0035] Fig.10 A flowchart of manufacturing another storage unit provided in an embodiment of the present application;

[0036] Fig.11 A flowchart for manufacturing another storage unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0038] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0039] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first described below.

[0040] The storage unit can be widely used in devices with storage functions, for example, it can be applicable to storage devices with only storage functions, such as memory, and it can also be applicable to electronic devices with storage functions and other functions (such as read and write functions). The electronic device can be a portable electronic device that includes functions such as a personal digital assistant and / or a music player, such as a mobile phone, a tablet computer, a wearable device with wireless communication functions (such as a smart watch), or a car-mounted device. Exemplary embodiments of portable electronic devices include but are not limited to devices equipped with Or a portable electronic device with other operating systems. The portable electronic device may also be a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of the present application, the electronic device may also be a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0041] Figure 1 The schematic diagram of the structure of the memory when it is used in an electronic device is shown as an example. Figure 1 The electronic device includes a housing 300 and a circuit board 200 disposed in the housing 300, and a memory 100 is disposed on the circuit board 200. The memory 100 may be a non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. It should be noted that the memory described in the present application is intended to include but is not limited to these and any other suitable types of memory.

[0042] Figure 2The internal structure diagram of a memory 100 applicable to the embodiments of the present application is exemplarily shown. It should be understood that the illustrated memory 100 is only an example, and the memory 100 may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations. The various components shown in the figure may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application-specific integrated circuits.

[0043] like Figure 2 As shown, the memory 100 may include a storage array 110 and a controller 120. The storage array 110 is used to store data, and is a matrix array composed of multiple storage units arranged in rows and columns. Each storage unit can be used to store 1 or more bits of binary data, such as "0" and / or "1". Among them, multiple storage units can be located in different tracks of the same disk, or in different disks, without specific limitation. The controller 120 is used to read or write data in the storage array 110, and is a device with control capabilities. The controller 120 can be connected to the storage array 110, and the connection method can be, for example, a bus connection. The controller 120 may include multiple functional components, such as including but not limited to a driving circuit, a decoding circuit, and an amplifier circuit. These functional components can be set as separate devices, or they can be implemented in one device, or they can be set in at least two devices in any combination, without specific limitation.

[0044] Continue to refer to Figure 2 As shown, the controller 120 can also be connected to an external device 400, which can be, for example, a read / write device or a processor. When reading / writing data, the external device 400 can send a read / write request to the controller 120, and the read / write request carries the row address information and column address information of the target storage unit to be read / written. The controller 120 decodes the row address information in the read / write request to determine the row where the target storage unit is located, and turns on all storage units corresponding to the row where the target storage unit is located by decoding the selection signal, and then decodes the column address information in the read / write request to obtain the column where the target storage unit is located, and then reads the data stored in the target storage unit at the column and sends it to the external device 400, or writes the data to be written sent by the external device 400 into the target storage unit at the column.

[0045] although Figure 2 Not shown in the figure, the memory 100 may also include other components, such as a main memory data register (memory data register, MDR) and a main memory address register (memory address register, MAR), etc., which are not described in detail here.

[0046] Ferroelectric memory is gradually being used as a new type of memory with high-speed read and write and non-volatility. The core structure of the ferroelectric memory is a metal-ferroelectric layer-metal device structure. The ferroelectric layer is used as a storage medium, and the two states of ferroelectric polarization are used to write and read "0" and "1", which can remain unchanged even after the electric field is withdrawn. Among them, the ferroelectric layer can be made of hafnium oxide material. Hafnium oxide material has a variety of phase structures, among which the most common are T phase, O phase and M phase. The ferroelectric phase is a type of O phase, and the size of the storage window of the ferroelectric memory is determined by the O phase ratio and the polar axis direction. The O phase ratio is positively correlated with the storage window, and the degree of orientation proximity between the polar axis and the C axis is positively correlated with the storage window, so the storage window can be adjusted by adjusting the O phase ratio and the polar axis direction. Pure hafnium oxide material itself is extremely difficult to stabilize in the O phase, so pure hafnium oxide material itself is difficult to show ferroelectric phase, and element doping can affect the crystallization and crystal phase formation of hafnium oxide, so through element doping, hafnium oxide can show ferroelectric phase, thus obtaining hafnium oxide-based ferroelectric material.

[0047] When hafnium oxide-based ferroelectric materials are used as dielectric layers in memory, their reliability also needs to be considered. When hafnium oxide-based ferroelectric materials are used as storage layers (i.e., dielectric layers) in storage capacitors, if there are many oxygen vacancies, the oxygen vacancies can capture accumulated electrons, introduce built-in electric fields, produce pinning effects on electric domains in a certain polarization direction, and may even cause the storage medium to be broken down, resulting in poor reliability of hafnium oxide-based ferroelectric memory. When hafnium oxide-based ferroelectric materials are used as gate insulating layers in transistors, if there are many oxygen vacancies, the gate insulating layer may still be broken down, resulting in poor reliability of hafnium oxide-based ferroelectric memory.

[0048] Therefore, the embodiments of the present application provide a storage unit, a manufacturing method thereof, a memory, and an electronic device to improve the reliability of hafnium oxide-based ferroelectric memory and improve the performance of the ferroelectric memory.

[0049] First embodiment: Figure 3 and Figure 4 The schematic diagram of the structure of the storage unit in the embodiment of the present application is shown as an example. Figure 3 and Figure 4 As shown, the memory cell may include: a first conductive layer 10, a functional layer 20, and a dielectric layer 30 disposed between the first conductive layer 10 and the functional layer 20; the dielectric layer 30 may include: a stacked ferroelectric layer 30a, a first doped layer 30b, and a second doped layer 30c. Figure 3 As shown, when the first doping layer 30b is provided as a multilayer, a ferroelectric layer 30a is provided between two adjacent first doping layers 30b; Figure 4As shown, when the second doping layer 30c is provided with multiple layers, a ferroelectric layer 30a is also provided between two adjacent second doping layers 30c, and a ferroelectric layer 30a is provided between the first doping layer 30b and the second doping layer 30c, so that the first doping layer 30b and the second doping layer 30c can be separated by the ferroelectric layer 30a, and each first doping layer 30b and each second doping layer 30c can also be separated by the ferroelectric layer 30a, so as to achieve uniform ferroelectric distribution in the dielectric layer 30. When the ferroelectric layer 30a also has multiple layers, the ferroelectric layer 30a, the first doping layer 30b and the second doping layer 30c can be alternately stacked (such as Figure 4 as shown) or non-alternating stacking (as Figure 3 As shown), as long as a ferroelectric layer 30a is provided between different first doping layers 30b, between different second doping layers 30c, and between the first doping layer 30b and the second doping layer 30c, the specific stacking method of the ferroelectric layer 30a, the first doping layer 30b and the second doping layer 30c can be designed according to actual needs and is not limited here.

[0050] Combination Figure 5 As shown in the schematic diagram and Table 1 below, the material of the ferroelectric layer 30a can include, but is not limited to, a hafnium oxide material. A simple hafnium oxide material is difficult to have ferroelectricity. When the dielectric layer 30 only includes a hafnium oxide layer and a first doping layer 30b, if the metal element (such as Figure 5 The Helmholtz free energy of metal hafnium (as shown in y1 in a1) is lower than that of metal hafnium (as shown in Figure 5 The Helmholtz free energy of the metal element y1 in the first doping layer 30b is shown as y0 in a1, indicating that the metal element y1 in the first doping layer 30b requires lower energy when moving, which makes it easier to generate defects in the dielectric layer 30, thereby generating more oxygen vacancies (such as Figure 5 The oxygen vacancies y3 can make the hafnium oxide layer exhibit ferroelectricity to form a ferroelectric layer 30a. However, since the defect energy level of the oxygen vacancies y3 is deep, more oxygen vacancies y3 can capture and accumulate electrons (such as Figure 5 As shown in b1 in FIG. 1 ), a built-in electric field is introduced, a pinning effect is generated on an electric domain in a certain polarization direction, and even the dielectric layer 30 may be broken down, resulting in a low reliability of the dielectric layer 30. It should be understood that in Figure 5 In b1, n1 represents the energy level of the metal used to make the first conductive layer, and n2 represents the energy level of the metal used to make the functional layer.

[0051] Table 1

[0052] Doping Type Whether a ferroelectric layer is formed Thermal Budget reliability First doped layer yes high Low The second doped layer no Not relevant Not relevant The first doped layer and the second doped layer yes Low high

[0053] When the dielectric layer 30 only includes the hafnium oxide layer and the second doping layer 30c, if the metal element (such as Figure 5 The Helmholtz free energy of the metal element y0 is not lower than that of the metal element y2 in the second doping layer 30c, indicating that the metal element y2 in the second doping layer 30c requires a higher energy when moving, and the defects generated in the dielectric layer 30 are less and the defect energy level is shallow, making it difficult to capture the accumulated electrons (such as Figure 5 As shown in b2 in the figure), and the hafnium oxide layer is less likely to exhibit ferroelectricity, so it is more difficult to form the ferroelectric layer 30a.

[0054] When the dielectric layer 30 includes: a hafnium oxide layer, a first doping layer 30b, and a second doping layer 30c, since the Helmholtz free energy of the metal element y1 in the first doping layer 30b is lower than the Helmholtz free energy of the metal hafnium element y0, it is easier to generate defects in the dielectric layer 30, thereby generating more oxygen vacancies y3. The oxygen vacancies y3 can make the hafnium oxide layer exhibit ferroelectricity to form a ferroelectric layer 30a. Since the Helmholtz free energy of the metal element y2 in the second doping layer 30c is not lower than the Helmholtz free energy of the metal element y0 in the ferroelectric layer 30a, fewer defects are generated in the dielectric layer 30 and the defect energy level is shallow. These shallow defects can channel the captured and accumulated electrons (such as Figure 5 b3 in the figure), to prevent the electrons from gathering and accumulating in the dielectric layer 30, and thus to prevent the dielectric layer 30 from being broken down due to the electron gathering and accumulation. Therefore, by introducing the first doping layer 30b and the second doping layer 30c with different functions, not only the ferroelectric layer 30a can be obtained, but also the reliability of the dielectric layer 30 and even the storage unit can be improved.

[0055] It should be understood that the material of the ferroelectric layer 30a may include other materials with similar properties to the hafnium oxide material in addition to the hafnium oxide material, which is not limited here. The hafnium oxide material property means that it is difficult for a pure hafnium oxide material to exhibit ferroelectricity, but when oxygen vacancies or the first doping layer 30b are introduced, the hafnium oxide can exhibit ferroelectricity.

[0056] Exemplarily, in addition to meeting the Helmholtz free energy requirement, the metal elements in the first doping layer 30b may also meet the following requirements: the difference in atomic radius between the metal elements in the first doping layer 30b and the metal elements in the ferroelectric layer 30a is not less than a threshold value, that is, the difference in atomic radius between the metal elements in the first doping layer 30b and the metal elements in the ferroelectric layer 30a is relatively large, so that when the metal in the first doping layer 30b is introduced, the lattice distortion of the material in the ferroelectric layer 30a is relatively large, which has a relatively large impact on the crystallization of the material in the ferroelectric layer 30a, thereby being more conducive to the formation of the ferroelectric layer 30a. Alternatively, the valence state of the metal elements in the first doping layer 30b is lower than the valence state of the metal elements in the ferroelectric layer 30a, so that the stability of the metal in the first doping layer 30b in combination with oxygen is relatively low, and thus it is easy to introduce more oxygen vacancies, which also has a relatively large impact on the crystallization of the material in the ferroelectric layer 30a, thereby being more conducive to the formation of the ferroelectric layer 30a. Alternatively, the difference in atomic radius between the metal element in the first doping layer 30b and the metal element in the ferroelectric layer 30a is not less than a threshold value, and the valence state of the metal element in the first doping layer 30b is lower than the valence state of the metal element in the ferroelectric layer 30a. This can promote the formation of the ferroelectric layer 30a from two perspectives: causing lattice distortion of the material in the ferroelectric layer 30a and introducing oxygen vacancies. At this time, the metal element in the first doping layer 30b may include, but is not limited to, at least one of lanthanum, cerium, molybdenum, zirconium, silicon, gadolinium, yttrium, etc. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is lower than the valence state of the metal element in the ferroelectric layer 30a, it can be considered that the metal meets the requirement of having a valence state lower than the valence state of the metal element in the ferroelectric layer 30a.

[0057] Moreover, taking the example that the material of the ferroelectric layer 30a includes hafnium oxide material, the hafnium oxide material has a variety of phase structures, among which the most common are T phase, O phase and M phase, and the ferroelectric phase is a kind of O phase. During the heat treatment process, the hafnium oxide can form the T phase as the temperature rises, and then transform into the O phase or the M phase during the cooling process. At this time, the first doping layer 30b can include a metal element, which can make the hafnium oxide stable in the O phase and show ferroelectricity to form the ferroelectric layer 30a. Alternatively, as shown in Table 2 below, the first doping layer 30b may include a plurality of metal elements, some of which (referred to as Class A metal elements) are used to promote the hafnium oxide to be stable in the O phase and exhibit ferroelectricity to form the ferroelectric layer 30a, so the role of the Class A metal elements includes promoting the formation of the ferroelectric layer 30a, and the other part of which (referred to as Class B metal elements) are used to promote the hafnium oxide to form the T phase, so that the hafnium oxide is a mixture of the O phase and the T phase, which can reduce the heat treatment temperature and the heat budget required for crystallization, so the role of the Class B metal elements includes reducing the heat treatment temperature required in the formation of the ferroelectric layer 30a, so that the ferroelectric layer 30a can be obtained and the reliability of the dielectric layer 30 can be improved, and the heat budget when forming the ferroelectric layer 30a can also be reduced. Among them, the Class A metal elements may include but are not limited to: at least one of lanthanum, cerium, molybdenum, etc., and the Class B metal elements may include but are not limited to: at least one of zirconium, silicon, gadolinium, yttrium, etc.

[0058] Table 2

[0059] Element Type Crystal phase Thermal Budget Class A Metal Elements O phase high B-type metal elements O phase mixed with T phase Low

[0060] Similarly, in addition to meeting the Helmholtz free energy requirement, the metal elements in the second doping layer 30c can also meet the following requirements: the difference between the atomic radius of the metal elements in the second doping layer 30c and the metal elements in the ferroelectric layer 30a is less than the threshold value, that is, the atomic radius of the metal elements in the second doping layer 30c and the metal elements in the ferroelectric layer 30a are close, so that when the metal in the second doping layer 30c is introduced, the lattice distortion of the material in the ferroelectric layer 30a is small, the crystallization of the material in the ferroelectric layer 30a is small, and the defect energy level generated is shallow, which can guide the accumulated electrons to avoid the aggregation of electrons. Or the valence state of the metal elements in the second doping layer 30c is not lower than the valence state of the metal elements in the ferroelectric layer 30a, so that the metal in the second doping layer 30c is relatively stable in combination with oxygen, it is difficult to introduce oxygen vacancies or the introduced oxygen vacancies are small, and the defect energy level generated is shallow, which can guide the accumulated electrons to avoid the aggregation of electrons. Alternatively, the difference in atomic radius between the metal element in the second doping layer 30c and the metal element in the ferroelectric layer 30a is less than a threshold value, and the valence state of the metal element in the second doping layer 30c is not lower than the valence state of the metal element in the ferroelectric layer 30a. At this time, the metal element in the second doping layer 30c may include, but is not limited to, at least one of titanium and niobium. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is not lower than the valence state of the metal element in the ferroelectric layer 30a, it can be considered that the metal meets the requirement that the valence state is not lower than the valence state of the metal element in the ferroelectric layer 30a.

[0061] The threshold value can be set according to factors such as the storage window and reliability requirements of the storage unit, for example, the threshold value can be set to 10 pm, which is not limited here. It should be understood that within the storage window of the storage unit, the polarization state of the ferroelectric is strong and remains unchanged, and outside the storage window, the polarization state is weak or flipped, so the storage window of the storage unit has a higher storage capacity, and information can be stably recorded to achieve data storage.

[0062] For example, taking the case where the metal elements in the first doping layer are lanthanum and zirconium and the metal elements in the second doping layer are titanium, referring to Table 3 below, La:HfO2 in the table represents lanthanum-doped hafnium oxide, Zr:HfO2 represents zirconium-doped hafnium oxide, Ti:HfO2 represents titanium-doped hafnium oxide, La:Ti:HfO2 represents lanthanum and titanium-doped hafnium oxide, and La:Zr:Ti:HfO2 represents lanthanum, zirconium and titanium-doped hafnium oxide.

[0063] Table 3

[0064] Types of doping elements Crystal phase Miniaturization Thermal Budget reliability <![CDATA[La:HfO2]]> O phase good high Low <![CDATA[Zr:HfO2]]> O phase mixed with T phase Difference Low middle <![CDATA[Ti:HfO2]]> Difficult to form O phase or T phase Not relevant Not relevant Not relevant <![CDATA[La:Ti:HfO2]]> O phase good high high <![CDATA[La:Zr:Ti:HfO2]]> O phase good Low high

[0065] From the results shown in Table 3, it can be seen that for lanthanum-doped hafnium oxide, although the proportion of O phase can be increased to make O phase the main phase so that hafnium oxide exhibits ferroelectricity, the required heat treatment temperature is high, resulting in a high thermal budget and poor reliability; for zirconium-doped hafnium oxide, since the crystal phase is a mixture of O phase and T phase, the proportion of O phase can be reduced, so both the hafnium oxide can exhibit ferroelectricity and the thermal budget can be reduced; for titanium-doped hafnium oxide, since it is difficult to form O phase or T phase, it is difficult to make hafnium oxide exhibit ferroelectricity; for lanthanum and titanium-doped hafnium oxide, due to the effects of lanthanum and titanium, hafnium oxide can exhibit ferroelectricity and improve reliability, but the thermal budget is high due to the effect of lanthanum; for lanthanum, zirconium and titanium-doped hafnium oxide, due to the effects of lanthanum, zirconium and titanium, hafnium oxide can exhibit ferroelectricity and improve reliability, and the thermal budget can be reduced due to the effect of zirconium. Moreover, for zirconium-doped hafnium oxide, since the O phase and T phase are easily mixed to form polycrystalline, when the device area is miniaturized, the consistency of the crystal phase between different storage units is difficult to ensure, resulting in poor device miniaturization; but for lanthanum, zirconium and titanium-doped hafnium oxide, the role of lanthanum and titanium can make up for the poor miniaturization problem caused by zirconium doping alone, thereby improving the miniaturization performance of the device. Therefore, when selecting doping elements in actual situations, they can be selected based on the requirements for thermal budget, reliability, miniaturization, etc.

[0066] The storage unit may include a storage capacitor. When the dielectric layer 30 is applied to the storage capacitor, the functional layer 20 may be used as the second conductive layer in the storage capacitor. The first conductive layer 10 and the second conductive layer are disposed on both sides of the dielectric layer 30 to form a storage capacitor. The storage window of the dielectric layer 30 in the storage capacitor affects the storage performance of the storage capacitor, and further affects the performance of the storage unit. By introducing the first doped layer 30b, a ferroelectric layer 30a may be obtained to obtain a sufficient storage window, thereby realizing data storage; and by introducing the second doped layer 30c, the reliability of the dielectric layer 30 may be improved, thereby improving the reliability of the dielectric layer 30 without losing the storage window.

[0067] Furthermore, in the storage capacitor, the storage capacitor is provided on the substrate ( Figure 3 and Figure 4 When the first conductive layer 10, the dielectric layer 30 and the functional layer 20 are placed on the substrate, the first conductive layer 10, the dielectric layer 30 and the functional layer 20 can be placed along a direction perpendicular to the substrate surface (i.e. Figure 3 and Figure 4 The first conductive layer 10 and the functional layer 20 are stacked (in the z direction shown in FIG. 1 ), and the dielectric layer 30 is disposed between the first conductive layer 10 and the functional layer 20. In this case, the storage capacitor can be regarded as a storage capacitor with a two-dimensional structure.

[0068] Exemplarily, the material of the first conductive layer 10 may include any material having a conductive function, such as but not limited to: metal, metal oxide, and conductive organic matter, etc., which can be selected according to actual needs and are not limited here. When the functional layer 20 is used as the second conductive layer, the material of the functional layer 20 can be the same as or different from the material of the first conductive layer 10, which can be selected according to actual needs and are not limited here.

[0069] The first conductive layer 10 and the functional layer 20 as the second conductive layer can both be referred to as conductive film layers. For example, Figure 4 As shown, a film layer with auxiliary functions may be provided between the conductive film layer and the dielectric layer 30, such as but not limited to an adhesion layer 40 or an interface passivation layer ( Figure 4 (not shown), etc., wherein when an adhesion layer 40 is provided, the adhesion between the dielectric layer 30 and the conductive film layer can be increased by the adhesion layer 40, and the separation between the conductive film layer and the dielectric layer 30 can be avoided during the use of the storage unit, thereby further improving the reliability of the storage unit. Among them, the adhesion layer 40 can be made of a material selected according to the material of the conductive film layer, and the adhesion layer 40 can be made of any material that can play an adhesion role. When an interface passivation layer is provided, the element diffusion between the dielectric layer and the conductive film layer can be suppressed by the interface passivation layer, and the functional degradation of the conductive film layer and the dielectric layer can be avoided, thereby improving the ferroelectricity of the dielectric layer and improving the reliability of the storage unit. Among them, the interface passivation layer can also be made of a material selected according to the material of the conductive film layer, and the interface passivation layer can be made of any material that can play an interface passivation role.

[0070] Second embodiment: Figure 6 The schematic diagram of the structure of the storage unit in the embodiment of the present application is shown as an example. Figure 6 As shown, the structure of the storage unit in the second embodiment is basically similar to that of the storage unit in the aforementioned first embodiment, except that the application scenario of the dielectric layer 30 is different. For example, when the storage unit includes a transistor, the dielectric layer 30 can be applied to the transistor. At this time, the functional layer 20 can be used as the channel of the transistor, the first conductive layer 10 can be used as the gate of the transistor, and the dielectric layer 30 is used as a gate insulating layer to isolate the gate and the channel in the transistor to avoid short circuit between the channel and the gate. Thus, when the dielectric layer 30 has better reliability, the reliability and performance of the transistor will also be improved. Furthermore, when the functional layer 20 is used as the communication of the transistor, it can be made of semiconductor material, which can be selected according to actual needs and is not limited here. Among them, Figure 6 The S in the figure represents the source of the transistor, and the D represents the drain of the transistor.

[0071] It should be understood that the similarities between the structures of the storage unit in the second embodiment and the storage unit in the first embodiment can be found in the first embodiment, and the repeated parts will not be repeated.

[0072] The third embodiment: Figure 7 Schematic diagram of the structure of the storage unit in the embodiment of the present application is exemplarily shown. The structure of the storage unit in the third embodiment is basically similar to that of the storage unit in the first embodiment, except that the storage capacitor is a three-dimensional structure. Figure 7 As shown, the functional layer 20 and the insulating layer 50 may be arranged along a direction perpendicular to the substrate ( Figure 7 The ferroelectric layer 30a, the first doped layer 30b and the second doped layer 30c are alternately stacked in the direction of the surface (i.e., the z direction) of the stack structure m1 (not shown), and then a through hole m2 is dug in the stack structure m1. The through hole m2 penetrates the stack structure m1 along the stacking direction (i.e., the z direction). Then, the dielectric layer 30 and the first conductive layer 10 are sequentially filled in the through hole m2. The dielectric layer 30 is arranged between the stack structure m1 and the first conductive layer 10. At this time, the stacking direction (i.e., the x direction) of the ferroelectric layer 30a, the first doped layer 30b and the second doped layer 30c is perpendicular to the extension direction (i.e., the z direction) of the through hole m2. The storage capacitor formed at this time can be regarded as a storage capacitor with a three-dimensional structure. As a result, the storage unit can be either a two-dimensional structure or a three-dimensional structure, which expands the application range of the storage unit. In addition, the dielectric layer 30, the first conductive layer 10 and the filling layer 60 can fill the through hole m2, and the filling layer 60 is arranged on the side of the first conductive layer 10 away from the dielectric layer 30 (such as Figure 7 The filling layer 60 can be made of insulating material, which can reduce the material used to make the first conductive layer 10. When the material cost of the first conductive layer 10 is high and the material cost of the filling layer 60 is low, the manufacturing cost of the storage unit can be effectively reduced. Alternatively, the dielectric layer 30 and the first conductive layer 10 can fill the through hole m2, that is, the first conductive layer 10 fills the space in the through hole m2 that is not occupied by the dielectric layer 20, which can simplify the manufacturing steps and manufacturing process of the storage unit and improve the manufacturing efficiency.

[0073] It should be understood that the similarities between the structures of the storage unit in the third embodiment and the storage unit in the first embodiment can be found in the first embodiment, and the repeated parts will not be repeated.

[0074] Fourth embodiment: Figure 8 The schematic diagram of the method for manufacturing the storage unit in the embodiment of the present application is exemplarily shown. Figure 8 As shown, taking the dielectric layer applied to the storage capacitor, using hafnium oxide to make the initial film layer, using lanthanum oxide to make the first doping layer, and using titanium oxide to make the second doping layer as an example, the specific manufacturing process of the storage unit may include:

[0075] S1, such as Figure 8 As shown in (a), a W film layer is formed on a substrate by physical vapor deposition as a functional layer, and the functional layer can be regarded as a second conductive layer;

[0076] S2, such as Figure 8 As shown in (b), an atomic layer deposition method is used to stack 10 hafnium oxide layers, 1 lanthanum oxide layer, 10 hafnium oxide layers, 1 titanium oxide layer, and 20 hafnium oxide layers on the functional layer; wherein the 10 hafnium oxide layers or the 20 hafnium oxide layers are used as initial film layers, a lanthanum oxide layer is used as a first doping layer, a titanium oxide layer is used as a second doping layer, and the initial film layer, the first doping layer, and the second doping layer form an initial dielectric layer;

[0077] For example, the deposition rate of the hafnium oxide layer may be, but is not limited to, 1.07 angstroms / time; the deposition rate of the lanthanum oxide layer may be, but is not limited to, 0.46 angstroms / time; and the deposition rate of the titanium oxide layer may be, but is not limited to, 0.50 angstroms / time. Furthermore, the total thickness of the initial film layer, the first doping layer, and the second doping layer of the stacked arrangement obtained by S2 may be, but is not limited to, 80 angstroms.

[0078] Furthermore, by making the uppermost initial film layer in the initial dielectric layer slightly thicker, the doping elements in the first doping layer or the second doping layer can be mainly retained inside the initial dielectric layer, preventing the doping elements from approaching the surface of the initial dielectric layer, thereby avoiding the introduction of additional interface effects and improving the reliability of the storage unit.

[0079] It should be understood that the multilayer hafnium oxide included in the initial film layer is produced continuously, so that the initial film layer can be ensured to have a certain thickness, and the number of hafnium oxide layers included in the initial film layer is not limited to 10 or 20 layers. This is just an example and can be set according to actual conditions and is not limited here.

[0080] S3, heating the initial dielectric layer, cooling it down when the temperature reaches a first preset temperature, and ending the heat treatment process when the temperature reaches a second preset temperature, so that the initial film layer is transformed into a ferroelectric layer to obtain a dielectric layer;

[0081] S4, such as Figure 8 As shown in (c), a TiN film layer is formed on the dielectric layer as the first conductive layer by using physical vapor deposition.

[0082] In this way, the introduction of the first doped layer can help the dielectric layer to exhibit ferroelectric properties, and the introduction of the second doped layer can guide the captured and accumulated electrons to avoid the aggregation and accumulation of electrons in the dielectric layer, thereby avoiding the breakdown of the dielectric layer due to the aggregation and accumulation of electrons, thereby improving the reliability of the dielectric layer and even the storage unit when obtaining a ferroelectric storage unit.

[0083] It should be understood that this embodiment is only based on Figure 8 The above is an example to illustrate the method of manufacturing a memory cell. The stacking order of the initial film layer, the first doping layer and the second doping layer is not limited to Figure 8 The one shown in the figure may also be other stacking orders, which are not shown in this embodiment. As long as the stacking order of ferroelectric layers is provided between different first doping layers, between different second doping layers, and between first doping layers and second doping layers, it is applicable to the embodiments of the present application.

[0084] The fifth embodiment: Fig. 9 The schematic diagram of the method for manufacturing the storage unit in the embodiment of the present application is exemplarily shown. Fig. 9 As shown, the manufacturing method in the fifth embodiment is basically similar to the manufacturing method in the fourth embodiment, except that the introduced doping elements are different. For example, in the fifth embodiment, taking hafnium oxide as the initial film layer, lanthanum oxide and zirconium oxide as the first doping layer, and titanium oxide as the second doping layer as an example, S2 in the fourth embodiment can be adjusted to: Fig. 9 As shown in (b), an atomic layer deposition method is used to stack 5 combined film layers of hafnium oxide and zirconium oxide, 1 lanthanum oxide layer, 5 combined film layers, 1 titanium oxide layer and 10 combined film layers on the functional layer; wherein the hafnium oxide in the combined film layer serves as the initial film layer, the lanthanum oxide and the zirconium oxide in the combined film layer both serve as the first doping layer, and the titanium oxide serves as the second doping layer, and the initial film layer, the first doping layer and the second doping layer form an initial dielectric layer; at this time, it can be understood that zirconium oxide is doped into the initial film layer, and the lanthanum oxide layer and the titanium oxide layer are both doped outside the initial film layer. Alternatively, an atomic layer deposition method is used to stack 5 layers of hafnium oxide, 1 layer of zirconium oxide, 5 layers of hafnium oxide, 1 layer of lanthanum oxide, 5 layers of hafnium oxide, 1 layer of titanium oxide and 10 layers of hafnium oxide on the functional layer; wherein hafnium oxide is used as the initial film layer, lanthanum oxide and zirconium oxide are both used as the first doping layer, titanium oxide is used as the second doping layer, and the initial film layer, the first doping layer and the second doping layer form the initial dielectric layer; at this time, it can be understood that the zirconium oxide, lanthanum oxide layer and titanium oxide layer are all doped outside the initial film layer. Among them, the deposition rate of the zirconium oxide layer can be but is not limited to 0.93 angstroms / time, and the deposition rates of the hafnium oxide, lanthanum oxide layer and titanium oxide layer can refer to the fourth embodiment above, and the repeated parts will not be repeated.

[0085] It should be understood that the similarities between the manufacturing method in the fifth embodiment and the manufacturing method in the aforementioned fourth embodiment can be referred to the aforementioned fourth embodiment, and the repeated parts will not be repeated.

[0086] Sixth embodiment: Fig.10The schematic diagram of the method for manufacturing the storage unit in the embodiment of the present application is exemplarily shown. Fig.10 As shown, the manufacturing method in the sixth embodiment is basically similar to the manufacturing method in the fourth embodiment, and the differences include:

[0087] (1) A step k1 is added between S1 and S2 in the fourth embodiment. The step k1 may specifically include: Fig.10 As shown in (b), an auxiliary layer having auxiliary functions is formed on the functional layer. The auxiliary functions of the film layer may be, but are not limited to, adhesion and interface passivation.

[0088] (2) Step k2 is added between S3 and S4 in the fourth embodiment. Step k2 may specifically include: Fig.10 As shown in (d) in the figure, an auxiliary layer with auxiliary functions is formed on the dielectric layer. The auxiliary functions of the film layer may include but are not limited to adhesion and interface passivation.

[0089] In this way, the reliability of the memory cell can be further improved by using the film layer with auxiliary functions.

[0090] It should be understood that the similarities between the manufacturing method in the sixth embodiment and the manufacturing method in the aforementioned fourth embodiment can be referred to the aforementioned fourth embodiment, and the repeated parts will not be repeated.

[0091] Seventh embodiment: Fig.11 The schematic diagram of the method for manufacturing the storage unit in the embodiment of the present application is exemplarily shown. Fig.11 As shown, the manufacturing method in the seventh embodiment is basically similar to the manufacturing method in the fourth embodiment, and the differences include:

[0092] (1) Adjust the above S1 to: Fig.11 As shown in (a), a chemical vapor deposition method is used to alternately deposit metal W film layers and insulating layers on a substrate to obtain a stacked structure m1, and the metal W film layer is used as a functional layer; wherein the stacked structure m1 includes multiple functional layers and multiple insulating layers;

[0093] (2) Add step k3 between S1 and S2 above. Step k3 may include: Fig.11 As shown in (b), the stacked structure m1 is opened by photolithography and high aspect ratio dry etching to obtain a columnar through hole T with a diameter of about 50 nm, and the through hole T penetrates the stacked structure m1 along the stacking direction;

[0094] (3) Each film layer formed in the above S2 to S4 is made in the through hole T, such as Fig.11 As shown in (c) and (d);

[0095] (4) If the TiN film layer formed in the above S4 does not fill the remaining space in the through hole T, it is necessary to continue to form a filling layer after the TiN film layer is formed, and fill the unoccupied space in the through hole T with the filling layer, which is not shown in the figure; the manufacturing process of the filling layer includes: using chemical vapor deposition method, using insulating material, and depositing an insulating layer on the TiN film layer to fill the through hole T; wherein the insulating material and the manufacturing material of the insulating layer can be the same or different.

[0096] In this way, the storage capacitor obtained is a three-dimensional structure, which expands the application range of the ferroelectric memory cell.

[0097] It should be understood that the similarities between the manufacturing method in the seventh embodiment and the manufacturing method in the aforementioned fourth embodiment can be referred to the aforementioned fourth embodiment, and the repeated parts will not be repeated.

[0098] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A storage unit, characterized in that: include: A first conductive layer, a functional layer, and a dielectric layer disposed between the first conductive layer and the functional layer, wherein the dielectric layer comprises: a ferroelectric layer, a first doped layer, and a second doped layer that are stacked; The Helmholtz free energy of the metal elements in the first doping layer is lower than the Helmholtz free energy of the metal elements in the ferroelectric layer, and the Helmholtz free energy of the metal elements in the second doping layer is not lower than the Helmholtz free energy of the metal elements in the ferroelectric layer.

2. The storage unit according to claim 1, characterized in that The difference between the atomic radius of the metal element in the second doping layer and the metal element in the ferroelectric layer is smaller than a threshold value, and / or the valence state of the metal element in the second doping layer is not lower than the valence state of the metal element in the ferroelectric layer.

3. The storage unit according to claim 1 or 2, characterized in that: The second doped layer is provided with multiple layers, and the ferroelectric layer is provided between two adjacent second doped layers.

4. The storage unit according to any one of claims 1 to 3, characterized in that: The second doping layer includes at least one of titanium and niobium.

5. The storage unit according to any one of claims 1 to 4, characterized in that: The difference in atomic radius between the metal element in the first doping layer and the metal element in the ferroelectric layer is not less than the threshold, and / or the valence state of the metal element in the first doping layer is lower than the valence state of the metal element in the ferroelectric layer.

6. The storage unit according to any one of claims 1 to 5, characterized in that: The first doped layer is provided with multiple layers, and the ferroelectric layer is provided between two adjacent first doped layers.

7. The storage unit according to any one of claims 1 to 6, characterized in that: The first doping layer includes at least one of lanthanum, cerium, molybdenum, zirconium, silicon, gadolinium, and yttrium.

8. The storage unit according to any one of claims 1 to 7, characterized in that: The ferroelectric layer is disposed between the first doping layer and the second doping layer.

9. The storage unit according to any one of claims 1 to 8, characterized in that: The storage unit includes a storage capacitor, and the functional layer is a second conductive layer.

10. The storage unit according to any one of claims 1 to 8, characterized in that: The memory cell includes a transistor, the functional layer is a channel in the transistor, and the first conductive layer is a gate in the transistor.

11. The storage unit according to any one of claims 1 to 10, characterized in that: The ferroelectric layer is made of a material including hafnium oxide.

12. A method for manufacturing a storage unit according to any one of claims 1 to 11, characterized in that: include: Forming a functional layer; A ferroelectric layer, a first doped layer and a second doped layer are stacked on the functional layer, the ferroelectric layer, the first doped layer and the second doped layer constitute a dielectric layer, the Helmholtz free energy of the metal element in the first doped layer is lower than the Helmholtz free energy of the metal element in the ferroelectric layer; the Helmholtz free energy of the metal element in the second doped layer is not lower than the Helmholtz free energy of the metal element in the ferroelectric layer; A first conductive layer is formed on the dielectric layer.

13. The method according to claim 12, characterized in that A ferroelectric layer, a first doping layer and a second doping layer are stacked on the functional layer, comprising: stacking an initial film layer, the first doping layer and the second doping layer on the functional layer; The initial film layer, the first doping layer and the second doping layer are thermally treated so that the initial film layer is transformed into the ferroelectric layer.

14. A memory, characterized in that: include: A storage array and a controller coupled to the storage array, wherein the storage array comprises a plurality of storage units according to any one of claims 1 to 11, and the plurality of storage units are deployed in an array manner; The storage array is used to store data; The controller is used to write data into the storage array or read data from the storage array.

15. An electronic device, characterized in that: include: A circuit board and a memory as claimed in claim 14, wherein the memory is arranged on the circuit board.

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