A silicon carbide MOSFET device and a method for preparing the same

Abstract

The present invention provides a silicon carbide MOSFET device and a preparation method thereof, and relates to the field of semiconductor technology. The device comprises: a source metal, a silicon carbide structure, an N-type second silicon carbide epitaxial layer, an interlayer insulating medium, a first P-type doped region, a second P-type doped region, a first N-type doped region, an N+ type first source region, a second N-type doped region, a P-type body region, and an N+ type second source region; a source trench penetrates the N-type second silicon carbide epitaxial layer to the first P-type doped region and the second P-type doped region, and is surrounded by a P-type source region on the outside, and has a source metal on the inside; a gate oxide layer is provided in the gate trench and polysilicon is deposited as a gate, the bottom of the gate oxide layer contacts the periodically arranged first P-type doped region, the first N-type doped region, and the N+ type first source region, and the bottom of the gate oxide layer contacts the periodically arranged second N-type doped region. The gate oxide layer can be protected, the electric field strength of the gate oxide layer at the corner can be reduced, and the on-resistance of the silicon carbide MOSFET device can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) device and a preparation method thereof. Background Art

[0002] As a wide bandgap semiconductor material, silicon carbide has the advantages of high critical breakdown electric field strength, high saturated electron mobility, high thermal conductivity, etc., and has great material advantages in the field of power electronic devices. Compared with the planar vertical double-diffused metal-oxide-semiconductor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, the trench silicon carbide MOSFET has a conductive channel located in the vertical direction, eliminating the parasitic junction field-effect transistor (JFET) resistance of VDMOS, reducing the cell size and increasing the cell density, thereby significantly increasing the current density and greatly reducing the on-resistance of the device.

[0003] At present, asymmetric trench MOSFET devices and double trench MOSFET devices are commonly used. One side of the gate trench of the asymmetric trench MOSFET device is used for conduction, and the other side is used to make a P+ shielding area. However, when the asymmetric trench MOSFET device is turned on, the P+ shielding area and the N-type epitaxial layer will form a depletion region, which greatly reduces the flow path of the electron current and increases the on-resistance of the MOSFET device; the double trench MOSFET device introduces a gate trench and a source trench. However, there is still a large gate oxide layer electric field strength in the center of the gate trench, and the electric field protection of the gate oxide layer is insufficient, especially the gate oxide layer at the corner is easily broken down by the electric field. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a silicon carbide MOSFET device and a preparation method thereof, so as to solve the problem that the on-resistance of the MOSFET device is increased after the gate oxide protection structure is introduced, and the electric field protection of the gate oxide layer is insufficient, especially the gate oxide layer at the corner is easily broken down by the electric field.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a silicon carbide MOSFET device, the silicon carbide MOSFET device comprising a silicon carbide structure, an N-type second silicon carbide epitaxial layer and an interlayer insulating medium arranged in sequence from bottom to top;

[0007] The top region of the silicon carbide structure is provided with a first periodic structure and a second periodic structure arranged periodically, the first periodic structure includes a first N-type doping region, an N+ type first source region and a first P-type doping region, and the second periodic structure includes a second N-type doping region and a second P-type doping region;

[0008] A P-type body region is formed in a middle top region of the N-type second silicon carbide epitaxial layer, and an N+ type second source region is formed in a middle top region of the P-type body region;

[0009] A source trench is formed in the regions on both sides of the N-type second silicon carbide epitaxial layer, the source trench penetrates the lower end of the N-type second silicon carbide epitaxial layer and extends to the first P-type doping region and the second P-type doping region, a P-type source region is arranged outside the source trench, and a source metal is arranged inside the source trench;

[0010] The gate trench extends downward from the middle area of ​​the upper surface of the N+ type second source region, and successively penetrates the N+ type second source region, the P type body region, the N- type second silicon carbide epitaxial layer to the first P type doping region and the second P type doping region. A gate oxide layer is arranged inside the gate trench, and polysilicon is deposited as a gate. The lower surface of the gate oxide layer contacts part of the first P type doping region, part of the first N type doping region and part of the N+ type first source region, or the lower surface of the gate oxide layer contacts part of the second N type doping region.

[0011] A second aspect of the present invention provides a method for preparing a silicon carbide MOSFET device, comprising:

[0012] Selecting an N+ type silicon carbide substrate, and depositing an N- type first silicon carbide epitaxial layer on the N+ type silicon carbide substrate;

[0013] Depositing an oxide layer on the N-type first silicon carbide epitaxial layer, and forming P-type doping regions on both sides of the top layer region of the N-type first silicon carbide epitaxial layer by means of photolithography, etching and ion implantation, wherein the P-type doping regions include a first P-type doping region and a second P-type doping region;

[0014] A first N-type doping region is formed between the first P-type doping regions on both sides, an N+ type first source region is formed in the first P-type doping regions on both sides to obtain a first current structure, and a second N-type doping region is formed between the second P-type doping regions on both sides to obtain a second current structure, wherein the N+ type first source regions are arranged at intervals on both sides of the first N-type doping region;

[0015] growing an N-type second silicon carbide epitaxial layer on the upper surfaces of the first current structure and the second current structure;

[0016] Depositing an oxide layer on the N-type second silicon carbide epitaxial layer, generating P-type body regions on both sides of the top region of the N-type second silicon carbide epitaxial layer by means of photolithography, etching and multiple ion implantation, and forming N+ type second source regions in the edge regions of the top region of the P-type body regions on both sides, wherein the edge regions are regions close to the center of the N-type second silicon carbide epitaxial layer;

[0017] An oxide layer is deposited on the N-type second silicon carbide epitaxial layer, and source trenches are etched in the two side regions of the N-type second silicon carbide epitaxial layer through photolithography and etching processes, wherein the source trenches penetrate the lower end of the N-type second silicon carbide epitaxial layer and extend into the first P-type doping region and the second P-type doping region;

[0018] Forming P-type source regions on the outside of the source trenches on both sides by ion implantation, and the P-type source region on one side of each source trench overlaps with the N+ type first source region, and filling the source trench with silicon dioxide by chemical vapor deposition, and one side of each source trench is a side close to the first N-type doping region;

[0019] A gate trench is etched at a position between two source trenches in the N-type second silicon carbide epitaxial layer by photolithography and etching processes, a gate oxide layer is grown on the inner wall of the gate trench, so that the lower surface of the gate oxide layer contacts part of the first P-type doping region, part of the first N-type doping region and part of the N+ type first source region, the lower surface of the gate oxide layer contacts part of the second N-type doping region, and polysilicon is deposited in the gate trench as a gate to obtain a third current structure; the gate trench extends downward from the middle area of ​​the upper surface of the N+ type second source region, and sequentially penetrates the N+ type second source region, the P-type body region, the N-type second silicon carbide epitaxial layer to the first P-type doping region and the second P-type doping region;

[0020] Depositing an interlayer insulating dielectric on the upper surface of the third current structure, removing the interlayer insulating dielectric above the silicon dioxide, a portion of the P-type body region and a portion of the N+-type second source region, and removing the silicon dioxide inside the source trench;

[0021] A source metal is formed inside the source trench and on the interlayer insulating medium, and a drain metal is formed on the lower surface of the N+ type silicon carbide substrate.

[0022] Compared with the prior art, the present invention provides a silicon carbide MOSFET device and a preparation method thereof, wherein the silicon carbide MOSFET device comprises a silicon carbide structure, an N-type second silicon carbide epitaxial layer and an interlayer insulating medium arranged in sequence from bottom to top; a first periodic structure and a second periodic structure arranged periodically are arranged in the top region of the silicon carbide structure, the first periodic structure comprises a first N-type doping region, an N+ type first source region and a first P-type doping region, and the second periodic structure comprises a second N-type doping region and a second P-type doping region; a P-type body region is formed in the middle top region of the N-type second silicon carbide epitaxial layer, and an N+ type second source region is formed in the middle top region of the P-type body region; a source trench is formed in the N-type second silicon carbide epitaxial layer, and a source trench is formed in the N-type second silicon carbide epitaxial layer. In the areas on both sides of the epitaxial layer, a source trench penetrates the lower end of the N-type second silicon carbide epitaxial layer and extends to the first P-type doping area and the second P-type doping area, a P-type source area is arranged on the outside of the source trench, and a source metal is arranged inside the source trench; a gate trench extends downward from the middle area of ​​the upper surface of the N+ type second source area, and successively penetrates the N+ type second source area, the P-type body area, the N-type second silicon carbide epitaxial layer to the first P-type doping area and the second P-type doping area, a gate oxide layer is arranged inside the gate trench, and polysilicon is deposited as a gate, and the lower surface of the gate oxide layer contacts part of the first P-type doping area, part of the first N-type doping area and part of the N+ type first source area, or the lower surface of the gate oxide layer contacts part of the second N-type doping area. In this way, the gate oxide layer of the gate trench can be protected by depleting the first P-type doping region, the first N-type doping region and the N-type first silicon carbide epitaxial layer below the gate oxide layer, or the gate oxide layer of the gate trench can be protected by depleting the second P-type doping region, the second N-type doping region and the N-type first silicon carbide epitaxial layer, thereby reducing the electric field strength of the gate oxide layer at the corner; by introducing the periodically changing N+ type first source region and the first P-type doping region, the lateral current path of the silicon carbide MOSFET device is increased, the current density is increased, and the on-resistance of the MOSFET device is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0024] Figure 1 The schematic diagram of the structure of a silicon carbide MOSFET device is shown schematically;

[0025] Figure 2 The cross-sectional structure diagram of a silicon carbide MOSFET device cut along the AA direction is schematically shown;

[0026] Figure 3The cross-sectional structure diagram of a silicon carbide MOSFET device cut along the AB direction is schematically shown;

[0027] Figure 4 The figure schematically shows the current path of a silicon carbide MOSFET device cut along the AA direction in the forward conduction state;

[0028] Figure 5 The current path diagram of a silicon carbide MOSFET device cut along the AB direction in a forward conduction state is schematically shown;

[0029] Figure 6 Schematically showing a top view of the periodic arrangement of the first periodic structure and the second periodic structure;

[0030] Figure 7 A flow chart schematically shows a method for preparing a silicon carbide MOSFET device;

[0031] Figure 8 The cross-sectional structure diagram of depositing the N-type first silicon carbide epitaxial layer is schematically shown;

[0032] Fig. 9 The cross-sectional structure diagram of the current device after forming the P-type doping region is schematically shown;

[0033] Fig.10 The schematic diagram of the cross-sectional structure of the current device after forming the first N-type doping region and the N+ type first source region is shown schematically;

[0034] Fig.11 The cross-sectional structure diagram of the current device after forming the N-type second silicon carbide epitaxial layer is schematically shown;

[0035] Fig.12 The cross-sectional structure diagram of forming a P-type body region and an N+-type second source region is schematically shown;

[0036] Fig.13 The cross-sectional structure diagram of forming a source trench is schematically shown;

[0037] Fig.14 The cross-sectional structure diagram of the source trench filled with silicon dioxide is schematically shown;

[0038] Fig.15 The cross-sectional structure diagram of forming a gate trench is schematically shown;

[0039] Fig.16 The cross-sectional structure diagram of forming a gate oxide layer and polysilicon is schematically shown;

[0040] Fig.17The cross-sectional structure diagram of forming an interlayer insulating medium is schematically shown;

[0041] Fig.18 The cross-sectional structure diagram of etching a source contact hole is schematically shown;

[0042] Fig.19 The cross-sectional structure diagram of forming source metal and drain metal is schematically shown.

[0043] Description of reference numerals:

[0044] 1. Silicon carbide structure; 101. N+ type silicon carbide substrate; 102. N-type first silicon carbide epitaxial layer; 2. First periodic structure; 201. First N-type doping region; 202. N+ type first source region; 203. First P-type doping region; 3. Second periodic structure; 301. Second N-type doping region; 302. Second P-type doping region; 4. N-type second silicon carbide epitaxial layer; 5. P-type body region; 6. N+ type second source region; 7. Source trench; 8. P-type source region; 9. Gate trench; 10. Gate oxide layer; 11. Polysilicon; 12. Interlayer insulating medium; 13. Source metal; 14. Drain metal. DETAILED DESCRIPTION

[0045] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0046] A silicon carbide MOSFET device in an embodiment of the present invention is described in detail below.

[0047] See also Figure 1 As shown, Figure 1 The structure diagram of a silicon carbide MOSFET device is schematically shown. The embodiment of the present invention provides a silicon carbide MOSFET device, comprising a silicon carbide structure 1, an N-type second silicon carbide epitaxial layer 4 and an interlayer insulating medium 12 arranged in sequence from bottom to top;

[0048] The top region of the silicon carbide structure 1 is provided with a first periodic structure 2 and a second periodic structure 3 having a second N-type doping region 301 arranged periodically, the first periodic structure 2 including a first N-type doping region 201, an N+ type first source region 202 and a first P-type doping region 203, and the second periodic structure 3 including a second N-type doping region 301 and a second P-type doping region 302;

[0049] A P-type body region 5 is formed in the middle top region of the N-type second silicon carbide epitaxial layer 4, and an N+-type second source region 6 is formed in the middle top region of the P-type body region 5;

[0050] A source trench 7 is formed in the regions on both sides of the N-type second silicon carbide epitaxial layer 4. The source trench 7 penetrates the lower end of the N-type second silicon carbide epitaxial layer 4 and extends to the first P-type doping region 203 and the second P-type doping region 302. A P-type source region 8 is disposed outside the source trench 7. A source metal 13 is disposed inside the source trench 7.

[0051] The gate trench 9 extends downward from the middle area of ​​the upper surface of the N+ type second source region 6, and successively penetrates the N+ type second source region 6, the P type body region 5, the N- type second silicon carbide epitaxial layer 4 to the first P type doping region 203 and the second P type doping region 302. A gate oxide layer 10 is arranged inside the gate trench 9, and polysilicon 11 is deposited as a gate. The lower surface of the gate oxide layer 10 contacts part of the first P type doping region 203, part of the first N type doping region 201 and part of the N+ type first source region 202, or the lower surface of the gate oxide layer 10 contacts part of the second N type doping region 301.

[0052] Specifically, the first N-type doping region 201 and the N+ type first source region 202 in the first periodic structure 2 are arranged periodically, and the second N-type doping region 301 in the second periodic structure 3 is arranged periodically. The first N-type doping region 201 and the second N-type doping region 301 are formed in one piece.

[0053] In the embodiment of the present invention, by introducing a periodically changing first P-type doping region 203 and a first N-type doping region 201, or introducing a periodically changing second P-type doping region 302 and a second N-type doping region 301, under the gate oxide layer 10 in the gate trench 9, when the silicon carbide MOSFET device is in a reverse withstand voltage state, the first P-type doping region 203 and the first N-type doping region 201 will be mutually depleted, or the second P-type doping region 302 and the second N-type doping region 301 will be mutually depleted, thereby reducing the electric field strength of the gate oxide layer 10, thereby protecting the gate oxide layer 10. By introducing the periodically changing N+ type first source region 202 and the first P-type doping region 203, the lateral current path of the silicon carbide MOSFET device is increased, and the unit current density of the silicon carbide MOSFET device is increased.

[0054] In this embodiment, the silicon carbide structure 1 includes an N+ type silicon carbide substrate 101 and an N-type first silicon carbide epitaxial layer 102 arranged in sequence from bottom to top; the silicon carbide MOSFET device also includes a drain metal 14, which is arranged on the lower surface of the N+ type silicon carbide substrate 101.

[0055] In this embodiment, the first P-type doping region 203 and the second P-type doping region 302 are both arranged in the top region of the N-type first silicon carbide epitaxial layer 102, the first N-type doping region 201 is arranged in the middle region of the first P-type doping region 203, and the N+ type first source region 202 is arranged at intervals in the two side regions of the first N-type doping region 201; the second N-type doping region 301 is arranged in the middle region of the second P-type doping region 302, and the length of the first N-type doping region 201 is less than the length of the second N-type doping region 301.

[0056] Specifically, the first N-type doping region 201 is disposed in the upper middle portion of the middle region of the first P-type doping region 203 ; portions of the gate oxide layer 10 on both sides of the gate trench 9 are in contact with the N+ type second source region 6 away from both sides of the P-type source region 8 .

[0057] In this embodiment, the distance from the upper surface of the N+ type first source region 202 to the upper surface of the first P type doping region 203 is 0.4-0.7 um.

[0058] Specifically, setting the distance from the upper surface of the N+ type first source region 202 to the upper surface of the first P-type doped region 203 to 0.4~0.7um can prevent the N+ type first source region 202 from penetrating with the drain, so that the current path of the silicon carbide MOSFET device including the first periodic structure 2 is not interfered by the current path of the silicon carbide MOSFET device including the second periodic structure 3.

[0059] In this embodiment, part of the P-type source region 8 is close to one side of the first N-type doping region 201, overlaps with one side of the N+-type first source region 202 away from the first N-type doping region 201 and contacts the source metal 13, or part of the P-type source region 8 is arranged alternately with the second N-type doping region 301; both sides of the P-type body region 5 away from the polysilicon 11 are in contact with the P-type source region 8;

[0060] The source metal 13 is also disposed on the interlayer insulating dielectric 12 , and contacts the upper surfaces of a portion of the P-type body region 5 and a portion of the N+-type second source region 6 through the gaps of the interlayer insulating dielectric 12 .

[0061] In this embodiment, the depth of the source trench 7 is less than or equal to the sum of the depths of the N-type second silicon carbide epitaxial layer 4 and the first P-type doping region 203 , and the depth of the source trench 7 is less than or equal to the sum of the depths of the N-type second silicon carbide epitaxial layer 4 and the second P-type doping region 302 .

[0062] In this embodiment, the length of the first N-type doping region 201 is equal to the width of the second N-type doping region 301 .

[0063] In this embodiment, the doping ions of the first P-type doping region 203 and the second P-type doping region 302 both include aluminum ions, and the doping concentration is 3e16 cm-3 ~6e16cm -3 .

[0064] In this embodiment, the doping ions of the first N-type doping region 201 and the second N-type doping region 301 both include nitrogen ions, and the doping concentration is 1.2e15 cm -3 ~6.5e15cm -3 .

[0065] Specifically, Figure 2 The cross-sectional structure diagram of a silicon carbide MOSFET device cut along the AA direction is schematically shown. In the silicon carbide MOSFET device cut along the AA direction, the lower surface of the gate oxide layer 10 has an N+ type first source region 202, and the silicon carbide MOSFET device has a lateral channel, wherein the AA direction specifically refers to the horizontal cutting direction along the silicon carbide MOSFET device, where there are a first N-type doped region 201 and a first P-type doped region 203 below the lower surface of the gate oxide layer 10. Figure 3 The cross-sectional structure diagram of a silicon carbide MOSFET device cut along the AB direction is schematically shown. In the silicon carbide MOSFET device cut along the AB direction, there is no N+ type first source region 202 on the lower surface of the gate oxide layer 10, and the silicon carbide MOSFET device has no lateral channel, wherein the AB direction specifically refers to the horizontal cutting direction along the silicon carbide MOSFET device, where there are the second N-type doping region 301 and the second P-type doping region 302 below the lower surface of the gate oxide layer 10.

[0066] The first P-type doping region 203 and the first N-type doping region 201 in the silicon carbide MOSFET device cut along the AA direction protect the gate oxide layer 10; the second P-type doping region 302 and the second N-type doping region 301 in the silicon carbide MOSFET device cut along the AB direction protect the gate oxide layer 10.

[0067] The corners of the gate oxide layer 10 in the gate trench 9 are protected by the lateral and longitudinal P-type doped regions.

[0068] The breakdown electric field strength of silicon carbide material is 2.5MV / cm. The biggest problem with trench silicon carbide at present is that when the device reaches the breakdown electric field strength, the electric field strength of the unprotected gate oxide layer 10 can reach about 7.5MV / cm, while the safe electric field strength of the gate oxide layer 10 for long-term operation must be below 3MV / cm. The silicon carbide MOSFET device proposed in the embodiment of the present invention has the effect of shielding and protecting the gate oxide layer 10. When the silicon carbide MOSFET device is in a reverse withstand voltage state, the first P-type doped region 203, the first N-type doped region 201 and the N-type first silicon carbide epitaxial layer 102 are specifically used as gate oxide protection structures. The lateral and longitudinal gate oxide protection structures are jointly depleted to protect the gate oxide layer 10 of the gate trench 9, thereby reducing the electric field strength at the gate corner. Specifically, Figure 1 As shown, the gate trench 9 spans the first P-type doping region 203 and the first N-type doping region 201. The silicon carbide MOSFET device cut along the AA direction is depleted through the first P-type doping region 203, the first N-type doping region 201 and the N-type first silicon carbide epitaxial layer 102 on the left and right sides below the gate to protect the gate oxide layer 10 of the gate trench 9. The silicon carbide MOSFET device cut along the AB direction is depleted through the second P-type doping region 302, the second N-type doping region 301 and the N-type first silicon carbide epitaxial layer 102 in front and behind to protect the gate oxide layer 10 of the gate trench 9.

[0069] While solving the problem of too high electric field strength at the corner of the gate oxide layer 10, the embodiment of the present invention increases the design of the current flow path of the silicon carbide MOSFET device, specifically designs a periodically changing transverse current path and a longitudinal current path. The transverse current path is the current path of the silicon carbide MOSFET device cut along the AA direction in the forward conduction state, and the longitudinal current path is the current path of the silicon carbide MOSFET device cut along the AB direction in the forward conduction state. The transverse current path and the longitudinal current path can effectively reduce the on-resistance of the silicon carbide MOSFET device by increasing the current density of the silicon carbide MOSFET device, and can improve the current path of the chip containing the silicon carbide MOSFET device.

[0070] When working, the silicon carbide MOSFET device has two current paths, namely the first current path and the second current path, wherein the first current path is a lateral current path and the second current path is a longitudinal current path. These two current paths are two conduction channels. Specifically, Figure 4The schematic diagram of the current path of the silicon carbide MOSFET device cut along the AA direction in the forward conduction state is schematically shown. For the first current path, the current flows from the drain metal 14 through the N+ type silicon carbide substrate 101 and the N-type first silicon carbide epitaxial layer 102 in sequence, and then the current goes to the left and right sides. The first current path is blocked by the first P-type doping regions 203 on the left and right sides. When a forward voltage of 15~20V is applied to the polysilicon 11, a very thin channel (about 50nm) is formed between the gate oxide layer 10 and the first P-type doping region 203. After the current flows through the channel, due to the special first N-type doping region 201 of the present invention being placed in the first P-type doping region 203, the current can only flow to the N+ type first source region 202 on the left and right sides, and then the current enters the source metal 13.

[0071] Figure 5 The figure schematically shows the current path of the silicon carbide MOSFET device cut along the AB direction in the forward conduction state. For the second current path, the current flows from the drain metal 14 through the N+ type silicon carbide substrate 101, the N-type first silicon carbide epitaxial layer 102, the second N-type doped region 301, and the N-type second silicon carbide epitaxial layer 4 in sequence. When the current flows through the P-type body region 5, it is blocked by the P-type body region 5; when a forward voltage of 15~20V is applied to the polysilicon 11, a very thin channel (about 50nm) will be formed between the gate oxide layer 10 and the P-type body region 5. At this time, the current will pass through the channel between the gate oxide layer 10 and the P-type body region 5, flow to the N+ type second source region 6, and then flow to the source metal 13.

[0072] Figure 6 The schematic diagram shows a top view of the periodic arrangement of the first periodic structure 2 and the second periodic structure 3, see Figure 6 As shown, the first periodic structure 2 is periodically arranged in the first P-type doping region 203, the second periodic structure 3 is periodically arranged in the second P-type doping region 302, the first N-type doping region 201 in the first periodic structure 2 and the second N-type doping region 301 in the second periodic structure 3 are periodically arranged, wherein the length C1 of the first N-type doping region 201 is equal to the width C2 of the second N-type doping region 301, and the length C1 of the first N-type doping region 201 and the width C2 of the second N-type doping region 301 are both 1.5~3um.

[0073] Based on the above Figure 1It can be seen from the implementation method that the silicon carbide MOSFET device of the embodiment of the present invention includes a silicon carbide structure 1, an N-type second silicon carbide epitaxial layer 4 and an interlayer insulating medium 12 arranged in sequence from bottom to top; the top region of the silicon carbide structure 1 is provided with a periodically arranged first periodic structure 2 and a second periodic structure 3, the first periodic structure 2 includes a first N-type doping region 201, an N+ type first source region 202 and a first P-type doping region 203, and the second periodic structure 3 includes a second N-type doping region 301 and a second P-type doping region 302; a P-type body region 5 is formed in the middle top region of the N-type second silicon carbide epitaxial layer 4, and an N+ type second source region 6 is formed in the middle top region of the P-type body region 5; a source trench 7 is formed in the two side regions of the N-type second silicon carbide epitaxial layer 4, and the source trench 7 penetrates The lower end of the N-type second silicon carbide epitaxial layer 4 extends to the first P-type doping region 203 and the second P-type doping region 302, a P-type source region 8 is arranged on the outer side of the source trench 7, and a source metal 13 is arranged inside the source trench 7; the gate trench 9 extends downward from the middle area of ​​the upper surface of the N+ type second source region 6, and successively penetrates the N+ type second source region 6, the P-type body region 5, the N-type second silicon carbide epitaxial layer 4 to the first P-type doping region 203 and the second P-type doping region 302, a gate oxide layer 10 is arranged inside the gate trench 9, and polysilicon 11 is deposited as a gate, the lower surface of the gate oxide layer 10 is in contact with part of the first P-type doping region 203, part of the first N-type doping region 201 and part of the N+ type first source region 202, or, the lower surface of the gate oxide layer 10 is in contact with part of the second N-type doping region 301. In this way, the gate oxide layer 10 of the gate trench 9 can be depleted by the first P-type doping region 203, the first N-type doping region 201 and the N-type first silicon carbide epitaxial layer 102 below the gate oxide layer 10, or the gate oxide layer 10 of the gate trench 9 can be depleted by the second P-type doping region 302, the second N-type doping region 301 and the N-type first silicon carbide epitaxial layer 102, thereby reducing the electric field strength of the gate oxide layer 10 at the corner; by introducing the periodically changing N+ type first source region 202 and the first P-type doping region 203, the lateral current path of the silicon carbide MOSFET device is increased, the current density is increased, and the on-resistance of the MOSFET device is reduced.

[0074] Figure 7 The method for preparing the silicon carbide MOSFET device in the embodiment of the present invention is schematically shown. Figure 7 As shown, the method for preparing the silicon carbide MOSFET device may include:

[0075] S701 , selecting an N+ type silicon carbide substrate 101 , and depositing an N− type first silicon carbide epitaxial layer 102 on the N+ type silicon carbide substrate 101 .

[0076] Specifically, Figure 8The cross-sectional structure diagram of depositing the N-type first silicon carbide epitaxial layer 102 is schematically shown. The N+ type silicon carbide substrate 101 is selected as the high-concentration N-type drain. The material of the N+ type silicon carbide substrate 101 can be 4H-SiC, 6H-SiC or 3C-SiC, and the most commonly used material is 4H-SiC. Then, the N-type first silicon carbide epitaxial layer 102 is epitaxially grown on the N+ type silicon carbide substrate 101, and then the epitaxial wafer is cleaned to obtain the following Figure 8 The device structure shown is a device structure in which an N-type first silicon carbide epitaxial layer 102 is deposited.

[0077] S702 , depositing an oxide layer on the N-type first silicon carbide epitaxial layer 102 , and forming P-type doped regions on both sides of the top layer region of the N-type first silicon carbide epitaxial layer 102 by means of photolithography, etching and ion implantation.

[0078] The P-type doping region includes a first P-type doping region 203 and a second P-type doping region 302 .

[0079] Specifically, Fig. 9 The schematic diagram of the cross-sectional structure of the current device after forming the P-type doping region is shown schematically. An oxide layer is deposited on the N-type first silicon carbide epitaxial layer 102. An ion implantation window is etched through a photolithography process and an etching process. Aluminum ions are selectively implanted in the ion implantation window to form a first P-type doping region 203 and a second P-type doping region 302. The energy of the ion implantation is 50-400 KeV. The deposited oxide layer is removed to obtain Fig. 9 The device structure for forming a P-type doped region is shown.

[0080] S703. Form a first N-type doping region 201 between the first P-type doping regions 203 on both sides, form an N+ type first source region 202 in the first P-type doping regions 203 on both sides to obtain a first current structure, and form a second N-type doping region 301 between the second P-type doping regions 302 on both sides to obtain a second current structure.

[0081] The N+ type first source regions 202 are arranged at intervals on both sides of the first N type doping region 201 .

[0082] Specifically, Fig.10The schematic diagram of the cross-sectional structure of the current device after forming the first N-type doping region 201 and the N+ type first source region 202 is schematically shown. An oxide layer is deposited on the N-type first silicon carbide epitaxial layer 102, and an ion implantation window is etched out through a photolithography process and an etching process. Nitrogen ions are selectively implanted through the ion implantation window to form the first N-type doping region 201. The energy of the ion implantation is 100-300KeV. After removing the deposited oxide layer, the oxide layer is re-deposited, and an ion implantation window is etched out through a photolithography process and an etching process. Nitrogen ions are selectively implanted through the ion implantation window to form the N+ type first source region 202. Fig.10 The first current structure shown includes a first N-type doping region 201 and an N+ type first source region 202 .

[0083] S704 , growing an N-type second silicon carbide epitaxial layer 4 on the upper surfaces of the first current structure and the second current structure.

[0084] Specifically, Fig.11 The schematic diagram of the cross-sectional structure of the current device after forming the N-type second silicon carbide epitaxial layer 4 is schematically shown. The N-type second silicon carbide epitaxial layer 4 is grown on the first current structure to obtain the following Fig.11 The device structure shown is one in which an N-type second silicon carbide epitaxial layer 4 is formed.

[0085] S705. Deposit an oxide layer on the N-type second silicon carbide epitaxial layer 4, generate P-type body regions 5 on both sides of the top layer region of the N-type second silicon carbide epitaxial layer 4 through photolithography, etching and multiple ion implantation, and form N+ type second source regions 6 in the edge regions of the top layer regions of the P-type body regions 5 on both sides.

[0086] The edge region is a region close to the center of the N-type second silicon carbide epitaxial layer 4 .

[0087] Specifically, four ion implantations are required to generate the P-type body region 5. The conditions for the first ion implantation are: an implantation dose of 3e13~5e13, and an implantation energy of 500 KeV; the conditions for the second ion implantation are: an implantation dose of 3e13~5e13, and an implantation energy of 300KeV; the conditions for the third ion implantation are: an implantation dose of 8.4e13~9e13, and an implantation energy of 200KeV; the conditions for the fourth ion implantation are: an implantation dose of 6e14~1e15, and an implantation energy of 80KeV.

[0088] Two ion implantations are required to form the N+ type second source region 6. The conditions for the first ion implantation are: an implantation dose of 1e14~3e14 and an implantation energy of 250KeV; the conditions for the second ion implantation are: an implantation dose of 5e14~6e14 and an implantation energy of 150KeV.

[0089] Fig.12 The cross-sectional structure diagram of forming the P-type body region 5 and the N+ type second source region 6 is schematically shown. An oxide layer is deposited on the N-type second silicon carbide epitaxial layer 4, and an ion implantation window is etched out by photolithography and etching. According to the ion implantation window, aluminum ions are implanted four times to form the P-type body region 5; after removing the deposited oxide layer, an oxide layer is re-deposited, and an ion implantation window is etched out by photolithography and etching. According to the ion implantation window, nitrogen ions are implanted twice to form the N+ type second source region 6, and the following is obtained: Fig.12 The device structure shown forms a P-type body region 5 and an N+-type second source region 6 .

[0090] S706. Deposit an oxide layer on the N-type second silicon carbide epitaxial layer, and etch source trenches 7 on both side regions of the N-type second silicon carbide epitaxial layer through photolithography and etching processes. The source trenches 7 penetrate the lower end of the N-type second silicon carbide epitaxial layer 4 and extend into the first P-type doping region 203 and the second P-type doping region 302.

[0091] Specifically, Fig.13 The cross-sectional structure diagram of forming the source trench 7 is schematically shown. An oxide layer is deposited on the N-type second silicon carbide epitaxial layer 4. Through photolithography and etching processes, the source trench 7 is etched from the two side regions of the upper surface of the N-type second silicon carbide epitaxial layer 4 to the first P-type doped region 203 to obtain the source trench 7. Fig.13 The device structure in which the source trench 7 is formed is shown.

[0092] S707, forming a P-type source region 8 on the outer side of the source trench 7 on both sides by ion implantation, and the P-type source region 8 on one side of each source trench 7 overlaps with the N+ type first source region 202, and filling the source trench 7 with silicon dioxide by chemical vapor deposition.

[0093] One side of each source trench 7 is close to the first N-type doping region 201 .

[0094] Specifically, Fig.14 The schematic diagram of the cross-sectional structure of the source trench 7 filled with silicon dioxide is shown schematically. P-type source regions 8 are formed on the outer sides of the source trenches 7 on both sides by ion implantation, and the P-type source region 8 on one side of each source trench 7 overlaps with the N+ type first source region 202. The source trench 7 is filled with silicon dioxide by chemical vapor deposition, and the silicon dioxide on the entire device surface is removed to obtain the following Fig.14 The device structure shown has a source trench 7 filled with silicon dioxide.

[0095] S708. Through photolithography and etching processes, a gate trench 9 is etched at a position between the two source trenches 7 in the N-type second silicon carbide epitaxial layer, and a gate oxide layer 10 is grown on the inner wall of the gate trench 9, so that the lower surface of the gate oxide layer 10 contacts part of the first P-type doping region 203, part of the first N-type doping region 201 and part of the N+ type first source region 202, and the lower surface of the gate oxide layer 10 contacts part of the second N-type doping region 301, and polysilicon 11 is deposited in the gate trench 9 as a gate to obtain a third current structure; the gate trench 9 extends downward from the middle area of ​​the upper surface of the N+ type second source region 6, and successively passes through the N+ type second source region 6, the P type body region 5, the N-type second silicon carbide epitaxial layer 4 to the first P type doping region 203 and the second P type doping region 302.

[0096] Specifically, Fig.15 The cross-sectional structure diagram of forming the gate trench 9 is schematically shown. The gate trench 9 is etched at the position between the two source trenches 7 in the N-type second silicon carbide epitaxial layer through photolithography and etching processes to obtain the following Fig.15 The device structure in which the gate trench 9 is formed is shown.

[0097] Fig.16 The cross-sectional structure diagram of forming the gate oxide layer 10 and the polysilicon 11 is schematically shown. A sacrificial oxide layer is grown in the gate trench 9, and the sacrificial oxide layer is removed within a certain period of time. Then, the gate oxide layer 10 is grown on the inner wall of the gate trench 9 through a high-temperature furnace tube, so that the lower surface of the gate oxide layer 10 is in contact with part of the first P-type doping region 203, part of the first N-type doping region 201 and part of the N+ type first source region 202; after cleaning with a standard cleaning solution, annealing treatment is performed, polysilicon 11 is deposited in the gate trench 9, and the remaining polysilicon 11 on the N-type second silicon carbide epitaxial layer 4 is removed to obtain the following Fig.16 The third current structure is shown.

[0098] S709 , depositing an interlayer insulating dielectric 12 on the upper surface of the third current structure, removing the silicon dioxide, part of the P-type body region 5 and part of the interlayer insulating dielectric 12 above the N+-type second source region 6 , and removing the silicon dioxide inside the source trench 7 .

[0099] Specifically, Fig.17 The schematic diagram of the cross-sectional structure of forming the interlayer insulating medium 12 is schematically shown. The interlayer insulating medium 12 is deposited on the upper surface of the third current structure. The interlayer insulating medium 12 can be a combination of silicon dioxide, silicon nitride and silicon oxynitride. Finally, the following is obtained: Fig.17 The device structure shown forms an interlayer insulating dielectric 12.

[0100] Specifically, Fig.18The cross-sectional structure diagram of etching a source contact hole is schematically shown. The mask layer is used to remove silicon dioxide, part of the P-type body region 5 and part of the interlayer insulating medium 12 above the N+ type second source region 6, and the silicon dioxide inside the source trench 7. The source trench 7 after removing the silicon dioxide is the source contact hole, and the following can be obtained: Fig.18 The device structure with the source contact hole etched is shown.

[0101] S710 , forming a source metal 13 inside the source trench 7 and on the interlayer insulating dielectric 12 , and forming a drain metal 14 on the lower surface of the N+ type silicon carbide substrate 101 .

[0102] Fig.19 The cross-sectional structure diagram of forming the source metal 13 and the drain metal 14 is schematically shown. The source metal 13 is formed inside the source trench 7 and on the interlayer insulating medium 12, and the drain metal 14 is formed on the lower surface of the N+ type silicon carbide substrate 101, so as to obtain Fig.19 The device structure shown forms a source metal 13 and a drain metal 14 .

[0103] A silicon carbide MOSFET device and a preparation method thereof provided in an embodiment of the present invention solve the technical problem in the prior art that the electric field protection of the gate oxide layer 10 of the trench-type silicon carbide MOSFET is insufficient, especially the gate oxide layer 10 at the corner is easily broken down by the electric field. The silicon carbide MOSFET device of the present invention not only solves the problem of the excessively high electric field of the gate oxide layer 10, but also proposes two conduction channels, vertical and horizontal, to improve the current density and solve the problem of increasing the on-resistance due to the introduction of the gate oxide protection structure.

[0104] It should be noted here that the description of the above embodiment of the method for preparing a silicon carbide MOSFET device is similar to the description of the above embodiment of the silicon carbide MOSFET device, and has similar beneficial effects as the embodiment of the silicon carbide MOSFET device. For technical details not disclosed in the embodiment of the method for preparing a silicon carbide MOSFET device of the embodiment of the present invention, please refer to the description of the embodiment of the silicon carbide MOSFET device of the present invention for understanding.

[0105] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict.

[0106] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A silicon carbide MOSFET device, characterized in that: The silicon carbide MOSFET device comprises a silicon carbide structure, an N-type second silicon carbide epitaxial layer and an interlayer insulating medium arranged in sequence from bottom to top; The top region of the silicon carbide structure is provided with a first periodic structure and a second periodic structure arranged periodically, the first periodic structure includes a first N-type doping region, an N+ type first source region and a first P-type doping region, and the second periodic structure includes a second N-type doping region and a second P-type doping region; A P-type body region is formed in the middle top region of the N-type second silicon carbide epitaxial layer, and an N+ type second source region is formed in the middle top region of the P-type body region; A source trench is formed in the regions on both sides of the N-type second silicon carbide epitaxial layer, the source trench penetrates the lower end of the N-type second silicon carbide epitaxial layer and extends into the first P-type doping region and the second P-type doping region, a P-type source region is arranged outside the source trench, and a source metal is arranged inside the source trench; The gate trench extends downward from the middle area of ​​the upper surface of the N+ type second source region, and sequentially penetrates the N+ type second source region, the P type body region, the N- type second silicon carbide epitaxial layer to the first P type doping region and the second P type doping region. A gate oxide layer is arranged inside the gate trench, and polysilicon is deposited as a gate. The lower surface of the gate oxide layer contacts part of the first P type doping region, part of the first N type doping region and part of the N+ type first source region, or the lower surface of the gate oxide layer contacts part of the second N type doping region.

2. The silicon carbide MOSFET device according to claim 1, characterized in that: The silicon carbide structure includes an N+ type silicon carbide substrate and an N-type first silicon carbide epitaxial layer arranged in sequence from bottom to top; the silicon carbide MOSFET device also includes a drain metal, and the drain metal is arranged on the lower surface of the N+ type silicon carbide substrate.

3. The silicon carbide MOSFET device according to claim 2, characterized in that: The first P-type doping region and the second P-type doping region are both arranged in the top region of the N-type first silicon carbide epitaxial layer, the first N-type doping region is arranged in the middle region of the first P-type doping region, and the N+-type first source region is arranged in the two side regions of the first N-type doping region at intervals; the second N-type doping region is arranged in the middle region of the second P-type doping region, and the length of the first N-type doping region is less than the length of the second N-type doping region.

4. The silicon carbide MOSFET device according to claim 1, characterized in that: The distance between the upper surface of the N+ type first source region and the upper surface of the first P type doping region is 0.4-0.7 um.

5. The silicon carbide MOSFET device according to claim 3, characterized in that: A part of the P-type source region is close to a side of the first N-type doping region, overlaps with a side of the N+ type first source region away from the first N-type doping region and contacts the source metal, or the part of the P-type source region is alternately arranged with the second N-type doping region; both sides of the P-type body region away from the polysilicon are in contact with the P-type source region; The source metal is also arranged on the interlayer insulating medium and contacts the upper surface of a portion of the P-type body region and a portion of the N+-type second source region through the gap of the interlayer insulating medium.

6. The silicon carbide MOSFET device according to claim 1, characterized in that: The depth of the source trench is less than or equal to the sum of the depths of the N-type second silicon carbide epitaxial layer and the first P-type doping region, and the depth of the source trench is less than or equal to the sum of the depths of the N-type second silicon carbide epitaxial layer and the second P-type doping region.

7. The silicon carbide MOSFET device according to claim 1, characterized in that: The doping ions of the first P-type doping region and the second P-type doping region both include aluminum ions, and the doping concentration is 3e16cm -3 ~6e16cm -3 .

8. The silicon carbide MOSFET device according to claim 1, characterized in that: The doping ions of the first N-type doping region and the second N-type doping region both include nitrogen ions, and the doping concentration is 1.2e15cm -3 ~6.5e15cm -3 .

9. A method for preparing a silicon carbide MOSFET device, characterized in that: The silicon carbide MOSFET device according to any one of claims 1 to 8 comprises: Selecting an N+ type silicon carbide substrate, and depositing an N-type first silicon carbide epitaxial layer on the N+ type silicon carbide substrate; Depositing an oxide layer on the N-type first silicon carbide epitaxial layer, and forming P-type doping regions on both sides of the top layer region of the N-type first silicon carbide epitaxial layer by photolithography, etching and ion implantation, wherein the P-type doping regions include a first P-type doping region and a second P-type doping region; A first N-type doping region is formed between the first P-type doping regions on both sides, an N+ type first source region is formed in the first P-type doping regions on both sides to obtain a first current structure, and a second N-type doping region is formed between the second P-type doping regions on both sides to obtain a second current structure, wherein the N+ type first source regions are arranged at intervals on both sides of the first N-type doping region; growing an N-type second silicon carbide epitaxial layer on the upper surfaces of the first current structure and the second current structure; Depositing the oxide layer on the N-type second silicon carbide epitaxial layer, generating P-type body regions on both sides of the top region of the N-type second silicon carbide epitaxial layer by means of the photolithography process, the etching process and multiple ion implantations, and forming N+ type second source regions in the edge regions of the top region of the P-type body regions on both sides, wherein the edge regions are regions close to the center of the N-type second silicon carbide epitaxial layer; Depositing the oxide layer on the N-type second silicon carbide epitaxial layer, etching source trenches in the two side regions of the N-type second silicon carbide epitaxial layer through the photolithography process and the etching process, wherein the source trenches penetrate the lower end of the N-type second silicon carbide epitaxial layer and extend into the first P-type doping region and the second P-type doping region; Forming a P-type source region on the outer sides of the source trenches on both sides by ion implantation, and the P-type source region on one side of each source trench overlaps with the N+ type first source region, and filling the source trench with silicon dioxide by chemical vapor deposition, and one side of each source trench is a side close to the first N-type doping region; By means of the photolithography process and the etching process, a gate trench is etched at a position between two source trenches in the N-type second silicon carbide epitaxial layer, a gate oxide layer is grown on the inner wall of the gate trench, so that the lower surface of the gate oxide layer contacts part of the first P-type doping region, part of the first N-type doping region and part of the N+ type first source region, the lower surface of the gate oxide layer contacts part of the second N-type doping region, and polysilicon is deposited in the gate trench as a gate to obtain a third current structure; the gate trench extends downward from the middle area of ​​the upper surface of the N+ type second source region, and sequentially penetrates the N+ type second source region, the P-type body region, the N-type second silicon carbide epitaxial layer to the first P-type doping region and the second P-type doping region; Depositing an interlayer insulating dielectric on the upper surface of the third current structure, removing the interlayer insulating dielectric above the silicon dioxide, a portion of the P-type body region and a portion of the N+-type second source region, and removing the silicon dioxide inside the source trench; A source metal is formed inside the source trench and on the interlayer insulating medium, and a drain metal is formed on the lower surface of the N+ type silicon carbide substrate.

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