Pixel structure and manufacturing method thereof

Abstract

The invention discloses a pixel structure and a manufacturing method thereof. The pixel structure comprises a substrate, a first electrode, a first insulating layer, a second insulating layer, a third insulating layer and a second electrode. The first electrode is located on the substrate. The first insulating layer is located on the first electrode and comprises at least two first openings. The first openings at least partially overlap the first electrode. The second insulating layer is located on the first insulating layer and is provided with a through hole overlapping the at least two first openings. The third insulating layer is located on the second insulating layer and comprises at least two second openings. The second openings are respectively overlapped with the first openings. The second openings at least partially overlap the through hole. The second electrode fills the first opening, the second opening and the through hole and is connected with the first electrode.

Description

Technical Field

[0001] The invention relates to a pixel structure and a manufacturing method thereof. Background Art

[0002] In recent years, with the continuous advancement of display technology, consumers have higher and higher requirements for display quality (such as image resolution, color saturation, etc.). However, in order to manufacture high-performance displays, the pixel structure in the display needs to include a number of conductive structures connecting different conductive layers.

[0003] In the pixel array, a large area is occupied by these conductive structures connecting different conductive layers, which limits the size of the pixel structure and affects the resolution of the display. Summary of the invention

[0004] The present invention provides a pixel structure and a manufacturing method thereof, which can avoid the problem of electrical instability of a connection point between a first electrode and a second electrode caused by process deviation.

[0005] At least one embodiment of the present invention provides a pixel structure, which includes a substrate, a first electrode, a first insulating layer, a second insulating layer, a third insulating layer and a second electrode. The first electrode is located on the substrate. The first insulating layer is located on the first electrode and includes at least two first openings, wherein at least two first openings at least partially overlap with the first electrode. The second insulating layer is located on the first insulating layer and has a through hole overlapping with the at least two first openings. The third insulating layer is located on the second insulating layer and includes at least two second openings. At least two second openings overlap with at least two first openings respectively. At least two second openings at least partially overlap with the through hole. The second electrode is filled in the at least two first openings, the at least two second openings and the through hole, and is connected to the first electrode.

[0006] At least one embodiment of the present invention provides a method for manufacturing a pixel structure, which includes the following steps. A first electrode is formed on a substrate. A first insulating layer is formed on the first electrode. A second insulating layer is formed on the first insulating layer. A through hole overlapping the first electrode is formed in the second insulating layer, and the through hole exposes the first insulating layer. A third insulating layer is formed on the second insulating layer and in the through hole. An etching process is performed to etch the first insulating layer and the third insulating layer to form at least two first openings at least partially overlapping the through hole in the first insulating layer, and at least two second openings respectively overlapping the at least two first openings are formed in the third insulating layer. A second electrode is formed in the at least two first openings, the at least two second openings and the through hole, and the second electrode is connected to the first electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a top view of a pixel structure according to an embodiment of the present invention.

[0008] Figure 1B It is along Figure 1A A schematic cross-sectional view of line AA' and line BB'.

[0009] FIG. 2A to FIG. 2F yes Figure 1B Schematic cross-sectional view of various stages of a method for manufacturing a pixel structure.

[0010] Figure 3A is a partial top view of a pixel structure according to an embodiment of the present invention.

[0011] Figure 3B and Figure 3C Along the Figure 3A A schematic cross-sectional view of line CC' and line D-D'.

[0012] Figure 4A is a partial top view of a pixel structure according to an embodiment of the present invention.

[0013] Figure 4B and Figure 4C Along the Figure 4A A schematic cross-sectional view of line CC' and line D-D'.

[0014] Figure 5 is a partial top view of a pixel structure according to an embodiment of the present invention.

[0015] Figure 6 is a partial top view of a pixel structure according to an embodiment of the present invention.

[0016] Figure 7 is a cross-sectional schematic diagram of a pixel structure according to an embodiment of the present invention.

[0017] Figure 8 is a cross-sectional schematic diagram of a pixel structure according to an embodiment of the present invention.

[0018] Description of reference numerals:

[0019] 10A, 10B, 10C, 10D, 10E, 10F: Pixel structure

[0020] 100: Substrate

[0021] 100t,120t: Top surface

[0022] 110: Dielectric layer

[0023] 120: First insulation layer

[0024] 120b: Bottom

[0025] 122,124,142,144: Partial

[0026] 130: Second insulation layer

[0027] 140: The third insulation layer

[0028] AO: Opening

[0029] AZ: Photoresist pattern

[0030] CP: Connector

[0031] CS1, CS2: Electrodes

[0032] D1: First direction

[0033] D2: Second direction

[0034] DL: Data Line

[0035] E1: First electrode

[0036] E2 Second electrode

[0037] E3: Signal line

[0038] G: Gate

[0039] LD: Light Emitting Diode

[0040] O1: First opening

[0041] O2: Second opening

[0042] S1, S2, S3, S4: Part of the side wall

[0043] SD1: First source / drain

[0044] SD2: Second source / drain

[0045] SM: Semiconductor layer

[0046] SL: Scan Line

[0047] SP: Platform Department

[0048] Thin Film Transistor

[0049] TH: Through Hole

[0050] X1,X1',X2,X2',X3,X3',X4,X4': distance DETAILED DESCRIPTION

[0051] Figure 1A is a top view of a pixel structure 10A according to an embodiment of the present invention. Figure 1B It is along Figure 1APlease refer to the cross-sectional diagram of the line A-A' and the line B-B'. Figure 1A and Figure 1B The pixel structure 10A includes a substrate 100, a first electrode E1, a first insulating layer 120, a second insulating layer 130, a third insulating layer 140 and a second electrode E2. In this embodiment, the pixel structure 10A further includes a dielectric layer 110, a scan line SL, a data line DL and a thin film transistor T.

[0052] The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylenenaphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

[0053] The thin film transistor T is located on the substrate 100 and includes a gate G, a semiconductor layer SM, a first source / drain SD1 and a second source / drain SD2 .

[0054] The scan line SL is electrically connected to the gate G. In this embodiment, the scan line SL and the gate G are integrated in the same conductive layer, but the present invention is not limited thereto. In other embodiments, the scan line SL and the gate G are respectively located in different conductive layers.

[0055] In some embodiments, the materials of the scan line SL and the gate G include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, their alloys, their oxides, their nitrides, or their combinations or other conductive materials. In some embodiments, the scan line SL and the gate G each have a single-layer structure or a multi-layer structure.

[0056] The dielectric layer 110 is located on the scan line SL and the gate G. In some embodiments, the material of the dielectric layer 110 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials), an organic material or other suitable materials or a combination thereof.

[0057] The semiconductor layer SM is located on the dielectric layer 110 and overlaps the gate G. In some embodiments, the material of the semiconductor layer SM includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (for example, indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials.

[0058] The first source / drain SD1 and the second source / drain SD2 are electrically connected to the semiconductor layer SM. The data line DL is electrically connected to the first source / drain SD1. In this article, source / drain is used to represent the source or drain. In other words, the data line DL is electrically connected to the source or drain of the thin film transistor T.

[0059] The first electrode E1 is located on the substrate 100. In this embodiment, the first electrode E1 is located on the dielectric layer 110. The first electrode E1 is electrically connected to the second source / drain SD2. In other words, the first electrode E1 is electrically connected to the source or drain of the thin film transistor T.

[0060] In this embodiment, the first source / drain SD1, the second source / drain SD2, the data line DL and the first electrode E1 are integrated in the same conductive layer, but the present invention is not limited thereto. In other embodiments, the first source / drain SD1, the second source / drain SD2, the data line DL and the first electrode E1 are located in different conductive layers.

[0061] In this embodiment, the thin film transistor T is a bottom gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the thin film transistor T is a top gate thin film transistor, a double gate thin film transistor or other types of thin film transistors.

[0062] In some embodiments, the materials of the first source / drain SD1, the second source / drain SD2, the data line DL, and the first electrode E1 include metals (e.g., chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, or combinations of the above metals), metal oxides (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides or combinations of the above metal oxides), metal nitrides, or other conductive materials. In some embodiments, the first source / drain SD1, the second source / drain SD2, the data line DL, and the first electrode E1 each have a single-layer structure or a multi-layer structure.

[0063] The first insulating layer 120 is located on the first source / drain SD1, the second source / drain SD2, the data line DL and the first electrode E1. The first insulating layer 120 includes at least two first openings O1. Both of the two first openings O1 at least partially overlap the first electrode E1.

[0064] In some embodiments, the material of the first insulating layer 120 includes an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials) or other suitable materials or a combination thereof.

[0065] The second insulating layer 130 is located on the first insulating layer 120. The second insulating layer 130 has a through hole TH overlapping at least two first openings O1. In some embodiments, the first insulating layer 120 includes more than three first openings O1, and one through hole TH of the second insulating layer 130 overlaps more than three first openings O1. In some embodiments, the second insulating layer 130 includes an organic material suitable for ultra-high aperture technology (Ultra / Super High Aperture, UHA / SHA), and the second insulating layer 130 can increase the distance between electrodes, thereby reducing capacitance and increasing the aperture ratio of the pixel structure 10A. For example, the second insulating layer 130 may include acrylic material, siloxane material, polyimide material, or epoxy material.

[0066] The third insulating layer 140 is located on the second insulating layer 130 and includes at least two second openings O2. At least two second openings O2 are at least partially overlapped with the through hole TH. At least two second openings O2 are respectively overlapped with at least two first openings O1. In other embodiments, more than three second openings O2 are respectively overlapped with more than three first openings O1, and more than three second openings O2 are at least partially overlapped with the through hole TH. In some embodiments, the material of the third insulating layer 140 includes an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials) or other suitable materials or a combination thereof.

[0067] In some embodiments, the second openings O2 of the third insulating layer 140 and the first openings O1 of the first insulating layer 120 are defined in the same etching process using the same photoresist pattern, and the two second openings O2 overlap the two first openings O1 respectively.

[0068] In some embodiments, a portion of the sidewall S1 of the first opening O1 is retracted due to undercutting in the etching process, resulting in a portion of the sidewall S1 of the first opening O1 being located between the bottom surface 120b of the second insulating layer 130 and the top surface 100t of the substrate 100. In some embodiments, a portion of the sidewall S3 of the second opening O2 overlaps the second insulating layer 130 and is located on the top surface 120t of the second insulating layer 130.

[0069] In some embodiments, a portion of the sidewall S2 of the first opening O1 and a portion of the sidewall S4 of the second opening O2 are located within the range of the through hole TH and do not overlap the second insulating layer 130. In this embodiment, a portion of the sidewall S2 of the first opening O1 and a portion of the sidewall S4 of the second opening O2 are not aligned with each other, but the present invention is not limited thereto. In other embodiments, a portion of the sidewall S2 of the first opening O1 and a portion of the sidewall S4 of the second opening O2 are aligned with each other.

[0070] In the present embodiment, a portion 142 of the third insulating layer 140 overlaps with a portion 122 of the first insulating layer 120 and is located at the bottom of the through hole TH of the second insulating layer 130. The portion 142 of the third insulating layer 140 contacts the portion 122 of the first insulating layer 120. Another portion 144 of the third insulating layer 140 overlaps with another portion 124 of the first insulating layer 120, and the two are separated from each other by the second insulating layer 130.

[0071] The second electrode E2 is located on the third insulating layer 140 and fills at least two second openings O2 of the third insulating layer 140 , the through hole TH of the second insulating layer 130 and at least two first openings O1 of the first insulating layer 120 , and is connected to the first electrode E1 located at the bottom of the first opening O1 .

[0072] The material of the second electrode E2 includes metal (e.g., chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, or combinations of the above metals), metal oxide (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides or combinations of the above metal oxides), metal nitride, or other conductive materials. In some embodiments, the second electrode E2 has a single-layer structure or a multi-layer structure.

[0073] In some embodiments, since a portion of the sidewall S1 of the first opening O1 has an undercut problem, the second electrode E2 may be broken at a portion of the sidewall S1 close to the first opening O1. However, since not all sidewalls of the first opening O1 will have an undercut problem, such as a portion of the sidewall S2 of the first opening O1 is not prone to an undercut problem. Therefore, the second electrode E2 can easily extend to the first electrode E1 along the portion of the sidewall S2 of the first opening O1. In other embodiments, the second electrode E2 is not broken at the undercut of the portion of the sidewall S1.

[0074] In some embodiments, the pixel structure 10A is suitable for a liquid crystal display device. For example, the pixel structure 10A further includes a common electrode (not shown) and a liquid crystal layer (not shown). The liquid crystal molecules in the liquid crystal layer can be controlled by the electric field between the second electrode E2 and the common electrode. In this case, the second electrode E2 can also be referred to as a pixel electrode.

[0075] FIG. 2A to FIG. 2F yes Figure 1B Schematic cross-sectional view of various stages of the manufacturing method of the pixel structure 10A. Figure 2A , forming a thin film transistor T, a dielectric layer 110 and a first electrode E1 on the substrate 100. In some embodiments, the method of forming the first electrode E1 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, sputtering, electroless plating or other processes.

[0076] Please refer to Figure 2B , forming a first insulating layer 120 on the thin film transistor T and the first electrode E1. In some embodiments, a method of forming the first insulating layer 120 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition or other suitable methods.

[0077] Please refer to Figure 2C , forming a second insulating layer 130 on the first insulating layer 120. In some embodiments, the second insulating layer 130 is formed on the first insulating layer 120 by a coating process or other suitable processes. A through hole TH is formed in the second insulating layer 130 overlapping the first electrode E1, and the through hole TH exposes the first insulating layer 120. For example, the through hole TH is formed by a photolithography process.

[0078] Please refer to Figure 2D , forming the third insulating layer 140 on the second insulating layer 130 and in the through hole TH. In some embodiments, the method of forming the third insulating layer 140 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition or other suitable methods.

[0079] Please refer to Figure 2E , a photoresist pattern AZ is formed on the second insulating layer 140. In the present embodiment, the photoresist pattern AZ includes at least two openings AO, and the at least two openings AO both overlap the first electrode E1.

[0080] Please refer to Figure 2F , an etching process is performed using the photoresist pattern AZ as a mask. The etching process is, for example, a wet etching process or a dry etching process. The dry etching process is, for example, a reactive ion etching (RIE) process.

[0081] The first insulating layer 120 and the third insulating layer 140 are etched by an etching process to form at least two first openings O1 at least partially overlapping the through hole TH in the first insulating layer 120, and at least two second openings O2 respectively overlapping the at least two first openings O1 are formed in the third insulating layer 140. In the present embodiment, the first insulating layer 120 and the third insulating layer 140 are etched by the same etching process.

[0082] Finally back Figure 1B , forming the second electrode E2 in the first opening O1, the second opening O2 and the through hole TH to connect the first electrode E1.

[0083] In this embodiment, since a plurality of first openings O1 and a plurality of second openings O2 are formed to overlap the through hole TH, the electrical stability (such as current resistance, resistance, etc.) between the second electrode E2 and the first electrode E1 can be improved. Figure 2E ) shifts to the left due to process errors, which will result in a reduction in the area of ​​the first opening O1 and the second opening O2 on the left overlapping the through hole TH in the subsequent process. However, the first opening O1 and the second opening O2 on the right will also shift to the left at the same time, so that the area they overlap with the through hole TH increases and compensates for the aforementioned reduced area. Based on this, the contact area between the second electrode E2 and the first electrode E1 is not easily changed due to process errors, thereby improving the electrical stability.

[0084] Figure 3A is a partial top view of a pixel structure 10B according to an embodiment of the present invention, wherein Figure 3AThe first electrode E1 , the first opening O1 , the through hole TH and the second opening O2 of the pixel structure 10B are shown, and other structures are omitted. Figure 3B and Figure 3C Along the Figure 3A It should be noted that: FIG. 3A to FIG. 3C The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0085] Please refer to FIG. 3A to FIG. 3C The first electrode E1 includes a platform portion SP and a connection portion CP. The platform portion SP is connected to other signal lines or thin film transistors (eg Figure 1A The platform portion SP may be in any geometric shape. In this embodiment, the platform portion SP is a rounded rectangle, but the present invention is not limited thereto. In other embodiments, the platform portion SP is a circle, a right-angled rectangle, or other geometric shapes.

[0086] The through hole TH of the second insulating layer 130 overlaps the platform portion SP of the first electrode E1. In the present embodiment, in the first direction D1, the width W2 of the through hole TH is greater than the width W1 of the platform portion SP. In other embodiments, the width W2 of the through hole TH is less than or equal to the width W1 of the platform portion SP. In the present embodiment, the width W2 is the maximum width of the through hole TH, and the width W1 is the maximum width of the platform portion SP. In the present embodiment, the through hole TH is a rounded rectangle, but the present invention is not limited thereto. In other embodiments, the through hole TH is a circle, a right-angled rectangle, or other geometric shapes.

[0087] The two first openings O1 of the first insulating layer 120 correspond to two opposite corners of the platform portion SP (and the through hole TH). In the present embodiment, the first openings O1 expose a portion of the top surface of the dielectric layer 110. In some embodiments, in the first direction D1, the distance X1 between the two first openings O1 is less than the width W2 of the through hole TH. In the present embodiment, the distance X1 is the shortest distance between the two first openings O1. In some embodiments, in the first direction D1, the longest distance X3 between the opposite sides of the two first openings O1 is greater than the width W2 of the through hole TH.

[0088] The two second openings O2 of the third insulating layer 140 correspond to two opposite corners of the platform portion SP (and the through hole TH). The two second openings O2 of the third insulating layer 140 overlap the two first openings O1 respectively. In some embodiments, in the first direction D1, the distance X2 between the two second openings O2 is less than the width W2 of the through hole TH. In this embodiment, the distance X2 is the shortest distance between the two second openings O2. In some embodiments, in the first direction D1, the longest distance X4 on the opposite sides between the two second openings O2 is greater than the width W2 of the through hole TH.

[0089] In some embodiments, the maximum width Z1 of each of the first openings O1 is smaller than the maximum width Z2 of each of the second openings O2. In some embodiments, the direction of the width Z1 is different from the direction of the width Z2.

[0090] Figure 4A is a partial top view of a pixel structure 10C according to an embodiment of the present invention, wherein Figure 4A The first electrode E1 , the first opening O1 , the through hole TH and the second opening O2 of the pixel structure 10C are shown, and other structures are omitted. Figure 4B and Figure 4C Along the Figure 4A It should be noted that: FIG. 4A to FIG. 4C The implementation examples are used FIG. 3A to FIG. 3C The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0091] FIG. 4A to FIG. 4C Examples and FIG. 3A to FIG. 3C The difference between the embodiments is that: FIG. 4A to FIG. 4C In the embodiment, the width W2 of the through hole TH is smaller than the width W1 of the terrace portion SP.

[0092] Figure 5 is a partial top view of a pixel structure 10D according to an embodiment of the present invention, wherein Figure 5 The first electrode E1, the first opening O1, the through hole TH and the second opening O2 of the pixel structure 10D are shown, and other structures are omitted. It must be noted here that Figure 5 The implementation examples are used FIG. 3A to FIG. 3C The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0093] Figure 5Examples and FIG. 3A to FIG. 3C The difference between the embodiments is that: Figure 5 In the embodiment, in the first direction D1, the width Z2 of each of the two second openings O2 is greater than or equal to the width W2 of the through hole TH. In some embodiments, the width Z2 is the maximum width of the second opening O2, and the width W2 is the maximum width of the through hole TH.

[0094] Figure 6 is a partial top view of a pixel structure 10E according to an embodiment of the present invention, wherein Figure 6 The first electrode E1, the first opening O1, the through hole TH and the second opening O2 of the pixel structure 10E are shown, and other structures are omitted. It must be noted here that Figure 6 The implementation examples are used FIG. 3A to FIG. 3C The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0095] Figure 6 Examples and FIG. 3A to FIG. 3C The difference between the embodiments is that: Figure 6 In the embodiment of the present invention, the two first openings O1 overlap two adjacent corners of the platform portion SP (and the through hole TH). In some embodiments, in the second direction D2, the distance X1' between the two first openings O1 is less than the width W2' of the through hole TH. In this embodiment, the distance X1' is the shortest distance between the two first openings O1. In some embodiments, in the second direction D2, the longest distance X3' on the opposite sides between the two first openings O1 is greater than the width W2' of the through hole TH.

[0096] The two second openings O2 correspond to two adjacent corners of the platform portion SP (and the through hole TH). The two second openings O2 overlap the two first openings O1, respectively. In some embodiments, in the second direction D2, the distance X2' between the two second openings O2 is less than the width W2' of the through hole TH. In this embodiment, the distance X2' is the shortest distance between the two second openings O2. In some embodiments, in the second direction D2, the longest distance X4' on the opposite sides between the two second openings O2 is greater than the width W2' of the through hole TH.

[0097] Figure 7 is a cross-sectional schematic diagram of a pixel structure 10F according to an embodiment of the present invention. It must be noted here that: Figure 7 The implementation examples are used Figure 1A and Figure 1BThe component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0098] In this embodiment, the pixel structure 10F is applicable to a light emitting diode display device. In this embodiment, the second electrode E2 is electrically connected to one electrode CS1 of the light emitting diode LD, and the other electrode CS2 of the light emitting diode LD is electrically connected to the signal line E3. In some embodiments, one of the electrode CS1 and the electrode CS2 is the cathode of the light emitting diode LD, and the other is the anode of the light emitting diode LD. In some embodiments, the first electrode E1 is electrically connected to the common signal line. In other embodiments, the first electrode E1 is electrically connected to the thin film transistor T, such as Figure 8 shown.

[0099] In the present embodiment, although a portion of the sidewall S1 of the first opening O1 has an undercut problem, the second electrode E2 is not broken at the portion of the sidewall S1 close to the first opening O1.

[0100] In summary, by making the at least two second openings of the third insulating layer at least partially overlap the through hole of the second insulating layer, the problem of electrical instability of the connection point between the first electrode and the second electrode caused by process deviation can be avoided.

Claims

1. A pixel structure, comprising: a substrate; a first electrode, located on the substrate; a first insulating layer, located on the first electrode and comprising at least two first openings, wherein the at least two first openings at least partially overlap the first electrode; a second insulating layer, located on the first insulating layer and having a through hole overlapping the at least two first openings; a third insulating layer, located on the second insulating layer, and comprising at least two second openings, wherein the at least two second openings overlap the at least two first openings respectively, and the at least two second openings at least partially overlap the through hole; as well as A second electrode is filled in the at least two first openings, the at least two second openings and the through hole, and is connected to the first electrode. 2 . The pixel structure as claimed in claim 1 , wherein a portion of the third insulating layer and a portion of the first insulating layer are located at a bottom of the through hole of the second insulating layer, and the portion of the third insulating layer contacts the portion of the first insulating layer. 3 . The pixel structure as claimed in claim 1 , wherein the shortest distance between the at least two first openings is smaller than the maximum width of the through hole. 4 . The pixel structure as claimed in claim 1 , wherein the first electrode is electrically connected to a source or a drain of a thin film transistor. 5 . The pixel structure as claimed in claim 1 , wherein the first insulating layer and the third insulating layer comprise inorganic materials, and the second insulating layer comprises organic materials. 6 . The pixel structure as claimed in claim 1 , wherein part of the sidewalls of the at least two first openings are located between a bottom surface of the second insulating layer and a top surface of the substrate. 7 . The pixel structure as claimed in claim 1 , wherein a maximum width of each of the at least two first openings is smaller than a maximum width of each of the at least two second openings. 8 . The pixel structure as claimed in claim 1 , wherein a maximum width of each of the at least two second openings is greater than or equal to a maximum width of the through hole.

9. A method for manufacturing a pixel structure, comprising: forming a first electrode on a substrate; forming a first insulating layer on the first electrode; forming a second insulating layer on the first insulating layer; forming a through hole in the second insulating layer overlapping the first electrode, wherein the through hole exposes the first insulating layer; forming a third insulating layer on the second insulating layer and in the through hole; Performing an etching process to etch the first insulating layer and the third insulating layer to form at least two first openings at least partially overlapping the through hole in the first insulating layer, and forming at least two second openings respectively overlapping the at least two first openings in the third insulating layer; as well as A second electrode is formed in the at least two first openings, the at least two second openings and the through hole, and the second electrode is connected to the first electrode.

10. The manufacturing method according to claim 9, further comprising: forming a photoresist pattern on the second insulating layer; as well as The etching process is performed with the photoresist pattern as a mask to form the at least two first openings and the at least two second openings.

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