Silicon wafer passivation method and battery preparation method

Abstract

The invention relates to a silicon wafer passivation method and a battery preparation method. The method comprises the following steps: providing an original base material; carrying out passivation treatment on the side surface of the original base material by adopting a chemical vapor deposition process to obtain a passivated base material; and carrying out fragmentation processing on the passivated substrate to obtain a plurality of edge passivated silicon wafers. By adopting the method, the edge passivation effect of the silicon wafer can be improved.

Description

Technical Field

[0001] The present application relates to the field of battery technology, and in particular to a silicon wafer passivation method and a battery preparation method. Background Art

[0002] In the research and development and production of battery cells and components, the battery edge problem has become a key issue that needs urgent attention. The edge area of ​​the battery is often faced with large stress and temperature changes, which leads to frequent edge defects. Common edge defects include recombination phenomena and photoluminescence (PL) blackening. These problems not only significantly reduce the overall performance of the battery, but also may increase the risk of leakage. In addition, the presence of edge defects makes it easier for water vapor and chemical components to invade, thereby accelerating the aging and failure of the battery. Therefore, the effective implementation of passivation and protection strategies for the edge area is particularly important for improving the durability and safety of the battery.

[0003] In traditional technology, wrap-around coating technology or organic colloid is usually used to passivate the edge of silicon wafers. Among them, wrap-around coating technology forms a protective film or functional film by evenly wrapping the coating material on the target surface to enhance the performance of the material. While passivation using organic colloid is to form a dense protective layer by coating a layer of organic substance on the edge of the silicon wafer to prevent the external environment from affecting the silicon wafer.

[0004] However, although these two methods improve the edge passivation effect to a certain extent, they still have the problem of poor passivation effect. Summary of the invention

[0005] Based on this, it is necessary to provide a silicon wafer passivation method and a battery preparation method that can improve the passivation effect of the silicon wafer edge in order to solve the above technical problems.

[0006] In a first aspect, the present application provides a silicon wafer passivation method, comprising:

[0007] Provide the original substrate;

[0008] Passivating the side of the original substrate by chemical vapor deposition process to obtain a passivated substrate;

[0009] The passivated substrate is sliced ​​to obtain a plurality of edge-passivated silicon wafers.

[0010] In one embodiment, the chemical vapor deposition process is used to passivate the side of the original substrate to obtain a passivated substrate, including:

[0011] Performing shielding treatment on the upper surface and the lower surface of the original substrate respectively;

[0012] The side of the original substrate after shielding is passivated by using a chemical vapor deposition process to obtain a passivated substrate.

[0013] In one embodiment, the above-mentioned providing of the original substrate includes:

[0014] Provide multiple raw silicon wafers;

[0015] stacking a plurality of original silicon wafers, and using the stacked original silicon wafers as original substrates;

[0016] Correspondingly, the passivated substrate is sliced ​​to obtain a plurality of edge passivated silicon wafers, including:

[0017] The passivated substrate is split to obtain a plurality of edge passivated silicon wafers.

[0018] In one embodiment, before stacking the plurality of original silicon wafers, the method further comprises:

[0019] Each original silicon wafer is sequentially cleaned and polished.

[0020] In one embodiment, the above-mentioned providing of the original substrate includes:

[0021] Providing a square-cut silicon block as an original substrate;

[0022] Correspondingly, the passivated substrate is sliced ​​to obtain a plurality of edge passivated silicon wafers, including:

[0023] The passivated substrate is cut to obtain a plurality of edge-passivated silicon wafers.

[0024] In a second aspect, the present application also provides a battery preparation method, comprising:

[0025] Performing texturing treatment on the edge passivated silicon wafer to obtain a silicon wafer with texturing;

[0026] Performing deposition processing on the velvet-bearing silicon wafer to obtain a target silicon wafer;

[0027] Electrodes are printed on both surfaces of the target silicon wafer using a screen printing process to form a battery.

[0028] In one embodiment, the above-mentioned deposition process is performed on the velvet silicon wafer to obtain the target silicon wafer, including:

[0029] An intrinsic amorphous silicon layer, a doped amorphous silicon layer and a transparent conductive oxide layer are sequentially deposited on two surfaces of the velvet silicon wafer to obtain a target silicon wafer.

[0030] In one embodiment, the above-mentioned deposition process is performed on the velvet silicon wafer to obtain the target silicon wafer, including:

[0031] An intrinsic tunneling oxide layer, a doped polysilicon layer and a passivation contact layer are sequentially deposited on two surfaces of the velvet silicon wafer to obtain a target silicon wafer.

[0032] In one embodiment, the above-mentioned texturing treatment of the edge passivated silicon wafer to obtain the silicon wafer with texturing includes:

[0033] Cleaning the edge passivated silicon wafer;

[0034] The cleaned edge passivated silicon wafer is subjected to texturing treatment to obtain a silicon wafer with texturing.

[0035] In one embodiment, the above-mentioned texturing treatment is performed on the cleaned edge passivated silicon wafer to obtain a silicon wafer with texturing, including:

[0036] The front and back sides of the cleaned edge passivated silicon wafer are respectively subjected to texturing treatment to form a velvet surface with a pyramid velvet structure on the front and back sides of the cleaned edge passivated silicon wafer.

[0037] In one embodiment, the above-mentioned texturing treatment is performed on the cleaned edge passivated silicon wafer to obtain a silicon wafer with texturing, including:

[0038] Performing a texturing process on the front side of the cleaned edge passivated silicon wafer to form a velvet surface with a pyramid velvet structure on the front side of the cleaned edge passivated silicon wafer;

[0039] The back side of the edge passivated silicon wafer after the front side is textured is polished to form a polished surface on the back side of the edge passivated silicon wafer after the front side is textured.

[0040] The above-mentioned silicon wafer passivation method and battery preparation method first provide an original substrate; then, use a chemical vapor deposition process to passivate the side of the original substrate to obtain a passivated substrate; finally, slice the passivated substrate to obtain multiple edge-passivated silicon wafers; in this method, by using a chemical vapor deposition process to individually passivate the side of the original substrate, a uniform passivation layer can be formed on the edge of the silicon wafer, and the passivated edge not only reduces the charge recombination rate, but also improves the mechanical and chemical stability of the edge of the silicon wafer. Edge-passivated silicon wafers have higher corrosion resistance and heat resistance, and show better durability in subsequent high-temperature annealing, packaging and other processes, which prolongs the service life of the battery and reduces losses in the production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 Schematic diagram of a silicon wafer passivation method according to an embodiment;

[0043] Figure 2 A schematic diagram of a structure in which an original substrate is used as a shielding layer in an embodiment;

[0044] Figure 3 is a schematic flow chart of a silicon wafer passivation method according to another embodiment;

[0045] Figure 4 A schematic diagram of a structure in which a shielding material is used as a shielding layer in an embodiment;

[0046] Figure 5 is a schematic flow chart of a silicon wafer passivation method according to another embodiment;

[0047] Figure 6 A schematic diagram of a process for preparing a battery in one embodiment;

[0048] Figure 7 is a schematic flow chart of a battery preparation method in another embodiment;

[0049] Figure 8 FIG. 4 is a schematic flow chart of a battery preparation method in another embodiment. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] First of all, before specifically introducing the technical solutions of the embodiments of the present application, the technical background or technical evolution context on which the embodiments of the present application are based is introduced. In the research and development and production of battery cells and components, the battery edge problem has become a key challenge that cannot be ignored. Since the edge area of ​​the battery is often subjected to large stress and temperature fluctuations, its physical and chemical structure is prone to change, resulting in frequent edge defects. These defects include recombination and PL blackening, which seriously affect the overall performance of the battery. In addition, defects in the edge area may increase the risk of battery leakage and provide a channel for the invasion of water vapor and other chemical components, thereby accelerating the aging process of the battery and shortening its life.

[0052] To solve these problems, the effective implementation of passivation and protection strategies is particularly important, especially in the protection of edge areas. In traditional technical solutions, wrap-around plating technology and organic colloid passivation are two commonly used treatment methods. Wrap-around plating technology forms a dense protective film by evenly attaching the coating material to the target surface, thereby enhancing the material's resistance to environmental stress. Organic colloid passivation forms a barrier by coating a layer of organic substance on the edge of the silicon wafer to prevent the external environment (such as moisture and chemical components) from corroding the edge of the battery. However, although these two methods have improved the passivation effect of the edge to a certain extent, there is a problem of poor passivation effect.

[0053] Based on the above analysis, if Figure 1 As shown, a silicon wafer passivation method is provided, which may include the following steps:

[0054] Step 101, providing an original substrate.

[0055] The original substrate refers to unprocessed silicon wafers, usually single crystal or multi-crystalline silicon wafers used in photovoltaic cell manufacturing.

[0056] In the embodiment of the present application, first, the original substrate needs to undergo a preliminary inspection. The first is an appearance inspection to ensure that there are no cracks, scratches or other physical defects on the surface of the original substrate. At the same time, electrical performance testing is also required to measure parameters such as the resistivity and minority carrier lifetime of the original substrate to ensure that its electrical performance meets the manufacturing requirements of photovoltaic cells.

[0057] Subsequently, the original substrate is cleaned to remove oxides, metal ions and other contaminants on the surface. Chemical cleaning methods are usually used, using special cleaning agents such as hydrofluoric acid and nitric acid for surface cleaning, and ultrasonic cleaning is used to further remove tiny particles attached to the surface of the original substrate.

[0058] The original substrate after cleaning needs to be dried quickly using dust-free air drying or nitrogen blowing technology to avoid water stains.

[0059] Step 102: Passivate the side of the original substrate using a chemical vapor deposition process to obtain a passivated substrate.

[0060] Among them, Chemical Vapor Deposition (CVD) is a process that uses gaseous chemical reactions to deposit solid thin films on the surface of a substrate under high temperature conditions. This process is often used to form a thin film layer on the surface of materials such as semiconductors and photovoltaic cells to achieve surface passivation or other functional coatings. Passivation treatment refers to the deposition of a protective film on the surface of the material to reduce the interaction between the original substrate and the external environment, thereby reducing surface charge recombination losses. Side passivation specifically refers to the passivation treatment of the side of the original substrate to reduce the impact of surface defects on electrical properties, thereby helping to improve the photoelectric conversion efficiency. A passivated substrate refers to a silicon wafer substrate that has been passivated.

[0061] In the embodiment of the present application, it is first necessary to place the cleaned and dried original substrate into a chemical vapor deposition device so that its side is exposed to the deposition area of ​​the reaction gas so that the passivation layer can be evenly covered on the side of the original substrate. During the chemical vapor deposition process, by introducing a specific reaction gas (such as silane or other silicon-containing gas), the gas is decomposed by plasma or thermal excitation, and the generated active silicon atoms are deposited layer by layer on the side of the original substrate to form a passivation layer, thereby obtaining a passivated substrate. The deposited passivation layer is usually a material such as silicon nitride or silicon oxide, which has good insulation and passivation properties, and can effectively reduce the charge recombination effect on the side of the silicon wafer, thereby improving the overall electrical performance of the photovoltaic cell.

[0062] After deposition, the passivation substrate needs to undergo temperature-controlled annealing to further optimize the physical structure of the film and enhance the passivation effect. After the deposition and annealing process is completed, the passivation substrate needs to be quality inspected to ensure that the thickness, uniformity and surface defects of the passivation layer of the passivation substrate meet the requirements.

[0063] In some embodiments, Figure 2 As shown, Figure 2 It is a schematic diagram of the structure using the original substrate as a shielding layer. When the side of the original substrate is passivated, the key point of the passivation layer is to ensure that the sides of the original substrate are evenly covered with the passivation layer. Therefore, the top and bottom of the original substrate 01 can be used as natural shielding layers to effectively protect these two sides from being covered by the passivation material during the deposition process, so that the passivation layer 02 is formed on the sides.

[0064] Step 103, slice the passivated substrate to obtain a plurality of edge-passivated silicon wafers.

[0065] Among them, the slicing process refers to dividing the passivated substrate into multiple smaller units, that is, multiple edge passivated silicon wafers. The edge passivated silicon wafer is a passivated substrate after slicing, and its edges have been passivated. These edge passivated silicon wafers have higher photoelectric conversion efficiency and lower surface recombination loss in photovoltaic cell manufacturing.

[0066] In the embodiment of the present application, first, the passivation substrate is placed in the corresponding processing equipment and ensured to be stable and easy to operate. Next, the passivation substrate is sliced ​​according to the preset specifications and sizes using a slicing process. After the slicing is completed, each edge passivation silicon wafer can be preliminarily cleaned to remove residues and tiny particles generated during the processing. Finally, a plurality of edge passivation silicon wafers are obtained.

[0067] In the above silicon wafer passivation method, first, an original substrate is provided; then, the side of the original substrate is passivated by a chemical vapor deposition process to obtain a passivated substrate; finally, the passivated substrate is sliced ​​to obtain multiple edge-passivated silicon wafers; in this method, by using a chemical vapor deposition process to individually passivate the side of the original substrate, a uniform passivation layer can be formed on the edge of the silicon wafer, and the passivated edge not only reduces the charge recombination rate, but also improves the mechanical and chemical stability of the edge of the silicon wafer. Edge-passivated silicon wafers have higher corrosion resistance and heat resistance, and show better durability in subsequent high-temperature annealing, packaging and other processes, which prolongs the service life of the battery and reduces losses in the production process.

[0068] In some embodiments of the present application, Figure 3 As shown, in the above embodiment, “passivating the side of the original substrate by a chemical vapor deposition process to obtain a passivated substrate” may include the following steps:

[0069] Step 201 , performing shielding processing on the upper surface and the lower surface of the original substrate respectively.

[0070] In the embodiments of the present application, Figure 4 As shown, Figure 4 In order to use the shielding material as a structural diagram of the shielding layer, according to the specific size and shape of the original substrate, a suitable high temperature resistant and chemical corrosion resistant material is selected for shielding to ensure that only the side of the original substrate is exposed in the deposition area during the chemical vapor deposition process. Common shielding materials 03 may include quartz plates or other special shielding tools.

[0071] Step 202: Passivate the side of the original substrate after shielding by using a chemical vapor deposition process to obtain a passivated substrate.

[0072] In the embodiment of the present application, after the shielding process is completed, the original substrate is sent to the chemical vapor deposition equipment for a separate passivation process on the side. At this time, by controlling the gas flow, temperature and reaction pressure, it is ensured that the passivation layer can be evenly deposited on the side. In a high temperature environment, the reaction gas decomposes, and the generated active substances react with the side of the silicon wafer to form a passivation layer such as silicon nitride or silicon oxide layer by layer.

[0073] After the passivation layer is deposited, annealing is performed to further optimize the physical and chemical properties of the passivation layer. Annealing is usually performed at a higher temperature to eliminate stress in the passivation layer, improve its structural density, and enhance the passivation effect, thereby improving the ability to suppress charge recombination. After the deposition and annealing process, the passivation substrate will be removed and the shielding material will be removed.

[0074] In the above embodiment, by shielding the upper and lower surfaces, the deposition of passivation material on the front and back sides of the original substrate during the chemical vapor deposition process can be effectively reduced, thereby focusing on the separate passivation treatment of the side surfaces of the original substrate.

[0075] In some embodiments of the present application, Figure 5 As shown, the "providing an original substrate" in the above embodiment may include the following steps:

[0076] Step 301, providing a plurality of original silicon wafers.

[0077] The original substrate may be a plurality of original silicon wafers.

[0078] In the embodiment of the present application, it is first necessary to provide a plurality of original silicon wafers that have been cleaned and dried. These original silicon wafers are usually tested for appearance and electrical properties to ensure that there are no physical defects on their surfaces and that they meet the requirements of subsequent processes. The thickness, size and other physical parameters of each original silicon wafer also need to be confirmed to achieve precise alignment and stable stacking during the stacking process.

[0079] Step 302 , stacking a plurality of original silicon wafers, and using the stacked original silicon wafers as original substrates.

[0080] Correspondingly, the passivation substrate is sliced ​​to obtain a plurality of edge-passivated silicon wafers, including: the passivation substrate is sliced ​​to obtain a plurality of edge-passivated silicon wafers.

[0081] In this embodiment, a plurality of original silicon wafers need to be stacked flatly in sequence to ensure that the original silicon wafers remain aligned.

[0082] In order to prevent mechanical stress or friction damage that may be caused during the stacking process, in some embodiments, a protective pad or a specific supporting material can be used to protect each layer of silicon wafers and ensure that the overall structure after stacking has good stability. After the stacking is completed, the original silicon wafer will be used as the overall substrate for subsequent processing.

[0083] Subsequently, the stacked original silicon wafers enter the chemical vapor deposition process. In this process, reactive gases such as silane, ammonia or oxygen are introduced into the reaction chamber and decomposed under high temperature. Active substances are gradually deposited on the sides of multiple original silicon wafers to form a passivation layer. Since the upper and lower surfaces of the entire stacked substrate are blocked, the passivation layer is only deposited on the sides, so that the passivation effect is focused on the edge area.

[0084] Correspondingly, after the passivation treatment is completed, the passivation substrate is split. Through the slicing process, the passivation substrate is separated one by one to obtain a plurality of edge passivated silicon wafers. After the slicing is completed, each edge passivated silicon wafer has an edge passivation layer.

[0085] In the above embodiment, by stacking multiple original silicon wafers and passivating them as a whole substrate, multiple original silicon wafers can be processed simultaneously in one process, which increases the processing capacity of the production line, reduces the time and equipment required for single-wafer operation, and thus improves the overall production efficiency. In addition, by stacking the original silicon wafers as a whole substrate, the passivation treatment can be performed on the sides of a batch of original silicon wafers at the same time, which realizes the batch process compared to passivating the side of each original silicon wafer separately, which not only shortens the process time, but also simplifies the production process and reduces repeated process operations.

[0086] In some embodiments of the present application, before “stack-stacking multiple original silicon wafers” in the above embodiment, the method may further include the following steps:

[0087] Each original silicon wafer is sequentially cleaned and polished.

[0088] Among them, the purpose of polishing is to further improve the smoothness of the silicon wafer surface and reduce the micro-roughness, thereby providing ideal surface conditions for the subsequent passivation process.

[0089] In an embodiment of the present application, first, a solution such as hydrofluoric acid, nitric acid or sodium hydroxide is used to remove organic matter, metal ions, oxides and other contaminants remaining on the surface of the original silicon wafer. After cleaning, the original silicon wafer can be ultrasonically cleaned to further remove tiny particles that may be attached to the surface. Ultrasonic cleaning uses high-frequency sound wave vibrations to form tiny bubbles in the liquid, and the particles are removed by the rapid bursting of these bubbles. After the ultrasonic cleaning is completed, the original silicon wafer will be rinsed with pure water to thoroughly remove any residual chemicals so that no contaminants remain on its surface.

[0090] After cleaning, the chemical mechanical polishing process is used to process the original silicon wafer surface at the micron level by combining the dual effects of chemical etching and mechanical grinding. After polishing, the original silicon wafer surface will achieve high smoothness, uniform thickness and good crystal structure.

[0091] In some embodiments, the original silicon wafer may be rinsed with pure water and dried again to ensure that it is not contaminated before subsequent processes.

[0092] In the above embodiment, impurities, oxides, metal ions and other contaminants on the surface of the original silicon wafer can be removed by cleaning. Polishing further optimizes the flatness of the surface of the original silicon wafer, eliminates microscopic surface roughness, and makes the surface of the original silicon wafer more uniform and smooth, which is conducive to the uniform attachment of the subsequent passivation layer or deposition layer. Cleaning and polishing provide ideal substrate conditions for the subsequent passivation treatment. After cleaning and polishing, the surface of the original silicon wafer can better accept the coverage of the passivation material.

[0093] In some embodiments of the present application, the “providing an original substrate” in the above embodiments may include the following steps:

[0094] A square-cut silicon block is provided as a raw substrate.

[0095] Correspondingly, the passivation substrate is sliced ​​to obtain a plurality of edge-passivated silicon wafers, including: the passivation substrate is cut to obtain a plurality of edge-passivated silicon wafers.

[0096] Among them, the squared silicon block is a polycrystalline or single-crystalline silicon material that has been preliminarily processed and has a regular geometric shape and appropriate size to facilitate subsequent passivation and slicing processing.

[0097] In the embodiment of the present application, a square-cut silicon block is first provided as an original substrate. At this stage, the silicon block needs to be inspected for quality, including its surface finish, volume uniformity, and integrity of crystal structure.

[0098] After the passivation process is completed, the next step is to cut the passivated substrate to obtain multiple edge passivated silicon wafers. During the wire sawing process, a cutting wire containing an abrasive is used to move at high speed to evenly divide the passivated substrate into thin slices.

[0099] In some embodiments, in order to reduce the damage of cutting stress to the structure of the passivated substrate, a cooling system is usually introduced into the process to reduce the temperature of the cutting area and the accumulation of thermal stress by continuously supplying cooling liquid during the cutting process.

[0100] After cutting, the edge passivated silicon wafer needs to be cleaned to remove residual coolant and cutting debris. The cleaning process usually combines ultrasonic cleaning with pure water rinsing to ensure that the surface of the edge passivated silicon wafer is clean and free of contamination. After cleaning, the edge passivated silicon wafer needs to be dried to avoid water stains or contaminants on the surface.

[0101] In the above embodiment, using a squared silicon block as the original substrate can ensure that the passivation material does not penetrate into the gaps of the silicon wafer during the cutting process, thereby improving the passivation effect on the side of the original substrate.

[0102] A detailed embodiment is given below to illustrate the process of the silicon wafer passivation method in the present application. Based on the above embodiment, the implementation process of the method may include the following contents:

[0103] Step 1: provide a plurality of original silicon wafers.

[0104] Step 2: Clean and polish each original silicon wafer in turn.

[0105] Step 3, stacking multiple original silicon wafers and using the stacked original silicon wafers as original substrates.

[0106] Step 4, performing shielding treatment on the upper surface and the lower surface of the original substrate respectively.

[0107] Step 5: Passivate the side of the original substrate after shielding by using a chemical vapor deposition process to obtain a passivated substrate.

[0108] Step 6: split the passivated substrate to obtain a plurality of edge-passivated silicon wafers.

[0109] Another detailed embodiment is given below to illustrate the process of the silicon wafer passivation method in the present application. Based on the above embodiment, the implementation process of the method may include the following contents:

[0110] Step 1: providing a square-cut silicon block as an original substrate.

[0111] Step 2, performing shielding treatment on the upper surface and the lower surface of the original substrate respectively.

[0112] Step 3: Passivate the side of the original substrate after shielding by using a chemical vapor deposition process to obtain a passivated substrate.

[0113] Step 4: cutting the passivated substrate to obtain a plurality of edge passivated silicon wafers.

[0114] In an exemplary embodiment, Figure 6 As shown, a method for preparing a battery is provided, which may include the following steps:

[0115] Step 401, performing texturing treatment on the edge passivated silicon wafer to obtain a texturized silicon wafer.

[0116] The purpose of the texturing process is to reduce light reflection by forming a micron-scale pyramid structure on the surface of the silicon wafer.

[0117] In the embodiment of the present application, the edge passivated silicon wafer is immersed in an alkaline solution composed of sodium hydroxide or potassium hydroxide solution for chemical etching. By controlling the appropriate solution concentration, temperature and time, a regular velvet structure is formed on the surface of the edge passivated silicon wafer. After the velvet is completed, the edge passivated silicon wafer needs to be cleaned with pure water and dried to ensure that there are no residual chemical reagents or impurities on the surface to obtain a velvet silicon wafer.

[0118] Step 402, performing deposition processing on the velvet-coated silicon wafer to obtain a target silicon wafer.

[0119] In the embodiment of the present application, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are respectively deposited on the surface of the silicon wafer using chemical vapor deposition technology to obtain the target silicon wafer. The intrinsic amorphous silicon layer and the doped amorphous silicon layer are used to passivate the surface of the silicon wafer and provide necessary electrical properties.

[0120] It should be noted that during the deposition process, the gas flow rate, temperature and pressure need to be strictly controlled to ensure the uniformity and quality of the intrinsic amorphous silicon layer and the doped amorphous silicon layer.

[0121] Step 403, using a screen printing process to print electrodes on two surfaces of the target silicon wafer to form a battery.

[0122] In the embodiment of the present application, first, the gate electrode is printed on the front side (light-exposed side) of the target silicon wafer. The gate electrode is usually made of silver paste material to ensure good conductivity and low resistivity. The printing process uses a precision screen template to evenly coat the silver paste on the surface of the target silicon wafer, and then the silver paste is solidified through baking and sintering steps to form a stable electrode structure.

[0123] Next, a back electrode is printed on the back of the target silicon wafer, usually using aluminum paste material to provide an effective current collection path. After completing electrode printing and sintering, a battery is obtained.

[0124] In the above embodiment, by performing a texturing treatment on the edge passivated silicon wafer, the surface reflectivity can be significantly reduced and the light absorption efficiency can be improved. After the passivation layer is deposited on the velvet silicon wafer, the recombination probability of the carriers on the surface of the velvet silicon wafer is effectively reduced, and the minority carrier lifetime is further improved, thereby enhancing the photoelectric performance of the battery. The metal electrodes are printed on the front and back sides of the target silicon wafer respectively by using the screen printing process. Since the screen printing process has the advantages of high precision and low cost, it can achieve uniform and stable electrode printing, ensuring the consistency of electrode thickness and conductivity.

[0125] In some embodiments of the present application, the method of “performing deposition treatment on the velvet-carrying silicon wafer to obtain a target silicon wafer” in the above embodiment may further include the following steps:

[0126] An intrinsic amorphous silicon layer, a doped amorphous silicon layer and a transparent conductive oxide layer are sequentially deposited on two surfaces of the velvet silicon wafer to obtain a target silicon wafer.

[0127] In the embodiment of the present application, when the deposition process is performed on the two surfaces of the velvet silicon wafer, the intrinsic amorphous silicon layer needs to be deposited in sequence first. This step adopts a plasma enhanced chemical vapor deposition process, using silane gas as a silicon source, decomposing silicon atoms in the gas under high temperature and plasma conditions, and making them evenly deposited on the surface of the velvet silicon wafer. Among them, the main function of the intrinsic amorphous silicon layer is to passivate the defect state on the surface of the silicon wafer, reduce the interface charge recombination phenomenon, and ensure that the electrical performance of the target silicon wafer surface is improved.

[0128] After the deposition of the intrinsic amorphous silicon layer is completed, the doped amorphous silicon layer is deposited on its surface. The layer is doped with impurity atoms introduced by doping gas (such as phosphine or borane) to form a semiconductor material with n-type or p-type conductivity. The function of the doped amorphous silicon layer is to provide a suitable potential difference for the photovoltaic cell, forming a pn junction or back electric field to ensure the effective flow of current.

[0129] After the amorphous silicon layer is deposited, a transparent conductive oxide layer, such as indium tin oxide or zinc oxide, is further deposited on the surface of the target silicon wafer using magnetron sputtering or chemical vapor deposition technology.

[0130] Among them, the transparent conductive oxide layer has excellent light transmittance and conductivity, which can not only allow light to enter the battery for photoelectric conversion, but also serve as an electrode to collect and conduct current.

[0131] Through the sequential deposition of the intrinsic amorphous silicon layer, the doped amorphous silicon layer and the transparent conductive oxide layer, the functional structure of the surface of the velvet silicon wafer is constructed, and finally the target silicon wafer with photoelectric conversion function is formed.

[0132] In the above embodiment, by depositing an intrinsic amorphous silicon layer, the passivation layer formed can effectively reduce the recombination rate on the surface of the fleece silicon wafer. The deposited intrinsic amorphous silicon layer can capture and limit the movement of surface carriers, reducing the recombination of photogenerated carriers. The deposition of the doped amorphous silicon layer can adjust the conductivity of the fleece silicon wafer, making it more suitable for the current conduction requirements of the battery. The deposition of the transparent conductive oxide layer can not only serve as an electrode layer, but also ensure that light effectively enters the fleece silicon wafer. The process design of sequentially depositing the intrinsic amorphous silicon layer, the doped amorphous silicon layer and the transparent conductive oxide layer significantly improves the photoelectric performance, reduces the recombination rate, and optimizes the conductivity.

[0133] In some embodiments of the present application, the method of “performing deposition treatment on the velvet-carrying silicon wafer to obtain a target silicon wafer” in the above embodiment may further include the following steps:

[0134] An intrinsic tunneling oxide layer, a doped polysilicon layer and a passivation contact layer are sequentially deposited on two surfaces of the velvet silicon wafer to obtain a target silicon wafer.

[0135] In the embodiment of the present application, thermal oxidation or chemical vapor deposition process is first used to react oxygen or water vapor with the surface of the velvet silicon wafer to form an extremely thin intrinsic tunneling oxide layer. The thickness of the intrinsic tunneling oxide layer is usually controlled between 1 and 2 nanometers, and its main function is to form a tunneling effect, allowing electrons or holes to pass through without generating interface recombination, and at the same time, it has a good passivation effect on the surface of the velvet silicon wafer.

[0136] After the intrinsic tunneling oxide layer is deposited, a low-pressure chemical vapor deposition process is then used, using silane gas as a silicon source, which is decomposed at a relatively low temperature to form a doped polysilicon layer.

[0137] It should be noted that in order to form a p-type or n-type doped layer with good conductivity, a doping gas (such as phosphine or borane) is introduced during the deposition process to dope the doped polysilicon layer with an appropriate amount of impurities to provide the required conductivity. Among them, the role of the doped polysilicon layer is to construct a low-resistance contact layer on the basis of the tunneling oxide layer to ensure that electrons or holes can be smoothly transmitted to the electrode area.

[0138] After the doped polysilicon layer is deposited, a passivation contact layer needs to be further deposited on its surface. This layer is usually made of transparent conductive oxide (such as indium tin oxide or zinc oxide) or silicon nitride and is deposited by magnetron sputtering or chemical vapor deposition.

[0139] By sequentially depositing an intrinsic tunneling oxide layer, a doped polysilicon layer, and a passivation contact layer, the surface structure of the velvet-coated silicon wafer is optimized, and ultimately a target silicon wafer with high-efficiency photoelectric conversion performance is obtained.

[0140] In the above embodiment, the deposition of the intrinsic tunneling oxide layer can effectively form an electric field and promote the separation of photogenerated carriers. The intrinsic tunneling oxide layer has a high electron and hole tunneling rate, which helps to reduce carrier recombination and improve the photoelectric conversion efficiency. The deposition of the doped polysilicon layer enables the photovoltaic cell to form a high-quality PN junction, which can improve the mobility of carriers, thereby enhancing the output current and voltage performance of the battery. The passivation contact layer can effectively reduce the recombination of photogenerated carriers and improve the photoelectric performance.

[0141] In an exemplary embodiment, Figure 7 As shown, in the above embodiment, "texturing the edge passivated silicon wafer to obtain a velvet silicon wafer", the method may also include the following steps:

[0142] Step 501, cleaning the edge passivated silicon wafer.

[0143] In the embodiment of the present application, when cleaning the edge passivated silicon wafer, surface pretreatment is first required to remove oxides, metal ions and other tiny contaminants that may exist on the surface of the edge passivated silicon wafer. Among them, the common cleaning process uses chemical wet cleaning, using solutions such as hydrofluoric acid or nitric acid to remove the oxide layer and particles on the surface.

[0144] After cleaning, the edge passivated silicon wafer surface needs to be dried to prevent residual water stains from causing secondary contamination to the edge passivated silicon wafer surface. The drying method usually uses nitrogen drying or dust-free air drying technology.

[0145] Step 502, performing texturing on the cleaned edge passivated silicon wafer to obtain a texturized silicon wafer.

[0146] In the embodiment of the present application, fine structures are formed on the surface of the cleaned edge passivated silicon wafer by chemical etching to increase the incident angle of light and reduce the surface reflectivity, thereby improving the photoelectric conversion efficiency. Among them, the commonly used texturing process is to use an alkaline solution (such as potassium hydroxide or ethanol aqueous solution) to anisotropically etch the surface of the cleaned edge passivated silicon wafer. The alkaline solution reacts with the silicon material to form a micron-scale structure on the surface of the silicon wafer, thereby obtaining a velvet-covered silicon wafer.

[0147] In the above embodiments, the cleaning process can effectively remove dirt, grease, particles and chemical residues on the surface of the edge passivated silicon wafer, ensuring that the surface of the edge passivated silicon wafer is clean, which can reduce defects in subsequent texturing and deposition processes and improve the overall quality of the edge passivated silicon wafer. The texturing process can significantly improve the light absorption capacity of the velvet silicon wafer.

[0148] In an exemplary embodiment, the method of “texturing the cleaned edge passivated silicon wafer to obtain a velvet silicon wafer” in the above embodiment may further include the following steps:

[0149] The front and back sides of the cleaned edge passivated silicon wafer are respectively subjected to texturing treatment to form a velvet surface with a pyramid velvet structure on the front and back sides of the cleaned edge passivated silicon wafer.

[0150] In the embodiment of the present application, the cleaned edge passivated silicon wafer is first placed in a specific texturing reaction tank, and it is ensured that the front and back sides of the cleaned edge passivated silicon wafer are exposed to the chemical etching solution at the same time.

[0151] In the texturing process, the temperature, concentration and reaction time of the solution must be regulated to ensure that the size and density of the pyramid structure meet the expected design requirements. The alkaline solution will preferentially corrode specific crystal planes on the edge passivation silicon wafer surface, thereby forming pyramid-shaped microstructures with low reflectivity. These pyramid-shaped microstructures can effectively increase the absorption angle of incident light, reduce light reflection, and improve the photoelectric conversion efficiency of photovoltaic cells.

[0152] It should be noted that during the entire texturing process, the front and back sides of the edge passivated silicon wafer should always be evenly immersed and reacted to avoid uneven texture structure due to uneven local solution concentration or temperature. At the same time, after the texturing reaction is completed, the edge passivated silicon wafer needs to be quickly cleaned to remove the residual etching solution to prevent excessive corrosion or side reactions from causing adverse effects on the texture structure.

[0153] After cleaning, the edge passivated silicon wafer will be thoroughly dried by dust-free gas drying or hot air drying to ensure that no moisture or residue remains on the surface to avoid affecting the implementation of subsequent processes. Finally, after a precisely controlled texturing process, a uniform pyramid texture structure is formed on both the front and back sides of the edge passivated silicon wafer.

[0154] In the above embodiment, the pyramid velvet structure can effectively increase the scattering and absorption of light. When light is incident, the pyramid velvet structure will cause the light to be reflected and refracted multiple times, thereby increasing the effective absorption rate of light, and further significantly improving the photoelectric conversion efficiency of the edge passivated silicon wafer.

[0155] In an exemplary embodiment, Figure 8 As shown, in the above embodiment, "the cleaned edge passivated silicon wafer is subjected to texturing to obtain a silicon wafer with texturing", the method may further include the following steps:

[0156] Step 601 , performing texturing treatment on the front side of the cleaned edge passivated silicon wafer to form a velvet surface with a pyramid velvet structure on the front side of the cleaned edge passivated silicon wafer.

[0157] In the embodiment of the present application, when the cleaned edge passivated silicon wafer is subjected to front texturing, the silicon wafer is first placed in a specific texturing reaction tank to ensure that its front side is completely immersed in a pre-configured etching solution. The etching solution is generally an alkaline solution, such as potassium hydroxide, which forms a pyramid-shaped microstructure by utilizing its anisotropic corrosion characteristics on specific crystal planes on the surface of the edge passivated silicon wafer.

[0158] After the texturing process is completed, the silicon wafer needs to be quickly removed from the etching solution and thoroughly cleaned with deionized water to remove residual chemicals. Subsequently, it is dried with dust-free gas or hot air to ensure that the front surface texture structure is dry to prevent moisture from affecting subsequent processes.

[0159] Step 602, polishing the back side of the edge passivated silicon wafer after the front side is textured, so as to form a polished surface on the back side of the edge passivated silicon wafer after the front side is textured.

[0160] In the embodiment of the present application, after the front surface is textured, the back side of the edge passivated silicon wafer is polished. This step usually adopts a chemical mechanical polishing process, and the back side is evenly polished by using a polishing slurry and a polishing pad to form a smooth polished surface. The key in the polishing process is to control the flow rate, pressure and polishing time of the polishing slurry to ensure that the flatness and finish of the back side after polishing meet the requirements.

[0161] In the above-mentioned embodiment, the pyramid velvet structure on the front side can significantly improve the light absorption rate. The structure can effectively scatter the incident light and increase the number of light reflections inside the edge passivated silicon wafer, thereby improving the generation rate of photogenerated carriers and enhancing the photoelectric conversion efficiency. The velvet treatment can reduce the light reflectivity of the edge passivated silicon wafer. The geometric shape of the pyramid structure can guide light into the edge passivated silicon wafer, reduce the reflection loss of light, and allow more light energy to be effectively absorbed. The back side after the front side is velveted is polished to form a smooth polished surface on the back side. This smooth surface helps to improve the deposition quality of the back electrode, enhance the bonding between the back electrode and the silicon wafer, reduce the occurrence of interface defects, and improve the overall performance of the battery.

[0162] Another detailed embodiment is given below to illustrate the process of the battery preparation method in the present application. Based on the above embodiment, the implementation process of the method may include the following contents:

[0163] Step 1: Clean the edge passivated silicon wafer.

[0164] Step 2, performing texturing treatment on the cleaned edge passivated silicon wafer to obtain a texturing silicon wafer.

[0165] In some embodiments, the front and back sides of the cleaned edge passivated silicon wafer are subjected to texturing treatment respectively to form a velvet surface with a pyramid velvet structure on the front and back sides of the cleaned edge passivated silicon wafer.

[0166] In some embodiments, the front side of the edge passivated silicon wafer after cleaning is subjected to a texturing treatment to form a velvet surface with a pyramid velvet structure on the front side of the edge passivated silicon wafer after cleaning; and the back side of the edge passivated silicon wafer after the front side is texturized is subjected to a polishing treatment to form a polished surface on the back side of the edge passivated silicon wafer after the front side is texturized.

[0167] Step 3, performing deposition processing on the velvet-coated silicon wafer to obtain a target silicon wafer.

[0168] In some embodiments, an intrinsic amorphous silicon layer, a doped amorphous silicon layer, and a transparent conductive oxide layer are sequentially deposited on two surfaces of a velvet-covered silicon wafer to obtain a target silicon wafer.

[0169] In some embodiments, an intrinsic tunneling oxide layer, a doped polysilicon layer, and a passivation contact layer are sequentially deposited on two surfaces of a velvet-covered silicon wafer to obtain a target silicon wafer.

[0170] Step 4: Print electrodes on both surfaces of the target silicon wafer using a screen printing process to form a battery.

[0171] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0172] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0173] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A silicon wafer passivation method, characterized in that: The method comprises: Provide the original substrate; Passivating the side of the original substrate by chemical vapor deposition process to obtain a passivated substrate; The passivated substrate is sliced ​​to obtain a plurality of edge-passivated silicon wafers.

2. The method according to claim 1, characterized in that The method of passivating the side of the original substrate by using a chemical vapor deposition process to obtain a passivated substrate comprises: Performing shielding treatment on the upper surface and the lower surface of the original substrate respectively; The side of the original substrate after shielding is passivated by using a chemical vapor deposition process to obtain the passivated substrate.

3. The method according to claim 1, characterized in that The providing of the original substrate comprises: Provide multiple raw silicon wafers; stacking a plurality of the original silicon wafers, and using the stacked original silicon wafers as the original substrate; Correspondingly, the passivated substrate is sliced ​​to obtain a plurality of edge-passivated silicon wafers, including: The passivated substrate is split to obtain a plurality of edge passivated silicon wafers.

4. The method according to claim 3, characterized in that Before stacking the plurality of original silicon wafers, the method further comprises: Each of the original silicon wafers is sequentially cleaned and polished.

5. The method according to claim 1, characterized in that The providing of the original substrate comprises: Providing a square-cut silicon block as the original substrate; Correspondingly, the passivated substrate is sliced ​​to obtain a plurality of edge-passivated silicon wafers, including: The passivated substrate is cut to obtain a plurality of edge-passivated silicon wafers.

6. A method for preparing a battery, characterized in that: The method comprises: Performing texturing treatment on the edge passivated silicon wafer to obtain a silicon wafer with texturing; Performing deposition processing on the velvet-covered silicon wafer to obtain a target silicon wafer; Electrodes are printed on two surfaces of the target silicon wafer using a screen printing process to form a battery.

7. The method according to claim 6, characterized in that The step of performing a deposition process on the velvet-covered silicon wafer to obtain a target silicon wafer comprises: An intrinsic amorphous silicon layer, a doped amorphous silicon layer and a transparent conductive oxide layer are sequentially deposited on two surfaces of the velvet-covered silicon wafer to obtain the target silicon wafer.

8. The method according to claim 6, characterized in that The step of performing a deposition process on the velvet-covered silicon wafer to obtain a target silicon wafer comprises: An intrinsic tunneling oxide layer, a doped polysilicon layer and a passivation contact layer are sequentially deposited on two surfaces of the velvet-covered silicon wafer to obtain the target silicon wafer.

9. The method according to claim 6, characterized in that The method of performing texturing on the edge passivated silicon wafer to obtain a silicon wafer with texturing comprises: Cleaning the edge passivated silicon wafer; The cleaned edge passivated silicon wafer is subjected to texturing treatment to obtain the silicon wafer with texturing.

10. The method according to claim 9, characterized in that The step of performing a texturing process on the cleaned edge passivated silicon wafer to obtain the silicon wafer with texturing comprises: The front and back sides of the cleaned edge passivation silicon wafer are respectively subjected to texturing treatment to form a velvet surface with a pyramid velvet structure on the front and back sides of the cleaned edge passivation silicon wafer.

11. The method according to claim 9, characterized in that The step of performing a texturing process on the cleaned edge passivated silicon wafer to obtain the silicon wafer with texturing comprises: Performing a texturing process on the front side of the cleaned edge passivated silicon wafer to form a velvet surface with a pyramid velvet structure on the front side of the cleaned edge passivated silicon wafer; The back side of the edge passivated silicon wafer after the front side is textured is polished to form a polished surface on the back side of the edge passivated silicon wafer after the front side is textured.

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