Solid-state imaging device for coded readout and method of operating same

Abstract

A solid-state imaging device (90) includes a pixel array (11) including pixel circuits (100), and a plurality of column readout circuits (20). Each pixel circuit (100) is assigned to one of the N pixel columns (31) and one of the M pixel rows (32). Each pixel circuit (100) generates a pixel signal including pixel lighting information. Each pixel circuit (100) outputs a pixel signal on the first data signal line (VSL1) or the second data signal line (VSL2) in accordance with the signal level of the row coded signal. Each column readout circuit (20) generates a first code signal by superimposing a pixel signal transmitted on a first data signal line (VSL1), generates a second code signal by superimposing a pixel signal transmitted on a second data signal line (VSL2), and generates a differential signal (DS) from the first code signal and the second code signal.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device having a pixel circuit suitable for a coded readout method. More specifically, the present disclosure relates to encoding pixel signals from a pixel circuit of a two-dimensional pixel array. The present disclosure also relates to a method of operating a solid-state imaging device, and in particular, to a readout method for encoding pixel signals. Background Art

[0002] The image sensor in the solid-state imaging device includes a photoelectric conversion element that generates a photocurrent whose rated current is proportional to the intensity of the received radiation. In an image sensor for intensity readout, the pixel circuit generates a pixel signal based on the photocurrent, and the downstream analog-to-digital converter converts the pixel signal into a digital pixel value. The pixel circuit for event detection sensors (such as dynamic vision sensors (DVS) and event-based vision sensors (EVS)) responds to changes in light intensity, and the image sensor provides information about the location and time of such events in the imaging scene. The photoelectric conversion elements are usually arranged in a two-dimensional pixel array. Regardless of the pixel type and whether a global shutter or a rolling shutter is used for exposure, the pixel circuit of the intensity readout type is usually read out sequentially row by row. A scanning mode for row-by-row readout of pixels for DVS solid-state imaging devices is also described. The readout time of each row and the number of rows determine the frame readout period required to read out a complete image ("frame") from the image sensor and the maximum frame rate at which continuously captured images can be read out.

[0003] As the number of pixel circuits in a pixel array increases, power consumption increases. Using lower operating voltages to reduce power consumption degrades the signal-to-noise ratio (SNR) of pixel readout. In addition, as the number of pixel rows increases, the frame readout period increases and the frame rate decreases. Reducing the readout time for each pixel row to increase the frame rate may have an adverse effect on the readout quality. Summary of the invention

[0004] Nowadays, there is a growing demand for solid-state imaging devices with high frame rates, high image readout SNR, and simple pixel circuits. The present disclosure is made in view of the above circumstances, and therefore it is desirable to provide a solid-state imaging device that enables high frame rates accompanied by high image readout SNR based on a proven and tested pixel circuit design.

[0005] In this regard, the present disclosure relates to a solid-state imaging device, which includes a pixel array and a plurality of column readout circuits. The pixel array includes a pixel circuit, wherein each pixel circuit is assigned to one of N pixel columns and one of M pixel rows. Each pixel circuit generates a pixel signal containing pixel lighting information. Depending on the signal level of the row coding signal, each pixel circuit outputs a pixel signal on a first data signal line or a second data signal line. Each column readout circuit generates a first code signal by superimposing the pixel signal transmitted on the first data signal line, generates a second code signal by superimposing the pixel signal transmitted on the second data signal line, and generates a differential signal from the first code signal and the second code signal.

[0006] The solid-state imaging device enables a method for operating a solid-state imaging device, wherein the method includes sequentially applying a codeword sequence of a binary spread spectrum code matrix with a number L to a pixel column of a two-dimensional pixel array. Each codeword has a code length L and is applied to some or all of the pixel columns simultaneously, wherein all bits of the codeword are applied to different pixel rows of the two-dimensional pixel array simultaneously. Individually for each of the pixel columns and depending on the element value of the binary spread spectrum code matrix received by the pixel circuit, each pixel circuit outputs a pixel signal to a first data signal line or a second data signal line. The method also includes generating a differential signal from a first code signal derived from a pixel signal output to the first data signal line and a second code signal derived from a pixel signal output to the second data signal line.

[0007] For the same group of pixel circuits, repeated readout can be performed using different codewords of a binary spread spectrum code, where multiple different differential signals are obtained from the same pixel signal. Each differential signal contains information about all the original pixel signals of a pixel column. At a later stage, the differential signal can be converted into a digital column signal and the digital column signal can be decoded, where the decoding uses essentially the same binary spread spectrum code matrix as the encoding. During decoding, the digital value is restored for each individual pixel signal. The entire encoding / decoding process provides a CDMA (code division multiple access) readout for the pixel circuit, where the averaging effect of the CDMA readout increases the SNR. In other words, for a given number of readouts of the same pixel signal, the CDMA readout results in a higher SNR.

[0008] The extent of the impact depends on the code length. For example, conventional row-by-row readout requires eight full-frame readout repetitions to achieve the same SNR improvement as a CDMA readout with a binary spread spectrum code with a code length L=8. In other words, to achieve the same SNR as the method according to the present disclosure, the frame rate of the conventional row-by-row readout is only 1 / 8 of the frame rate of the CDMA readout. In addition, transmitting the pixel signal of each pixel circuit on two different data signal lines facilitates the smooth integration of CDMA readout into existing pixel arrays with proven and tested pixel circuit designs.

[0009] The described embodiments, together with further advantages, will be best understood by reference to the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 : is a simplified block diagram illustrating a configuration example of a solid-state imaging device according to an embodiment based on a passive pixel circuit, which provides CDMA readout with two data signal lines per pixel column.

[0011] Figure 2 : is a simplified block diagram illustrating a configuration example of a solid-state imaging device according to an embodiment based on an active pixel circuit, which provides CDMA readout with two data signal lines per pixel column.

[0012] Figure 3 A simplified circuit diagram illustrating a pixel circuit connected to the same data signal line and a simplified timing diagram for encoding a pixel signal according to an embodiment is shown in relation to a passive pixel circuit and a column readout circuit including a differential amplifier with a resistive feedback element.

[0013] Figure 4 A simplified circuit diagram illustrating a pixel circuit connected to the same data signal line according to an embodiment and a simplified timing diagram for encoding a pixel signal are shown in relation to a passive pixel circuit and a column readout circuit including a differential amplifier with a capacitive feedback element.

[0014] Figure 5 A simplified circuit diagram illustrating a pixel circuit connected to the same data signal line and a simplified timing diagram for encoding a pixel signal according to an embodiment is shown in relation to an active pixel circuit and a column readout circuit including a differential amplifier with a capacitive feedback element.

[0015] Figure 6 is a simplified block diagram illustrating encoding pixel signals of a pixel array into column signals and decoding the column signals into original pixel signals according to an embodiment of the present disclosure.

[0016] Figure 7 is a simplified block diagram of a solid-state imaging device according to an embodiment of the present disclosure, which is used to illustrate a readout method including encoding pixel signals of a pixel column into a column signal and decoding the column signal into an original pixel signal.

[0017] Figures 8 to 10 is a simplified block diagram illustrating Figure 7 Block diagram of the different stages of the readout method used.

[0018] Fig.11A and Fig. 11B Different read-out addressing codes for discussing the effects of embodiments of the present disclosure are schematically shown.

[0019] Fig. 12A and Fig. 12B Different read-out addressing codes according to embodiments of the present disclosure are schematically illustrated.

[0020] Fig.13 : is a diagram illustrating an example of a laminated structure of a solid-state imaging device according to an embodiment of the present disclosure.

[0021] Fig.14 is a schematic circuit diagram of elements in an image sensor module formed on one of two chips of a solid-state imaging device having a laminated structure according to an embodiment.

[0022] Fig.15 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0023] Fig.16 It is an auxiliary explanation Fig.15 A diagram showing an example of installation positions of a vehicle exterior information detection portion and an imaging portion of a vehicle control system. DETAILED DESCRIPTION

[0024] The following will describe in detail the embodiments for implementing the technology disclosed herein using the accompanying drawings. The technology disclosed herein is not limited to the described embodiments, and the various numerical values ​​in the embodiments are only illustrative. The same elements or elements with the same functions are represented by the same reference numerals. Repeated descriptions are omitted.

[0025] The connected electronic components may be electrically connected via a direct and permanent low resistance connection (e.g., via a conductive wire). The terms "electrically connected" and "signal connected" may also include connections through other provided electronic components and suitable for permanent and / or temporary signal transmission and / or energy transmission. For example, electronic components may be electrically connected or signal connected via resistors, capacitors, and electronic switches (such as transistors or transistor circuits, e.g., MOSFETs, transmission gates, and others).

[0026] The load path of a transistor is the controlled path of the transistor. For example, a voltage applied to the gate of a field effect transistor (FET) controls the flow of current through the load path between the source and drain of the FET through the field effect.

[0027] Although techniques for coded pixel readout are described below primarily in the context of certain types of image sensors for intensity readout, the techniques may also be used for other types of image sensors, such as EVS and DVS.

[0028] Figure 1 and Figure 2 A configuration example of a solid-state imaging device 90 according to an embodiment of the present technology is illustrated.

[0029] The solid-state imaging device 90 includes a pixel array 11 and a plurality of column readout circuits 20. The pixel array 11 includes a pixel circuit 100, wherein each pixel circuit 100 is assigned to one of the N pixel columns 31 and one of the M pixel rows 32. Each pixel circuit 100 generates a pixel signal containing pixel lighting information. Depending on the signal level of the row encoding signal ES, each pixel circuit 100 outputs a pixel signal on a first data signal line VSL1 or a second data signal line VSL2. Each column readout circuit 20 generates a first code signal by superimposing a pixel signal transmitted on the first data signal line VSL1, generates a second code signal by superimposing a pixel signal transmitted on the second data signal line VSL2, and generates a differential signal DS from the first code signal and the second code signal.

[0030] The same row coding signal is simultaneously applied to multiple pixel circuits 100 of a pixel row 32, for example, to all pixel circuits 100 of the same pixel row 32. Multiple different row coding signals are simultaneously applied to multiple pixel circuits 100 of a pixel column 31, for example, to all pixel circuits 100 of the same pixel column 31 or all pixel circuits 100 of the pixel array 11.

[0031] Each differential signal DS can be obtained by subtracting the first code signal from the second code signal or by subtracting the second code signal from the first code signal. Alternatively, the differential signal DS can be obtained by subtracting the signal derived from the first code signal from the signal derived from the second code signal or by subtracting the signal derived from the second code signal from the signal derived from the first code signal. Each differential signal DS embodies an encoded analog signal containing information about a plurality of pixel signals (e.g., all pixel signals for the same pixel column 31).

[0032] To this end, the pixel array 11 includes a plurality of first data signal lines VSL1 and a plurality of second data signal lines VSL2. Each first data signal line VSL1 electrically connects a first pixel output of a plurality of pixel circuits 100 to a first input of one of the column readout circuits 20. Each second data signal line VSL2 electrically connects a second pixel output of a plurality of pixel circuits 100 to a second input of the same column readout circuit 20.

[0033] More specifically, the pixel array 11 includes a plurality of signal line pairs, each signal line pair including a first data signal line VSL1 and a second data signal line VSL2. Each signal line pair can be assigned to one of the pixel columns 31, and each pixel column 31 can be assigned to a signal line pair, such as Figure 1 and Figure 2 In particular, the first data signal line VSL1 of each signal line pair electrically connects the first pixel output of the pixel circuit 100 of one of the pixel columns 31 with the first input of the column readout circuit 20 assigned to the pixel column 31, and the second data signal line VSL2 of the same signal line pair electrically connects the second pixel output of the pixel circuit 100 of the same pixel column 31 with the second input of the column readout circuit 20 assigned to the pixel column 31.

[0034] Alternatively, one signal line pair may be assigned two or more pixel columns 31 so that the pixel circuits 100 of more than one pixel column 31 output pixel signals to the same signal line pair, or the same pixel column 31 may be assigned two or more signal line pairs so that the pixel circuits 100 of the same pixel column 31 output pixel signals to different signal line pairs.

[0035] Each pixel circuit 100 includes a photoelectric conversion element PD. The photoelectric conversion element PD converts incident electromagnetic radiation into electric charge by the photoelectric effect. The amount of charge generated in the photoelectric conversion element PD is a function of the intensity of the incident electromagnetic radiation. The photoelectric conversion element PD may include or consist of a photodiode, which converts electromagnetic radiation incident on the detection surface into a detector current (photocurrent). The electromagnetic radiation may include visible light, infrared radiation and / or ultraviolet radiation.

[0036] The pixel signal contains pixel lighting information. The pixel lighting information may include information about the radiation intensity and / or about the change of the radiation intensity.

[0037] The pixel circuit 100 may be a passive pixel circuit that outputs a detector current as a pixel signal. Alternatively, the pixel circuit 100 may be an active pixel circuit having at least one pixel transistor in addition to the photoelectric conversion element PD, wherein the pixel signal is obtained by amplifying, converting and / or buffering the detector current. The pixel transistor is a FET, for example, a MOSFET (metal oxide semiconductor FET), and the pixel circuit 100 is configured as any active pixel sensor for intensity readout and / or event detection.

[0038] The pixel array 11 is a two-dimensional pixel array and forms part of the image sensor assembly 10. Each pixel circuit 100 is part of one pixel column 31 and part of one pixel row 32. The pixel circuits 100 associated with the same pixel column 31 may be arranged along a straight line or a meandering line in the horizontal plane of the semiconductor pixel substrate. The pixel circuits 100 associated with the same pixel row 32 may be arranged along a straight line or a meandering line in the horizontal plane of the semiconductor pixel substrate, wherein the pixel row 32 extends substantially orthogonally to the pixel column 31. The number M of pixel circuits 100 per pixel column 31 may be less than, equal to, or greater than the number N of pixel columns 31. The number M of pixel circuits 100 per pixel column 31 is equal to the number of pixel rows 32 in the pixel array 11.

[0039] The pixel circuits 100 of the same pixel row 32 share a common row encoding line EL, such as Figure 1 As shown in , or both the common row encoding line EL and the common row control line RL can be shared, as shown in Figure 2 as shown in .

[0040] The row encoding line EL supplies the row encoding signal ES to the pixel circuits 100. Each row encoding line EL may be electrically connected to some pixel circuits 100 of the pixel row 32 or all pixel circuits 100 of one pixel row 32. One or two row encoding lines EL may be electrically connected to each pixel circuit 100.

[0041] The row encoding signal ES controls whether the pixel circuit 100 outputs the pixel signal to the first data signal line VSL1 via the first pixel output or to the second data signal line VSL2 via the second pixel output in the encoding period.

[0042] If a single row coding signal ES is supplied to the pixel circuit 100, the pixel circuit 100 may output the pixel signal to the first data signal line VSL1 when the voltage level of the row coding signal ES exceeds the voltage threshold, and the pixel circuit 100 may output the pixel signal to the second data signal line VSL2 when the voltage level of the row coding signal ES is lower than the voltage threshold, or vice versa. For example, the row coding signal ES is a binary or ternary signal having an effective high level and an effective low level, and the pixel circuit 100 outputs the pixel signal to the first data signal line VSL1 at the effective high level of the row coding signal ES, and outputs the pixel signal to the second data signal line VSL2 at the effective low level, or vice versa.

[0043] If two row coding signals ES are supplied to the pixel circuit 100, the pixel circuit 100 may output the pixel signal to the first data signal line VSL1 only at the effective voltage level of the first row coding signal, and may output the pixel signal to the second data signal line VSL2 only at the effective voltage level of the second row coding signal. The second row coding signal may be an inverted first row coding signal.

[0044] Each pixel circuit 100 spatially encodes information about the non-inverted or inverted phase of a pixel signal by selecting one of the data signal lines VSL1 and VSL2 to which the pixel signal is forwarded. For example, when the row encoding signal ES is valid, the pixel circuit 100 outputs the pixel signal to the first data signal line VSL1, thereby encoding the pixel signal as a non-inverted pixel signal, and when the row encoding signal ES is invalid, the pixel circuit 100 outputs the pixel signal to the second data signal line VSL2, thereby encoding the pixel signal as an inverted pixel signal.

[0045] Each column readout circuit 20 may include a differential unit 21 that generates a first code signal by superimposing a pixel signal transmitted on a first data signal line VSL1, generates a second code signal by superimposing a pixel signal transmitted on a second data signal line VSL2, and generates an analog differential signal DS from the first code signal and the second code signal.

[0046] The combination of the pixel circuit 100 that outputs a pixel signal on the first data signal line VSL1 or the second data signal line VSL2 depending on the voltage level of one or more row encoding signals ES and the column readout circuit 20 that generates a differential signal of the pixel signal superimposed on the first data signal line VSL1 and the pixel signal superimposed on the second data signal line VSL2 enables a coded readout method. After encoding the same pixel signal using different code words of a suitable binary spreading code, the original pixel signal of each single pixel circuit can be restored from the resulting differential signal by digital signal processing in a later stage without losing the lighting information. For a given frame rate (i.e., the frequency at which the complete image data is obtained at one time), the coded readout method provides a higher SNR than the conventional row-by-row readout method.

[0047] For example, the solid-state imaging device 90 may include an encoding unit 16 that controls the row encoding signal ES according to a binary spread spectrum code matrix having a number L of code words with a code length L, wherein the code length L is equal to or less than the number M of pixel circuits 100 per pixel column 31.

[0048] In particular, the binary spread code matrix may be a square matrix or a non-square matrix having a binary element having a first element value or a second element value different from the first element value. According to an embodiment, the binary spread code matrix is ​​a square matrix to reduce the computational load. For example, the binary spread code matrix is ​​a square matrix having a number L of code words having a code length L. The number L of code words is equal to or less than the number M of pixel circuits 100 per pixel column 31.

[0049] Each codeword is applied to some or all of the pixel circuits 100 simultaneously. The binary spread spectrum code matrix can be a matrix of orthogonal spread spectrum codes, such as a Walsh-Hadamard matrix. In particular, the binary spread spectrum code matrix is ​​a Walsh-Hadamard square matrix having a code length L equal to the number M of pixel circuits 100 per pixel column 31, wherein all pixel rows 32-1, ..., 32-M are addressed and read out simultaneously.

[0050] According to another embodiment, the binary spread spectrum code matrix may include a square matrix, in particular a Walsh-Hadamard matrix, having a code length L smaller than the number M of pixel circuits 100 per pixel column 31. For example, the pixel array may include two or more groups of pixel rows 32-1, …, 32-L, where L < M. The pixel rows in the same group of pixel rows 32-1, …, 32-L are addressed and encoded simultaneously. The groups of pixel rows 32-1, …, 32-L are addressed and encoded sequentially. In particular, during the decoding process, as explained below, the computational load can be reduced. L may be an integer divisor of M.

[0051] The memory unit 17 may store the elements of the binary spread spectrum code matrix. For example, the memory unit 17 may include a memory circuit having a read-only memory unit or a rewritable memory unit. The element values of the binary spread spectrum code matrix may be labeled as “+1” and “−1” and may be directly transformed into a suitable row-encoded signal that varies between two signal levels depending on the element value to be encoded.

[0052] For example, the encoding unit 16 converts the element value “+1” into a first signal level (active level) of a single row-encoded signal ES and converts the element value “−1” into a second signal level (inactive level) of the single row-encoded signal ES, where the first signal level causes the addressed pixel circuit 100 to output a pixel signal on the first data signal line VSL1, and where the second signal level causes the addressed pixel circuit 100 to output a pixel signal on the second data signal line VSL2.

[0053] According to another example, the encoding unit 16 may convert the element value “+1” into an active signal level of a first row-encoded signal ES and convert the element value “−1” into an active signal level of a second row-encoded signal ES, where the active signal level of the first row-encoded signal ES causes the addressed pixel circuit 100 to output a pixel signal on the first data signal line VSL1, and where the active signal level of the second row-encoded signal level causes the addressed pixel circuit 100 to output a pixel signal on the second data signal line VSL2.

[0054] Each column readout circuit 20 may further include an analog-to-digital conversion unit 27 that converts the analog differential signal DS into an encoded column value.

[0055] In particular, the analog-to-digital conversion unit 27 converts the analog differential signal DS output by the differential unit 21 into a digital value representing the encoded column value. Each encoded column value contains encoded information about all pixel signals forwarded from the pixel circuit 100 to the column readout circuit 20 connected to the pixel circuit 100.

[0056] Each column readout circuit 20 may also include a digital block 28 that sequentially receives a set of encoded column values ​​and decodes the set of encoded column values ​​by using a binary spreading code matrix, wherein the number of each set of encoded column values ​​is equal to the code length L of the binary spreading code matrix. The digital block outputs digital pixel values ​​of the original pixel signal.

[0057] In particular, each digital block 28-1, ..., 28-N receives a set of digital column values ​​from one of the column readout circuits 20-1, ..., 20-N. The number of digital values ​​of each set of digital column values ​​is equal to the code length L of the binary spreading code matrix. Each digital block 28-1, ..., 28-N decodes the received set of digital column values ​​by using the same binary spreading code matrix used to decode the respective pixel signals, and outputs L digital pixel values ​​for each of the pixel circuits 100 assigned to the column readout circuit 20.

[0058] The digital block 28 and the encoding unit 16 may use the same memory unit 17 to obtain the element values ​​of the binary spreading code matrix as illustrated. According to another example, the digital block 28 and the encoding unit 16 may use different memory units with the same or complementary contents.

[0059] Digital block 28 facilitates decoding of each frame previously encoded by L different codewords using a binary spreading code matrix.Digital blocks 28-1, ..., 28-N restore previously encoded pixel signals to digital values.

[0060] The column readout circuit 20 forms part of the column signal processing unit 14, which also includes an interface unit 29. The interface unit 29 receives digital pixel values ​​from all pixel columns 31-1, ..., 31-N and outputs digital frame data DPXS. The digital frame data includes digital pixel values ​​of all pixel signals obtained in the same exposure period.

[0061] The pixel array 11 , the column signal processing unit 14 , the encoding unit 16 , the memory unit 17 , and if applicable, the row driver unit 13 may be formed as part of the image sensor assembly 10 .

[0062] The image sensor assembly 10 may also include a sensor controller 15 that controls the components of the image sensor assembly 10. The sensor controller 15 may control the timing of the encoding unit 16 and, if applicable, may provide a signal to the encoding unit 16. Figure 2 The row driver unit 13 in the sensor controller 15 supplies a driving timing signal. In addition, the sensor controller 15 generates and drives one or more control signals for controlling the column signal processing unit 14 (eg, the column readout circuits 20-1, ..., 20-N, the digital blocks 28-1, ..., 28-N and the interface unit 29).

[0063] The solid-state imaging device 90 including the image sensor assembly 10 may further include a signal processing unit 80 that receives and further processes the digital frame data DPXS.

[0064] Figure 1 A solid-state imaging device 90 is shown having a passive pixel circuit 100 that is controlled only by the encoding unit 16 .

[0065] Figure 2 Another solid-state imaging device 90 is shown, which has an active pixel circuit 100 controlled by both a coding unit 16 and a row driver unit 13 that generates row control signals RES, TG, ... The row control line RL electrically connects the row driver unit 13 to the pixel circuit 100 in the pixel array 11. In particular, the row driver unit 13 may include a driver / buffer circuit that drives a suitable control signal, a reference potential and / or a voltage bias for the pixel transistor in the active pixel circuit 100. The row driver unit 13 may include one or more driver / buffer circuits for each pixel row 32. Alternatively, two or more pixel rows 32 or all pixel circuits 100 may share one, some or all of the driver / buffer circuits. The row control signals RES, TG, ... output by a driver / buffer circuit may be forwarded to the corresponding pixel transistors in the same pixel row 32, some pixel rows 32, or all pixel rows 32. Therefore, each row control line RL may be electrically connected to some pixel circuits 100 of a pixel row 32 , all pixel circuits 100 of one pixel row 32 , all pixel circuits 100 of multiple pixel rows 32 , or all pixel circuits 100 of the pixel array 11 .

[0066] Using the encoding unit 16 as described above, the pixel circuit 100 having a first pixel output connected to the first data signal line VSL1 and a second pixel output connected to the second data signal line VSL2, and the column readout circuit 20, the solid-state imaging device 90 enables a method of operating a solid-state imaging device by using CDMA readout.

[0067] The codewords of the binary spread spectrum code matrix, whose number L is, are sequentially applied to the pixel columns 31 of the two-dimensional pixel array 11. Each codeword has a code length L. Each codeword is simultaneously applied to some or all of the pixel columns 31, wherein all bits of the codeword are simultaneously applied to different pixel rows 32. Individually for each of the pixel columns 31 and depending on the element value of the binary spread spectrum code matrix received by the pixel circuit 100, the pixel circuit 100 outputs a pixel signal to the first data signal line VSL1 or the second data signal line VSL2. A differential signal DS is generated from a first code signal derived from the pixel signal output to the first data signal line VSL1 and a second code signal derived from the pixel signal output to the second data signal line VSL2.

[0068] The differential signal DS is generated from a first code signal obtained by superimposing the pixel signal output to the first data signal line VSL1 and a second code signal obtained by superimposing the pixel signal output to the second data signal line VSL2. The superposition can be linear, wherein the superposition includes signal sign multiplication and summation. However, for linear superposition, encoding with code words having code elements with the same element value (all +1 or all -1) can cause the output voltage Vo to become high, causing the amplifier output signal to be clipped. The use of a superposition of a current-voltage transfer function that is not as steep for higher current values ​​as for lower current values ​​can alleviate the disadvantages of pure linear superposition. For example, the superposition can be nonlinear, such as completely logarithmic, linear until a threshold and logarithmically beyond the threshold, or linear with a first slope until a threshold and linear with a second lower slope beyond the threshold.

[0069] Figures 3 to 5 Details of a solid-state imaging device 90 are shown, which has a pixel circuit 100 including a pixel encoding circuit 110, and has a column readout circuit 20 including a differential unit 21 based on a differential amplifier with differential outputs.

[0070] Each pixel circuit 100 may include a first coding switch 111 and a second coding switch 112, wherein the first coding switch is controlled by a row coding signal ES and is configured to pass the pixel signal to a first data signal line VSL1 when the row coding signal ES is valid, and the second coding switch is configured to pass the pixel signal to a second data signal line VSL2 when the row coding signal ES is invalid.

[0071] The first encoding switch 111 and the second encoding switch 112 may be enhancement type n-FETs. The non-inverting instance ESP of the row encoding signal ES controls the first encoding switch 111, and the inverting instance ESM of the row encoding signal ES controls the second encoding switch 112. The first encoding switch 111 and the second encoding switch 112 form at least a part of the pixel encoding circuit 110. The pixel encoding circuit 110 may include additional FETs for obtaining the inverting instance ESM from the non-inverting instance ESP of the row encoding signal ES, for obtaining the non-inverting instance ESP from the inverting instance ESM of the row encoding signal ES, or for obtaining both the inverting instance ESM and the non-inverting instance ESP from the same row encoding source signal.

[0072] Figure 3 and Figure 4 Details of a solid-state imaging device 90 with passive pixel circuits 100 are shown.

[0073] Each pixel circuit 100 includes a photoelectric conversion device PD that generates a photocurrent, wherein the photocurrent is a function of the light intensity received by the photoelectric conversion device PD. The pixel signal output by each pixel circuit 100 is a current signal obtained from the photocurrent of the photoelectric conversion device PD. In particular, the pixel signal can be the same as the photocurrent flowing to the first data signal line VSL1 or the second data signal line VSL2 through the pixel encoding circuit 110.

[0074] The first data signal line VSL1 connects the first pixel outputs of the plurality of pixel circuits 100 to the first input of the column readout circuit 20. The second data signal line VSL2 connects the second pixel outputs of the plurality of pixel circuits 100 to the second input of the column readout circuit 20. The pixel circuits 100 connected to the first data signal line VSL1 and the same second data signal line VSL2 may include all pixel circuits 100 of one pixel column 31.

[0075] The column readout circuit 20 can convert the current obtained by superimposing the pixel signal on the first data signal line VSL1 into a first voltage signal, can convert the current obtained by superimposing the pixel signal on the second data signal line VSL2 into a second voltage signal, and can generate a differential signal DS from the first voltage signal and the second voltage signal.

[0076] More specifically, the pixel circuits 100 connected to the same signal line pair simultaneously output photocurrents to the signal line pair, and the column readout circuit 20 includes a differential unit 21 that superimposes the photocurrents simultaneously delivered to the first data signal line VSL1, superimposes the photocurrents simultaneously delivered to the second data signal line VSL2, and obtains a differential voltage from a first voltage signal obtained by current-to-voltage conversion of the photocurrent delivered to the first data signal line VSL1 and a second voltage signal obtained by current-to-voltage conversion of the photocurrent delivered to the second data signal line VSL2.

[0077] The same gain factor can be used to convert the pixel signal on the first data signal line VSL1 into a first voltage signal and to convert the pixel signal on the second data signal line VSL2 into a second voltage signal, and the differential signal DS can be obtained by subtracting the first voltage signal from the second voltage signal or by subtracting the second voltage signal from the first voltage signal.

[0078] For example, the column readout circuit 20 includes a first amplifier circuit 211 and a first feedback element 212 electrically connected between an output of the first amplifier circuit 211 and an input of the first amplifier circuit 211, wherein the input of the first amplifier circuit 211 is configured to receive a pixel signal transmitted on a first data signal line VSL1. The column readout circuit 20 includes a second amplifier circuit 221 and a second feedback element 222 electrically connected between an output of the second amplifier circuit 221 and an input of the second amplifier circuit 221, wherein the input of the second amplifier circuit 221 is configured to receive a pixel signal transmitted on a second data signal line VSL2.

[0079] In particular, the first data signal line VSL1 electrically connects the first pixel output of the pixel circuit 100 with the input of the first amplifier circuit 211 , and the second data signal line VSL2 electrically connects the second pixel output of the pixel circuit 100 with the input of the second amplifier circuit 221 .

[0080] The first voltage signal output by the first amplifier circuit 211 is obtained by superimposing and amplifying the voltage generated by the photocurrent of all pixel circuits 100 connected to the first data signal line VSL1 during the same pixel array readout. For example, the first voltage signal is obtained by superimposing and amplifying the voltage generated across the first feedback element 212 by the photocurrent of all pixel circuits 100 encoded with the element value "+1". The second voltage signal output by the second amplifier circuit 221 is obtained by superimposing and amplifying the voltage generated by the photocurrent of all pixel circuits 100 connected to the second data signal line VSL2 during the same pixel array readout. For example, the second voltage signal is obtained by superimposing and amplifying the voltage generated across the second feedback element 222 by the pixel signal photocurrent of all pixel circuits 100 encoded with the element value "-1".

[0081] The first amplifier circuit 211 and the second amplifier circuit 212 may be separate amplifiers that operate independently of each other. According to the illustrated embodiment, the differential amplifier 230 includes the functionality of the first amplifier circuit 211 and the second amplifier circuit 212.

[0082] exist Figure 3 In the embodiment, the first feedback element 212 includes a first resistance element 213, and the second feedback element 222 includes a second resistance element 223. The resistance of the first resistance element 213 and the resistance of the second resistance element 223 may be equal.

[0083] The resistance of the first resistive element 213 and the second resistive element 223 adjusts the voltage response. The response of the column readout circuit 20 can be relatively fast. Additional components electrically connected in series with the first feedback element 213 and the second feedback element 223 can be provided to obtain a non-linear current-voltage transfer function.

[0084] exist Figure 4 In the embodiment, the first feedback element 212 includes a first capacitance element 214 and a first controllable switch 215 electrically connected in parallel, and the second feedback element 222 includes a second capacitance element 224 and a second controllable switch 225 electrically connected in parallel.

[0085] In particular, the first voltage signal output by the first amplifier circuit 211 is obtained by integrating and amplifying the photocurrent superimposed on the first data signal line VSL, and the second voltage signal output by the second amplifier circuit 221 is obtained by integrating and amplifying the photocurrent superimposed on the second data signal line VSL2. The capacitances of the first capacitor element 214 and the second capacitor element 224 may be equal.

[0086] The auto-zero signal AZ can control the first controllable switch 215 and the second controllable switch 225. In particular, the auto-zero signal AZ can turn on the first controllable switch 215 and the second controllable switch 225 simultaneously for a sufficiently long time to reliably discharge the first capacitive element 214 and the second capacitive element 224 before reading out the pixel signal.

[0087] For this integration scheme, each output voltage VO is relative to the previous value. Therefore, a capacitor reset is required to start the readout sequence with a zero voltage across the first capacitive element 214 and the second capacitive element 224. Each frame readout begins with an effective auto-zero signal AZ, thereby turning on the first controllable switch 215 to discharge the first capacitive element 214 and turning on the second controllable switch 225 to discharge the second capacitive element 224. Since only the first controllable switch 215 and the second controllable switch 225 require the auto-zero signal AZ, the first controllable switch 215 and the second controllable switch 225 can be located outside the pixel array 11. In the case where the first capacitive element 214 and the second capacitive element 224 are not discharged, the output voltage VO may become too large over time.

[0088] Line code signal ES for starting mode 0 kThe non-inverting instance ESP and the inverting instance ESM are either all valid (all encoding switches 111, 112 are turned on) or all invalid (all encoding switches 111, 112 are turned off). When t=t0, the ESP / ESM mode changes from 0 to p0, and when t=t1, the ESP / ESM mode changes from p0 to p1, the mode output voltage Vp0 associated with the ESP / ESM mode p0 is Vp0=VO(t1)-VO(t0), and the output voltage associated with the ESP / ESM mode pl is Vp1=VO(t2)-VO(t1), and so on. The duration of the ESP / ESM mode px between the mode change from the ESP / ESM mode p(xl) to px and the mode change from the ESP / ESM mode px to p(x+l) is the exposure time, and the mode voltages Vp0, Vp1, ... are proportional to the exposure time.

[0089] The integration approach makes the readout more robust against high frequency noise, at the expense of some additional delay due to the integration time constant.

[0090] Additional components may be provided electrically connected in series with the first capacitive element 214 and the second capacitive element 224 to obtain a non-linear current-voltage transfer function.

[0091] Figure 5 Details of a solid-state imaging device 90 are shown having an active pixel circuit 100. The pixel circuit 100 may be any active pixel sensor suitable for intensity readout.

[0092] Each pixel circuit 100 includes a photoelectric conversion device PD that generates a photocurrent, wherein the photocurrent is a function of the intensity of light received by the photoelectric conversion device PD, and wherein a pixel signal is a voltage signal derived from charges accumulated by the photocurrent during an exposure period.

[0093] For example, a pixel signal may be obtained from a voltage obtained by precharging a capacitive element and then continuously discharging the capacitive element by a photocurrent. Alternatively, a pixel signal may be obtained from a voltage obtained by continuously charging the capacitive element by a photocurrent. The photoelectric conversion element PD may include, for example, or may be composed of, for example, a photodiode, which converts electromagnetic radiation incident on a detection surface into a detector current by means of a photoelectric effect. In the intensity range of interest, the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0094] The pixel circuit 100 may include more than one photoelectric conversion device PD, wherein the sensitivity of the photoelectric conversion device PD may be different. Figure 5The example shown in ref ers to a pixel circuit 100 having one photoelectric conversion element PD and three active FETs as pixel transistors. Other examples may include two photoelectric conversion elements with different sensitivities and more than three active pixel transistors.

[0095] Each pixel circuit 100 may further include a floating capacitor FC and a source follower circuit 107. The floating capacitor FC is configured to be charged or discharged by the photocurrent of the photoelectric conversion element. The source follower circuit 107 is configured to be controlled by the voltage across the floating capacitor FC, wherein a pixel signal is obtained from an output signal of the source follower circuit 107.

[0096] The source follower circuit 107 may include an output transistor 108 and a source load 109. The output transistor 108 is a FET in a source follower configuration, wherein the transistor load path is between a positive power supply voltage VDD and the source load 109. The source load 109 may include a resistor element and / or a FET with a constant gate bias. The output signal of the source follower circuit 107 may be obtained at an output node between the source of the output transistor 108 and the source load 109. The output transistor 108 outputs a pixel signal via the output node, wherein the voltage amplitude of the pixel signal is a function of a floating capacitance potential Vfc of the floating capacitance FC.

[0097] When the first coding switch 111 is turned on, the output node can be capacitively coupled to the first data signal line VSL1. When the second coding switch 111 is turned on, the output node can be capacitively coupled to the second data signal line VSL2.

[0098] In addition to the floating capacitor FC and the source follower circuit 107 , each pixel circuit 100 may further include at least a transfer transistor 101 and a reset transistor 102 .

[0099] The transfer transistor 101 is electrically connected between the cathode of the photoelectric conversion element PD and the floating capacitor FC. The transfer transistor 101 is used as a transfer element for transferring the charge from the photoelectric conversion element PD to the storage electrode of the floating capacitor. The storage electrode of the floating capacitor FC may include a floating diffusion region. The floating capacitor FC is used as a local temporary charge storage body. The transfer signal TG is supplied to the gate (transfer gate) of the transfer transistor 101 through the transfer control line. Therefore, the transfer transistor 101 can transfer the electrons photoelectrically converted by the photoelectric conversion element PD to the floating capacitor FC. The transmission control line is an example of the row control line RL as described above. The transfer signal TG is an example of the row control signal as described above.

[0100] The reset transistor 102 is connected between the floating capacitor FC and the power supply line supplied with the positive power supply voltage VDD. The reset signal RES is supplied to the gate of the reset transistor 102 through the reset control line. Therefore, the reset transistor 102 used as a reset element resets the floating capacitor potential Vfc of the floating capacitor FC to the potential of the power supply line supplied with the positive power supply voltage VDD. The reset control line is another example of the row control line RL as described above. The reset signal RES is another example of the row control signal as described above.

[0101] The valid reset signal RES of all pixel circuits 100 read out using the same encoding matrix may precede the valid auto-zero signal AZ. The valid transmission signal TG of all pixel circuits 100 read out using the same encoding matrix may follow the valid auto-zero signal AZ.

[0102] The floating capacitor FC is connected to the gate of the output transistor 108. The floating capacitor FC serves as an input node of the source follower circuit 107. The voltage amplitude of the pixel signal across the first coupling capacitor 113 or the second coupling capacitor 114 is a function of the floating capacitor potential Vfc.

[0103] The pixel circuit 100 and the column readout circuit 20 are configured to superimpose the pixel signal transmitted to the first data signal line VSL1 into a first voltage signal through a first capacitance summing amplifier, superimpose the pixel signal on the second data signal line VSL1 into a second voltage signal through a second capacitance summing amplifier, and generate a differential signal DS from the first voltage signal and the second voltage signal. Each differential signal DS can be obtained by subtracting the first voltage signal from the second voltage signal or by subtracting the second voltage signal from the first voltage signal.

[0104] Each pixel circuit 100 may include a coupling circuit 115 that capacitively couples the pixel circuit 100 to the first data signal line VSL1 and the second data signal line VSL2 .

[0105] For example, the coupling circuit 115 includes a first coupling capacitor 113 coupling the pixel circuit 100 to the first data signal line VSL1 and a second coupling capacitor 114 coupling the pixel circuit 100 to the second data signal line VSL1. In particular, the first coupling capacitor 113 may be connected between the first coding switch 111 and the first data signal line VSL1, and the second coupling capacitor 114 may be connected between the second coding switch 112 and the second data signal line VSL2.

[0106] The first coding switch 111 is electrically connected between the output node and the first electrode of the first coupling capacitor 113. The second electrode of the first coupling capacitor 113 is connected to the first data signal line VSL1. The second coding switch 112 is electrically connected between the output node and the first electrode of the second coupling capacitor 114. The second electrode of the second coupling capacitor 114 is connected to the second data signal line VSL2.

[0107] Figure 6 An overview is given of the encoding and decoding process for CDMA readout of a pixel array 11 having a plurality of pixel circuits 100 arranged in N pixel columns 31-1, ..., 31-N and M pixel rows 32-1, ..., 32-M.

[0108] The encoding unit 16 generates the encoded signal ES using an M×M binary spread code matrix 171. The M×M binary spread code matrix 171 contains M different code words 171-1, ..., 171-M, wherein each code word 171-1, ..., 171-M includes M code elements. The binary spread code matrix 171 may be a Walsh-Hadamard matrix. Each code element has an element value "+1" indicated by a white square or an element value "-1" indicated by a black square.

[0109] In one encoding period, the encoding unit 16 applies one of the code words 171-1, ..., 171-M to each of the N pixel columns 31-1, ..., 31-N by converting the element value "+1" into a valid encoding signal on the row encoding line EL and converting the element value "-1" into an invalid encoding signal on the row encoding line. In the case where the encoding unit 16 applies a valid encoding signal, each of the pixel circuits 100 outputs a pixel signal to the first data signal line. In the case where the encoding unit 16 applies an invalid encoding signal, each of the pixel circuits 100 outputs a pixel signal to the second data signal line.

[0110] The pixel signals on the first data signal lines VSL1-1, ..., VSL-N are superimposed on the first column signals CSP-1, ..., CSP-M on the first data signal lines VSL1-1, ..., VSL1-N, wherein each first data signal line VSL1-1, ..., VSL-N connects the first output of the pixel circuit 100 of the pixel column 31-1, ..., 31-N to the first input of the column readout circuit 20-1, ..., 20-N associated with the corresponding pixel column 31-1, ..., 31-N. The pixel signals on the second data signal lines VS2-1, ..., VSL2-N are superimposed on the second column signals CSM-1, ..., CSM-M on the second data signal lines VS2-1, ..., VSL2-N, wherein each second data signal line VSL2-1, ..., VSL2-N connects the second output of the pixel circuit 100 of the pixel column 31-1, ..., 31-N to the second input of the column readout circuit 20-1, ..., 20-N associated with the corresponding pixel column 31-1, ..., 31-N. Each column readout circuit 20-1, ..., 20-N (particularly the differential unit 21-1, ..., 21-N associated with the corresponding pixel column 31-1, ..., 31-N) generates a differential signal from each pair of the first column signal CSP-1, ..., CSP-M and the second column signal CSM-1, ..., CSM-M, and converts the differential signal into a digital column value per encoding period and pixel column 31-1, ..., 31-N.

[0111] The complete frame readout period includes M encoding periods, wherein in each encoding period, the encoding unit 16 applies another codeword of the codewords 171-1, ..., 171-M to each of the N pixel columns 31-1, ..., 31-N. The column readout circuit 20-1, ..., 20-N transmits the digital column value of each pixel column 31-1, ..., 31-N and each codeword 171-1, 171-M to the memory unit 281 of the digital block 28.

[0112] After a complete frame readout period, the memory unit 281 holds a coded word containing M digital column values ​​for each of the N pixel columns 31-1, ..., 31-N. The digital block 28 also includes a decoder unit 282 that sequentially applies the words of the decoding matrix to decode the M digital column values ​​into M pixel values. The decoding matrix may be an inverse binary spreading code matrix 171.

[0113] To keep it simple, Figures 7 to 10 The diagram shows an encoding process using a binary spread spectrum code matrix 171 implemented as an 8×8 Walsh-Hadamard code matrix and a pixel array having 8 pixel rows. The eight pixel signals of the k-th pixel column 31-k have the following characteristics: Figure 7The amplitudes shown in the figure are a1, a2, a3, a4, a5, a6, a7, and a8.

[0114] Figure 8 It is shown that the first codeword 171-1 of the binary spread spectrum code matrix 171 is applied to the k-th pixel column 31-k in the first encoding period. Each pixel signal is inverted, that is, forwarded to the second data signal line VSL2. The resulting first differential signal of the k-th pixel column 31-k has an amplitude aDS1=-a1-a2-a3-a4-a5-a6-a7-a8. The first differential signal DS1 is converted into a first digital column value DC-kl of the k-th pixel column 31-k and is stored as the first element in the k-th column of the memory unit 281.

[0115] Fig. 9 The second codeword 171-2 of the binary spread spectrum code matrix 171 is shown to be applied to the k-th pixel column 31-k in the second encoding period. Each odd pixel signal is inverted, i.e., forwarded to the second data signal line VSL2. The other pixel signals are not inverted, i.e., forwarded to the first data signal line VSL1. The resulting second column signal CS2 of the k-th pixel column 31-k has an amplitude aCS2=-a1+a2-a3+a4-a5+a6-a7+a8. The second column signal CS2 is converted into a second digital column value DC-k2 of the k-th pixel column 31-k and is stored as the second element in the k-th column of the memory cell 281.

[0116] Fig.10 It is shown that the eighth codeword 171-8 of the binary spread spectrum code matrix 171 is applied to the k-th pixel column 31-k in the eighth encoding period. The first pixel signal, the fourth pixel signal, the sixth pixel signal and the seventh pixel signal are inverted, that is, they are forwarded to the second data signal line VSL2. The other pixel signals are not inverted, that is, they are forwarded to the first data signal line VSL1. The resulting eighth column signal CS8 of the k-th pixel column 31-k has an amplitude aCS8=-a1+a2+a3-a4+a5-a6-a7+a8. The eighth column signal CS8 is converted into the eighth digital column value DC-k8 of the k-th pixel column 31-k and is stored as the eighth element in the k-th column of the memory unit 281.

[0117] A complete frame readout period includes all eight encoding periods. Within the same frame readout period, the pixel signal to which the encoding is applied does not substantially change. As for the pixel output signal, for example, due to noise, it does change slightly, and the recovered signal represents the average value of the eight pixel signals within the eight encoding periods.

[0118] Fig.11AShows a typical binary spread - spectrum code matrix 171 of the Walsh - Hadamard type. Each time all pixel circuits 100 of a pixel column are read out by coded readout, such that the same pixel signal is read out 8 times, i.e., each codeword of the binary spread - spectrum code matrix 171 is read out once. The average effect inherent in each pixel signal improves the SNR by √8.

[0119] In contrast, in a conventional row - by - row readout schematically illustrated in Fig. 11B , each pixel circuit 100 is read out "once" only in each frame readout period, as indicated by the white squares in matrix 172. To achieve the same improvement in SNR by averaging, eight complete frames are necessary.

[0120] That is, to achieve the same SNR in the same frame readout period, CDMA coded readout allows the power supply voltage in the pixel array to be reduced by √M, and thus can contribute to a significant reduction in power consumption in the solid - state imaging device.

[0121] Fig. 12A and Fig. 12B Referring to the adaptive implementation of the coding unit 16 as illustrated in Figure 1 and Figure 2 for an illustrative example, the illustrative example has a binary spread - spectrum code matrix with a number of codewords M (M = 9). Generally, the number of codewords M is greater than 1000.

[0122] In particular, the coding unit 16 can change between a first coding mode and a second coding mode in response to an encoder control signal. In the first coding mode, the coding unit 16 uses a first binary spread - spectrum code matrix having a code length L equal to the number M of pixel circuits 100 in each pixel column 31. In the second coding mode, the coding unit 16 employs a second binary spread - spectrum code matrix having a code length L smaller than the number M of pixel circuits 100 in each pixel column 31.

[0123] Fig. 12A Shows a 9×9 binary spread - spectrum code matrix 171 for the first coding mode. All M pixel rows 32 - 1, ……, 32 - M are simultaneously addressed and read out in each coding period.

[0124] For the second coding mode, the pixel rows are grouped into two or more groups of pixel rows 32 - 1, ……, 32 - L, where L < M. The pixel rows in the same group of pixel rows 32 - 1, ……, 32 - L are simultaneously addressed and coded in the same coding period. L can be an integer divisor of M to allow the same binary spread - spectrum code matrix 171 to be applied to all groups of pixel rows 32 - 1, ……, 32 - L.

[0125] Fig. 12BA 3x3 binary spreading code matrix 171 is shown sequentially applied to three groups of pixel rows 32-1, ..., 32-L.

[0126] Can respond to changes in internal state or user settings. Figure 1 , Figure 2 or Figure 4 The encoder control signal is generated in the sensor controller 15.

[0127] Fig.13 23020 is a perspective view showing an example of a laminated structure of a solid-state imaging device having a plurality of pixel circuits arranged in a matrix in an array form. Each pixel circuit includes at least one photoelectric conversion element.

[0128] The solid-state imaging device 23020 has a laminated structure of a first chip (upper chip) 910 and a second chip (lower chip) 920 .

[0129] The laminated first chip 910 and the second chip 920 may be electrically connected to each other through a TC(S)V (Through Contact (Silicon) Via) formed in the first chip 910 .

[0130] The solid-state imaging device 23020 may be formed to have a laminated structure such that the first chip 910 and the second chip 920 are bonded together at a wafer level and cut by dicing.

[0131] In the lamination structure of upper and lower chips, the first chip 910 may be an analog chip (sensor chip) including at least one analog component of each pixel circuit, for example, photoelectric conversion elements arranged in an array.

[0132] For example, the first chip 910 may include only the photoelectric conversion elements of the pixel circuit as described above with reference to the previous figures. Alternatively, the first chip 910 may include additional elements of each pixel circuit. For example, in addition to the photoelectric conversion elements, the first chip 910 may also include at least a transfer transistor, a reset transistor, an output transistor and / or a source load of the pixel circuit. Alternatively, the first chip 910 may include each element of the pixel circuit.

[0133] The second chip 920 may be mainly a logic chip (digital chip) including elements complementary to those on the first chip 910 to complete pixel circuits and current control circuits. The second chip 920 may also include analog circuits, such as circuits for quantizing analog signals transmitted from the first chip 910 through TCVs.

[0134] The second chip 920 may have one or more bonding pads BPD, and the first chip 910 may have openings OPN for wire bonding to the second chip 920 .

[0135] The solid-state imaging device 23020 having a laminated structure of two chips 910 and 920 may have the following characteristic configuration:

[0136] The electrical connection between the first chip 910 and the second chip 920 is performed by, for example, TCV. TCV can be arranged at the end of the chip or between the pad area and the circuit area. TCV for transmitting control signals and supplying power can be mainly concentrated at, for example, the four corners of the solid-state imaging device 23020, thereby reducing the signal wiring area of ​​the first chip 910.

[0137] Fig.14 shows the components of a solid-state imaging device across Fig.14 Another possible allocation of the first chip 910 and the second chip 920 is shown.

[0138] The first chip 910 may include a pixel circuit 100 having a photoelectric conversion element, an encoding circuit, and (if applicable) a pixel transistor, and a coupling circuit, as well as a first data signal line VSL1 and a second data signal line VSL2 that connect the output of the pixel circuit 100 associated with the same pixel column on the first chip 910. The second chip 920 may include a column readout circuit 20-1 having a differential unit 21-1, .... One contact structure 915 (e.g., a through contact path) for each data signal line VSL1, VSL2 can transfer a pixel signal from the first chip 910 to the second chip 920.

[0139] Fig.15 is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a system to which the technology according to the embodiment of the present disclosure can be applied.

[0140] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.15 In the example depicted in FIG. 1 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0141] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0142] The body system control unit 12020 controls the operation of various devices provided to the body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights (such as headlights, reverse lights, brake lights, turn signal lights, fog lights, etc.). In this case, radio waves transmitted from a mobile device as a substitute for a key or signals of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, power window device, lights, etc. of the vehicle.

[0143] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 may perform a process of detecting an object (such as a person, a vehicle, an obstacle, a sign, a character on a road surface, etc.) or a process of detecting a distance therefrom.

[0144] The imaging unit 12031 may be or may include an image sensor component or a solid-state imaging device that implements the CDMA readout method according to an embodiment of the present disclosure. The light received by the imaging unit 12031 may be visible light, or may be invisible light (such as infrared rays, etc.).

[0145] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle and may be or may include an image sensor component or a solid-state imaging device that implements the CDMA readout method according to an embodiment of the present disclosure. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. For example, the driver state detection unit 12041 includes a camera that includes a solid-state imaging device and focuses on the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's attention level, or can determine whether the driver is dozing off.

[0146] The microcomputer 12051 may calculate a control target value for a driving force generation device, a steering mechanism, or a braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 may perform cooperative control of functions intended to implement an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, follow-up driving based on a following distance, vehicle speed maintenance driving, warning of a vehicle collision, warning of a vehicle leaving a lane, and the like.

[0147] In addition, the microcomputer 12051 can perform collaborative control for autonomous driving, which enables the vehicle to travel autonomously without relying on the driver's operation by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle, and the information is obtained by the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040.

[0148] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle, which is obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0149] The sound / image output unit 12052 transmits an output signal of at least one of sound or image to an output device that can visually or auditorily notify the passenger of the vehicle or the outside of the vehicle of information. In the example of FIG. 17 , an audio speaker 12061, a display unit 12062, and a dashboard 12063 are illustrated as output devices. For example, the display unit 12062 may include at least one of an onboard display or a head-up display.

[0150] Fig.16 12101 , 12102 , 12103 , 12104 , and 12105 .

[0151] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100, and at positions on the upper portion of the windshield inside the vehicle. The imaging unit 12101 provided to the front nose and the imaging unit 12105 provided to the upper portion of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images behind the vehicle 12100. The imaging unit 12105 provided to the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0152] By the way, Fig.16 An example of the shooting range of the imaging units 12101 to 12104 is depicted. Imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set to the side mirrors. Imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, by superimposing the image data imaged by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0153] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements (the imaging element has pixels for phase difference detection), or may include an image sensor component or a ToF module of a solid-state imaging device that implements the CDMA readout method according to an embodiment of the present disclosure.

[0154] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract, as the leading vehicle, a particularly nearest three-dimensional object that exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. In addition, the microcomputer 12051 can set in advance a following distance to be maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform cooperative control intended for autonomous driving, which allows the vehicle to travel autonomously without relying on the operation of the driver or the like.

[0155] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0156] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the imaging images of the imaging units 12101 to 12104. For example, such pedestrian recognition is performed by a program that extracts feature points in the imaging images of the imaging units 12101 to 12104 as infrared cameras and a program that determines whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed to be superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0157] An example of a vehicle control system to which the technology according to the embodiment of the present disclosure is applied has been described above. By applying an image sensor assembly or a solid-state imaging device that implements the CDMA readout method of the embodiment of the present disclosure, the sensor has lower power consumption and better signal-to-noise ratio.

[0158] In addition, the embodiment of the present technology is not limited to the above-described embodiment, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0159] The solid-state imaging device according to the present disclosure may be any device for analyzing and / or processing radiation (such as visible light, infrared light, ultraviolet light, and X-rays). For example, the solid-state imaging device may be any electronic device in the fields of transportation, household appliances, medicine and healthcare, security, beauty, sports, agriculture, image reproduction, etc.

[0160] Specifically, in the field of image reproduction, the solid-state imaging device may be a device for capturing images for appreciation, such as a digital camera, a smart phone, or a mobile phone device with a camera function. In the field of transportation, for example, the solid-state imaging device may be integrated in a sensor in a vehicle (which captures the front, rear, periphery, interior, etc. of the vehicle for safe driving, such as automatic parking, recognition of the driver's state, etc.), in a surveillance camera that monitors a moving vehicle and a road, or in a distance measurement sensor that measures the distance between vehicles, etc.

[0161] In the field of home appliances, solid-state imaging devices can be integrated into any type of sensor that can be used in devices provided for home appliances (such as TVs, receivers, refrigerators, and air conditioners) to capture user gestures and perform device operations according to gestures. Therefore, solid-state imaging devices can be integrated into home appliances (such as TV receivers, refrigerators, and air conditioners) and / or devices for controlling home appliances. In addition, in the field of medicine and healthcare, solid-state imaging devices can be integrated into any type of sensor, such as solid-state imaging devices for use in medicine and healthcare, such as endoscopes or devices for performing angiography by receiving infrared light.

[0162] In the field of security, solid-state imaging devices can be integrated into devices for use in security, such as surveillance cameras for crime prevention or cameras for personnel identity verification. In addition, in the field of beauty, solid-state imaging devices can be used in devices for use in beauty, such as skin meters that capture skin or microscopes that capture probes. In the field of sports, solid-state imaging devices can be integrated into devices for use in sports, such as sports cameras or wearable cameras for sports. In addition, in the field of agriculture, solid-state imaging devices can be used in devices for use in agriculture, such as cameras for monitoring the conditions of fields and crops.

[0163] This technology can also be configured as follows:

[0164] (1) A solid-state imaging device, comprising: a pixel array including pixel circuits, wherein each pixel circuit is assigned to one of N pixel columns and one of M pixel rows, each pixel circuit being configured to generate a pixel signal including pixel lighting information and output the pixel signal depending on a signal level of a row coding signal on a first data signal line or a second data signal line; and a plurality of column readout circuits, each column readout circuit being configured to generate a first code signal by superimposing a pixel signal transmitted on the first data signal line, generate a second code signal by superimposing a pixel signal transmitted on the second data signal line, and generate a differential signal from the first code signal and the second code signal.

[0165] (2) The solid-state imaging device according to (1), further comprising: an encoding unit configured to control the row encoding signal according to a binary spread spectrum code matrix having a number L of code words, the code words having a code length L, wherein the code length L is equal to or less than the number M of pixel circuits per pixel column.

[0166] (3) The solid-state imaging device according to any one of (1) to (2), wherein each column readout circuit includes an analog-to-digital conversion unit configured to convert the analog differential signal into an encoded column value.

[0167] (4) A solid-state imaging device according to (3), wherein each column readout circuit includes a digital block configured to sequentially receive a group of encoded column values ​​and decode the group of encoded column values ​​by using a binary spread spectrum code matrix, wherein the number of encoded column values ​​in each group is equal to a code length L of the binary spread spectrum code matrix.

[0168] (5) A solid-state imaging device according to any one of (1) to (4), wherein each pixel circuit includes a first coding switch and a second coding switch, wherein the first coding switch is controlled by a row coding signal and is configured to pass the pixel signal to a first data signal line when the row coding signal is valid, and the second coding switch is configured to pass the pixel signal to a second data signal line when the row coding signal is invalid.

[0169] (6) A solid-state imaging device according to any one of (1) to (5), wherein each pixel circuit includes a photoelectric conversion device configured to generate a photocurrent, wherein the photocurrent is a function of the intensity of light received by the photoelectric conversion device, and wherein the pixel signal is a current signal derived from the photocurrent.

[0170] (7) A solid-state imaging device according to (6), wherein the column readout circuit is configured to convert a current obtained by superimposing a pixel signal on a first data signal line into a first voltage signal, convert a current obtained by superimposing a pixel signal on a second data signal line into a second voltage signal, and generate a differential signal from the first voltage signal and the second voltage signal.

[0171] (8) A solid-state imaging device according to any one of (6) and (7), wherein the column readout circuit includes a first amplifier circuit and a first feedback element, the first feedback element is electrically connected between the output of the first amplifier circuit and the input of the first amplifier circuit, and wherein the input of the first amplifier circuit is configured to receive a pixel signal transmitted on a first data signal line, and wherein the column readout circuit includes a second amplifier circuit and a second feedback element, the second feedback element is electrically connected between the output of the second amplifier circuit and the input of the second amplifier circuit, and wherein the input of the second amplifier circuit is configured to receive a pixel signal transmitted on a second data signal line.

[0172] (9) The solid-state imaging device according to (8), wherein the first feedback element includes a first resistance element, and wherein the second feedback element includes a second resistance element.

[0173] (10) The solid-state imaging device according to (8), wherein the first feedback element includes a first capacitance element and a first controllable switch electrically connected in parallel with the first capacitance element, and wherein the second feedback element includes a second capacitance element and a second controllable switch electrically connected in parallel with the second capacitance element.

[0174] (11) A solid-state imaging device according to any one of (1) to (5), wherein each pixel circuit includes a photoelectric conversion device configured to generate a photocurrent, wherein the photocurrent is a function of the intensity of light received by the photoelectric conversion device, and wherein the pixel signal is a voltage signal obtained from charge accumulated by the photocurrent during an exposure period.

[0175] (12) A solid-state imaging device according to (11), wherein each pixel circuit also includes a floating capacitor and a source follower circuit, wherein the floating capacitor is configured to be charged or discharged by a photocurrent, wherein the source follower circuit is configured to be controlled by a voltage across the floating capacitor, and wherein a pixel signal is obtained from an output signal of the source follower circuit.

[0176] (13) A solid-state imaging device according to any one of (11) and (12), wherein the pixel circuit and the column readout circuit are configured to superimpose a pixel signal transmitted to a first data signal line into a first voltage signal through a first capacitor summing amplifier, superimpose a pixel signal on a second data signal line into a second voltage signal through a second capacitor summing amplifier, and generate a differential signal from the first voltage signal and the second voltage signal.

[0177] (14) The solid-state imaging device according to (13), wherein each pixel circuit includes a coupling circuit that couples the pixel circuit to the first data signal line and the second data signal line.

[0178] (15) A method of operating a solid-state imaging device, the method comprising: sequentially applying a number L of codewords of a binary spread spectrum code matrix to pixel columns of a two-dimensional pixel array, wherein each codeword has a code length L, wherein each codeword is simultaneously applied to some or all of the pixel columns, wherein bits of the codeword are simultaneously applied to different pixel rows of the pixel array, wherein, individually for each of the pixel columns and depending on the element value of the binary spread spectrum code matrix received by the pixel circuit, each pixel circuit outputs a pixel signal to a first data signal line or a second data signal line; and generating a differential signal from a first code signal derived from the pixel signal output to the first data signal line and a second code signal derived from the pixel signal output to the second data signal line.

Claims

1. A solid-state imaging device, comprising: A pixel array (11), comprising pixel circuits (100), wherein each pixel circuit (100) is assigned to one of N pixel columns (31) and one of M pixel rows (32), and each pixel circuit (100) is configured to generate a pixel signal including pixel lighting information, and output the pixel signal on a first data signal line (VSL1) or a second data signal line (VSL2) according to a signal level of a row coding signal; and A plurality of column readout circuits (20), each column readout circuit (20) being configured to generate a first code signal by superimposing the pixel signal transmitted on the first data signal line (VSL1), generate a second code signal by superimposing the pixel signal transmitted on the second data signal line (VSL2), and generate a differential signal (DS) from the first code signal and the second code signal.

2. The solid-state imaging device according to claim 1, further comprising: The coding unit (16) is configured to control the row coding signal according to a binary spread spectrum code matrix having a number L of code words, wherein the code words have a code length L, wherein the code length L is equal to or less than the number M of pixel circuits (100) per pixel column (31).

3. The solid-state imaging device according to claim 1, in, Each column readout circuit (20) includes an analog-to-digital conversion unit (27) configured to convert an analog differential signal (DS) into an encoded column value.

4. The solid-state imaging device according to claim 3, in, Each column readout circuit (20) includes a digital block (28) configured to sequentially receive a set of encoded column values ​​and decode the set of encoded column values ​​by using a binary spreading code matrix, wherein the number of encoded column values ​​in each set is equal to a code length L of the binary spreading code matrix.

5. The solid-state imaging device according to claim 1, in, Each pixel circuit (100) comprises a first coding switch (111) and a second coding switch (112), wherein the first coding switch is controlled by the row coding signal and is configured to transfer the pixel signal to the first data signal line (VSL1) when the row coding signal is valid, and the second coding switch is configured to transfer the pixel signal to the second data signal line (VSL2) when the row coding signal is invalid.

6. The solid-state imaging device according to claim 1, in, Each pixel circuit (100) comprises a photoelectric conversion device (PD) configured to generate a photocurrent, wherein the photocurrent is a function of the light intensity received by the photoelectric conversion device (PD), and wherein the pixel signal is a current signal derived from the photocurrent.

7. The solid-state imaging device according to claim 6, in, The column readout circuit (20) is configured to convert a current obtained by superimposing the pixel signal on the first data signal line (VSL1) into a first voltage signal, convert a current obtained by superimposing the pixel signal on the second data signal line (VSL2) into a second voltage signal, and generate the differential signal (DS) from the first voltage signal and the second voltage signal.

8. The solid-state imaging device according to claim 6, in, The column readout circuit (20) comprises a first amplifier circuit (211) and a first feedback element (212) electrically connected between an output of the first amplifier circuit (211) and an input of the first amplifier circuit (211), and wherein the input of the first amplifier circuit (211) is configured to receive the pixel signal transmitted on the first data signal line (VSL1), and The column readout circuit (20) comprises a second amplifier circuit (221) and a second feedback element (222) electrically connected between an output of the second amplifier circuit (221) and an input of the second amplifier circuit (221), wherein the input of the second amplifier circuit (221) is configured to receive the pixel signal transmitted on the second data signal line (VSL2).

9. The solid-state imaging device according to claim 8, in, The first feedback element (212) comprises a first resistance element (213), and wherein the second feedback element (222) comprises a second resistance element (223).

10. The solid-state imaging device according to claim 8, in, The first feedback element (212) comprises a first capacitance element (214) and a first controllable switch (215) electrically connected in parallel with the first capacitance element (214), and wherein the second feedback element (222) comprises a second capacitance element (224) and a second controllable switch (225) electrically connected in parallel with the second capacitance element (224).

11. The solid-state imaging device according to claim 1, in, Each pixel circuit (100) includes a photoelectric conversion device (PD) configured to generate a photocurrent, wherein the photocurrent is a function of the light intensity received by the photoelectric conversion device (PD), and wherein the pixel signal is a voltage signal obtained from the charge accumulated by the photocurrent during an exposure period.

12. The solid-state imaging device according to claim 11, in, Each pixel circuit (100) further includes a floating capacitor (FC) and a source follower circuit (107), wherein the floating capacitor (FC) is configured to be charged or discharged by the photocurrent, wherein the source follower circuit (107) is configured to be controlled by the voltage across the floating capacitor (FC), and wherein the pixel signal is obtained from an output signal of the source follower circuit (107).

13. The solid-state imaging device according to claim 11, in, The pixel circuit (100) and the column readout circuit (20) are configured to superimpose a pixel signal transmitted to the first data signal line (VSL1) into a first voltage signal through a first capacitor summing amplifier, superimpose the pixel signal on the second data signal line (VSL1) into a second voltage signal through a second capacitor summing amplifier, and generate the differential signal (DS) from the first voltage signal and the second voltage signal.

14. The solid-state imaging device according to claim 13, in, Each pixel circuit (100) comprises a coupling circuit (115) which capacitively couples the pixel circuit (100) to the first data signal line (VSL1) and the second data signal line (VSL2).

15. A method of operating a solid-state imaging device, the method comprising: sequentially applying L number of codewords of a binary spread spectrum code matrix to pixel columns (31) of a two-dimensional pixel array (11), wherein each of the codewords has a code length L, wherein each of the codewords is simultaneously applied to some or all of the pixel columns (31), wherein bits of the codewords are simultaneously applied to different pixel rows (32) of the pixel array (11), wherein, individually for each of the pixel columns (31) and depending on the element value of the binary spread spectrum code matrix received by the pixel circuit (100), each pixel circuit (100) outputs a pixel signal to a first data signal line (VSL1) or a second data signal line (VSL2); and A differential signal (DS) is generated from a first code signal obtained from the pixel signal output to the first data signal line ( VSL1 ) and a second code signal obtained from the pixel signal output to the second data signal line ( VSL2 ).

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