Probe card, test method of multi-structure power device chip, automatic synchronous test system and storage medium

Abstract

The invention discloses a probe card, a test method of a multi-structure power device chip, an automatic synchronous test system and a storage medium, the probe card is provided with probes of various structures which can be connected to the power device chip at the same time, and the probe card is also provided with probe layouts corresponding to the structures. Each probe layout comprises a circuit loop corresponding to the corresponding structure; the test method is applied to the test equipment and comprises the following steps: sequentially reading a group of parameter data from a test program, and testing the multi-structure power device chip according to the currently read group of parameter data until all parameter data in the test program are read. The probe card can be connected with all structures on the power device chip at the same time, and in combination with the test method, the test equipment can automatically switch signal loops according to a preset program so as to automatically switch parameter data to test different structures on the power device chip in sequence.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a probe card, a testing method for a multi-structure power device chip, an automated synchronous testing system and a storage medium. Background Art

[0002] When conducting electrical tests on power device wafers, a probe card is needed to test the chip devices. Specifically, the probes of the probe card need to contact the metal pads (PAD) of the chip devices, that is, the Gate Pad and Source Pad led by the front structure of the chip devices. The wafer carrier contacts the Drain end structure on the back of the device. The test equipment then provides an excitation signal, which is then transmitted to the inside of the chip through the probe to measure the electrical parameters of the chip. In actual production, in order to save costs or for functional coupling purposes, multiple device structures will be designed on the same wafer during the chip design stage. Therefore, for the same wafer, multiple different device structures need to be tested. Reference Figure 1 In the prior art, in response to this situation, it is necessary to make multiple different probe cards for different device structures to test all the device structures to be tested, or to make multiple interfaces on the probe card and switch the test circuits on the probe card by manual plugging and unplugging to test all the device structures to be tested. In addition, when performing electrical tests on test devices with different structures on the wafer, the entire test process also requires repeated adjustment and calibration of the wafer, coupled with the switching of the test probe cards, the entire test process is complicated and the test efficiency is low. Summary of the invention

[0003] The embodiments of the present invention provide a probe card, a testing method for a multi-structure power device chip, an automated synchronous testing system and a storage medium to solve the problem in the prior art that when conducting electrical tests on multiple device structures on the same wafer, the test probe card needs to be repeatedly replaced, or the test circuit of the probe card needs to be manually plugged in and adjusted to switch, making the entire electrical testing process complicated and inefficient.

[0004] In a first aspect, an embodiment of the present invention provides a probe card, which can be used to perform electrical detection on power device chips having various structures; wherein:

[0005] The probe card is provided with a probe layout capable of being connected to the multiple structures on the power device chip at the same time;

[0006] Each probe layout is provided with a circuit loop corresponding to the corresponding structure.

[0007] In a second aspect, an embodiment of the present invention provides a method for testing a multi-structure power device chip, which is used for a testing device connected to the probe card of the first aspect, comprising:

[0008] Reading a set of parameter data from the test program in sequence, and testing the multi-structure power device chip according to the set of parameter data currently read, until all the parameter data in the test program are read;

[0009] Wherein, each group of parameter data in the test program corresponds to a structure on the power device chip, each group of parameter data includes a channel identification parameter and a device test parameter corresponding to the corresponding structure, and the testing of the multi-structure power device chip according to the currently read group of parameter data includes:

[0010] Determine the target test structure according to the channel identification parameters in the set of parameter data currently read, and turn on the signal loop corresponding to the target test structure according to the channel identification parameters, while turning off the signal loops corresponding to the remaining structures in the power device chip;

[0011] A test signal is applied to a signal loop corresponding to a target test structure according to the device test parameters in a set of parameter data currently read, and a test result signal is obtained.

[0012] In a third aspect, an embodiment of the present invention provides an automated synchronous testing system for a multi-structure power device chip, characterized in that it includes:

[0013] A probe card, which is the probe card described in the first aspect;

[0014] A switch matrix is ​​provided with a path control module corresponding to each structure on the multi-structure power device chip for controlling the on and off of a signal loop corresponding to the corresponding structure, one end of which is connected to a test device and the other end is connected to a probe card;

[0015] The test equipment is deployed with a test program for calling a selected test program to test a multi-structure power device chip, which includes reading a set of parameter data from the selected test program in sequence, and testing the multi-structure power device chip according to the set of parameter data currently read, until all the parameter data in the test program are read.

[0016] In a fourth aspect, an embodiment of the present invention provides a method for testing a multi-structure power device chip, comprising:

[0017] Different structures on the power device chip are encoded respectively to form parameter data corresponding to each structure, and a test program is constructed according to the parameter data of the corresponding structure, and the test program is deployed on the test equipment, wherein the constructed test program defines multiple groups of parameter data for testing the multi-structure power device chip, each group of parameter data corresponds to a structure, and each group of parameter data includes a channel identification parameter and a device test parameter corresponding to the corresponding structure;

[0018] Connecting a switch matrix to a test device and connecting a probe card to the switch matrix, wherein the switch matrix includes a path control module corresponding to each structure on the multi-structure power device chip and used to control the on and off of a signal loop corresponding to the corresponding structure;

[0019] Connecting the probe card to the power device chip, and connecting the probes on the probe card to all structures on the power device chip at the same time;

[0020] The test equipment is started to perform automatic synchronous testing on the multi-structure power device chip.

[0021] In a fifth aspect, an embodiment of the present invention provides an electronic device, comprising: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the steps of the automated synchronous testing method for multi-structure power device chips of the second aspect above.

[0022] In a sixth aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for automated synchronous testing of multi-structure power device chips according to the second aspect.

[0023] The scheme of the embodiment of the present invention arranges the probe layout corresponding to all the structures to be tested on the power device chip on the same probe card, so that it can directly connect all the structures on the power device chip at the same time. At the same time, the scheme of the embodiment of the present invention also pre-encodes the various structures of the power device chip, and generates parameter data corresponding to each structure based on the test requirements and encoding of each structure of the power device chip. Based on this, the embodiment of the present invention pre-configures the parameter data corresponding to each structure in the same test program, and when the power device chip is electrically tested using the probe card, by sequentially obtaining the parameter data corresponding to each structure on the power device chip configured in the same test program, it is possible to sequentially control the conduction of the signal circuit corresponding to each structure and load the device test parameters of the corresponding structure after the signal circuit corresponding to the corresponding structure is turned on, and directly read all the parameter data in the same test program. Therefore, the embodiment of the present invention can realize that each structure on the power device chip can be tested in turn after one pin insertion, thereby fully automatically completing the electrical test of all the structures on the power device chip at one time. Compared with the prior art, the solution of the embodiment of the present invention does not require manual replacement of the test needle card or manual plugging and unplugging of the test circuit of the switching probe card to perform electrical tests on various device structures in the power device chip, effectively simplifying the entire electrical testing operation process and effectively improving the efficiency of the electrical testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0025] Figure 1 A flow chart of electrical testing of devices with different structures on a wafer in the prior art;

[0026] Figure 2 A principle block diagram of a switch matrix in a probe card for a multi-structure power device chip according to an embodiment of the present invention;

[0027] Figure 3 A flowchart of an automated synchronous testing method for a multi-structure power device chip according to an embodiment of the present invention;

[0028] Figure 4 A schematic diagram for reference in constructing a test program in an automated synchronous test method for a multi-structure power device chip according to an embodiment of the present invention;

[0029] Figure 5This is a flow chart of step S13 in the automated synchronous testing method for a multi-structure power device chip according to an embodiment of the present invention;

[0030] Figure 6 A flow chart of determining whether a conducting test loop is correct in an automated synchronous test method for a multi-structure power device chip according to an embodiment of the present invention;

[0031] Figure 7 An overall flow chart of an automated synchronous testing method for a multi-structure power device chip according to an embodiment of the present invention;

[0032] Figure 8 A principle block diagram of an automated synchronous testing device for a multi-structure power device chip according to an embodiment of the present invention;

[0033] Fig. 9 A schematic diagram of a probe card according to an embodiment of the present invention after being installed and loaded with a power device chip and connected to a signal circuit;

[0034] Fig.10 The schematic diagram of the hardware structure of a method for testing a multi-structure power device chip used in a testing device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0037] The present invention may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communications network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0038] In the present invention, "module", "device", "system" and the like refer to related entities applied to computers, such as hardware, a combination of hardware and software, software or software in execution, etc. In detail, for example, an element can be, but is not limited to, a process, a processor, an object, an executable element, an execution thread, a program and / or a computer running on a processor. In addition, an application or script program running on a server, a server can all be an element. One or more elements can be in an execution process and / or thread, and an element can be localized on a computer and / or distributed between two or more computers, and can be operated by various computer-readable media. An element can also communicate through local and / or remote processes according to a signal with one or more data packets, for example, a signal from a data that interacts with another element in a local system, a distributed system, and / or a network on the Internet through a signal to interact with other systems.

[0039] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include" and "comprise" include not only those elements, but also other elements that are not explicitly listed, or also include elements inherent to such processes, methods, articles or equipment. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or equipment that includes the elements.

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0041] The present invention provides a probe card, which can be used to perform electrical tests on power device chips with multiple structures. The power device chip in the embodiment of the present invention can be a wafer-level chip, a system-level chip, or an integrated chip formed by integrating single chips with different functions. The embodiment of the present invention does not limit the type of power device chip. A number of different structures can be arranged on the power device chip in the embodiment of the present invention. The scheme of the embodiment of the present invention can be used to automatically perform electrical tests on multiple structures on the power device chip. In the process of performing electrical tests on different structures, there is no need to replace the probe card, repeatedly adjust and calibrate the wafer, etc. Specifically, the probe card in the embodiment of the present invention has probe layouts corresponding to all structures to be tested on the power device chip to be measured on a single probe card, so that the probe card of the present invention can be connected to multiple structures on the power device chip at the same time. Circuit loops corresponding to the corresponding structures are arranged on the probe layout, so that each structure can be connected to a test device for electrical testing through a separate circuit loop. The circuit loop is a circuit loop used when testing the corresponding structure. Voltage can be applied to each structure through these circuit loops to perform electrical tests on the corresponding structure. Specifically, the probe card is designed for all structures to be tested on the power device chip to be measured. Based on the differences in the various structures on the power device chip and the differences in the layouts of the various structures on the power device chip, the probe layouts to be used when testing the corresponding structures will also be different. In an embodiment of the present invention, the probe layouts corresponding to the various structures are designed on the same probe card, and the circuit loop on the probe layout is connected to the test equipment used for electrical testing. In this way, by simultaneously inserting all the probes on the probe card into the corresponding positions of all the structures on the power device chip, the structures at the corresponding positions can be electrically connected to the test equipment through the inserted probes.

[0042] The present invention also provides a process of a testing method for a multi-structure power device chip, wherein the method adopts the probe card provided by the above-mentioned embodiment of the present invention to test the multi-structure power device chip, wherein the executor of the testing method is a testing device for performing electrical testing on the power device chip. Specifically, the testing method for a multi-structure power device chip of the present invention includes reading a set of parameter data from a test program in sequence, and testing the multi-structure power device chip according to the set of parameter data currently read, until all the parameter data in the test program are read.

[0043] In an embodiment of the present invention, when using a probe card to test a power device chip, the power device chip needs to be placed with its front side facing up on top of a wafer carrier, and then the probe card is used to press the probe down until it contacts the Gate Pad and Source Pad led out by the various structures on the front side of the power device chip, and contacts the Drain end structure on the back side of the power device chip through the wafer carrier. After that, the probe card needs to be connected to the test equipment, and once the connection is completed, the test equipment can be used to execute the above-mentioned test method to start electrical testing of the structures on the power device chip.

[0044] Among them, the test program is pre-constructed for power device chips with different structural layouts to be electrically tested, and it contains several groups of parameter data corresponding to each structure on the power device chip of the structural layout. Preferably, each group of parameter data corresponds to a structure on the power device chip, and each group of parameter data in the test program includes a channel identification parameter and a device test parameter corresponding to the corresponding structure. Specifically, the channel identification parameter is a parameter used to identify the signal loop that needs to be connected when using the parameter data. Through the channel identification parameter, it is possible to determine which signal loop needs to be connected for the current electrical test and how to connect the signal loop. When the signal loop is connected, the test equipment can be connected to the corresponding structure on the power device chip, so that the corresponding structure can be electrically tested. The device test parameter is the test parameter used by the structure to be electrically tested when the signal loop is connected. Through the device test parameter, it is possible to determine the test parameter required for the corresponding structure on the power device chip currently being tested, so that the corresponding structure can be electrically tested.

[0045] In some possible implementations, the channel identification parameters may include structure identification parameters corresponding to each structure and signal loop on-off parameters corresponding to each structure. The structure identification parameters are used to identify the structure corresponding to the current parameter data, and the signal loop on-off parameters are used to identify the on-off status of the signal loop corresponding to the structure corresponding to the current parameter data when the electrical test is performed. That is to say, each structure corresponds to a signal loop, and the signal loop can be controlled to be turned on or off by the test equipment according to the channel identification parameters. Among them, in some possible implementations, the signal loop may include a signal path between the circuit loop corresponding to the corresponding structure on the probe card and the test equipment, and the on-off of the signal loop corresponding to the corresponding structure can be controlled by controlling the on-off of the signal path. The signal path is provided with a path control module to control its on-off through the path control module. A signal path corresponding to a structure is provided with a path control module, so that the test equipment can control the path control module corresponding to the structure corresponding to the channel identification parameter according to the channel identification parameter to control the on-off and off-off of the signal path corresponding to the structure, so as to turn on or off the signal loop corresponding to the corresponding structure. In addition, in some other possible implementations, the signal loop can be understood as including a probe layout connected to the structure, a circuit loop corresponding to the structure, and a signal path arranged between the circuit loop corresponding to the structure and the test equipment. Similarly, the test equipment can control the path control module corresponding to the structure corresponding to the channel identification parameter according to the channel identification parameter to control the conduction and disconnection of the signal path corresponding to the structure, thereby realizing the conduction or disconnection of the signal loop corresponding to the corresponding structure.

[0046] Specifically, the signal loop may include a first signal path corresponding to the gate of the tested structure for applying a signal to the tested structure and a second signal path corresponding to the tested structure for obtaining a signal from the tested structure, as well as a third signal path corresponding to the source of the tested structure for applying a signal to the tested structure and a fourth signal path corresponding to the tested structure for obtaining a signal from the tested structure. By controlling the on-off of the four paths corresponding to the tested structure respectively, the signal loop corresponding to the corresponding structure can be turned on or off. The first signal path, the second signal path, the third signal path and the fourth signal path constitute a group of signal paths between the circuit loop corresponding to the corresponding structure on the probe card and the test equipment. Among them, the path control module includes four relays, and the four relays respectively control the on-off of the first signal path, the second signal path, the third signal path and the fourth signal path, and then the signal loop on-off parameters may include parameters for indicating the on-off of each relay in the corresponding signal loop.

[0047] Specifically, refer to Figure 2As shown, the four relays in the path control module may include a relay "GF" for controlling the on and off of the first signal path, a relay "GS" for controlling the on and off of the second signal path, a relay "SF" for controlling the on and off of the third signal path, and a relay "SS" for controlling the on and off of the fourth signal path. For each structure, there is a corresponding group of signal paths, such as structure A, the four relays in the path control module corresponding to it can be expressed as "GF_A", "GS_A", "SF_A" and "SS_A", structure B, the four relays in the path control module corresponding to it can be expressed as "GF_B", "GS_B", "SF_B" and "SS_B". Therefore, multiple groups of structures correspond to multiple groups of signal paths, that is, multiple groups of path control modules composed of four relays for controlling the on and off of signal paths are correspondingly provided. Since the on and off of the relay can be represented by "1" and "0", the on and off parameters of the signal loop can also be represented by a four-bit binary code. For example, if the signal loop on / off parameter is set to "0000", it means that the four relays in the signal loop are all in the disconnected state; if the signal loop on / off parameter is set to "1111", it means that the four relays in the signal loop are all in the on state.

[0048] For the structure identification parameter in the channel identification parameter, it may include an identifier of the structure corresponding to the current parameter data. Exemplarily, the structure may be directly represented by English letters, for example, the structure identification parameter of structure A is set to "A", the structure identification parameter of structure B is set to "B", and so on. In addition, since in the above embodiment, the signal loop on / off parameter is set to be represented by a four-bit binary code, in some possible implementations, the structure identification parameter may also be set to be represented by a four-bit binary code, so that the overall channel identification parameter can be composed of an eight-bit binary code. Figure 3 As shown, for example, the structure identification parameter of structure A is set to "0001", the structure identification parameter of structure B is set to "0010", and so on. Furthermore, in this embodiment, the channel identification parameter can be represented by an eight-bit binary code. For example, when the channel identification parameter is set to "00101111", it means that the four relays "GF_B", "GS_B", "SF_B" and "SS_B" of the signal loop corresponding to structure B are all in the on state, and then the test equipment can control the corresponding path control module according to the channel identification parameter to realize the conduction of the signal loop of the corresponding structure.

[0049] Figure 4 The method for testing a multi-power structure chip according to an embodiment of the present invention is schematically shown, and the method steps for testing the multi-structure power device chip according to a set of parameter data currently read are shown. Figure 4As shown, the step flow can be specifically implemented as including the following steps:

[0050] Step S11: determining a target test structure according to a channel identification parameter in a set of parameter data currently read, and switching on a signal loop corresponding to the target test structure according to the channel identification parameter, while switching off signal loops corresponding to other structures in the power device chip;

[0051] Step S12: applying a test signal to a signal loop corresponding to the target test structure according to the device test parameters in a set of parameter data currently read, and obtaining a test result signal fed back by the signal loop.

[0052] In step S11, the target test structure is determined according to the channel identification parameter, and can be determined based on the structure identification parameter in the channel identification parameter. After the target test structure is determined, the signal path corresponding to the structure and the path control module corresponding to the structure can be determined. The signal loop corresponding to the target test structure is turned on according to the channel identification parameter, and the path control module corresponding to the structure can be controlled based on the signal loop on-off parameter in the channel identification parameter, so that the signal path corresponding to the structure is turned on, and the signal loop is turned on. Finally, the signal loop corresponding to the remaining structures in the power device chip is turned off, and the other signal paths other than the signal path corresponding to the structure can be turned off by controlling the path control module other than the signal path corresponding to the structure. Then in step S11, the signal loop corresponding to the target structure is turned on, and all other signal loops are turned off, so as to ensure that the test equipment is currently only connected to the target structure, and only the target structure is electrically tested, and will not be affected by the interference of other signal loops. Then, step S12 can be executed to apply a test signal corresponding to the device test parameter to the target test structure according to the device test parameter in the parameter data to obtain the test result, so as to realize the electrical test of the target test structure. Specifically, after the target test structure is electrically tested, the test results will be fed back by the second signal path and the fourth signal path in the signal loop responsible for obtaining signals from the tested structure, so that the test equipment can obtain the test results of the electrical test of the corresponding structure.

[0053] In addition, when executing step S11, after the signal loop corresponding to the target test structure is turned on according to the channel identification parameter and the remaining corresponding signal loops in the power device suction cup are turned off, the turned-on signal loop can be tested first to determine whether the currently turned-on signal loop is correct, and the test signal is applied to the signal loop corresponding to the target test structure only when the turned-on signal loop is correct. In this way, it can be ensured that when the target test structure is currently being electrically tested, it will not be affected by the interference of the signal loops corresponding to other structures, and the electrical parameters applied during the electrical test can be applied to the correct signal loop, and it can prevent the signal reflux caused by the wrong short circuit from damaging the test equipment or the power device chip to be tested.

[0054] Figure 5 The method steps for detecting the conductive signal loop in the test method of the multi-structure power device chip according to one embodiment of the present invention are schematically shown. Figure 5 As shown, the method can be specifically implemented by comprising the following steps:

[0055] Step S21: applying a voltage signal within a safe range of the test to each signal circuit in turn, and detecting whether a voltage signal exists in each signal circuit;

[0056] Step S22a: judging according to the detection result, if there is a voltage signal in the signal loop that is not currently turned on, it is determined that the signal loop that is turned on is incorrect;

[0057] Step S22b: If only the currently turned-on signal loop has a voltage signal, it is determined that the turned-on signal loop is correct.

[0058] In this process, step S21 is first executed to apply a voltage signal within the safety range of the test to each signal circuit in turn to detect whether there is a voltage signal in each signal circuit. According to the detection result of the voltage signal, it can be known whether each signal circuit is conductive. If there is a voltage signal, it means that the signal circuit is conductive; if there is no voltage signal, it means that the signal circuit is not conductive. Step S22 is a step to determine whether the currently conductive signal circuit is correct according to the detection results of each signal circuit. The detection result obtained in step S21 can be divided into the following situations: First, only the signal loop that is turned on in step S11 has a voltage signal, and no voltage signal exists in other signal loops. At this time, it means that the current conduction of each signal loop meets the requirements for electrical testing of the target test structure, and the signal loop that is determined to be turned on is correct; second, there is a voltage signal in the signal loop that is turned on in step S11, and at least one of the other signal loops also has a voltage signal. At this time, it means that there is an unclosed signal loop in the other signal loops, which does not meet the requirements for electrical testing of the target test structure, and the signal loop that is determined to be turned on is incorrect; third, there is no voltage signal in the signal loop that is turned on in step S11. At this time, since the signal loop used for electrical testing of the target test structure is not turned on, the target test structure cannot be electrically tested, which does not meet the requirements for electrical testing of the target test structure, and the signal loop that is determined to be turned on is incorrect. In other words, only when the detection structure of each signal loop is consistent with the setting in step S11, it meets the requirements for electrical testing of the target test structure, and the signal loop that is determined to be turned on is correct.

[0059] When the judgment result is that the conductive signal loop is correct, step S12 can be continued to perform electrical testing on the current target test structure. When the judgment result is that the conductive signal loop is incorrect, the following steps can be performed: turn off all signal loops and turn on the signal loop corresponding to the target test device, re-judge whether the conductive signal loop is correct, and stop the test when the number of incorrect times exceeds a preset threshold. Among them, the preset threshold can be set according to actual conditions, and is specifically set to three times in this embodiment. In the above-mentioned implementation, the execution of the detection part of the conductive signal loop can be achieved by adding a code for signal loop detection and judgment in the constructed test program.

[0060] In some other possible implementations, after executing step S12, that is, after the target test structure is electrically tested and the test is completed, in order to reduce the probability of abnormalities occurring when the signal circuit is turned on and off during the subsequent electrical test of the target test structure, the signal circuit corresponding to the target test structure that has currently completed the electrical test can be turned off first. Specifically, the signal circuit corresponding to the target test structure that has currently completed the electrical test can be turned off in response to a test result signal received from the signal circuit feedback to ensure that the current electrical test has been completed and will not affect the current electrical test. After turning off the signal circuit, a Kelvin test can also be performed on the signal circuit to confirm whether the signal circuit is completely disconnected. Specifically, the test method for performing a Kelvin test on a signal circuit can be performed with reference to the relevant description in the prior art, and this will not be described in detail in the embodiments of the present invention.

[0061] After completing the above steps, the electrical test of one structure in the power device chip is completed. After that, it is only necessary to perform electrical tests on other structures on the power device chip in sequence according to the test procedure to complete the electrical tests of various structures on the power device chip. The entire process does not require the replacement of the probe card or the manual switching of the test circuit, which can effectively simplify the operation process of the entire electrical test and greatly improve the efficiency of the electrical test.

[0062] The invention also provides an automatic synchronous testing system for multi-structure power device chips. Figure 6 The module connection diagram of the multi-structure power device chip automatic synchronous test system according to one embodiment of the present invention is schematically shown. Figure 6 As shown, the multi-structure power device chip automatic synchronous testing system of the present invention includes the following structural components or modules:

[0063] Probe card 1 is the probe card described in any one of the above embodiments;

[0064] The switch matrix 2 is provided with a path control module corresponding to each structure on the multi-structure power device chip for controlling the on and off of the signal loop corresponding to the corresponding structure, one end of which is connected to the test equipment and the other end is connected to the probe card;

[0065] The test device 3 is deployed with a test program for calling a selected test program to test a multi-structure power device chip, which includes reading a set of parameter data from the selected test program in sequence, and testing the multi-structure power device chip according to the set of parameter data currently read, until all the parameter data in the test program are read.

[0066] Among them, the test program is pre-built for power device chips with different structural layouts to be electrically tested, and it contains several groups of parameter data corresponding to various structures on the power device chip with the structural layout. Each group of parameter data in the test program includes channel identification parameters and device test parameters corresponding to the corresponding structure. In other words, different power device chips correspond to different test programs. When testing, you only need to call the test program corresponding to the power device chip to be tested to implement electrical testing of the power device chip.

[0067] The test device is also deployed with a switching control program to call the selected test program to test the multi-structure power device chip. The switching control program can be pre-built and deployed on the test device. In this embodiment, the switching control program can be separated from the test program, and built and deployed on the test device separately, so that when building the test program, there is no need to build a switching control program separately, and when switching the power device chip for electrical testing, it only needs to call the corresponding test program to carry out.

[0068] Specifically, when the test equipment in the embodiment of the present invention performs automated synchronous testing of multi-structure power device chips, its implementation process and implementation principles can be specifically referred to the corresponding description of the above-mentioned method embodiment, such as the corresponding description of the conduction and disconnection of the signal loop, the identification of the target test structure, etc. in the method embodiment, so they will not be repeated here.

[0069] In addition, the present invention also provides a method flow for a worker to perform electrical testing on a power device chip using the above-mentioned multi-structure power device chip automatic synchronous testing system. Figure 7 The test method of the multi-structure power device chip of another embodiment of the present invention is schematically shown, which is applicable to the scenario in which an operator who performs electrical testing on the multi-structure power device chip operates the above-mentioned multi-structure power device chip automatic synchronous testing system. Figure 7 As shown, the method flow specifically includes the following steps:

[0070] Step S31: Encode different structures on the power device chip respectively to form parameter data corresponding to each structure, and construct a test program according to the parameter data of the corresponding structure, and deploy the test program on the test equipment, wherein the constructed test program defines multiple groups of parameter data for testing the multi-structure power device chip, each group of parameter data corresponds to a structure, and each group of parameter data includes a channel identification parameter and a device test parameter corresponding to the corresponding structure;

[0071] Step S32: connecting the switch matrix to the test equipment, and connecting the probe card to the switch matrix, wherein the switch matrix includes a path control module corresponding to each structure on the multi-structure power device chip and used to control the on and off of the signal loop corresponding to the corresponding structure;

[0072] Step S33: connecting the probe card to the power device chip, and connecting the probes on the probe card to all structures on the power device chip at the same time;

[0073] Step S34: starting a switching control program to perform an automated synchronous test on the multi-structure power device chip.

[0074] When the above method is used, before the power device chip is automatically and synchronously tested, it is necessary to first construct the test program and switching control program required for the test equipment to run. Step S31 is the step of constructing the test program. Specifically, when constructing the test program, it is necessary to encode the different structures on the power device chip respectively to compile the channel identification parameters and device test parameters required for the test program, and then form parameter data corresponding to each structure, so as to construct the test program. After the test program is constructed, the test program is deployed on the test equipment, and step S31 is completed.

[0075] After completing the construction of the test program and the switching control program required for the operation of the test equipment in step S31, execute steps S32 and S33, connect the switch matrix with the probe card and the test equipment, and place the probe card on the power device chip, and then execute step S34 to start the test equipment to call the test program deployed on the test equipment, so as to automatically perform electrical testing on the power device chip. The method flow of the specific test equipment when performing electrical testing on the power device chip can refer to the relevant description in the previous text, which will not be repeated here.

[0076] Figure 8 The overall process diagram of the testing method of a multi-structure power device chip according to an embodiment of the present invention is schematically shown. Figure 8 As shown, in the present invention, it is first necessary to construct a recipe (test program) and make a probe card. When making the probe card, a corresponding probe layout and circuit loop are compositely laid out according to all structures to be tested in the power device chip to be electrically tested, to obtain a probe card that composites the probe layout and circuit loop of all structures to be tested in the power device chip. When constructing the test program, all structures to be tested in the power device chip to be electrically tested are encoded separately to form several groups of channel identification parameters and device test parameters corresponding to all structures to be tested in the power device chip, and deployed to the test equipment. After completion, the probe card can be replaced and installed, and then the power device chip can be loaded to start electrical testing of the power device chip. Refer to Fig. 9 As shown, Fig. 9 The state of the probe card after installing and loading the power device chip and the schematic diagram of the probe card connected to the signal circuit according to one embodiment of the present invention is schematically shown. When performing electrical testing, the test program deployed in the test equipment is called to perform electrical testing on each structure on the power device chip in sequence according to the test program. After completing the electrical test of one structure, the test equipment can automatically switch the parameter data in the test program to perform electrical testing on the next structure, and then the entire process can complete the electrical testing of all structures in the power device chip without manual intervention by personnel. When all structures to be tested are tested, the power device chip can be unloaded, and the electrical test of the power device chip is ended.

[0077] In some embodiments, an embodiment of the present invention provides a non-volatile computer-readable storage medium, in which one or more programs including execution instructions are stored, and the execution instructions can be read and executed by an electronic device (including but not limited to a computer, a server, or a network device, etc.) to execute the test method for a multi-structure power device chip of a test device according to any of the above embodiments of the present invention, so that the electronic device that reads and executes the non-volatile computer-readable storage medium can be used as a test device to implement electrical testing of the multi-structure power device chip.

[0078] In some embodiments, an embodiment of the present invention further provides a computer program product, comprising a computer program stored on a non-volatile computer-readable storage medium, wherein the computer program comprises program instructions, and when the program instructions are executed by a computer, the computer is caused to execute any one of the above-mentioned embodiments of the testing method for a multi-structure power device chip of a testing device, so that the computer program product can be used as a testing device to implement electrical testing of the multi-structure power device chip.

[0079] In some embodiments, an embodiment of the present invention further provides a storage medium having a computer program stored thereon, characterized in that when the program is executed by a processor, the program implements a testing method for a multi-structure power device chip of a testing device according to any of the above-mentioned embodiments, so that a device that reads and executes the storage medium can be used as a testing device to implement electrical testing of the multi-structure power device chip.

[0080] Fig.10 FIG. 1 is a schematic diagram of a hardware structure of a method for testing a multi-structure power device chip for testing equipment provided by another embodiment of the present invention. Fig.10 As shown, the device includes:

[0081] One or more processors 610 and memory 620, Fig.10 A processor 610 is taken as an example.

[0082] The device for executing the test method of a multi-structure power device chip may further include: an input device 630 and an output device 640 .

[0083] The processor 610, the memory 620, the input device 630 and the output device 640 may be connected via a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0084] The memory 620, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the test method for a multi-structure power device chip in the embodiment of the present invention. The processor 610 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 620, that is, the test method for a multi-structure power device chip in the above method embodiment is implemented.

[0085] The memory 620 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created according to the use of a test method for a multi-structure power device chip, etc. In addition, the memory 620 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 620 may optionally include a memory remotely arranged relative to the processor 610, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0086] The input device 630 may receive input digital or character information and generate signals related to user settings and function control of the image processing device. The output device 640 may include a display device such as a display screen.

[0087] The one or more modules are stored in the memory 620 , and when executed by the one or more processors 610 , the testing method for a multi-structure power device chip in any of the above method embodiments is executed.

[0088] The above product can execute the method provided by the embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not described in detail in this embodiment, please refer to the method provided by the embodiment of the present invention.

[0089] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A probe card, characterized in that: The probe card can be used to perform electrical testing on power device chips with various structures; wherein, The probe card is provided with a probe layout capable of being connected to the multiple structures on the power device chip at the same time; Each probe layout is provided with a circuit loop corresponding to the corresponding structure.

2. A method for testing a multi-structure power device chip, used for a test device connected to the probe card of claim 1, characterized in that: include: Reading a set of parameter data from the test program in sequence, and testing the multi-structure power device chip according to the set of parameter data currently read, until all the parameter data in the test program are read; Wherein, each set of parameter data in the test program corresponds to a structure on the power device chip, each set of parameter data includes a channel identification parameter and a device test parameter corresponding to the corresponding structure, and the testing of the multi-structure power device chip according to the currently read set of parameter data includes: Determine the target test structure according to the channel identification parameters in the set of parameter data currently read, and turn on the signal loop corresponding to the target test structure according to the channel identification parameters, while turning off the signal loops corresponding to the remaining structures in the power device chip; A test signal is applied to a signal loop corresponding to a target test structure according to the device test parameters in a set of parameter data currently read, and a test result signal is obtained.

3. The testing method according to claim 2, characterized in that: The channel identification parameters include structure identification parameters corresponding to each structure and signal loop on-off parameters corresponding to each structure, and both the structure identification parameters and the signal loop on-off parameters are identified by binary codes.

4. The testing method according to claim 3, characterized in that: The signal loop corresponding to each structure includes a signal path arranged between the circuit loop corresponding to the structure and the test device. A path control module is arranged on the signal path and its on and off is controlled by the path control module. The test device controls the connected path control module according to the channel identification parameters to control the on and off of the signal path corresponding to the corresponding structure, thereby realizing the conduction or disconnection of the signal loop corresponding to the corresponding structure.

5. The testing method according to claim 4, characterized in that: The signal circuit corresponding to each structure includes a first signal path corresponding to the gate of the tested structure for applying a signal to the tested structure and a second signal path corresponding to the gate of the tested structure for obtaining a signal from the tested structure, and a third signal path corresponding to the source of the tested structure for applying a signal to the tested structure and a fourth signal path corresponding to the source of the tested structure for obtaining a signal from the tested structure. The first signal path, the second signal path, the third signal path and the fourth signal path constitute a group of signal paths, wherein the path control module includes four relays, and the four relays respectively control the on and off of the first signal path, the second signal path, the third signal path and the fourth signal path, and the signal circuit on-off parameters include parameters used to indicate the on or off of each relay in the corresponding signal circuit.

6. The testing method according to claim 2, characterized in that: The method further comprises: After the signal loop corresponding to the target test structure is turned on according to the channel identification parameters and the signal loops corresponding to the remaining structures in the power device chip are turned off, the signal loop is detected to determine whether the turned-on signal loop is correct, and a test signal is applied to the signal loop corresponding to the target test structure only when the turned-on signal loop is correct.

7. The testing method according to claim 6, characterized in that: The detecting of the signal loop to determine whether the conductive signal loop is correct includes: Apply a voltage signal within the safety range of the test to each signal circuit in turn, and detect whether there is a voltage signal in each signal circuit; According to the detection result, if there is a voltage signal in the signal circuit that is not currently turned on, it is determined that the signal circuit that is turned on is incorrect; If only the currently turned-on signal loop has a voltage signal, it is determined that the turned-on signal loop is correct.

8. The method according to claim 6, characterized in that The method further comprises: When the conducted signal loop is incorrect, all signal loops are turned off and the signal loop corresponding to the target test structure is turned on, and it is re-determined whether the conducted signal loop is correct, and the test is stopped when the number of incorrect times exceeds a preset threshold.

9. The method according to claim 2, characterized in that: After the test result signal is obtained, the signal loop corresponding to the target test structure is turned off, and a Kelvin test is performed on the signal loop to confirm whether the signal loop is completely disconnected.

10. An automatic synchronous testing system for multi-structure power device chips, characterized in that: include: A probe card, which is the probe card according to claim 1; A switch matrix is ​​provided with a path control module corresponding to each structure on the multi-structure power device chip for controlling the on and off of a signal loop corresponding to the corresponding structure, one end of which is connected to a test device and the other end is connected to a probe card; The test equipment is deployed with a test program for calling a selected test program to test a multi-structure power device chip, which includes reading a set of parameter data from the selected test program in sequence, and testing the multi-structure power device chip according to the set of parameter data currently read, until all the parameter data in the test program are read.

11. A method for testing a multi-structure power device chip, characterized in that: The automatic synchronous testing system for multi-structure power device chips as described in claim 10 above comprises: Different structures on the power device chip are encoded respectively to form parameter data corresponding to each structure, and a test program is constructed according to the parameter data of the corresponding structure, and the test program is deployed on the test equipment, wherein the constructed test program defines multiple groups of parameter data for testing the multi-structure power device chip, each group of parameter data corresponds to a structure, and each group of parameter data includes a channel identification parameter and a device test parameter corresponding to the corresponding structure; Connecting a switch matrix to a test device and connecting a probe card to the switch matrix, wherein the switch matrix includes a path control module corresponding to each structure on the multi-structure power device chip and used to control the on and off of a signal loop corresponding to the corresponding structure; Connecting the probe card to the power device chip, and connecting the probes on the probe card to all structures on the power device chip at the same time; The test equipment is started to perform automatic synchronous testing on the multi-structure power device chip.

12. A storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method described in any one of claims 2 to 9 are implemented.

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