Optical chip structure, preparation method thereof and electronic equipment

Abstract

The invention relates to an optical chip structure, a preparation method thereof and electronic equipment. The optical chip structure comprises a substrate; the dielectric layer is located on the substrate; the multi-layer metal structure is located on the dielectric layer, and the uppermost layer of the multi-layer metal structure is a metal barrier layer; a light reflecting layer on the metal barrier layer; an oxide layer on the light reflecting layer; the barrier layer is located on the side wall of a target through hole, the target through hole is formed in the oxide layer, the light reflecting layer and the metal barrier layer, the target through hole forms an opening in the top of the oxide layer, and the target through hole penetrates through the oxide layer and the light reflecting layer in the direction perpendicular to the substrate and exposes part of the metal barrier layer; and the metal filling layer is located on the barrier layer and fills the target through hole. According to the invention, at least metal can be prevented from diffusing into the through hole, and the influence on the electrical data and the yield of the optical chip due to resistance increase can be avoided.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to an optical chip structure and a preparation method thereof, and electronic equipment. Background Art

[0002] An optical chip is a chip that uses optical technology rather than traditional electronic technology to process and transmit information. It realizes the processing, conversion and transmission of optical signals by integrating optical components (such as lasers, modulators, detectors, etc.) with microelectronic circuits. Optical chips can handle higher-speed data transmission and are more suitable for large-scale data communication than traditional electronic chips. Compared with traditional electronic circuits, optical chips generate less heat during transmission, which can effectively reduce energy consumption, support larger bandwidth, and are suitable for high-speed data flow and parallel processing. The future development of optical chips is becoming increasingly important and can promote technological innovation in many fields such as communications, computing and medicine.

[0003] In the related technology, in traditional deep submicron and above BCD (Bipolar-CMOS-DMOS) products, the back-end connection layer metal generally adopts a sandwich structure to reduce contact resistance and prevent metal layer diffusion.

[0004] However, in optical chip products, the metal layer needs to form a light reflecting layer. In the subsequent through-hole manufacturing process, the high temperature will cause the metal of the light reflecting layer to diffuse into the through-hole, resulting in a large contact resistance, which in turn has a significant impact on the electrical data and yield rate. Summary of the invention

[0005] Based on this, it is necessary to provide an optical chip structure and its preparation method, and electronic device to address the above technical problems, which can at least prevent metal from diffusing into the through holes, prevent resistance from increasing, and further affect the electrical data and yield of the optical chip.

[0006] In order to achieve the above-mentioned purpose and other purposes, in a first aspect, the present disclosure provides an optical chip structure, including: a substrate; a dielectric layer, located on the substrate; a multi-layer metal structure, located on the dielectric layer, the top layer of the multi-layer metal structure is a metal barrier layer; a light reflecting layer, located on the metal barrier layer; an oxide layer, located on the light reflecting layer; a barrier layer, located on the side wall of a target through hole, the target through hole is formed in the oxide layer, the light reflecting layer and the metal barrier layer, the target through hole forms an opening at the top of the oxide layer, the target through hole passes through the oxide layer and the light reflecting layer in a direction perpendicular to the substrate and exposes part of the metal barrier layer; a metal filling layer, located on the barrier layer, and filling the target through hole.

[0007] In the optical chip structure of the above embodiment, a metal barrier layer is formed on the top layer of the multi-layer metal structure, thereby avoiding the high temperature required for the subsequent formation of through holes, which causes the metal in the multi-layer metal structure to enter the through holes, thereby avoiding an increase in the resistance of the optical chip, and further avoiding affecting the electrical data and yield of the optical chip.

[0008] In one embodiment, the multi-layer metal structure includes: a lower metal layer located on the dielectric layer; an intermediate metal layer located on the lower metal layer; and a metal barrier layer located on the intermediate metal layer.

[0009] In one embodiment, the thickness of the light reflecting layer is 1000 Å-2000 Å.

[0010] In one embodiment, the thickness of the metal barrier layer is 300 Å-500 Å, the thickness of the underlying metal layer is 300 Å-500 Å, and the thickness of the intermediate metal layer is 3000 Å-5000 Å.

[0011] In one embodiment, the depth of the trench formed by the target through hole on the metal barrier layer is 100 Å-200 Å.

[0012] In a second aspect, an embodiment of the present disclosure further provides an electronic device, including: the optical chip structure in any of the above embodiments.

[0013] In a third aspect, the embodiments of the present disclosure also provide a method for preparing an optical chip structure, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a multi-layer metal structure on the dielectric layer, the topmost layer of the multi-layer metal structure being a metal barrier layer; forming a light reflecting layer on the metal barrier layer; forming an oxide layer on the light reflecting layer; forming a target through hole in the optical chip structure, the target through hole forming an opening at the top of the oxide layer, the bottom of the barrier layer being located in the metal barrier layer, the target through hole penetrating the oxide layer and the light reflecting layer in a direction perpendicular to the substrate and exposing a portion of the metal barrier layer; forming a barrier layer on the side wall of the target through hole; forming a metal filling layer in the target through hole on the barrier layer, the metal filling layer filling the target through hole.

[0014] In the preparation method of the optical chip structure in the above embodiment, a metal barrier layer is formed on the topmost layer of the multi-layer metal structure, thereby avoiding the high temperature required for the subsequent formation of through holes, which causes the metal in the multi-layer metal structure to enter the through holes, thereby avoiding an increase in the resistance of the optical chip, and further avoiding affecting the electrical data and yield of the optical chip.

[0015] In one embodiment, a multilayer metal structure is formed on a dielectric layer, including: depositing a lower metal layer on the dielectric layer under a first deposition condition; forming an intermediate metal layer on the lower metal layer under a second deposition condition; and forming a metal barrier layer on the intermediate metal layer under a third deposition condition.

[0016] In the method for preparing the optical chip structure of the above embodiment, the deposition thickness of the multi-layer metal structure is ensured by setting different deposition conditions.

[0017] In one of the embodiments, a target through hole is formed in an optical chip structure, including: forming a patterned photoresist layer on an oxide layer; using the patterned photoresist layer as a mask, etching the oxide layer, the light reflecting layer, and the metal barrier layer using a dry etching process to obtain a target through hole that penetrates the oxide layer and the light reflecting layer in a direction perpendicular to the substrate and exposes a portion of the metal barrier layer.

[0018] In one embodiment, after a metal filling layer is formed in a target through hole on the barrier layer, the method further includes: polishing and grinding the top surface of the optical chip structure based on a chemical mechanical polishing process to make the top surface of the optical chip structure form a plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of a process for preparing an optical chip structure provided in an embodiment;

[0021] Figure 2 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S3000 in a method for preparing an optical chip structure provided in an embodiment;

[0022] Figure 3 A schematic diagram of a structure obtained in step S5000 in a method for preparing an optical chip structure provided in an embodiment;

[0023] Figure 4 A schematic diagram of a structure obtained in step S8000 in a method for preparing an optical chip structure provided in an embodiment;

[0024] Figure 5 It is a schematic diagram of the longitudinal cross-section structure of an optical chip structure provided in a comparative embodiment.

[0025] Description of reference numerals:

[0026] 201, substrate; 202, dielectric layer; 203, multi-layer metal structure; 2031, lower metal layer; 2032, middle metal layer; 2033, metal barrier layer; 301, light reflection layer; 302, oxide layer; 401, barrier layer; 402, metal filling layer. DETAILED DESCRIPTION

[0027] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0029] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0030] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0031] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0033] Please refer to Figure 1-Figure 5 The present disclosure provides a method for preparing an optical chip structure, comprising the following steps:

[0034] Step S1000: providing a substrate 201 .

[0035] Wherein, the substrate 201 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 201 can be a single-layer structure or a multi-layer structure. For example, the substrate 201 can be a silicon substrate 201, a silicon germanium substrate 201, a silicon germanium carbon substrate 201, a silicon carbide substrate 201, a gallium arsenide substrate 201, an indium arsenide substrate 201, an indium phosphide substrate 201 or other III / V semiconductor substrates 201 or II / VI semiconductor substrates 201. Alternatively, for example, the substrate 201 can be a layered substrate 201 including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate 201 should not limit the scope of protection of the present disclosure.

[0036] Step S2000 : forming a dielectric layer 202 on the substrate 201 .

[0037] Step S3000 : forming a multi-layer metal structure 203 on the dielectric layer 202 .

[0038] The topmost layer of the multi-layer metal structure 203 is a metal barrier layer 2033 .

[0039] Step S4000 : forming a light reflection layer 301 on the metal barrier layer 2033 .

[0040] Step S5000 : forming an oxide layer 302 on the light reflecting layer 301 .

[0041] Step S6000: forming a target through hole in the optical chip structure.

[0042] The target through hole forms an opening at the top of the oxide layer 302 , the bottom of the barrier layer 401 is located in the metal barrier layer 2033 , and the target through hole penetrates the oxide layer 302 and the light reflection layer 301 in a direction perpendicular to the substrate 201 and exposes part of the metal barrier layer 2033 .

[0043] Step S7000: forming a barrier layer 401 on the sidewall of the target through hole.

[0044] Step S8000 : forming a metal filling layer 402 on the barrier layer 401 and in the target through hole.

[0045] The metal filling layer 402 fills the target through hole.

[0046] Here, the dielectric layer 202, the multilayer metal structure 203, the light reflection layer 301, the oxide layer 302, the barrier layer 401 and the metal filling layer 402 can be deposited on the substrate 201 by a deposition process. The deposition process may include but is not limited to at least one of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) and a spin-on dielectric layer 202 (Spin-on Dielectric, SOD) process.

[0047] In the optical chip structure of the above embodiment, a metal barrier layer 2033 is formed on the top layer of the multi-layer metal structure 203, thereby preventing the high temperature required for the subsequent formation of a through hole from causing the metal in the multi-layer metal structure 203 to enter the through hole, thereby preventing the resistance of the optical chip from increasing, and further preventing the electrical data and yield of the optical chip from being affected.

[0048] Please refer to the figure Figure 5 , Figure 5 A comparative example provided for this application, such as Figure 5 As shown in, in existing optical chip products, the metal barrier layer 2033 is not deposited on the top layer of the multi-layer metal structure 203. During the subsequent deposition of the barrier layer 401, the high temperature (about 400°C) will cause the metal in the multi-layer metal structure 203 to diffuse into the through hole, thereby resulting in a large contact resistance, affecting the electrical properties and reducing the yield.

[0049] As an example, in an existing optical chip, a substrate 201, a dielectric layer 202, a multi-layer metal structure 203, an oxide layer 302, a barrier layer 401 and a metal filling layer 402 are included, wherein the barrier layer 401 and the metal filling layer 402 are formed in a through hole.

[0050] See also Figure 5 In the prior art, the metal barrier layer 2033 is not deposited; in the subsequent process of depositing the barrier layer 401, the high temperature (about 400°C) will cause the metal to diffuse into the through hole, resulting in a large contact resistance, affecting electrical properties and reducing yield.

[0051] In step S2000 , the dielectric layer 202 may be an oxide layer 302 , such as silicon dioxide or the like.

[0052] The thickness of the oxide layer 302 may be 100Å-200Å.

[0053] As an example, the thickness of the oxide layer 302 may be 100 Å, 110 Å, 130 Å, 150 Å, 170 Å, 200 Å, etc.

[0054] In step S3000, please continue to refer to Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S3000 in a method for preparing an optical chip structure provided in an embodiment. Figure 2 The multi-layer metal structure 203 includes: a lower metal layer 2031 located on the dielectric layer 202; an intermediate metal layer 2032 located on the lower metal layer 2031; and a metal barrier layer 2033 located on the intermediate metal layer 2032.

[0055] Specifically, the steps of forming a multilayer metal structure 203 on the dielectric layer 202 include: under a first deposition condition, depositing a lower metal layer 2031 on the dielectric layer 202; under a second deposition condition, forming an intermediate metal layer 2032 on the lower metal layer 2031; under a third deposition condition, forming a metal barrier layer 2033 on the intermediate metal layer 2032.

[0056] The lower metal layer 2031 may be Ti and / or TiN.

[0057] The thickness of the lower metal layer 2031 may be 300 Å-500 Å.

[0058] As an example, the thickness of the lower metal layer 2031 can be 300 Å, 400 Å, 500 Å, etc.

[0059] The intermediate metal layer 2032 may be AlCu.

[0060] Specifically, the thickness of the intermediate metal layer 2032 may be 3000 Å-5000 Å.

[0061] As an example, the thickness of the intermediate metal layer 2032 may be 3000 Å, 4000 Å, 5000 Å, etc.

[0062] The metal barrier layer 2033 may be Ti and / or TiN.

[0063] Specifically, the thickness of the metal barrier layer 2033 may be 300 Å-500 Å.

[0064] As an example, the thickness of the metal barrier layer 2033 may be 3000 Å, 400 Å, 500 Å, etc.

[0065] In step S4000, please refer to Figure 3In the step of forming the light reflecting layer 301 on the metal barrier layer 2033 , the light reflecting layer 301 may be AlCu.

[0066] Specifically, the thickness of the light reflecting layer 301 may be 1000 Å-2000 Å.

[0067] As an example, the thickness of the light reflecting layer 301 may be 1000 Å, 1100 Å, 1400 Å, 1700 Å, 2000 Å, etc.

[0068] Here, it should be noted that in optical chips, the optical reflection layer (or reflector layer) is a key layer for controlling the propagation direction of optical signals. It guides the optical signal to the desired position by reflecting light, and is usually used for path control of optical signals, signal focusing or improving optical efficiency. The application of optical reflection layers in optical chips mainly includes: beam guidance and focusing. Optical reflection layers are often used for path guidance of optical signals, especially in optical devices (such as optical modulators, optical detectors, lasers, etc.), used to transmit optical signals from one part to another. They can also be used to focus optical signals, especially in the design of lasers and other light sources, to improve the radiation efficiency of light by reflecting the light beam; improve optical efficiency, by optimizing the design of the reflection layer, reducing the scattering and loss of light, and improving the transmission efficiency of optical signals. The reflection layer can concentrate the optical signal and reduce energy loss, which is particularly important for efficient optical communications and other optical systems; wavelength selective reflection, some optical reflection layers are designed to be wavelength selective, which means that they only reflect light of a specific wavelength. This property is very important in some optical devices. For example, in wavelength division multiplexing (WDM) optical communication systems, it is used to selectively reflect and transmit optical signals of different wavelengths; to reduce crosstalk. In multi-channel optical communication systems, the optical reflective layer can effectively reduce the crosstalk between different channels, ensuring that the optical signal of each channel can be transmitted independently and clearly.

[0069] The light reflecting layer may also be made of a material with high reflectivity such as silver or gold.

[0070] In step S5000, please refer to Figure 3 In the step of forming the oxide layer 302 on the light reflecting layer 301 , the oxide layer 302 may be deposited by a CVD (chemical vapor deposition) process.

[0071] Here, Chemical Vapor Deposition (CVD) is a technology that uses gas chemical reactions to deposit solid substances onto the surface of a substrate. Usually carried out at high temperatures, the gas reactants react with the surface of the substrate by heating or excitation to form a solid film or coating. CVD technology is widely used in semiconductor manufacturing, optoelectronic devices, solar cells, metal coatings and other fields. Its basic principle is to introduce a gas (precursor gas) containing the target material into the reaction chamber, and generate a solid substance through a chemical reaction under high temperature or other conditions and deposit it on the substrate.

[0072] The thickness of the oxide layer 302 may be 2000 Å-6000 Å.

[0073] As an example, the thickness of the oxide layer 302 may be 2000 Å, 3000 Å, 3500 Å, 4000 Å, 5000 Å, 6000 Å, etc.

[0074] In step S6000, please refer to Figure 4 , forming a target through hole in the optical chip structure, including: forming a patterned photoresist layer on the oxide layer 302; using the patterned photoresist layer as a mask, etching the oxide layer 302, the light reflecting layer 301, and the metal barrier layer 2033 by a dry etching process, to obtain a target through hole that penetrates the oxide layer 302 and the light reflecting layer 301 in a direction perpendicular to the substrate 201 and exposes a portion of the metal barrier layer 2033.

[0075] Here, dry etching is a technique that uses physical or chemical methods such as gas or plasma to remove specific areas on the surface of a material without a liquid medium. Compared with traditional wet etching (using chemical liquid solutions), the advantage of dry etching is that it can achieve higher precision and smaller-scale pattern etching, and is often used in the manufacture of microelectronic devices. The dry etching process is usually carried out in a vacuum environment, using gas or plasma reactions to etch the surface of the material. The gas source (usually a gas precursor) reacts with the surface of the material through excitation, plasma chemical reaction or physical impact to remove unwanted areas. The main types of dry etching include: plasma etching, which uses high-energy particles of plasma (such as ions, free radicals, electrons, etc.) to react with the material to remove the surface material. Plasma etching is a typical dry etching method that can accurately control the etching rate and depth; reactive ion etching (RIE) combines the effects of plasma and ion bombardment. The reactive ions in the gas bombard the surface of the material under the action of the electric field to achieve etching. RIE can precisely control the directionality of etching and is suitable for etching of complex patterns; Deep Reactive Ion Etching (DRIE) is mainly used in micro-electromechanical systems (MEMS) and can achieve deeper etching. It is usually used to etch deep holes and vertical sidewalls. Dry laser etching (Laser Etching) irradiates the surface of the material with a high-energy laser beam, locally heats and evaporates the material, thereby achieving etching. Laser etching is usually used for larger patterns or harder materials; Ion Beam Etching (IBE) uses an accelerated ion beam to directly bombard the surface of the material to remove the surface material. This method has high precision, but the etching rate is slow. Dry etching is a key step in the manufacture of integrated circuits (ICs) and is used to define circuit patterns, etch wires, transistors and other microstructures. Dry etching has the characteristics of high precision, strong directionality and no pollution. Dry etching can achieve high-precision and small-scale graphic etching, which is suitable for precision manufacturing such as microelectronics and MEMS; especially reactive ion etching (RIE), which can accurately control the directionality of etching and is suitable for the production of complex structures; compared with wet etching, dry etching does not use liquid chemicals, so it can reduce pollution and corrosion problems in some cases.

[0076] Here, the gas used for dry etching in this application can be CHF3, CF4, C4F6, O2, CL2, CL3, etc.

[0077] The depth of the trench formed by the target through hole on the metal barrier layer 2033 is 100 Å-200 Å.

[0078] As an example, the depth of the trench formed by the target through hole on the metal barrier layer 2033 can be 100Å, 110Å, 130Å, 150Å, 170Å, 200Å, etc.

[0079] In step S8000, please continue to refer to Figure 4 After forming a metal filling layer 402 in the target through hole on the barrier layer 401, the method further includes: polishing and grinding the top surface of the optical chip structure based on a chemical mechanical polishing process to make the top surface of the optical chip structure form a plane.

[0080] Among them, the CMP process (Chemical Mechanical Planarization) is a surface flattening technology widely used in semiconductor manufacturing. It combines the dual effects of chemical reaction and mechanical grinding, and is mainly used to remove the unevenness of the wafer surface to achieve high-precision flatness requirements.

[0081] Among them, the CMP process is to place a wafer (usually a silicon wafer) on a rotating flattening disk (polishing disk), cooperate with a specific chemical polishing liquid (called polishing liquid or chemical liquid), and rotate and pressurize it at the same time to achieve surface material removal. Chemical liquid can help soften and remove the material of the surface layer, while mechanical grinding smoothes the uneven surface by applying physical pressure. The CMP process has the advantages of high precision and flatness. CMP can achieve nanometer-level flatness and meet the manufacturing requirements of modern integrated circuits and microelectronic devices; CMP can be flattened on different materials (such as silicon, copper, aluminum, etc.) and has a high degree of material adaptability; CMP can also remove surface defects, reduce surface roughness, make the surface smoother, and improve the reliability of subsequent processes.

[0082] Figure 5 An implementation method of forming an optical chip structure in the related art is given. Specifically, in the preparation method of the optical chip in the prior art, a dielectric layer 202 is first deposited, and then a multilayer metal structure 203 is formed. The multilayer metal structure 203 can be a Ti / TiN and AlCu structure to form a light reflection layer 301, so as to improve the light reflection efficiency and reduce the stray signal intensity. Then, an oxide layer 302 is deposited by CVD (chemical vapor deposition), and a through hole is formed by photolithography and dry etching. Then, a barrier layer 401 is deposited and filled with tungsten to form a through hole. Finally, a CMP process is used for grinding to form a plane for subsequent process.

[0083] The above process and Figure 1-Figure 4 The steps of the embodiments given in are the same or similar, and the specific process steps are not repeated here.

[0084] Compared to Figure 1-Figure 4In the method for preparing the optical chip structure exemplified in the example, Figure 5 In the process of depositing the barrier layer 401 as shown in the example, high temperature (about 400°C) will cause the metal to diffuse into the through hole. Therefore, the metal barrier layer 2033 is formed on the top layer of the multilayer metal structure 203, which at least prevents the high temperature required for subsequent formation of the through hole from causing the metal in the multilayer metal structure 203 to enter the through hole, thereby preventing the resistance of the optical chip from increasing, and further preventing the electrical data and yield of the optical chip from being affected.

[0085] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0086] Based on the same inventive concept, the disclosed embodiment also provides a method for preparing an optical chip structure, and the obtained optical chip structure. The implementation scheme for solving the problem provided by the optical chip structure is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more optical chip structure embodiments provided below can refer to the limitations of the preparation method of the optical chip structure above, and will not be repeated here.

[0087] In some embodiments, please refer to Figure 4 , an optical chip structure, comprising: a substrate 201; a dielectric layer 202, located on the substrate 201; a multi-layer metal structure 203, located on the dielectric layer 202, the top layer of the multi-layer metal structure 203 being a metal barrier layer 2033; a light reflection layer 301, located on the metal barrier layer 2033; an oxide layer 302, located on the light reflection layer 301; a barrier layer 401, located on the sidewall of a target through hole, the target through hole being formed in the oxide layer 302, the light reflection layer 301 and the metal barrier layer 2033, the target through hole forming an opening at the top of the oxide layer 302, the target through hole penetrating the oxide layer 302 and the light reflection layer 301 in a direction perpendicular to the substrate 201 and exposing a portion of the metal barrier layer 2033; a metal filling layer 402, located on the barrier layer 401, and filling the target through hole.

[0088] In some embodiments, the multi-layer metal structure 203 includes: a lower metal layer 2031 located on the dielectric layer 202 ; an intermediate metal layer 2032 located on the lower metal layer 2031 ; and a metal barrier layer 2033 located on the intermediate metal layer 2032 .

[0089] In some embodiments, the thickness of the light reflecting layer 301 is 1000 Å-2000 Å.

[0090] In some embodiments, the thickness of the metal barrier layer 2033 is 300 Å -500 Å, the thickness of the lower metal layer 2031 is 300 Å -500 Å, and the thickness of the intermediate metal layer 2032 is 3000 Å -5000 Å.

[0091] In some embodiments, the depth of the trench formed by the target through hole on the metal barrier layer 2033 is 100 Å-200 Å.

[0092] In the optical chip structure in the above-mentioned embodiment, by forming a metal barrier layer 2033 on the top layer of the multilayer metal structure 203, the high temperature required for subsequent formation of the through hole is avoided so that the metal in the multilayer metal structure 203 enters the through hole, thereby avoiding the increase of the resistance of the optical chip, and thus avoiding the impact on the electrical data and yield rate of the optical chip. In some embodiments, the present disclosure provides an electronic device, including the optical chip structure of any one of the embodiments of the present disclosure. The electronic device is, for example but not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Consumer electronic products are such as mobile phones, tablet computers, laptops, desktop monitors, all-in-one computers, etc. Home electronic products are such as smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products are such as vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products are such as ATM machines, self-service terminals, etc.

[0093] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. An optical chip structure, characterized in that: include: substrate; A dielectric layer, located on the substrate; A multi-layer metal structure is located on the dielectric layer, and the top layer of the multi-layer metal structure is a metal barrier layer; a light reflecting layer, located on the metal barrier layer; an oxide layer, located on the light reflecting layer; A barrier layer is located on the side wall of a target through hole, wherein the target through hole is formed in the oxide layer, the light reflecting layer and the metal barrier layer, wherein an opening is formed at the top of the oxide layer, and the target through hole penetrates the oxide layer and the light reflecting layer in a direction perpendicular to the substrate and exposes a portion of the metal barrier layer; The metal filling layer is located on the barrier layer and fills the target through hole.

2. The optical chip structure according to claim 1, characterized in that: The multi-layer metal structure comprises: A lower metal layer, located on the dielectric layer; an intermediate metal layer, located on the lower metal layer; The metal barrier layer is located on the middle metal layer.

3. The optical chip structure according to claim 1, characterized in that: The thickness of the light reflecting layer is 1000 Å-2000 Å.

4. The optical chip structure according to claim 2, characterized in that: The thickness of the metal barrier layer is 300 Å-500 Å, the thickness of the lower metal layer is 300 Å-500 Å, and the thickness of the intermediate metal layer is 3000 Å-5000 Å.

5. The optical chip structure according to claim 3, characterized in that: The depth of the trench formed by the target through hole on the metal barrier layer is 100 Å-200 Å.

6. An electronic device, characterized in that: include: The optical chip structure according to any one of claims 1 to 5.

7. A method for preparing an optical chip structure, characterized in that: The method comprises: providing a substrate; forming a dielectric layer on the substrate; forming a multi-layer metal structure on the dielectric layer, wherein the top layer of the multi-layer metal structure is a metal barrier layer; forming a light reflecting layer on the metal barrier layer; forming an oxide layer on the light reflecting layer; A target through hole is formed in the optical chip structure, wherein the target through hole forms an opening at the top of the oxide layer, the bottom of the barrier layer is located in the metal barrier layer, and the target through hole penetrates the oxide layer and the light reflecting layer in a direction perpendicular to the substrate and exposes a portion of the metal barrier layer; forming a barrier layer on the sidewall of the target through hole; A metal filling layer is formed on the barrier layer and in the target through hole, and the metal filling layer fills the target through hole.

8. The preparation method according to claim 7, characterized in that: A multi-layer metal structure is formed on the dielectric layer, comprising: Under a first deposition condition, depositing a lower metal layer on the dielectric layer; forming an intermediate metal layer on the lower metal layer under a second deposition condition; Under a third deposition condition, a metal barrier layer is formed on the intermediate metal layer.

9. The preparation method according to claim 8, characterized in that: Forming a target through hole in the optical chip structure includes: forming a patterned photoresist layer on the oxide layer; The patterned photoresist layer is used as a mask and a dry etching process is adopted to etch the oxide layer, the light reflecting layer and the metal barrier layer to obtain a target through hole that penetrates the oxide layer and the light reflecting layer in a direction perpendicular to the substrate and exposes a portion of the metal barrier layer.

10. The preparation method according to claim 7, characterized in that: After forming a metal filling layer on the barrier layer and in the target through hole, the method further includes: Based on the chemical mechanical polishing process, the top surface of the optical chip structure is polished and ground to form a plane on the top surface of the optical chip structure.

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