Loop stability enhancing circuit and low dropout regulator chip

Abstract

The invention discloses a loop stability enhancing circuit, which relates to the technical field of integrated circuits and comprises a PMOS (P-channel Metal Oxide Semiconductor) tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an NMOS (N-channel Metal Oxide Semiconductor) tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, M NMOS tubes connected in series, an NMOS tube NM5, an NMOS tube NM6,..., an NMOS tube NMM + 4, N NMOS tubes connected in series, an NMOS tube NMM + 5, an NMOS tube NMM + 6,..., an NMOS tube MM + N + 4, an NMOS depletion tube NMOS1, a resistor R1, a resistor R2, a capacitor C1 and a current source IQ. The invention further discloses a low dropout regulator chip which is provided with the loop stability enhancing circuit. According to the invention, the phase margin is increased, and the stability is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a circuit for enhancing loop stability and a low voltage drop linear regulator chip. Background Art

[0002] DC / DC power converters have occupied a huge market share of power supply and are widely used due to their high conversion efficiency. However, DC / DC power converters have large ripples, so low-dropout linear regulators play a huge role in applications that require low ripples. Low-dropout linear regulators have the characteristics of low power consumption, simple structure, small chip area, low noise and high power supply rejection ratio, but the challenge encountered in the design of low-dropout linear regulators is frequency compensation.

[0003] The traditional frequency compensation method is Miller compensation, where a capacitor C is connected across the input and output of the second-stage operational amplifier A2. C , which is equivalent to placing a capacitor with a value of (1+A2)C at the input of A2 C The pole moves toward the origin, that is, the low frequency direction, and the output pole moves away from the origin, achieving pole separation. At this time, a zero point is introduced. By adjusting the resistor R A The size of the zero point is adjusted to the appropriate position to compensate the second pole and realize loop compensation. However, when the load current fluctuates in a large range, loop oscillation may occur.

[0004] Therefore, those skilled in the art are committed to developing a circuit for enhancing loop stability and a low voltage drop linear regulator chip. Summary of the invention

[0005] In view of the above-mentioned defects in the prior art, the technical problem to be solved by the present invention is how to enhance loop stability.

[0006] Research has found that when the load current fluctuates greatly, the position of the pole changes. If the size of the zero-adjusting resistor can follow the change of the pole, when the load current becomes larger, the position of the zero point will also move to the high frequency, and the position of this zero point and the output pole will not be much different. This zero point can compensate for the additional phase shift caused by the output pole.

[0007] In one embodiment of the present invention, a loop stability enhancement circuit is provided, including a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, M NMOS tubes connected in series, including an NMOS tube NM5, an NMOS tube NM6, ..., an NMOS tube NM7, an NMOS tube NM8, an NMOS tube NM9, an NMOS tube NM10, an NMOS tube NM11, an NMOS tube NM12, an NMOS tube NM13, an NMOS tube NM14, an NMOS tube NM15, an NMOS tube NM16, ..., an NMOS tube NM17, an NMOS tube NM18, an NMOS tube NM19, an NMOS tube NM20, an NMOS tube NM21 M+4 , N NMOS tubes connected in series, including NMOS tube NMM+5 、NMOS tube NM M+6 、……、NMOS tube M M+N+4 , NMOS consumption NMOS1, resistor R1, resistor R2, capacitor C1, current source I Q ; The sources of PMOS tubes PM1, PM2, PM3, PM4 and PM5 are connected together to VDD, and the gates of PMOS tubes PM1, PM2 and PM3 are connected to the drain of PMOS tube PM1 and the current source I Q One end of the current source I Q The other end of the transistor is grounded, the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2, the gate, the gates of the NMOS transistors connected in series, and the gate of the NMOS transistor NMOS1, the source of the NMOS transistor NM2 is grounded, the drain of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM5, one end of the capacitor C1, the gates of the NMOS transistors NM1, NMOS transistor NM3, and NMOS transistor NM4, the gates of the M NMOS transistors connected in series are connected to the resistors R1 and R2, the source of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM6, the source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7, and so on. M+3 The source of the NMOS tube NM M+4 The drain connection of NMOS tube NM M+4 The source of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected to the NMOS tube NM M+5 , the drains of NMOS tube NM3 are connected together, and the drains of NMOS tube NM M+5 The source of the NMOS tube NM M+6 The drain connection of NMOS tube NM M+6 The source of the NMOS tube NM M+7 The drain connection of NMOS tube M M+N+3 The source of NMOS tube M M+N+4 The drain connection of NMOS tube M M+N+4 The source of NMOS tube NM3 is connected to the drain of NMOS tube NM4, the source of NMOS tube NM4 is grounded, the gate and drain of PMOS tube PM4 are connected to the gate of PMOS tube PM5, the drain of NMOS tube NMOS1 is connected together, the source of NMOS tube NMOS1 is connected to the drain of NMOS tube NM1, the source of NMOS tube NM1 is grounded, the drain of PMOS tube PM5 is connected to the other end of resistor R1, and the other end of resistor R2 is grounded; N series-connected NMOS tubes operate in a linear region, and NMOS tubes NM3 and NMOS tubes NM4 operate in a linear region. The gate voltage of the N series-connected NMOS tubes does not change with the load current. When the load current is small, a zero point is provided to offset the influence of the pole. When the load current increases, the gate voltage of the NMOS tubes NM3 and NMOS tubes NM4 increases accordingly. The equivalent resistance of the N series-connected NMOS tubes is connected in parallel with the equivalent resistance of the NMOS tubes NM3 and NMOS tubes NM4. The position of the zero point moves toward high frequency accordingly, and the position of the zero point and the output pole are not much different. The zero point can compensate for the additional phase shift caused by the output pole.

[0008] Optionally, in the loop stability enhancement circuit of any of the above embodiments, M is greater than or equal to 8 and less than or equal to 20.

[0009] Preferably, in the loop stability enhancement circuit of the above embodiment, M is equal to 12.

[0010] Optionally, in the loop stability enhancement circuit of any of the above embodiments, the channel length of the M series-connected NMOS tubes is greater than or equal to 10 um and less than or equal to 20 um.

[0011] Preferably, in the loop stability enhancement circuit of the above embodiment, the channel length of the M series-connected NMOS tubes is equal to 15 um.

[0012] Furthermore, in the loop stability enhancement circuit of the above embodiment, the width and length of the channels of the M series-connected NMOS transistors are equal.

[0013] Optionally, in the loop stability enhancement circuit of any of the above embodiments, N is greater than or equal to 6 and less than or equal to 12.

[0014] Optionally, in the loop stability enhancement circuit of any of the above embodiments, the channel length of the N series-connected NMOS tubes is greater than or equal to 10 um and less than or equal to 20 um.

[0015] Preferably, in the loop stability enhancement circuit of the above embodiment, the channel length of the N series-connected NMOS transistors is equal to 18 um.

[0016] Furthermore, in the loop stability enhancement circuit of the above embodiment, the width and length of the channels of the N series-connected NMOS transistors are equal.

[0017] Preferably, in the circuit for enhancing loop stability of the above embodiment, N is equal to 8.

[0018] Optionally, in the loop stability enhancement circuit of any of the above embodiments, the channel lengths of the NMOS transistors NM3 and NMOS transistors NM4 are greater than or equal to 15 um and less than or equal to 20 um.

[0019] Preferably, in the loop stability enhancement circuit of the above embodiment, the channel lengths of the NMOS transistors NM3 and NMOS transistors NM4 are equal to 18 um.

[0020] Optionally, in the loop stability enhancement circuit of any of the above embodiments, the value of the capacitor C1 is greater than or equal to 600 fF and less than or equal to 800 fF.

[0021] Preferably, in the loop stability enhancement circuit of the above embodiment, the value of the capacitor C1 is equal to 700 fF.

[0022] Based on the above embodiment, in another embodiment of the present invention, a low voltage dropout linear regulator chip is provided, which is provided with the loop stability enhancement circuit in the above embodiment.

[0023] The present invention improves the prior art, uses N series-connected NMOS tubes working in a linear region to replace resistors, and connects NMOS tubes NM3 and NMOS tubes NM4 working in a linear region in parallel. The gate voltages of the NMOS tubes NM3 and NMOS tubes NM4 are voltages that follow the output load current transformation, and the zero points generated by their equivalent resistances follow the load current frequency compensation. When the load current changes, the positions of the zero points and the poles change, thereby achieving the purpose of increasing the phase margin and ensuring the stability.

[0024] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram illustrating the structure of a conventional frequency compensation circuit according to an exemplary embodiment; Figure 2 is a schematic diagram illustrating a structure of a circuit for enhancing loop stability according to an exemplary embodiment; Figure 3 is a schematic diagram illustrating the structure of a low dropout linear regulator chip according to an exemplary embodiment. DETAILED DESCRIPTION

[0026] The following describes several preferred embodiments of the present invention with reference to the drawings in the specification, so that the technical content is clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0027] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is schematically exaggerated in some places in the drawings.

[0028] The traditional frequency compensation circuit is Miller compensation, such as Figure 1 As shown, a capacitor C is connected across the input and output of the second stage operational amplifier A2. C , which is equivalent to placing a capacitor with a value of (1+A2)C at the input of A2 C The pole moves toward the origin, that is, the low frequency direction, and the output pole moves away from the origin, achieving pole separation. At this time, a zero point is introduced. By adjusting the resistor R A The size of the zero point is adjusted to a suitable position to compensate the second pole and realize loop compensation. However, when the load current fluctuates in a large range, loop oscillation may occur.

[0029] This embodiment designs a circuit to enhance loop stability, such as Figure 2 As shown, it includes: PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, M NMOS tubes connected in series, including NMOS tube NM5, NMOS tube NM6, ..., NMOS tube NM M+4 , N NMOS tubes connected in series, including NMOS tube NM M+5 、NMOS tube NM M+6 、……、NMOS tube M M+N+4 , NMOS consumption NMOS1, resistor R1, resistor R2, capacitor C1, current source I Q ; Wherein M is equal to 12, the channel length of the 12 NMOS tubes connected in series is equal to 15um, and the width and length of the channel of the 12 NMOS tubes connected in series are equal; N is equal to 8, the channel length of the 8 NMOS tubes connected in series is equal to 18um, and the width and length of the channel of the 8 NMOS tubes connected in series are equal; the value of capacitor C1 is equal to 700fF.

[0030] The sources of the PMOS tubes PM1, PM2, PM3, PM4 and PM5 are connected together to VDD, and the gates of the PMOS tubes PM1, PM2 and PM3 are connected to the drain of the PMOS tube PM1 and the current source I Q One end of the current source I QThe other end of the transistor is grounded, the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2, the gate, the gates of the 8 series-connected NMOS transistors, and the gate of the NMOS transistor NMOS1, the source of the NMOS transistor NM2 is grounded, the drain of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM5, one end of the capacitor C1, the gates of the NMOS transistors NM1, NMOS transistor NM3, and NMOS transistor NM4, the gates of the 12 series-connected NMOS transistors are connected to one end of the resistor R1 and the resistor R2, the source of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM6, the source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7, and so on. 15 The source of the NMOS tube NM 16 The drain connection of NMOS tube NM 16 The source of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected to the NMOS tube NM 17 , the drains of NMOS tube NM3 are connected together, and the drains of NMOS tube NM 17 The source of the NMOS tube NM 18 The drain connection of NMOS tube NM 18 The source of the NMOS tube NM 19 The drain connection of NMOS tube M M23 The source of NMOS tube M 24 The drain of the NMOS tube M24 is connected, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM4, the source of the NMOS tube NM4 is grounded, the gate and drain of the PMOS tube PM4 are connected to the gate of the PMOS tube PM5, and the drain of the NMOS tube NMOS1 is connected together, the source of the NMOS tube NMOS1 is connected to the drain of the NMOS tube NM1, the source of the NMOS tube NM1 is grounded, the drain of the PMOS tube PM5 is connected to the other end of the resistor R1, and the other end of the resistor R2 is grounded.

[0031] To verify the actual effect of this embodiment, 8 NMOS tubes connected in series are operated in a linear region, NMOS tube NM3 and NMOS tube NM4 are operated in a linear region, and the gate voltage of the 8 NMOS tubes connected in series does not change with the change of the load current. When the load current is small, a zero point is provided to offset the influence of the pole. When the load current increases, the gate voltage of the NMOS tube NM3 and NMOS tube NM4 increases accordingly, and the equivalent resistance of the 8 NMOS tubes connected in series is connected in parallel with the equivalent resistance of the NMOS tube NM3 and NMOS tube NM4. The position of the zero point moves toward high frequency accordingly, and the position of the zero point and the output pole is not much different. The zero point can compensate for the additional phase shift caused by the output pole.

[0032] When the load current changes from 1mA to 300mA, the position of the pole changes. At this time, the value of the equivalent zero adjustment resistance of NMOS tube NM3 and NMOS tube NM4 also changes accordingly. When the load current gradually increases, the position of the zero point also moves to the high frequency, and the position of this zero point and the output pole are not much different. This zero point can compensate for the additional phase shift caused by the output pole to ensure the stability of the loop and prevent oscillation.

[0033] Based on the above embodiment, in another embodiment of the present invention, Figure 3 As shown, a low voltage dropout linear regulator chip is provided, and the low voltage dropout linear regulator chip is provided with the loop stability enhancement circuit in the above embodiment.

[0034] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A circuit for enhancing loop stability, characterized in that: include: PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, M NMOS tubes connected in series, including NMOS tube NM5, NMOS tube NM6, ..., NMOS tube NM M+4 , N NMOS tubes connected in series, including NMOS tube NM M+5 、NMOS tube NM M+6 、……、NMOS tube M M+N+4 , NMOS consumption NMOS1, resistor R1, resistor R2, capacitor C1, current source I Q ; The sources of the PMOS tube PM1, the PMOS tube PM2, the PMOS tube PM3, the PMOS tube PM4 and the PMOS tube PM5 are connected together to VDD, and the gates of the PMOS tube PM1, the PMOS tube PM2 and the PMOS tube PM3 are connected to the drain of the PMOS tube PM1 and the current source I Q One end of the current source I Q The other end of the PMOS tube PM2 is grounded, the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM2, the gate, the gates of the N series-connected NMOS tubes, the gate of the NMOS tube NMOS1, the source of the NMOS tube NM2 is grounded, the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM5, one end of the capacitor C1, the gates of the NMOS tube NM1, the NMOS tube NM3, and the NMOS tube NM4, the gates of the M series-connected NMOS tubes are connected to the resistor R1 and one end of the resistor R2, the source of the NMOS tube NM5 is connected to the drain of the NMOS tube NM6, the source of the NMOS tube NM6 is connected to the drain of the NMOS tube NM7, and so on. M+3 The source of the NMOS tube NM M+4 The drain connection of the NMOS tube NM M+4 The source of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected to the NMOS tube NM M+5 , the drains of the NMOS tube NM3 are connected together, and the NMOS tube NM M+5 The source of the NMOS tube NM M+6 The drain connection of the NMOS tube NM M+6 The source of the NMOS tube NM M+7 The drain of the NMOS tube M M+N+3 The source of the NMOS tube M M+N+4 The drain of the NMOS tube M M+N+4 The source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM4, the source of the NMOS tube NM4 is grounded, the gate and drain of the PMOS tube PM4 are connected to the gate of the PMOS tube PM5, and the drain of the NMOS tube NMOS1 is connected together, the source of the NMOS tube NMOS1 is connected to the drain of the NMOS tube NM1, the source of the NMOS tube NM1 is grounded, the drain of the PMOS tube PM5 is connected to the other end of the resistor R1, and the other end of the resistor R2 is grounded.

2. The loop stability enhancement circuit according to claim 1, characterized in that: The M is greater than or equal to 8 and less than or equal to 20.

3. The loop stability enhancement circuit as claimed in claim 2, characterized in that: The channel length of the M series-connected NMOS tubes is greater than or equal to 10 um and less than or equal to 20 um.

4. The loop stability enhancement circuit as claimed in claim 3, characterized in that: The width and length of the channels of the M series-connected NMOS tubes are equal.

5. The loop stability enhancement circuit according to claim 1, characterized in that: The N is greater than or equal to 6 and less than or equal to 12.

6. The loop stability enhancement circuit as claimed in claim 5, characterized in that: The channel length of the N series-connected NMOS tubes is greater than or equal to 10 um and less than or equal to 20 um.

7. The loop stability enhancement circuit as claimed in claim 5, characterized in that: The width and length of the channels of the N series-connected NMOS tubes are equal.

8. The loop stability enhancement circuit as claimed in claim 1, characterized in that: The channel length of the NMOS transistor NM3 and the NMOS transistor NM4 is greater than or equal to 15 um and less than or equal to 20 um.

9. The loop stability enhancement circuit according to claim 1, characterized in that: The value of the capacitor C1 is greater than or equal to 600fF and less than or equal to 800fF.

10. A low voltage dropout linear regulator chip, characterized in that: A loop stability enhancing circuit as described in any one of claims 1 to 9 is provided.

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