Storage device and operating method thereof

Abstract

The invention provides a storage device and an operation method thereof. The memory apparatus includes: a non-volatile memory device configured to store fast cell information, the fast cell information being obtained from a threshold voltage distribution formed by a single program for a memory cell; and a memory controller configured to read the fast cell information from the non-volatile memory device during boot or initialization to perform mapping of a fast cell region based on a fast cell management policy, the fast unit information is obtained by the single program performed in a test phase or a mass production evaluation phase, and is stored in the non-volatile memory device before firmware of the memory controller is run.

Description

Technical Field

[0001] The present disclosure described herein relates to semiconductor memory devices, and more particularly to a memory device having fast cell information and a method of operating the memory device. Background Art

[0002] The memory device stores data in response to a write request and outputs the stored data in response to a read request. The memory device can be mainly divided into a volatile memory device and a non-volatile memory device. For example, a dynamic random access memory (DRAM) and a static random access memory (SRAM) are volatile memory devices in which the stored data is lost when the power is cut off. On the other hand, flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM) and resistive random access memory (RRAM) are non-volatile memory devices that retain stored data even when the power is cut off.

[0003] The memory cells of non-volatile memory devices are programmed with threshold voltages corresponding to data bit values. However, the programming speed and retention characteristics of the memory cells vary depending on the state of the insulating film forming the memory cells. As degradation proceeds, the differences in the characteristics of these memory cells become an important factor causing errors. Therefore, various coping techniques are needed to prepare for the degradation of memory cells. However, in order to cope with degradation, most of the techniques are related to subsequent measures performed after the degradation occurs. Summary of the invention

[0004] Embodiments of the present disclosure provide a nonvolatile memory device, a storage apparatus, and an operating method thereof that acquire and store fast cell information in advance before degradation occurs.

[0005] According to one aspect of the embodiment, a storage device includes: a nonvolatile memory device, the nonvolatile memory device being configured to store fast cell information, the fast cell information being obtained from a threshold voltage distribution formed by a single programming for a memory cell; and a storage controller, the storage controller being configured to read the fast cell information from the nonvolatile memory device during booting or initialization to map a fast cell area based on a fast cell management policy, wherein the fast cell information is obtained by the single programming performed in a test phase or a mass production evaluation phase, and is stored in the nonvolatile memory device before firmware of the storage controller is run.

[0006] According to one aspect of an embodiment, a method for operating a storage device includes: loading firmware for driving the storage device into a working memory of a storage controller; reading fast cell information programmed in a secure area of ​​a non-volatile memory device; loading the fast cell information into the working memory; mapping a fast cell area based on the loaded fast cell information; and applying a fast cell management policy when accessing the mapped fast cell area, wherein the fast cell information is provided in a programmed state in the secure area of ​​the non-volatile memory device before initialization of the firmware.

[0007] According to one aspect of the embodiment, a storage device includes a nonvolatile memory device and a storage controller, the nonvolatile memory device storing fast cell information, the storage controller being configured to: load and run firmware in a working memory during boot or initialization, read the fast cell information from the nonvolatile memory device, and apply a fast cell management policy based on the fast cell information, wherein the fast cell information is generated in a test phase or a mass production evaluation phase of the nonvolatile memory device to be provided in the nonvolatile memory device in a programmed state before the firmware is run. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present disclosure will become clear by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram showing a memory system including a memory device according to an embodiment;

[0010] Figure 2 is shown in more detail Figure 1 A block diagram of a configuration of a storage controller;

[0011] Figure 3 It shows Figure 1 A block diagram of a structure of a non-volatile memory device;

[0012] Figure 4 is a flow chart showing a method for obtaining fast unit information according to an embodiment;

[0013] Figure 5A and Figure 5B is a graph showing the effect of single programming on distribution and the effect of fast cells on distribution;

[0014] Figure 6 An example of a loading and use strategy of fast cell information performed when initializing or booting a storage device according to an embodiment is shown;

[0015] Figure 7 is a diagram showing a process for loading fast cell information and setting a usage policy performed during initialization or booting of a storage device according to an embodiment;

[0016] Figure 8 It shows Figure 7 FIG. 1 is a diagram showing an example of a memory management strategy based on fast cell information as mentioned in FIG. 1 ;

[0017] Fig. 9 is a flow chart illustrating a strategy for loading and using fast cell information according to an embodiment;

[0018] Fig. 10A and Fig. 10B is a diagram showing an example of an adaptive kernel technique according to an embodiment; and

[0019] Fig.11 is a block diagram illustrating a storage system including a solid state drive according to an embodiment. DETAILED DESCRIPTION

[0020] It should be understood that both the foregoing general description and the following detailed description are exemplary. Whenever possible, the same reference numerals are used in the specification and drawings to refer to the same or like parts.

[0021] Figure 1 1 is a block diagram showing a storage system including a storage device of an embodiment. The storage system 1000 may include a host 1100 and a storage device 1200. The storage device 1200 includes a storage controller 1210 and a non-volatile memory device (NVM) 1230.

[0022] The host 1100 can manage and process the overall operation of the storage system 1000. The host 1100 can send a read request or a write request to the storage device 1200. To this end, the host 1100 can generate a write command or a read command. The host 1100 can perform various arithmetic / logic operations to access the storage device 1200. For example, the host 1100 may include one or more processor cores. The host 1100 can be implemented using a dedicated circuit such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), or can be implemented as a system on a chip (SoC). The host 1100 may include a general-purpose processor, a dedicated processor, or an application processor AP. The host 1100 may be a processor itself or an electronic device or system including a processor.

[0023] The storage device 1200 may include a storage controller 1210 and a nonvolatile memory device 1230. The storage controller 1210 may program data in the nonvolatile memory device 1230 according to a write request from the host 1100. Alternatively, the storage controller 1210 may read data stored in the nonvolatile memory device 1230 according to a read request from the host 1100. To this end, the storage controller 1210 may manage a mapping table that defines a correspondence between a logical address and a physical address of data stored (or to be stored) in the nonvolatile memory device 1230.

[0024] In addition, the storage controller 1210 may include a fast cell manager 1220. The storage controller and the fast cell manager may be implemented by a processor such as a CPU that runs instructions, by client hardware, by a hardware state machine, or by a combination of hardware and software. The instructions may be stored, for example, in an NVM. When the storage device 1200 is booted or initialized, the fast cell manager 1220 uses the fast cell information 1240 stored in the secure area of ​​the non-volatile memory device 1230 to execute a memory management policy. For example, the fast cell manager 1220 can manage the programming voltage or the erase voltage to be applied to the fast cell area differently from the programming voltage or the erase voltage of the normal memory cell. Alternatively, the fast cell manager 1220 may use the fast cell area as an area for storing frequently updated hot data. The fast cell manager 1220 may be provided in software and loaded into the memory of the storage controller 1210, or may be provided in hardware as part of the storage controller 1210. The functions and features of the fast cell manager 1220 will be explained in more detail through the drawings described later.

[0025] The nonvolatile memory device 1230 stores data or outputs the stored data under the control of the storage controller 1210. In particular, the nonvolatile memory device 1230 is capable of storing fast cell information 1240 in a secure area. The fast cell information 1240 is data that is programmed into the secure area of ​​the nonvolatile memory device 1230 before the nonvolatile memory device 1230 is mounted on the storage apparatus 1200. For example, the fast cell information 1240 may be information stored in the nonvolatile memory device 1230 during a mass production evaluation or test phase of the nonvolatile memory device 1230. Therefore, the fast cell information 1240 is data that has been programmed in the nonvolatile memory device 1230 before the firmware in the storage controller 1210 is loaded and driven.

[0026] Here, fast cell information 1240 may be address information of a page or block designated as a fast cell or a fast cell area. Alternatively, fast cell information 1240 may be page data itself formed by a single programming. The form or type of fast cell information 1240 is not limited to the disclosure herein. When the firmware is running and initialization or booting of storage device 1200 is in progress, fast cell information 1240 is loaded into storage controller 1210 by fast cell manager 1220 to be used as data for reliability-based mapping.

[0027] Each of the memory controller 1210 and the nonvolatile memory device 1230 constituting the memory device 1200 may be provided as one chip, one package, or one module. Alternatively, the memory controller 1210 and the nonvolatile memory device 1230 are formed of one chip, one package, or one module to be provided as a memory system such as a memory card, a memory stick, a solid state drive (SSD), or the like.

[0028] The above-described memory system 1000 can perform a memory management operation by using the fast cell information 1240 that has been written in the nonvolatile memory device 1230 before configuring the memory device 1200. Therefore, accurate fast cell information generated by a single programming in a mass production evaluation stage can be provided, rather than fast cell information detected after a program or erase operation occurs in the nonvolatile memory device 1230.

[0029] Figure 2 is shown in more detail Figure 1 A block diagram of the storage controller configuration. Figure 2 , the storage controller 1210 includes a processing unit 1211, a working memory 1213, a host interface 1215, a buffer manager 1217, and a flash memory interface 1219. However, it should be understood that the components of the storage controller 1210 are not limited to the components shown. For example, the storage controller 1210 may also include a read-only memory ROM that stores code data or an error correction code ECC block required for a boot operation.

[0030] The processing unit 1211 may include a central processing unit or a microprocessor. The processing unit 1211 may drive firmware running on the storage controller 1210. In particular, the processing unit 1211 is capable of driving various firmware or software loaded into the working memory 1213. For example, the processing unit 1211 may run the fast cell manager 1220 loaded into the working memory 1213. In addition, the processing unit 1211 may run firmware or software responsible for core functions of the storage device 1200, such as a host interface layer HIL or a flash translation layer FTL.

[0031] Software (or firmware) or data for controlling the storage controller 1210 is loaded into the working memory 1213. The software and data loaded into the working memory 1213 are driven or processed by the processing unit 1211. In particular, according to an embodiment, a flash translation layer FTL or a fast cell manager 1220 may be loaded into the working memory 1213. Alternatively, a flash translation layer FTL including the function of the fast cell manager 1220 may be loaded into the working memory 1213. The flash translation layer FTL driven by the processing unit 1211 generally performs functions such as address mapping, useless cell collection, and wear leveling.

[0032] When the storage system 1000 is booted or initialized, the fast cell manager 1220 driven by the processing unit 1211 may be loaded into the working memory 1213. And when the fast cell manager 1220 is driven by the processing unit 1211, the fast cell manager 1220 reads the fast cell information 1240 stored in the security area of ​​the non-volatile memory device 1230 and loads it into the working memory 1213. And the fast cell manager 1220 will map the storage area of ​​the non-volatile memory device 1230 according to the reliability level based on the fast cell information 1240. For example, the fast cell manager 1220 may map the storage area classified as a fast cell to a frequently updated hot data area. On the other hand, the fast cell manager 1220 may map the storage area classified as a normal cell to a cold data area with a low update frequency.

[0033] In another embodiment, the fast cell manager 1220 can manage programming or erasing conditions differently for the fast cell area and the normal cell area. In short, the fast cell manager 1220 can manage the programming voltage level or erasing voltage level of the fast cell to be lower than the programming voltage level or erasing voltage level of the normal cell. This management method is called adaptive core technology. In other words, the fast cell manager 1220 can apply the adaptive core technology based on the fast cell information 1240 loaded into the working memory 1213.

[0034] The host interface 1215 provides an interface between the host and the storage controller 1210. The host and the storage controller 1210 may be connected through one of various standard interfaces. Here, the standard interface includes various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) and PCI Express (PCIe), Universal Serial Bus (USB), IEEE 1394, Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), and Non-Volatile Memory Express (NVMe).

[0035] The buffer manager 1217 controls a read operation and a write operation of a buffer such as a DRAM. For example, the buffer manager 1217 controls the buffer to provide a buffer function for temporarily storing data programmed into the nonvolatile memory device 1230 or data output from the nonvolatile memory device 1230.

[0036] The flash memory interface 1219 provides an interface between the memory controller 1210 and the nonvolatile memory device 1230. For example, data processed by the processing unit 1211 is stored in the nonvolatile memory device 1230 through the flash memory interface 1219. As another example, data stored in the nonvolatile memory device 1230 may be exchanged with the memory controller 1210 through the flash memory interface 1219.

[0037] The configuration of the memory controller 1210 described above illustratively has been described. According to the function of the memory controller 1210, the fast cell information 1240 stored in the nonvolatile memory device 1230 can be loaded into the working memory 1213 during booting or initialization. And, based on the fast cell information 1240 detected by the fast cell manager 1220 in the mass production evaluation stage, the storage area of ​​the nonvolatile memory device 1230 can be mapped according to the reliability level.

[0038] Figure 3 It briefly shows Figure 1 A block diagram of the structure of a nonvolatile memory device. Figure 3 , the nonvolatile memory device 1230 may include a cell array 1231, a row decoder 1232, a page buffer circuit 1233, a control logic circuit 1234, and a voltage generator 1235. The nonvolatile memory device 1230 may also include a data input / output circuit or an input / output interface. Additionally, the nonvolatile memory device 1230 may also include components such as column logic, a pre-decoder, a temperature sensor, a command decoder, and an address decoder.

[0039] The cell array 1231 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. A plurality of memory blocks may be included on one memory plane, but the embodiment is not limited thereto. The cell array 1231 may be connected to the page buffer circuit 1233 via bit lines (BLs). The cell array 1231 may be connected to the row decoder 1232 via word lines (WL), string selection lines (SSL) and ground selection lines (GSL). In an example embodiment, the cell array 1231 may include a three-dimensional memory cell array.

[0040] In particular, there is a security area in the cell array 1231 that is not allowed to be accessed by the user. And the fast cell information 1240 is stored in the security area. The fast cell information 1240 is programmed into the security area before the non-volatile memory device 1230 is installed on the storage device 1200. The fast cell information 1240 may be information stored in the security area during the mass production evaluation stage of the non-volatile memory device 1230. Therefore, before the firmware in the storage controller 1210 is loaded and driven, the fast cell information 1240 already exists in the security area of ​​the cell array 1231 in a programmed state. The fast cell information 1240 can be programmed in the storage controller 1210 (see Figure 2 ) reads and loads into the working memory 1213 (see Figure 2 )middle.

[0041] The row decoder 1232 may select one of the memory blocks of the cell array 1231 in response to the address ADDR. The row decoder 1232 may select one of the word lines of the selected memory block in response to the address ADDR. The row decoder 1232 delivers a word line voltage VWL corresponding to the operation mode to the word line of the selected memory block. During a programming operation, the row decoder 1232 delivers a program voltage and a verification voltage to the selected word line, and delivers a pass voltage to an unselected word line. During a read operation, the row decoder 1232 delivers a read voltage to the selected word line and delivers a read pass voltage to an unselected word line.

[0042] The page buffer circuit 1233 may include a plurality of page buffers PB0 to PBn-1. The plurality of page buffers PB0 to PBn-1 may be connected to the memory cells respectively through a plurality of bit lines BLs. The page buffer circuit 1233 may select at least one bit line among the bit lines BLs in response to a column address. Depending on the operation mode, the page buffer circuit 1233 may operate as a write driver or a sense amplifier. For example, during a programming operation, the page buffer circuit 1233 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer circuit 1233 may detect the data stored in the memory cell by detecting the current or voltage of the selected bit line. The page buffer circuit 1233 may be configured to detect the data stored in the memory cell in the memory controller 1210 (see Figure 2 ) to send / receive input / output (I / O) data under the control of the .

[0043] The control logic circuit 1234 is generally capable of controlling various operations within the nonvolatile memory device 1230. The control logic circuit 1234 programs data into the cell array 1231, reads data from the cell array 1231, or erases data stored in the cell array 1231 in response to a control signal CTRL, a command CMD, and / or an address ADDR. For example, the control logic circuit 1234 may output a voltage control signal VTG_C, an address ADDR, etc. In an exemplary embodiment, the control logic circuit 1234 may output a control signal for programming multi-bit data according to the received control signal CTRL, the command CMD, and / or the address ADDR.

[0044] The voltage generator 1235 can generate various types of voltages for performing programming operations, reading operations, and erasing operations based on the voltage control signal VTG_C. For example, the voltage generator 1235 can generate a programming voltage, a reading voltage, and a programming verification voltage as a word line voltage VWL. For example, the programming voltage can be generated using an incremental step pulse programming ISPP method. The voltage generator 1235 can generate a programming voltage or an erasing voltage for a fast cell differently from a programming voltage or an erasing voltage for a normal cell under the control of the storage controller 1210.

[0045] In particular, the voltage generator 1235 may provide a program voltage or an erase voltage for the fast cell at a level different from that for the normal cell. That is, during a program operation in the fast cell region mapped by the fast cell information 1240, the voltage generator 1235 may provide a level lower than the program voltage of the normal cell. Additionally, during an erase operation in the fast cell region, the voltage generator 1235 may provide an erase voltage lower than the erase voltage of the normal cell.

[0046] The above-mentioned nonvolatile memory device 1230 can provide the flash cell information 1240 prepared in advance during the mass production evaluation stage. Additionally, the nonvolatile memory device 1230 can program or erase the memory cell according to the flash cell management policy under the control of the memory controller 1210.

[0047] Figure 4 FIG. 1 is a flow chart showing a method for obtaining fast unit information according to an embodiment. Figure 4 , the fast cell information of the nonvolatile memory device 1230 is obtained in a test phase or a mass production evaluation phase through a single programming. Figure 3The circuit arrangement can be the target of single-shot programming during the test phase or mass production evaluation phase. Factory test equipment can be used to perform the test or evaluation. And the obtained fast cell information can be programmed into the secure area of ​​the non-volatile memory device 1230. The single-shot programming and the acquisition of fast cell information can be performed on a test device or board provided for mass production evaluation. Hereinafter, the entity that obtains the single-shot programming and fast cell information will be referred to as a test device.

[0048] In S110, a memory block BLKi for obtaining fast cell information is selected. The fast cell information can be obtained on a memory block unit or a word line unit. For example, the number of fast cells included in a memory block or the number of fast cells included in a word line can be used as the fast cell information. Alternatively, the average value or maximum value of the number of fast cells on a word line unit or a memory block unit can be used as the fast cell information. In another embodiment, the fast cell information can be the data itself obtained by reading the result of a single programming in units of word lines or memory blocks.

[0049] In S120, a word line WLj for obtaining single programming and fast cell information is selected within the selected memory block BLKi. Here, single programming will be performed on the memory cells connected to one word line. Alternatively, fast cell information can be obtained by performing a read operation using a reference read voltage Vref for the single-programmed memory cells. However, it should be well understood that after the single programming for the entire memory block is completed, fast cell information can be obtained by a read operation using the reference read voltage Vref on the unit of the memory block.

[0050] In S130, single programming for the nonvolatile memory device 1230 is performed. The programming voltage for single programming will be applied through the selected word line. The application of the programming voltage may consist of a single cycle in which one pulse is applied through the word line. Single programming is a detection method for obtaining relatively accurate fast cell information. Fast cell information can be obtained by detecting the distribution of memory cells of a NAND flash memory. In a NAND flash memory, distribution refers to the number of memory cells relative to a threshold voltage. Single programming refers to a method of programming a memory cell using one programming pulse. And the distribution of memory cells formed by single programming is called a single distribution.

[0051] Generally, programming for writing data to a memory cell is performed using an incremental step pulse programming (ISPP) method in which gradually increasing pulses are applied and verified during each cycle. In this case, the accuracy of identifying a fast cell is low. On the other hand, in single-shot programming, a single distribution is formed by one application of a programming pulse. Therefore, in a single-shot distribution, a fast cell / slow cell characteristic is clearly displayed.

[0052] In S140, a reference read voltage Vref is applied to a word line WLj for which single programming has been completed, and the selected memory cell is sensed to be turned on or off. If the threshold voltage of the memory cell is higher than the reference read voltage Vref, the memory cell is sensed as a turn-off cell. On the other hand, if the threshold voltage of the memory cell is lower than the reference read voltage Vref, the memory cell will be sensed as a turn-on cell. Finally, among the memory cells connected to one word line, the memory cell sensed as a turn-off cell can be determined as a fast cell. The fast cell information can be the number of fast cells or the data itself sensed on the word line unit. The fast cell information in units of read word lines can be output to the test equipment.

[0053] In S150, it is checked whether the word line WLj from which the single programming and fast cell information is obtained is the last word line of the selected memory block BLKi. If the word line WLj is not the last word line of the memory block BLKi, the process moves to S155. On the other hand, if the word line WLj is the last word line of the memory block BLKi, the process moves to S160.

[0054] In S155, the word line count is incremented (j=j+1) to select a new word line for single-time programming. Next, the process returns to S120, where the word line corresponding to the count is selected, and the output of single-time programming and fast cell information continues.

[0055] In S160, it is checked whether the memory block BLKi from which the single programming and fast cell information is obtained is the last memory block of the nonvolatile memory device 1230. If the memory block BLKi is not the last memory block, the process moves to S165. On the other hand, if the memory block BLKi is the last memory block, the process moves to S170.

[0056] In S165, the block count is incremented (i=i+1) to select a new memory block for single-time programming. Then, the process returns to S110, and the memory block with the count incremented will be selected.

[0057] In S170, fast cell information of a storage block unit may be generated. The fast cell information of a storage block unit is generated by collecting fast cell information of a word line unit. The block-based fast cell information may be calculated based on the average value or maximum value of the number of fast cells of each word line in the block. That is, the fast cell information of a storage block can be expressed as the average value of the number of fast cells in each word line, or as the maximum value of the number of fast cells in each word line. In another embodiment, the block-by-block fast cell information may be expressed as the total number of fast cells included in the block. In another embodiment, the block-by-block fast cell information may include the position information of the word line where the fast cell exists. In addition, the fast cell information may also include information about the blocks where the fast cell exists and the blocks where the fast cell does not exist among the storage blocks.

[0058] In S180, the test device programs the obtained flash cell information into a specific storage area of ​​the nonvolatile memory device 1230. For example, the flash cell information may be programmed into a secure area among the storage areas of the nonvolatile memory device 1230 that is invisible to the user.

[0059] In the above, a process for obtaining fast cell information of the nonvolatile memory device 1230 through single programming according to an embodiment has been described. In addition, the obtained fast cell information can be programmed into the security area of ​​the nonvolatile memory device 1230. When the nonvolatile memory device 1230 is driven by the memory controller 1210, the fast cell information obtained through single programming can be provided. Finally, the fast cell information is information obtained before the firmware is driven in the memory controller 1210, and can be provided as a more accurate value than the fast cell information generated when the firmware is driven.

[0060] Figure 5A and Figure 5B is a graph showing the effect of single programming on the distribution and the effect of fast cells on the distribution. Figure 5A The distribution of memory cells formed by a single programming is shown. Figure 5B is a diagram showing the influence of fast cells on the distribution of memory cells in a triple-level cell (TLC) nonvolatile memory device.

[0061] refer to Figure 5A, the threshold voltage of the memory cell increases from the erased state ES to the programmed state PS by single programming. If the programming characteristics of the memory cells are the same, even after the single programming, the distribution of the programmed state PS will be formed in the same shape as the erased state ES. However, depending on the state of the insulating film, the memory cells have different programming characteristics. In particular, for fast cells, the increase in threshold voltage is relatively large even when the same programming voltage is applied. On the other hand, slow cells have a relatively small increase in threshold voltage even when the same programming voltage is applied. Therefore, the programmed state PS of the memory cell formed after the single programming will appear in a widely distributed form. In addition, the retention characteristics and programming characteristics are different between the slow cell and the fast cell. Since the charge leakage from the fast cell is relatively large, the reduction of the threshold voltage after programming is more noticeable in the fast cell.

[0062] The fast cell information is obtained by a read operation using a reference read voltage Vref after a single programming. After the reference read voltage Vref is applied to the word line of the memory cell, it is sensed whether the memory cell is an off cell or an on cell. A memory cell sensed as an off cell relative to the reference read voltage Vref is determined to be a fast cell. By reading memory cells connected to one word line (e.g., one page) to count the number of bits "0" corresponding to the off cell, the number of fast cells can be counted. When the number of fast cells obtained in word line units is collected, it can also be expressed as the number of fast cells in memory block units.

[0063] According to single-shot programming, a programming voltage is applied to a memory cell once. On the other hand, according to typical ISPP programming, a programming voltage is applied multiple times, and cells higher than a verification voltage Vfy are prohibited by repeated verification. Therefore, even for memory cells connected to the same word line, the number of times the programming voltage is actually applied varies. Ultimately, it is impossible to obtain accurate fast cell information. Therefore, fast cells can be accurately identified among memory cells manufactured by single-shot programming.

[0064] refer to Figure 5B , briefly showing the influence of fast cells on the distribution change of memory cells. The first distribution D1 shows the initial distribution immediately after programming the memory cells. The second distribution D2 shows the maintained distribution after a certain period of time has passed since programming. According to the second distribution D2, among the memory cells initially included in the programming state P7, there are memory cells whose read voltage is lower than the read voltage R7. Ultimately, the threshold voltage change that causes this error is caused by the fast cells. In order to manage these fast cells, various wear leveling techniques must be used and the frequency of useless cell collection also increases. Therefore, the performance of the memory device 1200 is reduced due to the fast cells.

[0065] Embodiments can perform accurate identification of fast cells.Accurate identification of fast cells is based on single programming and reading before the firmware of the memory device 1200 is driven or during a test phase.

[0066] Figure 6 An example of loading of fast unit information and a fast unit management strategy performed when initializing or booting a storage device according to an embodiment is shown. Figure 6 , the nonvolatile memory device 1230 included in the memory apparatus 1200 is provided in a programmed state with the flash cell information 1240 acquired through a single programming in a test stage or a mass production evaluation stage.

[0067] In S210, booting or initialization of the memory device 1200 begins. When power is supplied to the memory device 1200 or an initialization command is provided, initialization settings of the memory controller 1210 and the nonvolatile memory device 1230 will begin.

[0068] In S220, a device initialization process is performed. For example, for initialization, firmware or software for driving the storage device 1200 is loaded from the storage controller 1210 into the working memory 1213. The firmware or software can be loaded into the working memory 1213 from a separate ROM or storage device. In addition, a fast unit manager 1220 for managing fast units will also be loaded into the working memory 1213 at this time.

[0069] In S230, as the fast cell manager 1220 is driven, the fast cell information 1240 stored in the security area of ​​the nonvolatile memory device 1230 may be output. The output of the fast cell information 1240 stored in the security area may be set as an initialization sequence of the fast cell manager 1220. The fast cell manager 1220 can read the fast cell information 1240 by accessing a predetermined security area during initialization. The fast cell information 1240 may include information on the number or location of fast cells in each memory block.

[0070] In S240, the fast cell manager 1220 loads the fast cell information 1240 output from the nonvolatile memory device 1230 into the memory of the memory controller 1210. That is, the fast cell information 1240 delivered to the memory controller 1210 may be loaded into the working memory 1213 or the buffer memory.

[0071] In S250, the fast cell manager 1220 may perform storage area mapping according to a management policy for managing fast cell areas based on the loaded fast cell information 1240. For example, the fast cell manager 1220 may allocate a storage area containing a fast cell as an area for storing hot data to designate the storage area as a write area for hot data, wherein the number of updates per hour of the hot data exceeds a reference value. Hot data refers to data that is frequently updated. And cold data refers to data that is maintained for a long time without being updated once programmed. When hot data is stored in a storage block, the data is reprogrammed in a short period of time. Therefore, when hot data is stored in a fast cell area, the influence of reliability degradation of the storage block due to charge leakage can be reduced. Therefore, the fast cell manager 1220 can map hot-cold data areas according to the fast cell information 1240. In this case, frequent useless cell collection due to reduced reliability can also be suppressed.

[0072] In the above, the loading and use strategy of the fast cell information 1240 executed when the storage device is initialized or booted according to the embodiment has been briefly described. The fast cell information 1240 is provided by a single programming performed in the test phase before the firmware is driven. Therefore, accurate fast cell information can be provided to the storage device 1200. In addition, it should be well understood that the mapping to the fast cell area can be applicable not only to the allocation of hot-cold data, but also to various wear leveling strategies.

[0073] Figure 7 is a diagram illustrating a process for loading fast unit information and setting a management policy performed during initialization or booting of a storage device according to an embodiment. Figure 7 , the memory controller 1210 may read the fast cell information 1240 obtained through the one-time programming from the nonvolatile memory device 1230 during booting or initialization and load it into the memory.

[0074] In S310, when power is supplied to the memory device 1200 or an initialization request occurs, a power-on reset is performed. According to the power-on reset, power is supplied to the memory controller 1210 and the nonvolatile memory device 1230 constituting the memory device 1200, and a reset is performed.

[0075] In S320, the storage device 1200 may perform hardware initialization and booting. For example, the hardware layers of the storage controller 1210 and the non-volatile memory device 1230 may be initialized or booted. A communication channel between the storage controller 1210 and the non-volatile memory device 1230 may be formed according to the initialization of the hardware layer. And a read operation or a write operation of the storage controller 1210 to the non-volatile memory device 1230 will be possible.

[0076] In S330, firmware initialization of the storage device 1200 is performed. For example, firmware or software for memory management (such as a host interface layer HIL or a flash translation layer FTL) will be loaded into the working memory 1213 of the storage controller 1210. In addition, the working memory 1213 may be loaded with a fast cell manager 1220 that uses fast cell information to run a memory management policy.

[0077] In S340, a secure area read request for obtaining fast cell information 1240 is sent by fast cell manager 1220 to nonvolatile memory device 1230. Before the first firmware loading occurs in storage apparatus 1200, fast cell information 1240 has been stored in nonvolatile memory device 1230. Therefore, fast cell information 1240 may be information about accurate fast cells obtained before nonvolatile memory device 1230 is programmed, erased, or read by storage controller 1210.

[0078] In S345 , the flash cell information 1240 read from the secure area of ​​the nonvolatile memory device 1230 is transmitted to the memory controller 1210 .

[0079] In S350, the fast cell manager 1220 running on the storage controller 1210 loads the fast cell information 1240 output from the non-volatile memory device 1230 into the working memory 1213. And the fast cell manager 1220 maps the storage area of ​​the non-volatile memory device 1230 according to the fast cell management policy based on the fast cell information 1240. For example, the fast cell manager 1220 can map the storage area classified as a fast cell to a hot data area that is frequently updated. On the other hand, the fast cell manager 1220 can map the storage area classified as a normal cell to a cold data area with a low update frequency. The fast cell management policy is not limited to the hot data / cold data area.

[0080] In S360, the fast cell manager 1220 performs a memory management function based on the mapped information. For example, when a write request occurs, the fast cell manager 1220 can allocate frequently updated metadata to the hot data area. On the other hand, in the case of a write request for infrequently updated data, the fast cell manager 1220 can allocate it to the cold data area.

[0081] In the above, a process for obtaining and loading pre-stored fast cell information during booting or initialization of the storage device 1200 has been described. According to the fast cell information loading method, memory management can be performed based on the fast cell information acquired in the test phase or the mass production evaluation phase. Therefore, compared with the fast cell information generated after loading the firmware, more accurate fast cell information can be provided, thereby improving memory management efficiency.

[0082] Figure 8 It shows Figure 7 Figure 1 shows an example of a memory management strategy based on fast cell information as mentioned in . Figure 8 , the fast cell manager 1220 can allocate the hot data area 1231c and the cold data area 1231d using the fast cell information obtained in the initialization step.

[0083] The fast cell manager 1220 performs hot-cold data mapping based on the fast cell information 1240 loaded into the working memory 1213. The fast cell manager 1220 maps the detected fast cell area 1231a to the hot data area 1231c. And the normal cell area 1231b can be mapped to the cold data area 1231d. The mapping can be managed in the form of an address table. And after the initialization is completed, if the LBA of the data requested to be written corresponds to the hot data area 1231c, the fast cell manager 1220 will program the requested data to the hot data area 1231c.

[0084] If the fast cell area is mapped to the hot data area 1231c, the data stored in the fast cell area may be frequently programmed and erased. Therefore, the data stored in the hot data area 1231c has a short programming or erasing interval, so there is no need to consider the reliability degradation caused by retention degradation. In addition, the number of frequent useless cell collections triggered by the degradation of storage cell reliability can be reduced.

[0085] Fig. 9 FIG. 1 is a flow chart showing a strategy for loading and using fast unit information according to another embodiment. Fig. 9 , the nonvolatile memory device 1230 included in the memory apparatus 1200 is provided in a programmed state with the flash cell information 1240 acquired through a single programming in a test stage or a mass production evaluation stage.

[0086] In S410, booting or initialization of the memory device 1200 begins. When power is supplied to the memory device 1200 or an initialization command is provided, initialization settings of the memory controller 1210 and the nonvolatile memory device 1230 will begin.

[0087] In S420, a device initialization process of the storage device 1200 is performed. For example, for initialization, firmware or software for driving the storage device 1200 is loaded from the storage controller 1210 into the working memory 1213. The firmware or software can be loaded from a separate ROM or storage device into the working memory 1213. In addition, a fast unit manager 1220 for executing a management policy for a fast unit will also be loaded into the working memory 1213.

[0088] In S430, fast cell information 1240 stored in the security area of ​​the nonvolatile memory device 1230 may be obtained by loading and running the fast cell manager 1220. The fast cell manager 1220 is capable of reading the fast cell information 1240 by accessing a predetermined security area during initialization. The fast cell information 1240 may include information about the number of fast cells in each memory block. Alternatively, the fast cell information 1240 may be the number of fast cells of a word line having the largest number of fast cells among the word lines. Then, the fast cell manager 1220 loads the fast cell information 1240 output from the nonvolatile memory device 1230 into the memory of the memory controller 1210. That is, the fast cell information 1240 delivered to the memory controller 1210 may be loaded into the working memory 1213 or the buffer memory.

[0089] In S440, the fast cell manager 1220 sets an adaptive core condition of the fast cell based on the loaded fast cell information 1240. Adaptive core refers to a technique for changing programming or erasing conditions according to the programming speed of the cell. Therefore, the fast cell manager 1220 can be configured to apply a relatively low programming voltage when programming the memory cell mapped to the fast cell area. For example, if the address provided in the write request corresponds to the fast cell area, the fast cell manager 1220 can indicate the non-volatile memory device 1230 to a programming condition different from the programming condition of the normal cell. This adaptive core technology can be applied not only to write operations in the same manner, but also to erase operations.

[0090] In S450, the flash cell manager 1220 detects a program or erase request. When a program or erase command is provided, the flash cell manager 1220 will identify whether the provided address corresponds to a flash cell area.

[0091] In S460, the fast cell manager 1220 applies conditions different from those of the normal cells to the fast cells selected during the program or erase operation. In short, the nonvolatile memory device 1230 will be controlled to apply a program voltage or an erase voltage to the selected memory cell according to the adaptive core setting set in S440.

[0092] In the above, the method of loading fast cell information 1240 and applying adaptive core technology according to the embodiment performed during the initialization or booting of the storage device has been briefly described. The fast cell information 1240 is provided by a single programming performed in the test phase before the firmware is driven. Therefore, accurate fast cell information can be provided to the storage device 1200. In addition, it should be well understood that the mapping strategy for the fast cell area can be applied not only to the adaptive core technology, but also to various memory management strategies.

[0093] Fig. 10A and Fig. 10B is a diagram showing an example of an adaptive kernel technique according to an embodiment. Fig. 10A , showing an example in which different programming voltages are applied to fast cells and normal cells.

[0094] When the fast cell area is selected for programming, the nonvolatile memory device 1230 will start a programming loop with a relatively low first programming start voltage Vpgm_f. And as the programming loop increases, the level of the programming pulse also increases. The verification voltage Vfy for program verification can be applied equally to fast cells and normal cells.

[0095] On the other hand, when the normal cell area is selected for programming, the nonvolatile memory device 1230 will start a programming loop with a second programming start voltage Vpgm_n. The second programming start voltage Vpgm_n is a programming start voltage higher than the first programming start voltage Vpgm_f provided to the fast cell by a first voltage difference ΔV1. As with the fast cell, as the programming loop increases, the level of the programming pulse applied to the normal cell also increases.

[0096] Here, the first voltage difference ΔV1 of the program voltage between the fast cell and the normal cell may be a value for converging the program speeds of the fast cell and the normal cell during the program operation. The first voltage difference ΔV1 may be an experimental value or a value determined through simulation.

[0097] refer to Fig. 10B , shows an example in which different erase voltages are applied to fast cells and normal cells. When a fast cell area (e.g., a fast cell block) is selected for erasure, the nonvolatile memory device 1230 will start an erase cycle with a relatively low first erase start voltage Vers_f. And as the number of erase cycles increases, the level of the erase pulse also increases. The verification voltage Vefy for erase verification can be applied equally to fast cells and normal cells.

[0098] On the other hand, when the normal cell area (or normal cell block) is selected for erasure, the nonvolatile memory device 1230 will start an erase cycle with a second erase start voltage Vers_n. The second erase start voltage Vers_n is an erase start voltage higher than the first erase start voltage Vers_f provided to the fast cell by a second voltage difference ΔV2. As with the fast cell, as the erase cycle increases, the level of the erase pulse applied to the normal cell also increases.

[0099] Here, the second voltage difference ΔV2 of the erase voltage between the fast cell and the normal cell may be a value to match the erase speeds of the fast cell and the normal cell during the erase operation. The second voltage difference ΔV2 may be an experimental value or a value determined by simulation.

[0100] According to the adaptive core technology applied to the program operation, the fast program / erase speed of the fast cell can be compensated and the threshold voltage distribution of the memory cell can be improved.

[0101] Fig.11 is a block diagram showing a storage system including a solid state drive according to an embodiment. Fig.11 , the storage system 2000 includes a host 2100 and a storage device 2200 implemented as a solid state drive. In an example embodiment, the host 2100 and the storage device 2200 may be a reference Figures 1 to 10B Alternatively, the host 2100 and the storage device 2200 may be based on the reference Figures 1 to 10B The described run method works.

[0102] The storage device 2200 exchanges a signal SIG with the host 2100 through a signal connector 2201 and receives power PWR through a power connector 2202. The storage device 2200 includes an SSD controller 2210, a plurality of nonvolatile memory devices (NVMs) 2230, a buffer memory 2250, and an auxiliary power supply 2270.

[0103] The SSD controller 2210 may control a plurality of nonvolatile memory devices 2230 in response to a signal SIG received from the host 2100. The plurality of nonvolatile memory devices 2230 may operate under the control of the SSD controller 2210. The auxiliary power supply 2270 is connected to the host 2100 through the power connector 2202. The auxiliary power supply 2270 may receive power PWR from the host 2100 and charge it. When the power supply from the host 2100 is not stable, the auxiliary power supply 2270 may provide power to the storage device 2200. The buffer memory 2250 may be used as a buffer memory of the storage device 2200.

[0104] In an example embodiment, the storage device 2200 may include a fast cell manager 2220. When the storage device 2200 is booted or initialized, the fast cell manager 2220 uses the fast cell information 2240 stored in the secure area of ​​the nonvolatile memory device 2230 to perform a memory management operation. For example, the fast cell manager 2220 can manage the program voltage or erase voltage to be applied to the fast cell area differently from the program voltage or erase voltage of the normal memory cell. Alternatively, the fast cell manager 2220 can use the fast cell area as an area for storing frequently updated hot data. The fast cell manager 2220 may be provided in the form of software and loaded into the memory of the SSD controller 2210, or may be provided in hardware as part of the SSD controller 2210.

[0105] In addition, the nonvolatile memory device 2230 stores data or outputs the stored data under the control of the SSD controller 2210. In particular, the nonvolatile memory device 2230 is capable of storing fast cell information 2240 in the secure area. The fast cell information 2240 is data programmed into the secure area before the nonvolatile memory device 2230 is mounted on the storage device 2200. For example, the fast cell information 2240 may be information stored in the nonvolatile memory device 2230 during a mass production evaluation stage of the nonvolatile memory device 2230. Therefore, the fast cell information 2240 is data that has been programmed in the nonvolatile memory device 2230 before the firmware in the SSD controller 2210 is loaded and driven.

[0106] The above-described memory system 2000 can perform a memory management operation by utilizing the fast cell information 2240 that has been written in the nonvolatile memory device 2230 before configuring the memory device 2200. Therefore, accurate fast cell information generated by a single programming in a mass production stage can be used instead of fast cell information detected after a program or erase operation occurs in the nonvolatile memory device 2230.

[0107] In addition to the above-described embodiments, design changes may be made without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined by the claims and the equivalents of the claims.

Claims

1. A storage device, comprising: a nonvolatile memory device configured to store fast cell information obtained from a threshold voltage distribution formed by a single programming for a memory cell; as well as a memory controller configured to read the fast cell information from the nonvolatile memory device during boot or initialization to map a fast cell area based on a fast cell management policy, and The fast cell information is acquired through the one-time programming performed in a test phase or a mass production evaluation phase, and is stored in the nonvolatile memory device before the firmware of the storage controller is executed.

2. The storage device according to claim 1, wherein: The single-shot programming corresponds to a single programming loop in which one programming voltage pulse is applied to the memory cell.

3. The storage device according to claim 1, wherein: The flash cell information is stored in a secure area of ​​the nonvolatile memory device.

4. The storage device according to claim 1, wherein: The fast cell information corresponds to the number of memory cells or read data formed as a result of the single programming for memory cells having a threshold voltage higher than a reference read voltage.

5. The storage device according to claim 1, wherein: The storage controller includes a fast cell manager configured to: load the fast cell information into a working memory at the booting or the initialization, and execute the fast cell management policy based on the fast cell information.

6. The storage device according to claim 5, wherein: The fast cell manager is further configured to map the fast cell area in a cell area of ​​the nonvolatile memory device based on the fast cell management policy.

7. The storage device according to claim 6, wherein: The fast cell manager is further configured to allocate the fast cell area as a hot data area based on the fast cell management policy to designate the fast cell area as a write area for hot data, wherein the number of updates per hour of the hot data exceeds a reference value.

8. The storage device according to claim 6, wherein: The fast cell manager is further configured to execute an adaptive core policy that controls the nonvolatile memory device to provide a program voltage or an erase voltage different from a program voltage or an erase voltage of a normal cell region based on receiving a write request or an erase request to the fast cell region.

9. A method for operating a storage device, the method comprising: Loading firmware for driving the storage device into a working memory of a storage controller; reading flash cell information programmed in a secure area of ​​a nonvolatile memory device; loading the fast unit information into the working memory; Mapping the fast cell area based on the loaded fast cell information; as well as Apply the fast cell management policy when accessing the mapped fast cell area. The fast cell information is provided in the security area of ​​the nonvolatile memory device in a programmed state before initialization of the firmware.

10. The method according to claim 9, further comprising: generating the flash cell information corresponding to the first memory cell of the nonvolatile memory device by single programming; as well as The flash cell information is programmed into the secure area.

11. The method according to claim 10, wherein: A threshold voltage of the first memory cell is higher than a reference read voltage.

12. The method according to claim 11, wherein: The fast cell information corresponds to a value calculated by counting the number of fast cells on a word line unit or a memory block unit, or the fast cell information corresponds to a data value read on the word line unit or the memory block unit.

13. The method according to claim 9, wherein: The mapping includes allocating the fast cell area to a hot data area, and allocating the normal cell area to a cold data area.

14. The method according to claim 9, wherein: The mapping includes allocating a management area to the fast cell area, a first program voltage or a first erase voltage of the management area being different from a second program voltage or a second erase voltage of the normal cell area.

15. The method according to claim 14, further comprising: Based on a request for access to the fast cell region, the first program voltage or the first erase voltage is applied to a word line of the fast cell region, wherein the first program voltage and the first erase voltage are respectively lower than the second program voltage and the second erase voltage for the normal cell region.

16. A storage device, comprising a non-volatile memory device and a storage controller, wherein the non-volatile memory device stores fast cell information, and the storage controller is configured to: Loading and running firmware in working memory during boot or initialization, reading the flash cell information from the nonvolatile memory device, and applying a fast unit management policy based on the fast unit information, in, The flash cell information is generated in a test phase or a mass production evaluation phase of the nonvolatile memory device to be provided in the nonvolatile memory device in a programmed state before the firmware is executed.

17. The storage device according to claim 16, wherein: The fast cell information is obtained by a single programming performed in the test stage or the mass production evaluation stage.

18. The storage device according to claim 17, wherein: The single programming corresponds to a single programming loop in which a single programming voltage pulse is applied to memory cells of the nonvolatile memory device.

19. The storage device according to claim 16, wherein: A fast cell area including fast cells is allocated as a hot data area according to the fast cell management policy, and The hot data area corresponds to a writing area for hot data whose update times per hour exceed a reference value.

20. The storage device according to claim 16, wherein: The fast cell management policy includes an adaptive core policy that controls the nonvolatile memory device to provide a program voltage or an erase voltage different from a program voltage or an erase voltage of a normal cell region based on receiving a write request or an erase request for a fast cell region.

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