Data storage method and device in direct mode and electronic equipment

Abstract

The embodiment of the invention provides a data storage method and device in a direct connection mode, electronic equipment and a computer readable storage medium, and relates to the technical field of video transmission. Comprising the following steps: receiving a pixel value and first address information of a first pixel; determining a first physical storage address of the first pixel in a memory, a first target strip to which the first pixel belongs and a target matrix corresponding to the first target strip; determining a first target address block to which the first physical storage address belongs, a first position of an identifier of the first target address block in the initial address block matrix, and a second position of the first physical storage address in the first target address block; and determining a second target address block corresponding to the first position in the target matrix corresponding to the first target strip, and storing the pixel value of the first pixel in a physical storage address corresponding to the second position in the second target address block. According to the embodiment of the invention, the data transmission efficiency in the direct mode is improved, and the consumption of physical resources is reduced.

Description

Technical Field

[0001] The present application relates to the field of video transmission technology, and in particular to a data storage method, device, electronic device and computer-readable storage medium in a pass-through mode. Background Art

[0002] In traditional video interaction, video data occupies a large amount of backbone bus bandwidth and double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR) resources, so direct transmission of video data between the generation and consumption ends without passing through the backbone bus has become a requirement for more and more chips.

[0003] Since the order in which the generator writes data to the memory is different from the order in which the consumer reads data from the memory, in the existing video pass-through mode, there are problems of low video data transmission efficiency and large physical resource occupation. Summary of the invention

[0004] The purpose of the embodiments of the present application is to solve the problems of low efficiency in transmitting video data and large physical resource occupation in the prior art of video transmission in video pass-through mode.

[0005] According to a first aspect of an embodiment of the present application, a data storage method in a pass-through mode is provided, the method comprising: Receive pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a width and a height of a video frame in the target video are w pixels and h pixels respectively; and each video frame is divided into a plurality of continuous strips of a size of w pixels in width and m pixels in height; Determine, according to the first address information, a first physical storage address of the first pixel in the memory; wherein the memory includes t*k*m physical storage addresses, the physical storage addresses of the memory are divided into m*t continuous address blocks, and t is w / k rounded up; wherein k*m is the number of pixels read by the second device in one data reading operation in the memory, one data reading operation includes m column-by-column reading operations performed on pixels in m rows, and the number of pixels read by one column-by-column reading operation is k pixels in one row; determining a first target stripe to which the first pixel belongs; Obtain a target matrix corresponding to the first target strip; wherein the target matrix corresponding to the first strip of the target video is an initial address block matrix, and the target matrix corresponding to the non-first strip is a second matrix obtained by matrix transformation of the first matrix. The first matrix is ​​the target matrix corresponding to the previous strip, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are the identifiers of the m*t address blocks. The second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in the order of the number of rows where the elements are located, and then sequentially dividing the sorted elements; Determine a first target address block to which the first physical storage address belongs in the memory; Determine a first position of the identifier of the first target address block in the initial address block matrix and a second position of the first physical storage address within the first target address block; A second target address block corresponding to the first position in the target matrix corresponding to the first target stripe is determined, and a pixel value of the first pixel is stored in a physical storage address corresponding to the second position in the second target address block.

[0006] According to a second aspect of an embodiment of the present application, a data storage device in a pass-through mode is provided, the device comprising: A receiving module, configured to receive pixel information of a first pixel of a target video sent by a first device, wherein the pixel information includes a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a width and a height of a video frame in the target video are w pixels and h pixels respectively; and each video frame is divided into a plurality of continuous strips of a size of w pixels in width and m pixels in height; an address translation module, configured to determine, according to the first address information, a first physical storage address of the first pixel in the memory; wherein the memory includes t*k*m physical storage addresses, the physical storage addresses of the memory are divided into m*t continuous address blocks, and t is w / k rounded up; wherein k*m is the number of pixels read by the second device in a data reading operation in the memory, and a data reading operation includes m column-by-column reading operations performed on pixels in m rows, and the number of pixels read by a column-by-column reading operation is k pixels in a row; A target matrix acquisition module determines a first target stripe to which the first pixel belongs; acquires a target matrix corresponding to the first target stripe; wherein the target matrix corresponding to the first stripe of the target video is an initial address block matrix, and the target matrix corresponding to a non-first stripe is a second matrix obtained by matrix transformation of the first matrix; the first matrix is ​​a target matrix corresponding to the previous stripe, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are identifiers of the m*t address blocks; the second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in the order of the number of rows where the elements are located, and then sequentially dividing the sorted elements; A storage module is used to determine the first target address block to which the first physical storage address belongs in the memory; determine the first position of the identifier of the first target address block in the initial address block matrix, and the second position of the first physical storage address inside the first target address block; determine the second target address block corresponding to the first position in the target matrix corresponding to the first target stripe, and store the pixel value of the first pixel in the physical storage address corresponding to the second position in the second target address block.

[0007] According to a third aspect of an embodiment of the present application, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory, and when the processor executes the program, the steps of the method provided in the first aspect are implemented.

[0008] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method provided in the first aspect are implemented.

[0009] According to the fifth aspect of the embodiment of the present application, a computer program product is provided, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. When a processor of a computer device reads the computer instructions from the computer-readable storage medium, the processor executes the computer instructions, so that the computer device executes the steps of implementing the method provided in the first aspect.

[0010] The beneficial effects of the technical solution provided by the embodiment of the present application are: By receiving the pixel information sent by the first device, the pixel value of the pixel to be stored and the first address information of the pixel to be stored are obtained, and the first address information can represent the logical storage address designated by the pixel; by the first address information, the first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, the target matrix corresponding to the target stripe can be determined. According to the first target address block described by the first physical storage address in the memory and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and according to the second position of the first physical storage address in the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing the pixels to the memory, thereby improving the efficiency of video data transmission and reducing the space occupied by physical resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in describing the embodiments of the present application are briefly introduced below.

[0012] Figure 1 A schematic diagram of a data storage system architecture in a pass-through mode provided in an embodiment of the present application; Figure 2 A schematic diagram of a flow chart of a data storage method in a direct mode provided in an embodiment of the present application; Figure 3 A schematic diagram of a stripe size and a memory size provided in an embodiment of the present application; Figure 4 A schematic diagram of a write rule for a first device and a read rule for a second device provided in an embodiment of the present application; Figure 5 A schematic diagram of a matrix conversion process provided in an embodiment of the present application; Figure 6 A schematic diagram of a pixel storage process provided by an embodiment of the present application; Figure 7 A schematic diagram of a logical storage address in a video frame provided in an embodiment of the present application; Figure 8 A schematic diagram of a logical storage address in a video frame provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a data storage device in a pass-through mode provided in an embodiment of the present application; Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0014] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation as other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0015] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0016] First, several terms involved in this application are introduced and explained: Double Data Rate SDRAM (DDR), the characteristics of DDR are a large number of lines, fast speed, and complex operation. In video interaction, video data will occupy a large amount of backbone bus bandwidth and DDR resources.

[0017] Image Signal Processor (ISP) is a dedicated digital signal processor that processes the raw image data captured from the digital camera sensor and converts it into high-quality images. When the ISP writes video data to the memory, it writes the data row by row according to the order of the physical addresses in the memory.

[0018] The Video Processing Unit (VPU) is a new core engine of the video processing platform, which has the function of hard decoding and the ability to reduce the CPU load. In addition, the VPU can reduce the server load and network bandwidth consumption. When the VPU reads pixels from the memory, it reads all the pixels in a pixel block in the memory by column according to the order of the addresses in the memory.

[0019] Static Random-Access Memory (SRAM), SRAM is used to store video data in the embodiment of the present application.

[0020] Video Direct Transfer Scheme (VDTS). In the embodiments of the present application, VDTS is used to represent the video direct transfer scheme in the present application.

[0021] The data storage method, device, electronic device, computer-readable storage medium and computer program product in the direct mode provided by the present application are intended to solve the technical problem of low data transmission efficiency caused by the order in which a writing device writes data to a memory and the order in which a reading device reads data from the memory in the prior art.

[0022] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0023] Figure 1 A schematic diagram of the data storage system architecture for implementing a pass-through mode is provided for an embodiment of the present application, wherein a direct frame bridge (DFB) is a circuit function module in the system, which is a hardware module. The circuit function module can be a hardware IP core. The circuit function module includes a memory. In the embodiment of the present application, the memory is SRAM, and the video data pass-through between the ISP and the VPU is achieved through the circuit function module.

[0024] In an embodiment of the present application, the video data includes multiple frame data, each frame data includes multiple strip data, the storage capacity of the SRAM is the data amount of one strip data, the first device can be an ISP, the ISP sends the pixel information of the pixels in each strip to the DFB, the processor in the DFB is used to perform logical processing on the address information in the pixel information, determine the physical storage address where the pixel is stored in the memory, and store the pixel in the physical address corresponding to the memory, the second device can be a VPU, when the VPU reads the pixel from the memory, it also sends the address information of the read pixel to the DFB, the processor performs logical processing on the address information, determines the corresponding physical storage address in the DFB, and sends the pixel stored in the physical address to the second device.

[0025] The data storage system in the pass-through mode in the embodiment of the present application solves the problem that in the traditional video transmission system that stores data through DDR, video data occupies a large amount of backbone bus bandwidth and DDR resources, resulting in system performance bottlenecks, affecting data processing speed and response time, and other system components that use backbone bus and DDR resources may not be able to obtain sufficient resources because the resources are occupied by video data, resulting in performance degradation. On the other hand, the embodiment of the present application performs logical processing on the received address information through the processor, thereby solving the problem of low data transmission efficiency caused by the different order in which the first device writes pixels to the memory and the second device reads pixels from the memory.

[0026] The present application provides a method for storing data in a direct mode, such as Figure 2 As shown, the method includes steps S201-S207.

[0027] S201. Receive pixel information of a first pixel of a target video sent by a first device, where the pixel information includes a pixel value and first address information indicating a logical storage address of the first pixel in a memory.

[0028] In the embodiment of the present application, the first device may be an image signal processor ISP, and the ISP corresponds to a device for acquiring video, such as a camera; the target video may be a video acquired by the device for acquiring video corresponding to the ISP, or may be a video after the ISP performs image processing on the video acquired by the device for acquiring video. The data format of the target video may be a YUV format, and the target video is composed of multiple continuous video frames. The process of the memory storing the pixel value of a pixel sent by the ISP may also be referred to as the ISP writing pixels to the memory.

[0029] When the ISP writes pixels to the memory, it scans the pixels in each video frame row by row according to the arrangement order of the video frames, obtains the pixel values, and specifies a logical storage address in the memory for each pixel. In the embodiment of the present application, the first pixel is any pixel in the target video, and the pixel information of the first pixel sent by the ISP to the DFB includes the pixel value and the first address information of the first pixel, wherein the first address information is used to indicate the logical storage address corresponding to the first pixel.

[0030] In the embodiment of the present application, the ISP can specify a logical storage address for each pixel in each video frame according to the starting address of the physical storage address of the data stored in the memory. That is, in the embodiment of the present application, the logical storage address corresponding to the pixel in the first row and the first column in each video frame corresponds to the first physical storage address in the memory.

[0031] S202: Determine a first physical storage address of a first pixel in a memory according to the first address information.

[0032] In the embodiment of the present application, after the processor in the DFB receives the first address information of the first pixel, it can determine the first physical storage address of the first pixel in the memory according to the corresponding relationship between the preset logical storage address and the physical storage address.

[0033] In an embodiment of the present application, a memory is designed according to a rule for storing pixels of a first device and a rule for reading pixels of a memory, and the memory includes w*m physical storage addresses, w is the number of pixels corresponding to the width of a video frame corresponding to the first device, and m is the number of pixel blocks read corresponding to a first data reading operation performed by the second device, and each pixel block includes at least k pixels, where k is a pixel reading parameter preset by the second device, and k is generally 32. It should be understood that if w is not an integer multiple of k, the number of pixels in the last pixel block of each row read by the second device is less than k. For the sake of convenience, a pixel block including k pixels is called a standard pixel block. When w is a multiple of k, each pixel block is a standard pixel block.

[0034] In the embodiment of the present application, a video frame is divided into at least one strip of data, the height of the video frame is h pixels, and the video frame is divided into multiple continuous strips with a width of w pixels and a height of m pixels. Figure 3 As shown, Figure 3 A schematic diagram of a stripe size and a memory size provided in an embodiment of the present application, in Figure 3In the example, w is an integer multiple of k, and h is less than or equal to 2*m, so the video frame is divided into two strips, the height of the first strip is m pixels, and the height of the second strip is hm pixels. It should be understood that if h is less than or equal to n*m, and n is any positive integer, the video frame includes n strips, and the height of the first n-1 strips is m pixels and the width is w pixels. The height of the nth strip is h-(n-1)m pixels and the width is w pixels. For the convenience of expression, the strip with a width of w pixels and a high position of m pixels is called a standard strip. It can be seen from the strip division and pixel block division in the present application that the present application has no restrictions on the width and height of the target video, and can transmit target videos corresponding to any resolution.

[0035] from Figure 3 It can also be seen that when w is a multiple of k, the memory includes w*m physical storage addresses. Therefore, a memory in the embodiment of the present application corresponds to the number of pixels corresponding to a standard strip. Therefore, the memory in the embodiment of the present application can store the pixels in the standard strip. If the number of pixels in the last strip in the video frame is less than or equal to the standard strip, the memory can also store all the pixels in the last strip.

[0036] It should be understood that when w is not a multiple of k, the number of physical storage addresses of the memory is greater than the number of pixels in the strip, so the memory can also store the pixel values ​​of all pixels in the strip.

[0037] like Figure 4 As shown, Figure 4 A schematic diagram of a write rule for a first device and a read rule for a second device provided in an embodiment of the present application. Figure 4 In the figure, w takes the value of 4, m takes the value of 2, h takes the value of 4, and the number of pixels in the pixel block read by the second device is 1. The video frame includes two stripes, AP is the pixel value, the memory includes 8 physical storage addresses, and 0-7 is the physical storage address in the memory. For the first stripe, the ISP write rule is as shown in the figure, scanning the pixel value of each pixel by row, and the physical storage address corresponding to pixel A is 0, and the physical storage address corresponding to pixel B is 1, and in this order, until the physical storage address corresponding to H is 7, entering the second stripe, the physical storage address corresponding to I is 0, and the physical storage address corresponding to J is 1, and in this order, until the physical storage address corresponding to P is 7. VPU reads the pixels in each physical storage address in the memory by column. After pixels A to H are stored in the memory, the reading order of VPU is as shown in the figure.

[0038] Therefore, after the ISP finishes writing the pixel values ​​of the first strip to the memory, the VPU reads the pixel values. At this time, if the ISP continues to read the pixel values ​​of the second strip from the memory, for example, pixel J, since the physical storage address corresponding to pixel J is 1, and the VPU first reads pixel E at address 4, pixel B at address 1 is replaced by the newly written pixel J before being read by the VPU. In this case, it is necessary to wait for the VPU to finish reading the pixel values ​​of one strip before the ISP writes the pixel values ​​of the next strip to the memory. However, this processing method has the problem of low efficiency in transmitting video. Therefore, the present application improves the transmission efficiency of video data by changing the physical storage address corresponding to the pixel through the following steps.

[0039] S203, determining a first target stripe to which the first pixel belongs; S204: Obtain a target matrix corresponding to the first target stripe.

[0040] In the embodiment of the present application, the logical storage address of the first pixel can be determined according to the first address information of the first pixel, and the first target stripe corresponding to the first pixel in the target video can be determined according to the logical storage address of the first pixel. The ISP can specify a different logical storage address for each pixel in the target video, and the memory determines which stripe in the target video the first pixel belongs to according to the logical storage address corresponding to each pixel.

[0041] As an optional embodiment, the ISP can set the logical storage address corresponding to the first pixel of the video frame to the physical storage address of the memory, combined with Figure 4 , the logical storage address of pixel A is 0, the logical storage address of pixel B is 1, and in this order, the logical storage address of pixel P is 15. The memory can determine how many times the first address information is received in total, thereby determining the video frame to which the first pixel belongs, and then determining the first target stripe corresponding to the first pixel according to the width and height of a standard stripe.

[0042] In an embodiment of the present application, the physical storage addresses in the memory are divided into m*t consecutive address blocks, where t is w / k rounded up, so each address block corresponds to at least k physical storage addresses. For the convenience of expression, the address block including k physical storage addresses is called a standard address block. Only the last address block of each row in the memory may not be a standard address block, and each address block stores the pixel value in a pixel block.

[0043] In an embodiment of the present application, each strip corresponds to a target address block, and the target matrix corresponding to the first strip of the target video is the initial address block matrix. The elements in the initial address block matrix are identifiers of the address blocks in the memory, that is, the initial address block matrix is ​​a matrix of m rows and t columns, and the element value of each element is the identifier of an address block. It should be understood that the position of the address block in the memory is the same as the position of the identifier of the address block in the initial address block matrix.

[0044] In an embodiment of the present application, the target matrix of the non-first strip of the target video is obtained by matrix transformation of the target matrix of the previous strip of the strip. Specifically, the target matrix of the previous strip of the strip is used as the first matrix, and the transposed matrix of the first matrix is ​​obtained. After the elements in the transposed matrix are arranged in the order of the number of rows in which the elements are located, the arranged matrix is ​​divided into m*t matrices, and the divided matrix is ​​used as the second matrix, and the second matrix is ​​used as the target matrix of the strip. It should be noted that the previous strip of the first strip data of the non-first video frame in the target video is the last strip of the previous video frame, that is, the target video of the present application is composed of continuous strip data.

[0045] like Figure 5 As shown, Figure 5 A schematic diagram of a matrix conversion process provided for an embodiment of the present application. Taking t as 4 and m as 2 as an example, 0-8 are the identifiers of the corresponding address blocks, where matrix A is the first matrix. First, matrix A is transposed to obtain the transposed matrix of matrix A, that is, matrix B. Matrix B is expanded row by row to obtain matrix C. Matrix C is divided into 4 units to obtain matrix D. It can be seen that matrix D and matrix A are both matrices with 2 rows and 4 columns.

[0046] S205: Determine a first target address block to which the first physical storage address belongs in the memory.

[0047] In an embodiment of the present application, the memory includes multiple address blocks, each address block includes multiple physical storage addresses, and for each physical storage address, the processor can determine the address block described by the physical storage address, and thus can determine the first target address block to which the first physical storage address belongs in the memory.

[0048] S206, determining a first position of the identifier of the first target address block in the initial address block matrix, and a second position of the first physical storage address in the first target address block; S207 , determining a second target address block corresponding to a first position in a target matrix corresponding to the first target stripe, and storing a pixel value of the first pixel in a physical storage address corresponding to a second position in the second target address block.

[0049] In an embodiment of the present application, after determining the first target address block corresponding to the first physical address, the identifier of the first target address block is obtained, and the identifier of the first target address block is found from the initial address block matrix, and the position of the identifier of the first target address block in the initial address block can be determined. The position can be the row number and column number of the identifier in the initial address block matrix, and the position is recorded as the first position.

[0050] In an embodiment of the present application, when the processor determines the first target matrix to which the first physical storage address belongs, it can also determine the position of the first physical storage address in the first target address block. The position can be the nth physical storage address of the first physical storage address in the first target address block, and the position is recorded as the second position.

[0051] In an embodiment of the present application, after obtaining the first position, the processor determines the address block identifier corresponding to the first position in the target matrix corresponding to the first target strip, uses the address block corresponding to the address block identifier as the second target address block, stores the pixel value of the first pixel in the physical storage address corresponding to the second position in the second target address block, uses the physical storage address corresponding to the second position as the third physical storage address, and the processor implements the address conversion from the first physical storage address to the physical storage address of the third position.

[0052] like Figure 6 As shown, Figure 6 A schematic diagram of a pixel storage process provided by an embodiment of the present application. Taking k as 1 as an example, at this time, a physical storage address corresponds to an address block, and the identifier of the physical storage address is used as the address block identifier. The video frame is the first video frame of the target video. For the first stripe, the target matrix of the stripe is the initial address block matrix. At this time, according to the pixel information sent by the ISP, it is stored in the memory row by row to obtain the memory storage result of the first stripe. According to the reading order of the VPU described above, the VPU reads the pixels in the memory in the order of AEBFCGDH. When the ISP writes the pixel value of the second stripe, the processor converts the storage address of the pixel value according to the target matrix of the second stripe. For example, for pixel J, the original physical storage address of the pixel is 1, and 1 is the physical storage address in the address block 1 of the memory. Address block 1 is the first target address block. Therefore, the position of identifier 1 in the initial address block matrix is ​​determined, that is, the first row and second column, and then the identifier at this position of the target matrix of the second stripe is determined, that is, identifier 4. At this time, it is determined that pixel J is stored in address block 4. Address block 4 is the second target address block. There is only one physical storage address in address block 4, that is, address 4. Therefore, pixel J is stored in the physical storage address 4 of the memory. The storage results of other pixels of the second stripe are similarly obtained.

[0053] It can be seen that the order in which the pixel values ​​of the second strip are stored in the addresses is consistent with the order in which the pixel values ​​of the first strip read in sequence by the VPU are located. Therefore, the present application does not need to wait for the VPU to read all the data of the previous strip before storing the data of the current strip in the memory, thereby improving the transmission efficiency of the video data.

[0054] As an optional embodiment, the identifier of the address block can be the high-order address of each physical storage address in the address block, and the second position of each physical storage address in the address block is the low-order address of each physical storage address block. The high-order addresses of the physical storage addresses in different address blocks in the memory are different, and the high-order addresses of the physical storage addresses in the same address block are the same, but the low-order addresses are different. Therefore, the present application only needs to perform address conversion on the high-order address of the first physical storage address of the first pixel, and then concatenate the high-order address obtained after the conversion with the low-order address of the first physical address to obtain the second physical storage address.

[0055] In an embodiment of the present application, by receiving pixel information sent by a first device, a pixel value of a pixel to be stored, i.e., a first pixel, and first address information of the pixel to be stored are obtained, wherein the first address information can represent a logical storage address designated for the pixel; by analyzing the first address information, a first physical storage address corresponding to the pixel to be stored in a memory can be determined; and by determining a first target strip to which the first pixel belongs in a target video, a target matrix corresponding to the first target strip can be determined.

[0056] According to the first target address block described by the first physical storage address in the memory and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and according to the second position of the first physical storage address inside the first target address block, the pixel to be stored is stored in the second position of the second target address block.

[0057] Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0058] As an optional embodiment of the present application, the data storage method in the direct mode further includes: When the pixel values ​​of all pixels belonging to the same stripe are stored in the memory, the value of the first parameter in the first record table is increased by 1, and the value of the first parameter represents the number of stripes that have been stored; Determining a first target stripe to which the first pixel belongs includes: Get the first record table; A first target stripe to which the first pixel belongs in the target video is determined according to a value of the first parameter in the first record table.

[0059] In the embodiment of the present application, the processor in the DFB records the number of stripes that have been read from the memory, and can record the number in a first record table, and set a first parameter in the first record table to indicate the number of stripes that have been read.

[0060] In the embodiment of the present application, after storing the last pixel of a stripe, the processor may add 1 to the value of the first parameter in the first record table. As an optional embodiment, when the first physical storage address corresponding to the first address information of the first pixel is the last physical storage address of the memory, the first pixel is determined to be the last pixel of the stripe to which the pixel belongs; or, after determining that the first pixel is the first pixel of the stripe to which the processor belongs, the processor adds 1 to the value of the first parameter in the first record table, and when the first physical storage address corresponding to the first address information of the first pixel is the first physical storage address of the memory, the first pixel is determined to be the first pixel of the stripe to which the pixel belongs.

[0061] In the embodiment of the present application, after receiving the pixel information of the first pixel, the processor can determine the stripe number of the first pixel in the target video according to the first parameter in the first record table.

[0062] As an optional embodiment, the processor may also determine the number of times the first physical storage address is received according to the first physical storage address corresponding to the first pixel, and determine the stripe number of the target video to which the first pixel belongs.

[0063] In the embodiment of the present application, by recording the number of strips stored in the memory, the first target strip to which the first pixel belongs in the target video can be effectively determined, thereby further determining the target matrix of the first target strip.

[0064] As an optional embodiment of the present application, for a non-first strip of the target video, the target matrix corresponding to the strip is obtained in the following manner: Obtain a target matrix corresponding to a previous strip, and use the target matrix corresponding to the previous strip as a first matrix; After sorting the elements in the transposed matrix of the first matrix according to the row number sequence corresponding to the row where the elements are located, the m*t matrix obtained by sequentially slicing the sorted elements is used as the second matrix; The second matrix is ​​used as a target matrix corresponding to the first target stripe to which the first pixel belongs.

[0065] As an optional embodiment of the present application, when pixel information of the first pixel of a non-first strip is received, a matrix transformation is performed on a target matrix of a strip preceding the non-first strip to obtain a target matrix of the non-first strip.

[0066] In an embodiment of the present application, the processor can determine that the first pixel is the first pixel of a non-first strip based on the first physical storage address corresponding to the first pixel, which is the first physical storage address in the memory, and the strip to which the first pixel belongs is not the first strip of the target video. At this time, the processor can obtain the target matrix of the previous strip as the first matrix, perform the above matrix transformation on the first matrix, obtain the second matrix, and use the second matrix as the target matrix of the first target strip to which the first pixel belongs.

[0067] In the embodiment of the present application, by determining that the first pixel is the first pixel of a non-first strip of the target video, it is determined that a matrix conversion operation needs to be performed, which is helpful for determining a target matrix corresponding to the first target strip.

[0068] As an optional embodiment, the present application may also pre-generate target matrices corresponding to respective strips in the target video, thereby improving the transmission efficiency of the processor during video transmission.

[0069] As an optional embodiment, determining a first physical storage address of a first pixel in a memory according to the first address information includes: Determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs; A first physical storage address of the first pixel in the memory is obtained according to the first address offset and the first physical storage address of the memory, wherein the address offset of the first physical storage address relative to the first physical storage address of the memory is equal to the first address offset.

[0070] In the embodiment of the present application, the processor receives first address information of the first pixel, and the first address information is used to represent the logical storage address of the first pixel. The processor can obtain the logical storage address of the first pixel of the first target stripe to which the first pixel belongs, and determine the first address offset, and the first address offset is used to represent the address offset between the first pixel and the first pixel of the first target stripe.

[0071] The processor can determine the first physical storage address according to the first address offset and the first physical storage address in the memory. It should be understood that the ISP is each pixel in the strip scanned by row, and the position of each pixel in the strip corresponds to the position of the first physical storage address corresponding to each pixel in the memory. For example, if the position of the first pixel in the strip is the second row and the second column, the position of the first physical storage address in the memory is also the second row and the second column.

[0072] By determining the logical storage address of the first pixel of the first target strip to which the first pixel belongs, the relative position relationship between the first pixel and the first pixel can be determined. Then, since the first pixel corresponds to the first physical storage address in the memory, the physical storage address with the relative position relationship is determined to be the first physical storage address corresponding to the first pixel.

[0073] like Figure 7 As shown, Figure 7 A schematic diagram of the logical storage address in a video frame provided by an embodiment of the present application. Wherein, w=4, k=2, that is, w is an integer multiple of k. It can be seen from the figure that for pixel G, the logical storage address of the pixel is 6, the first pixel of the strip to which the pixel belongs is pixel A, and the logical storage address of pixel A is 0, then the first address offset is 6, combined with the first physical storage address of the memory is 0, then the first physical storage address to pixel G is address 6; for pixel O, the logical storage address of the pixel is 14, the first pixel of the strip to which the pixel belongs is pixel I, and the logical storage address of pixel I is 8, then the first address offset is 6, combined with the first physical storage address of the memory is 0, the first physical storage address of pixel O is 6.

[0074] To further illustrate the logical storage address of each pixel in the video frame when w is not an integer multiple of k, such as Figure 8 As shown, Figure 8 Another schematic diagram of the logical storage address in a video frame provided for an embodiment of the present application. Wherein w is not an integer multiple of k, k=2, w=3, at this time, the first device will specify the logical storage address of the pixel according to the size of the k value and the width of the video frame, so that the position of the pixel in the strip is aligned with the position of the physical storage address that ultimately corresponds to the pixel in the memory. For example, for the first address information used to represent the logical storage address 3, the first physical storage address corresponding to the address is the address of the first row and fourth column in the memory, and the pixel d is the pixel in the second row and first column. Therefore, when the first device executes the logical storage address of pixel d, the logical storage address 3 will be left blank, and the logical storage address of pixel d will be specified as 4.

[0075] In the embodiment of the present application, the first physical storage address of the first pixel is determined by determining the first address offset between the first pixel and the first pixel in the strip to which it belongs.

[0076] As an optional embodiment of the present application, determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs includes: Determine an intra-frame address offset of a logical storage address of the first pixel relative to a logical storage address of a first pixel of the corresponding video frame, wherein the logical storage address of the first pixel of each video frame corresponds to a first physical storage address of the memory; Determine, according to the number of physical storage addresses in the memory, an intra-frame address offset of a first pixel in a strip to which the first pixel belongs; The first address offset is determined according to the intra-frame address offset of the first pixel and the intra-frame address offset of the first pixel in the strip to which the first pixel belongs.

[0077] In an embodiment of the present application, the ISP corresponds the logical storage address of the first pixel in each video frame to the first physical storage address of the memory, and the DFB pre-stores the correspondence between the logical storage address of the pixel in the first row and the first column of each video frame and the first physical storage address. The ISP and the VPU can also obtain the correspondence in advance. Therefore, after the processor receives the first address information of the first pixel, it obtains the logical storage address specified by the ISP for the first pixel. Since the logical storage address of the first pixel of the video frame to which the first pixel belongs is determined, the intra-frame address offset of the first pixel can be obtained, where the intra-frame address offset is used to indicate the relative position of the first pixel relative to the first pixel of the video frame to which it belongs.

[0078] In an embodiment of the present application, the processor can determine the in-frame address offset of the first pixel in the strip to which the first pixel belongs based on the number of physical storage addresses t*k*m in the memory, that is, the number of pixels in a standard strip. The processor can determine the first address offset based on the difference between the in-frame address offset of the first pixel and the in-frame address offset of the first pixel in the first target strip. It should be understood that the in-frame address offset of the first pixel is used to indicate the relative position of the first pixel relative to the first pixel of the video frame, and the in-frame address offset of the first pixel of the first target strip is used to indicate that the first pixel of the first target strip is equivalent to the relative position of the first pixel of the video frame. Therefore, according to the difference between the in-frame address offset of the first pixel and the in-frame address offset of the first pixel in the first target strip, the relative position of the first pixel relative to the first pixel of the first target strip, that is, the first address offset, can be determined.

[0079] like Figure 7As shown in , for pixel O, the intra-frame address offset of the pixel is 14. According to the number of physical storage addresses of the memory 8, and 8<14<16, the logical storage address of the first pixel I of the strip to which pixel O belongs is 8, and the intra-frame address offset of pixel I is 8, so the first address offset of pixel I is 6.

[0080] like Figure 8 As shown in , for pixel j, the intra-frame address offset of the pixel is 12. According to the number of physical storage addresses of the memory 8, and 8<12<16, the logical storage address of the first pixel g of the strip to which pixel j belongs is 8, and the intra-frame address offset of pixel g is 8, so the first address offset of pixel j is 4.

[0081] In the embodiment of the present application, the relative position of the first pixel in the frame is determined by determining the intra-frame address offset of the first pixel, and the relative position of the first pixel in the frame is determined by determining the intra-frame address offset of the first pixel of the strip to which the first pixel belongs, thereby determining the relative position of the first pixel in the strip.

[0082] As an optional embodiment of the present application, the data storage method in the pass-through mode further includes: receiving a pixel read request sent by a second device, wherein the pixel read request includes second address information of logical storage addresses of k pixels to be read; Determine, according to the second address information, a second physical storage address of each of the k pixels in the memory; Determine a second target stripe corresponding to the pixel read request, and determine a target matrix corresponding to the second target stripe; Determine a third target address block to which the k second physical storage addresses belong in the memory; Determine a third position of the identifier of the third target address block in the initial address matrix; A third target address block corresponding to a third position in the target matrix corresponding to the second target stripe is determined, and k pixel values ​​in the third target address block are sent to the second device.

[0083] In the embodiment of the present application, the VPU reads pixels in a block manner. When the VPU sends a pixel read request to the DFB, the pixel read request includes second address information of the logical storage addresses of k pixels.

[0084] In the embodiment of the present application, the processor of the DFB can determine the second physical storage address corresponding to each pixel according to the second address information of each pixel. For ease of understanding, each pixel to be read is regarded as a second pixel. The processor can determine the second physical storage address corresponding to each second pixel in the same manner as the first physical storage address corresponding to the first pixel. It should be understood that each second pixel is a pixel stored in the same address block.

[0085] In the embodiment of the present application, the processor also needs to determine the second target stripe corresponding to each second pixel, and determine the target matrix corresponding to the second target stripe. As an optional embodiment, the processor can record the number of stripes that have been read, and use the number of stripes that have been read as the second parameter in the first record table. When the processor sends the pixels of the last address block in the memory to the second device, the second parameter can be increased by 1; or when the processor determines that the address block corresponding to the pixel read request is the first address block, the second parameter is increased by 1.

[0086] In the embodiment of the present application, the processor can determine the third target block address described in the memory according to the k second physical storage addresses. It should be understood that the k second physical storage addresses correspond to the same address block in the memory. Then determine the third position of the identifier of the third address block in the initial address block matrix, determine the identifier corresponding to the third position in the target matrix corresponding to the second target stripe, determine the fourth target address block corresponding to the identifier, send each pixel in the fourth target address block to the second device in sequence according to the fourth position of each pixel in the fourth target address, and use the physical storage address corresponding to the fourth position as the fourth physical storage address, that is, the processor realizes the address conversion from the second physical storage address to the fourth physical address.

[0087] In the embodiment of the present application, when the second device reads the pixel, the second physical storage address corresponding to each pixel is also converted, so that the pixel storage and reading process are converted in the same address, which ensures that the pixel read by the VPU is correct, thereby ensuring the normal transmission of the video data. In the embodiment of the present application, there is no need to change the writing rules and reading rules originally set by the ISP and the VPU. Through two corresponding address conversions, a memory of the size of a stripe data can be realized, thereby realizing video pass-through with high data transmission efficiency.

[0088] The comparison results of the data storage scheme in the pass-through mode in the present application and the data storage scheme of the memory with twice the area of ​​the sample are shown in Table 1. Among them, the experimental environment is based on TSMC cln16, the video resolution is 4K, and the stripe height is 64 lines. Among them, the area index is the area of ​​the memory, which is used to represent the capacity of the memory. The scheme before optimization is to use a memory with twice the capacity of the stripe data, which is used when the VPU reads the data of one stripe, and the ISP can continue to store the pixels of another stripe in another storage space. It is also used to solve the problem that the ISP can continue to write stripe data only after the VPU reads all the data of a stripe. The optimized scheme is the scheme provided in this application. It can be obviously obtained from the area yield and the static power consumption yield that the video storage scheme in the pass-through mode provided in the embodiment of the present application occupies less storage resources and generates lower power consumption.

[0089] Table 1 Comparison of benefits of different video direct solutions

[0090] Fig. 9 A schematic diagram of a data storage device in a pass-through mode provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the apparatus of this embodiment may include: a receiving module 901 , an address translation module 902 , a target matrix acquisition module 903 and a storage module 904 .

[0091] A receiving module 901 is used to receive pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a width and a height of a video frame in the target video are w pixels and h pixels respectively; and each video frame is divided into a plurality of continuous strips of a size of w pixels in width and m pixels in height; An address translation module 902 is used to determine a first physical storage address of the first pixel in the memory according to the first address information; wherein the memory includes t*k*m physical storage addresses, and the physical storage addresses of the memory are divided into m*t continuous address blocks, and t is w / k rounded up; wherein k*m is the number of pixels read by the second device in a data reading operation in the memory, and a data reading operation includes m column-by-column reading operations performed on m rows of pixels, and the number of pixels read by a column-by-column reading operation is k pixels in a row; The target matrix acquisition module 903 determines the first target stripe to which the first pixel belongs; obtains the target matrix corresponding to the first target stripe; wherein the target matrix corresponding to the first stripe of the target video is the initial address block matrix, and the target matrix corresponding to the non-first stripe is the second matrix obtained by matrix transformation of the first matrix. The first matrix is ​​the target matrix corresponding to the previous stripe, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are the identifiers of the m*t address blocks. The second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in the order of the number of rows where the elements are located, and then sequentially dividing the sorted elements; The storage module 904 is used to determine the first target address block to which the first physical storage address belongs in the memory; determine the first position of the identifier of the first target address block in the initial address block matrix, and the second position of the first physical storage address inside the first target address block; determine the second target address block corresponding to the first position in the target matrix corresponding to the first target stripe, and store the pixel value of the first pixel in the physical storage address corresponding to the second position in the second target address block.

[0092] As an optional embodiment of the present application, the data storage device in the pass-through mode further includes: A recording module, used for adding 1 to the value of the first parameter in the first recording table when the pixel values ​​of each pixel belonging to the same stripe are stored in the memory, the value of the first parameter indicating the number of stripes that have been stored; When used to determine the first target stripe to which the first pixel belongs, the target matrix acquisition module 903 is specifically used to: Obtaining the first record table; A first target strip to which the first pixel belongs in the target video is determined according to a value of the first parameter in the first record table.

[0093] As an optional embodiment of the present application, the target matrix acquisition module 903 is further used for: Obtain a target matrix corresponding to a previous strip, and use the target matrix corresponding to the previous strip as a first matrix; After sorting the elements in the transposed matrix of the first matrix according to the row number sequence corresponding to the row where the elements are located, the m*t matrix obtained by sequentially slicing the sorted elements is used as the second matrix; The second matrix is ​​used as a target matrix corresponding to a first target stripe to which the first pixel belongs.

[0094] As an optional embodiment of the present application, the target matrix acquisition module 903 is further used to perform matrix transformation on the target matrix of the previous strip of the non-first strip when receiving pixel information of the first pixel of the non-first strip, so as to obtain the target matrix of the non-first strip.

[0095] As an optional embodiment of the present application, when the address translation module 902 is used to determine the first physical storage address of the first pixel in the memory according to the first address information, it is specifically used to: Determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs; A first physical storage address of the first pixel in the memory is obtained according to the first address offset and a first physical storage address of the memory, wherein an address offset of the first physical storage address relative to the first physical storage address of the memory is equal to the first address offset.

[0096] As an optional embodiment of the present application, when the address translation module 902 is used to determine the first address offset between the logical storage address of the first pixel and the logical storage address of the first pixel in the first target stripe to which the first pixel belongs, it is specifically used to: Determine an intra-frame address offset of a logical storage address of the first pixel relative to a logical storage address of a first pixel of a corresponding video frame, wherein the logical storage address of the first pixel of each video frame corresponds to a first physical storage address of the memory; Determine, according to the number of physical storage addresses in the memory, an intra-frame address offset of a first pixel in the strip to which the first pixel belongs; The first address offset is determined according to the intra-frame address offset of the first pixel and the intra-frame address offset of the first pixel in the strip to which the first pixel belongs.

[0097] As an optional embodiment of the present application, the receiving module 901 is further configured to receive a pixel reading request sent by a second device, where the pixel reading request includes second address information of a logical storage address of k pixels to be read; The address translation module 902 is further configured to determine a second physical storage address of each of the k pixels in the memory according to the second address information; The target matrix acquisition module 903 is further used to determine a second target stripe corresponding to the pixel read request, and determine a target matrix corresponding to the second target stripe; The storage module 904 is also used to determine the third target address block to which the k second physical storage addresses belong in the memory; determine the third position of the identifier of the third target address block in the initial address matrix; determine the fourth target address block corresponding to the third position in the target matrix corresponding to the second target strip, and send the k pixel values ​​in the fourth target address block to the second device.

[0098] The device of the embodiments of the present application can execute the method provided by the embodiments of the present application, and the implementation principles are similar. The actions performed by each module in the device of each embodiment of the present application correspond to the steps in the method of each embodiment of the present application. For the detailed functional description of each module of the device, please refer to the description in the corresponding method shown in the previous text, which will not be repeated here.

[0099] In an embodiment of the present application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, the processor executes the above-mentioned computer program to implement the steps of the data storage method in the direct mode, which can be implemented compared with the related art: by receiving the pixel information sent by the first device, the pixel value of the pixel to be stored is obtained, and the first address information of the pixel to be stored is obtained, and the first address information can represent the logical storage address designated by the pixel; by the first address information, the first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, the target matrix corresponding to the target stripe can be determined. According to the first target address block described by the first physical storage address in the memory, and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and according to the second position of the first physical storage address in the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0100] In an alternative embodiment, an electronic device is provided, such as Fig.10 As shown, Fig.10The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0101] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0102] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0103] The memory 4003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0104] The memory 4003 is used to store the computer program for executing the embodiment of the present application, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0105] Among them, electronic devices may include but are not limited to mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.10 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0106] The embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented. Compared with the prior art, it can be implemented as follows: by receiving the pixel information sent by the first device, the pixel value of the pixel to be stored is obtained, and the first address information of the pixel to be stored is obtained, and the first address information can represent the logical storage address designated by the pixel; by the first address information, the first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, the target matrix corresponding to the target stripe can be determined. According to the first target address block described in the memory by the first physical storage address, and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and according to the second position of the first physical storage address in the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0107] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer readable signal media may also be any computer readable medium other than computer readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0108] The embodiment of the present application also provides a computer program product, including a computer program, which can implement the steps and corresponding contents of the aforementioned method embodiment when executed by a processor. Compared with the prior art, it can be achieved that: by receiving the pixel information sent by the first device, the pixel value of the pixel to be stored is obtained, and the first address information of the pixel to be stored is obtained, and the first address information can represent the logical storage address designated by the pixel; by the first address information, the first physical storage address corresponding to the pixel to be stored in the memory can be determined; by determining the target stripe described by the first pixel in the video, the target matrix corresponding to the target stripe can be determined. According to the first target address block described by the first physical storage address in the memory, and the first position of the first target address block in the initial address block matrix, the second target address block corresponding to the first position in the target matrix can be determined, and according to the second position of the first physical storage address in the first target address block, the pixel to be stored is stored in the second position of the second target address block. Since the target matrix of the non-first strip is obtained after matrix transformation based on the target matrix of the previous strip, the order in which the address blocks in the target matrix of the non-first strip are read by row is the order in which the address blocks in the target matrix of the previous strip are read by column, which ensures that when the pixels to be read are stored in the memory, the pixels at the corresponding positions in the memory have been read by the second device. Therefore, the embodiment of the present application does not require the second device to read all the pixels in the memory before writing pixels to the memory, thereby improving the efficiency of video data transmission.

[0109] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in the drawings.

[0110] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0111] The above is only an optional implementation method for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A data storage method in direct mode, characterized in that: include: Receive pixel information of a first pixel of a target video sent by a first device, the pixel information including a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a width and a height of a video frame in the target video are w pixels and h pixels respectively; and each video frame is divided into a plurality of continuous strips of a size of w pixels in width and m pixels in height; Determine, according to the first address information, a first physical storage address of the first pixel in the memory; wherein the memory includes t*k*m physical storage addresses, the physical storage addresses of the memory are divided into m*t continuous address blocks, and t is w / k rounded up; wherein k*m is the number of pixels read by the second device in one data reading operation in the memory, one data reading operation includes m column-by-column reading operations performed on pixels in m rows, and the number of pixels read by one column-by-column reading operation is k pixels in one row; determining a first target stripe to which the first pixel belongs; Obtain a target matrix corresponding to the first target strip; wherein the target matrix corresponding to the first strip of the target video is an initial address block matrix, and the target matrix corresponding to the non-first strip is a second matrix obtained by matrix transformation of the first matrix, the first matrix is ​​the target matrix corresponding to the previous strip, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are the identifiers of the m*t address blocks, and the second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in the order of the number of rows where the elements are located, and sequentially slicing the sorted elements; Determine a first target address block to which the first physical storage address belongs in the memory; Determine a first position of the identifier of the first target address block in the initial address block matrix and a second position of the first physical storage address within the first target address block; A second target address block corresponding to the first position in the target matrix corresponding to the first target stripe is determined, and a pixel value of the first pixel is stored in a physical storage address corresponding to the second position in the second target address block.

2. The method according to claim 1, characterized in that Also includes: When the pixel values ​​of all pixels belonging to the same stripe are stored in the memory, the value of the first parameter in the first record table is increased by 1, and the value of the first parameter represents the number of stripes that have been stored; The determining the first target stripe to which the first pixel belongs includes: Obtaining the first record table; A first target strip to which the first pixel belongs in the target video is determined according to a value of the first parameter in the first record table.

3. The method according to any one of claims 1 to 2, characterized in that: For non-first strips of the target video, the target matrix corresponding to the strip is obtained in the following way: Obtain a target matrix corresponding to a previous strip, and use the target matrix corresponding to the previous strip as a first matrix; After sorting the elements in the transposed matrix of the first matrix according to the row number sequence corresponding to the row where the elements are located, the m*t matrix obtained by sequentially slicing the sorted elements is used as the second matrix; The second matrix is ​​used as a target matrix corresponding to a first target stripe to which the first pixel belongs.

4. The method according to claim 3, characterized in that When pixel information of a first pixel of a non-first strip is received, a matrix transformation is performed on a target matrix of a strip preceding the non-first strip to obtain a target matrix of the non-first strip.

5. The method according to claim 1, characterized in that The determining, according to the first address information, a first physical storage address of the first pixel in the memory includes: Determining a first address offset between a logical storage address of a first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs; A first physical storage address of the first pixel in the memory is obtained according to the first address offset and a first physical storage address of the memory, wherein an address offset of the first physical storage address relative to the first physical storage address of the memory is equal to the first address offset.

6. The method according to claim 5, characterized in that The determining of a first address offset between a logical storage address of the first pixel and a logical storage address of a first pixel in a first target stripe to which the first pixel belongs comprises: Determine an intra-frame address offset of a logical storage address of the first pixel relative to a logical storage address of a first pixel of a corresponding video frame, wherein the logical storage address of the first pixel of each video frame corresponds to a first physical storage address of the memory; Determine, according to the number of physical storage addresses in the memory, an intra-frame address offset of a first pixel in the strip to which the first pixel belongs; The first address offset is determined according to the intra-frame address offset of the first pixel and the intra-frame address offset of the first pixel in the strip to which the first pixel belongs.

7. The method according to claim 1, characterized in that The method further comprises: receiving a pixel read request sent by a second device, wherein the pixel read request includes second address information of logical storage addresses of k pixels to be read; Determine, according to the second address information, a second physical storage address of each of the k pixels in the memory; Determine a second target stripe corresponding to the pixel read request, and determine a target matrix corresponding to the second target stripe; Determine a third target address block to which the k second physical storage addresses belong in the memory; Determining a third position of the identifier of the third target address block in the initial address matrix; Determine a fourth target address block corresponding to the third position in the target matrix corresponding to the second target stripe, and send k pixel values ​​in the fourth target address block to the second device.

8. A data storage device in direct mode, characterized in that: include: A receiving module, configured to receive pixel information of a first pixel of a target video sent by a first device, wherein the pixel information includes a pixel value and first address information indicating a logical storage address of the first pixel in a memory; wherein a width and a height of a video frame in the target video are w pixels and h pixels respectively; and each video frame is divided into a plurality of continuous strips of a size of w pixels in width and m pixels in height; an address translation module, configured to determine, according to the first address information, a first physical storage address of the first pixel in the memory; wherein the memory includes t*k*m physical storage addresses, the physical storage addresses of the memory are divided into m*t continuous address blocks, and t is w / k rounded up; wherein k*m is the number of pixels read by the second device in a data reading operation in the memory, and a data reading operation includes m column-by-column reading operations performed on pixels in m rows, and the number of pixels read by a column-by-column reading operation is k pixels in a row; A target matrix acquisition module determines a first target stripe to which the first pixel belongs; acquires a target matrix corresponding to the first target stripe; wherein the target matrix corresponding to the first stripe of the target video is an initial address block matrix, and the target matrix corresponding to a non-first stripe is a second matrix obtained by matrix transformation of the first matrix; the first matrix is ​​a target matrix corresponding to the previous stripe, the initial address block matrix is ​​an m*t matrix, and the element values ​​of the m*t elements are identifiers of the m*t address blocks; the second matrix is ​​an m*t matrix obtained by sorting the elements in the transposed matrix of the first matrix in the order of the number of rows where the elements are located, and then sequentially dividing the sorted elements; A storage module is used to determine the first target address block to which the first physical storage address belongs in the memory; determine the first position of the identifier of the first target address block in the initial address block matrix, and the second position of the first physical storage address inside the first target address block; determine the second target address block corresponding to the first position in the target matrix corresponding to the first target stripe, and store the pixel value of the first pixel in the physical storage address corresponding to the second position in the second target address block.

9. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images