Generation method of test program, test method and related device
By generating a set of memory warm-up instructions, the problem of the difference between program slices and original programs in memory state is solved, and the accuracy of performance evaluation and chip performance simulation is improved.
Patent Information
- Application Number
- CN202311068803.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-23
- Publication Date
- 2025-02-25
AI Technical Summary
There is a difference in memory state between program slices and original programs, which affects performance evaluation and chip performance simulation accuracy.
By obtaining memory access-related information during the operation of the target program, a set of memory warm-up instructions is generated to pre-access the target memory page before executing instructions in the area of interest, ensuring the consistency of memory state.
Improves the performance consistency between program slices and original programs, and enhances the accuracy of program performance evaluation and chip performance simulation.
Smart Images
Figure CN119512886A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a test program generation method, a test method and related devices. Background Art
[0002] Program slicing technology is widely used in program performance evaluation and chip performance simulation during chip design. Program slicing is to intercept the dynamic execution fragment of the original program, and then encapsulate the intercepted dynamic execution fragment into a binary executable file. By executing this binary executable file, a dynamic instruction execution flow consistent with the original program can be generated. By analyzing the performance of program slices during operation, the performance of the original program can be obtained.
[0003] However, since the memory state of a program slice when it is running is different from the memory state of the dynamic execution fragment corresponding to the program slice when it is running in the original program, there will be differences in the performance of the program slice and the original program, affecting the accuracy of program performance evaluation or chip performance simulation. Summary of the invention
[0004] The present application provides a test program generation method, a test method and related devices, which are beneficial to improving the consistency of program slices with the performance of the original program.
[0005] In the first aspect, the present application provides a method for generating a test program. The method includes: obtaining memory access related information during the running of the target program, the memory access related information including a first address set and indication information, the first address set including the memory address accessed by each instruction in the region of interest of the target program, the indication information being used to indicate the memory address corresponding to the instruction that generates a page fault in the first address set; generating a memory preheating instruction set based on the memory access related information, the memory preheating instruction set including at least one memory preheating instruction, the at least one memory preheating instruction being used to access the memory address corresponding to at least one target memory page, the at least one target memory page including the memory pages corresponding to the first address set, except for the memory page to which the memory address indicated by the indication information belongs; generating a test program based on the memory preheating instruction set and the instruction stream of the region of interest.
[0006] In the present application, a test program is generated according to the memory preheating instruction set and the instruction stream of the region of interest. By executing the memory preheating instruction in the memory preheating instruction set, the memory address corresponding to at least one target memory page can be accessed in advance before executing the instruction corresponding to the region of interest. Since the at least one target memory page includes the memory pages corresponding to the first address set, except for the memory pages to which the memory address indicated by the indication information belongs, the memory pages touched by the region of interest can be preloaded except for the memory pages corresponding to the instructions that cause page faults. In this way, the memory state of the region of interest when the instruction stream is executed can be made basically consistent with the memory state of the region of interest of the target program when it is running, so that the performance of the part of the test program corresponding to the region of interest is closer to the performance of the original program, which is conducive to improving the accuracy of program performance evaluation or chip performance simulation.
[0007] Optionally, obtaining the memory access related information during the running of the target program includes: inserting the target program; and running the inserted target program to obtain the memory access related information. Obtaining the memory access related information by inserting is a relatively mature technology and is easy to implement.
[0008] Optionally, the indication information includes a page fault-related event, and the page fault-related event is used to indicate a memory address corresponding to an instruction that generates a page fault; and obtaining memory access-related information during the running of the target program further includes: recording the page fault-related event. By recording the page fault-related event, the instruction that generates the page fault can be accurately determined, thereby determining the memory address corresponding to the instruction that generates the page fault.
[0009] In a possible implementation, the page fault-related events include a first switching event and a second switching event, the first switching event is an event of switching from user mode to kernel mode, and the second switching event is an event of switching from kernel mode to user mode; recording the page fault-related events includes: recording the first switching event and the second switching event according to changes in the exception level of the processor running the target program.
[0010] Through the occurrence of the switching event between the user state and the kernel state, the instruction causing the page fault can be accurately identified, thereby determining the memory address corresponding to the instruction causing the page fault.
[0011] In another possible implementation, the page fault related event includes a page fault event; and recording the page fault related event includes: when the address of the currently executed instruction is within the address range indicated by the exception vector table, and the value of the register used to indicate the exception type indicates that the exception type is a page fault, recording the page fault event. By recording the occurrence of the page fault event, the instruction that generates the page fault can be accurately identified, thereby determining the memory address corresponding to the instruction that generates the page fault.
[0012] Optionally, generating a memory preheating instruction set based on the memory access related information includes: determining a first memory page set based on the first address set, the first memory page set including at least one first memory page, and the at least one first memory page is a memory page to which a memory address in the first address set belongs; determining the memory page to which the memory address indicated by the indication information belongs as a second memory page set; determining a memory page in a complement set of the second memory page set in the second memory page set as the target memory page; and generating the memory preheating instruction set based on the target memory page.
[0013] Optionally, determining the first memory page set based on the first address set may include: calculating the memory page base address of each memory address in the first address set to obtain a first memory page base address set, the first memory page base address set including multiple different memory page base addresses, each memory page base address corresponding to a first memory page.
[0014] Optionally, the second memory page set can be implemented in any of the following two ways. First, the memory page base address of each memory address in the second address set is calculated to obtain the second memory page base address set. Second, according to the indication information, the second memory page base address set is determined from the first memory page base address set. The second memory page base address set includes at least one memory page base address, and each memory page base address corresponds to a second memory page.
[0015] Optionally, according to the target memory page, the memory warm-up instruction set may be generated in any one of the following three ways.
[0016] The first method is to generate a memory warm-up instruction for the memory page base address of each target memory page. The memory addresses accessed by different memory warm-up instructions correspond to different memory page base addresses.
[0017] The second method: determine the address range corresponding to each target memory page according to the memory page base address and the size of the memory page of each target memory page; select a memory address from the address range corresponding to each target memory page; generate a memory preheating instruction for each selected memory address. Each memory preheating instruction is used to access a memory address, and different memory preheating instructions access different memory addresses.
[0018] The third method: generating a memory warm-up instruction for each memory address belonging to the target memory page in the first address set.
[0019] In the first and second methods, the number of memory preheating instructions is the same as the number of target memory pages, and memory preheating can be achieved with fewer memory preheating instructions. In addition, the implementation process of the first method is simpler, which is conducive to simplifying the generation process of the test program.
[0020] Optionally, the method further includes: obtaining a register recovery instruction set, the register recovery instruction set including at least one register recovery instruction, the at least one register recovery instruction being used to recover the register state at the beginning of the region of interest. Generating a test program according to the memory warm-up instruction set and the instruction stream of the region of interest includes: generating the test program according to the memory warm-up instruction set, the register recovery instruction set and the instruction stream of the region of interest.
[0021] In a second aspect, a test method is provided. The method can be executed by a computer device, for example, by a chip simulator in the computer device. The method comprises: obtaining a test program, the test program comprising a memory preheating instruction set and an instruction stream of an area of interest of a target program, the memory preheating instruction set comprising at least one memory preheating instruction; executing the at least one memory preheating instruction to obtain a target memory state; and running the instruction stream in the target memory state to obtain a test result.
[0022] In a third aspect, the present application provides a device for generating a test program. The device for generating the test program has the function of implementing the method described in the first aspect or any optional method of the first aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.
[0023] In a fourth aspect, the present application provides a testing device. The testing device has the function of implementing the method described in the second aspect or any optional method of the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.
[0024] In a fifth aspect, an electronic device is provided. The electronic device includes a processor and a memory. The memory is used to store software programs and modules. The processor implements the method in the first aspect or any possible implementation of the first aspect by running or executing the software program and / or module stored in the memory, or implements the method in the second aspect or any possible implementation of the second aspect.
[0025] Optionally, the number of the processors is one or more, and the number of the memories is one or more.
[0026] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.
[0027] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.
[0028] In a sixth aspect, a computer program product is provided. The computer program product includes computer program code, and when the computer program code is executed by a computer, the computer executes the method in the first aspect or any possible implementation of the first aspect, or executes the method in the second aspect or any possible implementation of the second aspect.
[0029] In the seventh aspect, the present application provides a computer-readable storage medium, which is used to store program codes executed by a processor, and the program codes include instructions for implementing the method in any possible implementation of the above-mentioned first aspect, or implementing the method in any possible implementation of the above-mentioned second aspect or the second aspect.
[0030] In an eighth aspect, the present application provides a chip comprising a processor, wherein the processor is used to call and execute instructions stored in a memory from the memory, so that an electronic device equipped with the chip executes a method in any possible implementation of the first aspect above, or executes a method in any possible implementation of the second aspect above or the second aspect.
[0031] In a ninth aspect, the present application provides another chip. The other chip includes an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected via an internal connection path. The processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the method in any possible implementation of the first aspect above, or execute the method in any possible implementation of the second aspect or the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a flowchart of a method for generating a test program provided in an embodiment of the present application;
[0033] Figure 2 It is a schematic diagram of the contents of an instruction stream data file provided by an embodiment of the present application;
[0034] Figure 3 It is a schematic diagram of the contents of another instruction stream data file provided in an embodiment of the present application;
[0035] Figure 4 It is a schematic diagram of the working principle of an embodiment of the present application;
[0036] Figure 5 It is a flow chart of a testing method provided in an embodiment of the present application;
[0037] Figure 6 It is a block diagram of a test program generation device provided in an embodiment of the present application;
[0038] Figure 7 is a block diagram of a testing device provided in an embodiment of the present application;
[0039] Figure 8 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0041] In order to facilitate understanding of the embodiments of the present application, some nouns or terms involved in the embodiments of the present application are explained below.
[0042] Binary executable file: A machine language representation of a program, usually stored in binary form, which can only be read and executed by a computer. A binary executable file refers to the final executable file generated after the source code is compiled and can be run directly on a computer.
[0043] Instruction execution flow: The sequence of instructions executed by a program during its execution.
[0044] Program slicing: The dynamic execution fragment of the original program is intercepted, and then the intercepted dynamic execution fragment is encapsulated into a binary executable file.
[0045] Region of interest (also known as interval of interest): refers to the representative interval in the program, that is, the program will have periodic behavior. This periodic behavior is manifested in the repeated execution of the same code, or the execution of different codes with similar characteristics. The interval corresponding to the periodic behavior is the representative interval.
[0046] Chip simulator: is a tool used to verify and test chip designs. It can simulate the behavior of the chip so that designers can test and debug before actually manufacturing the chip. Chip simulators usually include a simulation engine (a stand-alone software) that can simulate the circuit behavior of the chip and provide some debugging and analysis tools to help designers identify and solve problems.
[0047] Chip performance simulation: refers to the use of computer software to simulate the operation process of a chip to evaluate the performance and function of the chip. During the chip design process, designers need to perform various tests and verifications on the chip to ensure that the chip can operate normally and meet the design requirements. Chip performance simulation can help designers predict the performance and function of the chip before the chip is actually manufactured, thereby improving design efficiency and reducing manufacturing costs. At the same time, chip performance simulation can also help designers discover and solve potential problems and improve the reliability and stability of the chip.
[0048] Figure 1 FIG. 1 is a flow chart of a method for generating a test program provided in an embodiment of the present application. Figure 1 As shown, the method includes the following steps 101-103.
[0049] 101: Obtain memory access related information during the running of the target program.
[0050] Among them, the memory access related information includes first address set indication information, the first address set includes the memory address accessed by each instruction in the area of interest of the target program, and the indication information is used to indicate the memory address corresponding to the instruction that generates a page fault in the first address set.
[0051] In the embodiment of the present application, the target program is a complete application program, which may also be referred to as an original program.
[0052] 102: Generate a memory warm-up instruction set according to the memory access related information.
[0053] The memory preheating instruction set includes at least one memory preheating instruction, and the at least one memory preheating instruction is used to access a memory address corresponding to at least one target memory page. The at least one target memory page includes memory pages corresponding to the first address set, except for the memory page to which the memory address indicated by the indication information belongs.
[0054] 103: Generate a test program according to the memory warm-up instruction set and the instruction stream of the region of interest.
[0055] The test program may also be called a program slice. The instruction flow of the region of interest is the instruction execution flow of the region of interest.
[0056] In an embodiment of the present application, a test program is generated according to a memory preheating instruction set and an instruction stream of an area of interest. By executing the memory preheating instruction in the memory preheating instruction set, a memory address corresponding to at least one target memory page can be accessed in advance before executing the instruction in the area of interest. Since the at least one target memory page includes memory pages corresponding to the first address set, except for the memory page to which the memory address indicated by the indication information belongs, all memory pages touched by the area of interest except for the memory page corresponding to the instruction that generates the page fault can be preloaded. In this way, the memory state of the part of the test program corresponding to the area of interest during execution can be made substantially consistent with the memory state of the area of interest of the target program during operation, so that the performance of the part of the test program corresponding to the area of interest is closer to the performance of the original program, which is conducive to improving the accuracy of program performance evaluation or chip performance simulation.
[0057] The implementation method of each step is exemplified below.
[0058] Optionally, step 101 may include: a first step of inserting a target program; and a second step of running the inserted target program to obtain memory access related information.
[0059] In a possible implementation, inserting a target program includes: inserting a first recording logic before each instruction in the target area of the target program, and inserting a second recording logic after each instruction. The first recording logic is used to record basic instruction information of each instruction, and the basic instruction information includes an instruction address and an instruction code. Among them, the instruction address refers to the storage address of the instruction, and the instruction code is used to indicate the specific type of the instruction. The second recording logic is used to record instruction memory access information, and the instruction memory access information includes the memory address and memory data accessed by the instruction.
[0060] After inserting the first recording logic and the second recording logic, the target program after the insertion is run to obtain an instruction stream data file, which includes basic instruction information and instruction memory access information of each instruction in the area of interest, that is, the instruction stream data file includes memory access related information.
[0061] In the embodiment of the present application, recording logic refers to the code added to record the required instruction stream data.
[0062] Optionally, the indication information includes a page fault related event, and the page fault related event is used to indicate a memory address corresponding to an instruction that generates a page fault. Accordingly, the second step includes: recording the page fault related event.
[0063] Optionally, there are two implementations of page fault related events:
[0064] In the first mode, the page fault related events include a first switching event and a second switching event, the first switching event is an event of switching from a user state to a kernel state, and the second switching event is an event of switching from a kernel state to a user state. In the first mode, recording the page fault related events includes: recording the first switching event and the second switching event according to a change in an exception level (EL) of a processor running a target program.
[0065] Different ELs correspond to different states of the processor. When the processor is in user mode, the EL is at the first level, and when the processor is in kernel mode, the EL is at the second level. When the EL changes from the first level to the second level, a first switching event is recorded; when the EL changes from the second level to the first level, a second switching event is recorded.
[0066] For example, for an advanced RISC (reduced instruction set computer) machine (ARM) architecture processor, when EL is 0, it indicates that the processor is in user mode, and when EL is 1, it indicates that the processor is in kernel mode. Therefore, when EL changes from 0 to 1, a first switching event is recorded; when EL changes from 1 to 0, a second switching event is recorded.
[0067] Figure 2 Schematic diagram of the contents of an instruction stream data file provided by an embodiment of the present application. Figure 2 As shown, the instruction stream data file includes two categories, one is Figure 2 As shown in part (a) of , it includes memory access instructions and the memory access addresses and memory access data corresponding to the memory access instructions; the other type is as follows Figure 2As shown in part (b), it includes memory access instructions (user-mode instructions), the first switching event, the kernel-mode instruction stream of the page fault processing function, the second switching event, and the memory access address and memory access data corresponding to the memory access instruction. Figure 2 From parts (a) and (b), it can be seen that when a memory access instruction corresponds to a first switching event, a kernel-mode instruction stream of a page fault handling function, and a second switching event, it indicates that the memory access instruction is an instruction that generates a page fault. Therefore, the first switching event, the kernel-mode instruction stream of a page fault handling function, and the second switching event can be used as indication information.
[0068] In the second mode, the page fault related event includes a page fault event. In the second mode, recording the page fault related event includes: when the address of the currently executed instruction is located in the address range indicated by the exception vector table, and the value of the register for indicating the exception type indicates that the exception type is a page fault, recording the page fault event.
[0069] The exception vector table is pre-stored in the processor before the processor leaves the factory. During the operation of the processor, the exception handling operation will be performed based on the relationship between the instruction address of the currently executed instruction and the address range indicated by the exception vector table. When the address of the currently executed instruction is within the address range indicated by the exception vector table, it indicates that the exception handling event has occurred; when the address of the currently executed instruction is outside the address range indicated by the exception vector table, it indicates that the exception handling event has not occurred. During implementation, the address range indicated by the exception vector table can be calculated based on the value of the system register used to indicate the mapping address of the exception vector table. For example, for an ARM architecture processor, the address range indicated by the exception vector table can be calculated based on the value of the vector base address register (VBAR).
[0070] After determining that an exception handling event has occurred, obtain the value of the register used to indicate the exception type. If the value of the register used to indicate the exception type indicates that the exception type is a page fault, the page fault event is recorded; if the value of the register used to indicate the exception type indicates that the exception type is not a page fault, the page fault event is not recorded. For example, for an ARM architecture processor, bits 26 to 31 of the exception syndrome register (ESR) are used to indicate the exception type. When the 5-bit data is 0b00011, it indicates a page fault.
[0071] Figure 3 Schematic diagram of another instruction stream data file provided by the embodiment of the present application. Figure 3 As shown, the instruction stream data file includes two categories, one is Figure 3 As shown in part (a) of , it includes memory access instructions and the memory access addresses and memory access data corresponding to the memory access instructions; the other type is as follows Figure 3 As shown in part (b), it includes memory access instructions (user-mode instructions), page fault events, and the memory access address and memory access data corresponding to the memory access instructions. Figure 2 From parts (a) and (b) of FIG. 1 , it can be seen that when a memory access instruction corresponds to a page fault event, it indicates that the memory access instruction is an instruction that generates a page fault. Therefore, the page fault event can be used as indication information.
[0072] The first and second methods can effectively record page fault related events, so that the memory address corresponding to the instruction causing the page fault can be determined according to the page fault related events later.
[0073] In an embodiment of the present application, the target area includes an area of interest. In some examples, the area of interest is a part of the target area, for example, the target area may be instruction X to instruction X+20000 of the target program, and the area of interest may be instruction X to instruction X+10000 of the target program. In other examples, the area of interest is the same as the target area, for example, both the target area and the area of interest are instruction X to instruction X+10000 of the target program.
[0074] The target area can be selected by manually analyzing the business key interval, or by analyzing the instruction execution frequency through an algorithm model. The embodiment of the present application does not limit the manual analysis method and the implementation of the algorithm model, and any method in the relevant technology can be used.
[0075] Since the entire target program needs to be run to collect the instruction stream data file, if the target program is run using a chip simulator, the running time will be very long, so the target program can be run on a hardware device, such as a chip sample, a server based on the chip sample, or other computing devices.
[0076] In a possible implementation, step 102 includes: a first step, determining a first memory page set based on a first address set, the first memory page set including at least one first memory page, and the at least one first memory page is a memory page to which a memory address in the first address set belongs; a second step, determining the memory page to which the memory address indicated by the indication information belongs as a second memory page set; a third step, determining a memory page in a complement set of the second memory page set in the second memory page set as a target memory page; and a fourth step, generating a memory preheating instruction set based on the target memory page.
[0077] In the first step, the memory page base address corresponding to each memory address in the first address set can be calculated to obtain a first memory page base address set, wherein the first memory page base address set includes a plurality of different memory page base addresses, each memory page base address corresponding to a first memory page. The memory page base address can be calculated based on the memory address and the memory page size.
[0078] In the second step, the second memory page set can be implemented in any of the following two ways. First, the memory page base address of each memory address in the second address set is calculated to obtain a second memory page base address set, and the second address set includes the memory address indicated by the indication information. Second, according to the indication information, the second memory page base address set is determined from the first memory page base address set. The second memory page base address set includes at least one memory page base address, and each memory page base address corresponds to a second memory page.
[0079] Optionally, in the fourth step, the memory preheating instruction set can be obtained using any one of methods A to C.
[0080] Method A: Generate a memory warm-up instruction for the memory page base address of each target memory page. The memory addresses accessed by different memory warm-up instructions correspond to different memory page base addresses.
[0081] Method B: Determine the address range corresponding to each target memory page according to the memory page base address and the size of the memory page of each target memory page; select any memory address from the address range corresponding to each target memory page; generate a memory preheating instruction for each selected memory address. Each memory preheating instruction is used to access a memory address, and different memory preheating instructions access different memory addresses.
[0082] Method C: Generate a memory warm-up instruction for each memory address belonging to the target memory page in the first address set.
[0083] In methods A and B, the number of memory preheating instructions is the same as the number of target memory pages, and memory preheating can be achieved with fewer memory preheating instructions. In addition, the implementation process of method A is simpler, which is conducive to simplifying the generation process of the test program.
[0084] In the embodiment of the present application, the memory preheating instruction can be any memory access instruction, including but not limited to a read instruction or a write instruction, etc., as long as the target memory page can be loaded into the memory in advance. In order to improve the efficiency of instruction execution, the memory preheating instructions can all be read instructions.
[0085] Optionally, step 103 includes: combining each memory preheating instruction in the memory preheating instruction set with the instruction stream in the region of interest, with the memory preheating instruction preceding the instruction stream in the region of interest; and generating a test program based on the combined instruction stream.
[0086] In order to further ensure that the execution logic of the part corresponding to the region of interest in the test program is completely consistent with the execution logic of the target program, it is also necessary to ensure that the register state of the part corresponding to the region of interest in the test program during execution is consistent with the register state corresponding to the region of interest in the target program. Therefore, the method also includes: obtaining a register recovery instruction set, the register recovery instruction set includes at least one register recovery instruction, and the at least one register recovery instruction is used to restore the register state at the beginning of the region of interest.
[0087] Optionally, the register restore instruction includes a general register restore instruction and a system register restore instruction. The system register includes at least a condition flag register (CFR). The condition flag register is used to store the execution result of the relevant instruction, or to provide a behavioral basis for the processor to execute the relevant instruction, or to control the relevant working mode of the processor.
[0088] Exemplarily, the register recovery instruction may be a register load instruction (load register), which includes a memory address, and is used to instruct that the data corresponding to the memory address is loaded into the corresponding register. The memory address and the corresponding data may also be stored in the aforementioned instruction stream data file, that is, the register recovery instruction is also generated based on the instruction stream data file.
[0089] Accordingly, step 103 includes: generating a test program according to the memory warm-up instruction set, the register recovery instruction set and the instruction stream of the region of interest.
[0090] Optionally, the memory warm-up instruction set, the register recovery instruction set and the instruction stream of the region of interest are sequentially combined together, and then a test program is generated based on the combined instruction stream.
[0091] Exemplarily, the combined instruction stream and the execution context of the instruction stream in the region of interest are converted into a binary executable file, and the binary executable file is the test program.
[0092] Combine the following Figure 4 The working principle and effect of the embodiment of the present application are described. Assume that the program slice includes M instructions, where M is greater than 1 and is an integer. The first instruction of the program slice corresponds to the N+1th instruction in the target program, and the Mth instruction of the program slice is the N+Mth instruction in the target program, where N is greater than 1 and is an integer. Figure 4 The solid-line frame in the figure represents the memory page corresponding to the instruction that did not cause a page fault, and the dotted-line frame represents the memory page corresponding to the instruction that caused a page fault.
[0093] Figure 4 Part (a) of FIG. 1 shows the memory state of the program slice in the related art when it is running and the memory state of the region of interest of the target program when it is running. Figure 4 As shown in part (a) of , before the target program executes the N+1th instruction, N instructions have been executed, and these N instructions have accessed some memory pages. For example, memory page 1, memory page 2, and memory page 3 are accessed. Therefore, when the N+1th instruction is executed, the data corresponding to memory page 1, memory page 2, and memory page 3 have all been loaded into the physical memory.
[0094] During the execution of the N+1th instruction to the N+Mth instruction, memory page 1 and memory page 2 need to be accessed, and the corresponding data can be obtained directly from the physical memory. If a memory page that has not been accessed before is accessed, such as memory page 4, a page fault will occur. At this time, the corresponding data needs to be loaded from the external memory into the physical memory.
[0095] During the execution of the 1st to Mth instructions of the program slice, when the memory page 1 is accessed for the first time, the memory page 2 is accessed for the first time, and the memory page 4 is accessed for the first time, the corresponding data needs to be loaded from the external memory into the physical memory.
[0096] It can be seen that for the first access to memory page 1 and memory page 2, additional memory page fault processing will be generated when running the program slice. The memory access operation during the running of the program slice is different from that during the running of the target program's region of interest.
[0097] Figure 4 Part (b) of FIG. 1 shows the memory status of the test program of the embodiment of the present application when it is running and the memory status of the region of interest of the target program when it is running. The region of interest of the target program and the memory access status during the execution of the instructions before the region of interest are shown in FIG. Figure 4 The same as part (a) of . When the test program of the embodiment of the present application is running, since the memory preheating instruction is run first, the data corresponding to memory page 1 and memory page 2 can be pre-loaded into the physical memory before the execution of the first instruction of the program slice. In this way, during the execution of the 1st to Mth instructions of the program slice, a memory page fault processing is generated only when accessing memory page 4. It can be seen that the access operation to the memory during the operation of the program slice and the operation of the region of interest of the target program are the same.
[0098] Therefore, the embodiments of the present application can improve the consistency of the performance of program slices and the original program (ie, the target program), thereby facilitating improving the accuracy of program performance evaluation or chip performance simulation.
[0099] Figure 5 FIG. 1 is a flow chart of a method for generating a test program provided in an embodiment of the present application. Figure 5 As shown, the method includes the following steps 501-503.
[0100] 501: Obtain a test program, the test program including a memory warm-up instruction set and an instruction stream of an area of interest of a target program, the memory warm-up instruction set including at least one memory warm-up instruction.
[0101] 502: Execute each memory preheating instruction in the memory preheating instruction set to obtain a target memory state.
[0102] The target memory state is the same as the memory state corresponding to the region of interest during the running of the target program. That is, the first memory page during the running of the target program is the same as the second memory page during the running of the test program. The first memory page and the second memory page both refer to the memory pages accessed by the instructions in the region of interest, and the memory pages corresponding to the instructions that generate page faults.
[0103] 503: Execute the instruction stream in the region of interest in the target memory state to obtain a test result.
[0104] Optionally, the test result is a chip performance simulation result, or a program performance evaluation result.
[0105] In actual applications, there may be multiple test programs for a target program, and different test programs correspond to different regions of interest of the target program. Each test program can be run separately to obtain the corresponding test results; then, based on the weights and test results of the regions of interest corresponding to each test program, the performance test results of the entire target program can be obtained.
[0106] Optionally, the weight of the region of interest corresponding to the test program can be set as needed, and this application does not impose any restrictions on this.
[0107] Figure 5 The test method shown can be executed by a computer device, for example, by a chip simulator in the computer device. The embodiment of the present application does not limit the type of chip simulator, which can be a register transfer level (RTL) simulator, a clock-accurate single-core performance simulator, a trace analysis simulator, a processor abstract model or an instruction set function simulator, etc.
[0108] In the embodiment of the present application, the memory warm-up instruction and the register recovery instruction are both additional instructions other than the original program instructions for maintaining the correct execution of the program instruction flow, and may also be referred to as compensation instructions.
[0109] Figure 6 1 is a block diagram of a test program generation device provided in an embodiment of the present application. The device can be implemented as all or part of a computer device through software, hardware, or a combination of both. Figure 6 As shown, the device 600 may include: an obtaining unit 601 , a first generating unit 602 , and a second generating unit 603 .
[0110] Among them, the obtaining unit 601 is used to obtain the memory access related information during the operation of the target program, and the memory access related information includes a first address set and indication information. The first address set includes the memory address accessed by each instruction in the target program's area of interest, and the indication information is used to indicate the memory address corresponding to the instruction that generates the page fault in the first address set. The first generating unit 602 is used to generate a memory preheating instruction set based on the memory access related information. The memory preheating instruction set includes at least one memory preheating instruction, and the at least one memory preheating instruction is used to access the memory address corresponding to at least one target memory page. The at least one target memory page includes the memory pages corresponding to the first address set, except for the memory page to which the memory address indicated by the indication information belongs. The second generating unit 603 is used to generate a test program based on the memory preheating instruction set and the instruction stream of the area of interest.
[0111] Optionally, the obtaining unit 601 includes: an inserting subunit 6011 and an operating subunit 6012. The inserting subunit 6011 is used to insert a target program; the operating subunit 6012 is used to operate the target program after inserting, and obtain memory access related information.
[0112] Optionally, the indication information includes page fault related events, and the page fault related events are used to indicate the memory address corresponding to the instruction that generates the page fault; the execution subunit 6012 is also used to record the page fault related events.
[0113] In a possible implementation, the page fault related event includes a first switching event and a second switching event, the first switching event is an event of switching from a user state to a kernel state, and the second switching event is an event of switching from a kernel state to a user state. The running subunit 6012 is used to record the first switching event and the second switching event according to the change of the exception level of the processor running the target program.
[0114] In another possible implementation, the page fault related event includes a page fault event. The execution subunit 6012 is used to record the page fault event when the address of the currently executed instruction is within the address range indicated by the exception vector table and the value of the register indicating the exception type indicates that the exception type is a page fault.
[0115] Optionally, the first generation unit 602 includes: a determination subunit 6021 and a generation subunit 6022. The determination subunit 6021 is used to determine a first memory page set according to the first address set, the first memory page set including at least one first memory page, and the at least one first memory page is a memory page to which a memory address in the first address set belongs; determine the memory page to which the memory address indicated by the indication information belongs as a second memory page set; and determine the memory page in the complement set of the second memory page set in the second memory page set as a target memory page. The generation subunit 6022 is used to generate a memory preheating instruction set according to the target memory page.
[0116] Optionally, the device further includes: an acquisition unit 604. The acquisition unit 604 is used to acquire a register recovery instruction set, the register recovery instruction set includes at least one register recovery instruction, and the at least one register recovery instruction is used to restore the register state at the beginning of the region of interest. A second generation unit 603 is used to generate a test program according to the memory warm-up instruction set, the register recovery instruction set and the instruction stream of the region of interest.
[0117] It should be noted that the test program generation device provided in the above embodiment only uses the division of the above functional units as an example when generating the test program. In actual applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the device is divided into different functional units to complete all or part of the functions described above. In addition, the test program generation device provided in the above embodiment and the test program generation method embodiment belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.
[0118] Figure 7 is a block diagram of a test device provided in an embodiment of the present application. The device can be implemented as all or part of a computer device through software, hardware, or a combination of both. Figure 7 As shown, the device 700 may include: an obtaining unit 701 and an executing unit 702 .
[0119] The acquisition unit 701 is used to obtain a test program, which includes a memory preheating instruction set and an instruction stream of an area of interest of a target program, wherein the memory preheating instruction set includes at least one memory preheating instruction. The execution unit 702 is used to execute the memory preheating instruction in the memory preheating instruction set to obtain a target memory state; and execute the instruction stream of the area of interest under the target memory state to obtain a test result.
[0120] It should be noted that the test device provided in the above embodiment only uses the division of the above functional units as an example when conducting the test. In actual applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the device is divided into different functional units to complete all or part of the functions described above. In addition, the test device provided in the above embodiment belongs to the same concept as the test method embodiment. The specific implementation process is detailed in the method embodiment and will not be repeated here.
[0121] The descriptions of the processes corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process, please refer to the relevant descriptions of other processes.
[0122] Figure 8 8 is a schematic diagram of the structure of an electronic device 800 provided in an embodiment of the present application. Figure 8 As shown, the electronic device 800 includes at least one processor 801 , a memory 802 , and at least one network interface 803 .
[0123] Optionally, the electronic device 800 is a single physical computer. Alternatively, the electronic device 800 includes multiple physical computers, and at least one processor 801, a memory 802, and at least one network interface 803 of the electronic device 800 are distributed on different physical computers. For example, the electronic device 800 is a cluster computer.
[0124] The processor 801 is, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 801 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.
[0125] The memory 802 is, for example, a read-only memory (ROM) or other static storage device that can store static information and instructions, a random access memory (RAM) or other dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. Optionally, the memory 802 exists independently and is connected to the processor 801 through the internal connection 804. Alternatively, the memory 802 and the processor 801 are optionally integrated together.
[0126] The network interface 803 uses any transceiver-like device for communicating with other devices or communication networks. The network interface 803 includes, for example, at least one of a wired network interface or a wireless network interface. The wired network interface is, for example, an Ethernet interface. The Ethernet interface is, for example, an optical interface, an electrical interface, or a combination thereof. The wireless network interface is, for example, a wireless local area network (WLAN) interface, a cellular network interface, or a combination thereof.
[0127] In some embodiments, the processor 801 includes one or more CPUs, such as Figure 8 CPU0 and CPU1 are shown in the figure.
[0128] In some embodiments, the electronic device 800 optionally includes multiple processors, such as Figure 8 801 and processor 805 are shown in FIG. Each of these processors is, for example, a single-core processor (single-CPU), or a multi-core processor (multi-CPU). The processor here optionally refers to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).
[0129] In some embodiments, the electronic device 800 further includes an internal connection 804. The processor 801, the memory 802, and the at least one network interface 803 are connected via the internal connection 804. The internal connection 804 includes a path to transmit information between the above components. Optionally, the internal connection 804 is a single board or a bus. Optionally, the internal connection 804 is divided into an address bus, a data bus, a control bus, etc.
[0130] In some embodiments, the electronic device 800 further includes an input-output interface 806. The input-output interface 806 is connected to the internal connection 804.
[0131] In some embodiments, the input / output interface 806 is used to connect to an input device to receive commands or data related to the above method embodiments input by a user through an input device, such as the aforementioned code for inserting a target program, etc. The input device includes but is not limited to a keyboard, a touch screen, a microphone, a mouse, or a sensor device, etc.
[0132] Optionally, the processor 801 implements the method in the above embodiment by reading the program code 810 stored in the memory 802, or the processor 801 implements the method in the above embodiment by the program code stored internally. In the case where the processor 801 implements the method in the above embodiment by reading the program code 810 stored in the memory 802, the memory 802 stores the program code for implementing the method provided in the embodiment of the present application.
[0133] For more details on how the processor 801 implements the above functions, please refer to the descriptions in the previous method embodiments, which will not be repeated here.
[0134] In some embodiments, a computer-readable storage medium is also provided, which stores computer instructions. When the computer instructions stored in the computer-readable storage medium are executed by an electronic device, the electronic device executes the test program generation method or testing method provided above.
[0135] In some embodiments, a computer program product is also provided, which includes one or more computer program instructions. When the computer program instructions are loaded and run by a computer, the computer executes the test program generation method or testing method provided in the above method embodiment.
[0136] In some embodiments, a chip is also provided, including a memory and a processor, the memory is used to store computer instructions, and the processor is used to call and run the computer instructions from the memory to execute the test program generation method or testing method provided in the above method embodiment.
[0137] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which this application belongs. The words "first", "second", "third" and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprises" include the elements or objects listed after "include" or "comprises" and their equivalents, and do not exclude other elements or objects. A and / or B means that there are three situations: A; B; and A and B.
[0138] The above is only an embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A method for generating a test program, characterized in that: include: Obtaining memory access related information during the running of the target program, the memory access related information including a first address set and indication information, the first address set including memory addresses accessed by each instruction in the region of interest of the target program, the indication information being used to indicate the memory address corresponding to the instruction generating the page fault in the first address set; Generate a memory preheating instruction set according to the memory access related information, the memory preheating instruction set including at least one memory preheating instruction, the at least one memory preheating instruction being used to access a memory address corresponding to at least one target memory page, the at least one target memory page including memory pages corresponding to the first address set, except for a memory page to which the memory address indicated by the indication information belongs; A test program is generated according to the memory warm-up instruction set and the instruction stream of the region of interest.
2. The method according to claim 1, characterized in that: The obtaining of memory access related information during the running of the target program includes: Instrumenting the target program; The target program after the instrumentation is run to obtain the memory access related information.
3. The method according to claim 2, characterized in that The indication information includes page fault related events; The running of the instrumented target program to obtain the memory access related information includes: The page fault related events are recorded.
4. The method according to claim 3, characterized in that The page fault related events include a first switching event and a second switching event, the first switching event is an event of switching from a user state to a kernel state, and the second switching event is an event of switching from a kernel state to a user state; The recording of the page fault related events includes: The first switching event and the second switching event are recorded according to a change in an exception level of a processor running the target program.
5. The method according to claim 3, characterized in that: The page fault related events include page fault events; The recording of the page fault related events includes: When the address of the currently executed instruction is within the address range indicated by the exception vector table, and the value of the register for indicating the exception type indicates that the exception type is a page fault, the page fault event is recorded.
6. The method according to any one of claims 1 to 5, characterized in that: Generating a memory preheating instruction set according to the memory access related information includes: Determine a first memory page set according to the first address set, where the first memory page set includes at least one first memory page, and the at least one first memory page is a memory page to which a memory address in the first address set belongs; Determine the memory page to which the memory address indicated by the indication information belongs as a second memory page set; Determine a memory page of the second memory page set in a complement of the second memory page set as the target memory page; The memory preheating instruction set is generated according to the target memory page.
7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Acquire a register restoration instruction set, wherein the register restoration instruction set includes at least one register restoration instruction, and the at least one register restoration instruction is used to restore the register state at the beginning of the region of interest; The step of generating a test program according to the memory warm-up instruction set and the instruction stream of the region of interest includes: The test program is generated according to the memory warm-up instruction set, the register recovery instruction set and the program slice of the region of interest.
8. A testing method, characterized in that: include: Obtain a test program, wherein the test program includes a memory warm-up instruction set and an instruction stream of an area of interest of a target program, wherein the memory warm-up instruction set includes at least one memory warm-up instruction; Executing the at least one memory preheating instruction to obtain a target memory state; The instruction stream is executed in the target memory state to obtain a test result.
9. A test program generating device, characterized in that: include: an obtaining unit, configured to obtain memory access related information during the running of a target program, wherein the memory access related information includes a first address set and indication information, wherein the first address set includes a memory address accessed by each instruction in an area of interest of the target program, and the indication information is used to indicate a memory address corresponding to an instruction in the first address set that generates a page fault; A first generating unit is configured to generate a memory preheating instruction set according to the memory access related information, wherein the memory preheating instruction set includes at least one memory preheating instruction, and the at least one memory preheating instruction is used to access a memory address corresponding to at least one target memory page, wherein the at least one target memory page includes memory pages corresponding to the first address set, except for a memory page to which the memory address indicated by the indication information belongs; The second generating unit is used to generate a test program according to the memory warm-up instruction set and the instruction stream of the area of interest.
10. The device according to claim 9, characterized in that The obtaining unit comprises: An instrumentation subunit, used for instrumenting the target program; The running subunit runs the target program after the insertion to obtain the memory access related information.
11. The device according to claim 10, characterized in that The indication information includes page fault related events; The running subunit is further used to record the page fault related events.
12. The device according to claim 11, characterized in that The page fault related events include a first switching event and a second switching event, the first switching event is an event of switching from a user state to a kernel state, and the second switching event is an event of switching from a kernel state to a user state; The running subunit is used to record the first switching event and the second switching event according to the change of the exception level of the processor running the target program.
13. The device according to claim 11, characterized in that The page fault related events include page fault events; The execution subunit is used to record the page fault event when the address of the currently executed instruction is located in the address range indicated by the exception vector table and the value of the register used to indicate the exception type indicates that the exception type is a page fault.
14. The device according to any one of claims 9 to 13, characterized in that The first generating unit comprises: A determination subunit is configured to determine a first memory page set according to the first address set, the first memory page set including at least one first memory page, the at least one first memory page being a memory page to which a memory address in the first address set belongs; determine the memory page to which the memory address indicated by the indication information belongs as a second memory page set; and determine a memory page in a complement set of the second memory page set in the second memory page set as the target memory page; A generating subunit is used to generate the memory preheating instruction set according to the target memory page.
15. The device according to any one of claims 9 to 14, characterized in that Also includes: Get the unit, The acquisition unit is used to acquire a register restoration instruction set, wherein the register restoration instruction set includes at least one register restoration instruction, and the at least one register restoration instruction is used to restore the register state at the beginning of the region of interest; The second generating unit is used to generate the test program according to the memory warm-up instruction set, the register recovery instruction set and the program slice of the area of interest.
16. A testing device, characterized in that: include: An obtaining unit, configured to obtain a test program, wherein the test program includes a memory warm-up instruction set and an instruction stream of an area of interest of a target program, wherein the memory warm-up instruction set includes at least one memory warm-up instruction; The execution unit is used to execute the at least one memory warm-up instruction to obtain a target memory state; and run the instruction stream in the target memory state to obtain a test result.
17. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory is used to store a software program, and the processor runs or executes the software program stored in the memory so that the electronic device implements the method according to any one of claims 1 to 7, or implements the method according to claim 8.
18. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program codes executed by a processor, wherein the program codes include instructions for implementing the method according to any one of claims 1 to 7, or instructions for implementing the method according to claim 8.