Data transmission method and device
By managing the synchronization of DMA descriptors and memory pointers in the multi-port chip local configuration, the problem of data transmission and processing delay in the prior art is solved, improving management real-timeness and reducing the burden of managing servers.
Patent Information
- Application Number
- CN202411577846.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-02-25
AI Technical Summary
In the prior art, when a multi-port chip transmits data to the management server, the delay of data transmission and data processing is large, resulting in a reduction in real-time management.
By managing DMA descriptors locally on a multi-port chip, the management server does not need to participate in the configuration of the DMA descriptors, and synchronizes the DMA descriptors through memory pointers, reducing additional communication to exchange and confirm DMA descriptors, thereby reducing the delay in data transmission and data processing.
It realizes the reduction of latency of data transmission and data processing, improves the real-time management of multi-port chips, and synchronizes DMA descriptors and memory pointers locally, avoiding the additional burden of managing servers.
Smart Images
Figure CN119512997A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission method and device. Background Art
[0002] With the rapid development of science and technology, in order to meet the user's requirements for the rate at which multi-port chips transmit reported data to management servers, the management port of the multi-port chip begins to use PCIe (PCI-Express) to transmit data to the management server, and uses multi-channel DMA (Direct Memory Access) to transmit data to the management server to increase the rate of data transmission.
[0003] The types of data transmitted from the management port of the multi-port chip to the management server are complex, and there are many small packets of data. The data upload method in the current technology is to assemble the small packets of the multi-port chip and transmit them to the management server through DMA technology; further, before the data transmission starts, the management server needs to configure / update the corresponding DMA descriptor, which contains all the information required to realize data transmission through DMA technology.
[0004] It can be seen from this that in the data uploading method in the current technology, the delay of data transmission and data processing is relatively large, which reduces the real-time management of the multi-port chip. Summary of the invention
[0005] Based on the above problems, the present application provides a data transmission method and device to reduce the delay of data transmission and data processing, thereby improving the real-time management of multi-port chips.
[0006] The embodiments of the present application disclose the following technical solutions:
[0007] In a first aspect, the present application discloses a data transmission method, which is applied to a multi-port chip, comprising:
[0008] Based on the reported data, configuring a DMA descriptor of the reported data; wherein the DMA descriptor at least includes: a target address of the reported data, the target address being determined according to a memory unit corresponding to the reported data;
[0009] Based on the DMA descriptor, transmitting the reported data to a memory unit corresponding to the target address in the management server through a corresponding DMA channel;
[0010] When the transmission of the reported data is completed, a message signal interrupt MSI is triggered so that the management server responds to the MSI and reads the reported data from the memory cell array according to the memory pointer.
[0011] Optionally, before transmitting the reported data to a memory unit corresponding to the target address in the management server through a corresponding DMA channel based on the DMA descriptor, the method further includes:
[0012] Generate corresponding packet header information according to the reported data; the packet header information at least includes: the data length of the reported data and the type of the reported data;
[0013] Encapsulating the reported data separately and adding the header information to obtain a data packet corresponding to the reported data;
[0014] The transmitting the reported data to the memory unit corresponding to the target address in the management server through the corresponding DMA channel based on the DMA descriptor includes:
[0015] Based on the DMA descriptor, the corresponding data packet is transmitted to the memory unit corresponding to the target address in the management server through the corresponding DMA channel.
[0016] Optionally, the target address of the reported data is configured in the following manner:
[0017] Based on the reported data, determining a DMA channel corresponding to the reported data;
[0018] Based on the corresponding DMA channel, determining a memory unit corresponding to the DMA channel; the memory unit is pre-allocated by the management server for each DMA channel;
[0019] Based on the memory unit, a target address of the reported data is configured.
[0020] Optionally, the memory unit is allocated in the following manner:
[0021] In response to the power-on startup, the management server enumerates a plurality of logical device units implementing DMA functions in the multi-port chip to determine a corresponding plurality of DMA channels;
[0022] The management server allocates corresponding memory cell arrays based on the multiple DMA channels, and the memory cell array is used to receive reported data transmitted by the multiple DMA channels; the memory cell array includes: independent memory units corresponding one by one to the multiple DMA channels, and the memory units include multiple memory blocks.
[0023] Optionally, after the management server allocates a corresponding memory cell array based on the multiple DMA channels, the method further includes:
[0024] Receiving the information of the memory cell array synchronized by the management server through PCIe ELBI, and storing the information of the memory cell array; the information of the memory cell array includes: a base address of each memory cell, and the number and size of memory blocks in each memory cell;
[0025] The configuring, based on the memory unit, a target address of the reported data includes:
[0026] Based on the information of the memory unit corresponding to the DMA channel in the stored information of the memory unit array, the target address of the reported data is configured.
[0027] Optionally, the message signal interrupt MSI includes an interrupt vector identifier, and the interrupt vector identifier is used to indicate a DMA channel; the management server responds to the MSI and reads the reported data from the memory cell array according to a memory pointer, including:
[0028] The management server obtains an interrupt vector identifier of the MSI in response to the MSI;
[0029] The management server obtains a memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier based on the interrupt vector identifier;
[0030] The management server reads the reported data from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier according to the memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier.
[0031] Optionally, the memory pointer includes a write memory pointer and a read memory pointer; the management server obtains the memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier based on the interrupt vector identifier, including:
[0032] The management server reads the write memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier through the PCIe ELBI based on the interrupt vector identifier;
[0033] The management server obtains, based on the interrupt vector identifier, a read memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier from a local computer;
[0034] The management server reads the reported data from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier according to the memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier, including:
[0035] The management server reads the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier.
[0036] Optionally, before the management server reads the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier, the method further includes:
[0037] The management server determines whether the write memory pointer and the read memory pointer are consistent;
[0038] The step of reading the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier comprises:
[0039] When the management server determines that the write memory pointer and the read memory pointer are inconsistent, the management server reads the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier.
[0040] Optionally, after reading the reported data stored in the memory block between the write memory pointer and the read memory pointer, the method further includes:
[0041] The management server updates the write memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier to the local read memory pointer to release the memory pointer.
[0042] In a second aspect, the present application discloses a data transmission device, comprising:
[0043] A configuration module, configured to configure a DMA descriptor of the reported data based on the reported data; wherein the DMA descriptor at least includes: a target address of the reported data, wherein the target address is determined according to a memory unit corresponding to the reported data;
[0044] A transmission module, configured to transmit the reported data to a memory unit corresponding to the target address in the management server through a corresponding DMA channel based on the DMA descriptor;
[0045] The interrupt module is used to trigger a message signal interrupt MSI when the reported data transmission is completed, so that the management server responds to the MSI and reads the reported data from the memory cell array according to the memory pointer.
[0046] Optionally, the data transmission device further includes:
[0047] The packet header information generating module is used to generate corresponding packet header information according to the reported data; the packet header information at least includes: the data length of the reported data and the type of the reported data;
[0048] The data packet encapsulation module is used to encapsulate the reported data separately and add header information to obtain the data packet corresponding to the reported data;
[0049] The transmission module is specifically used to transmit the corresponding data packet to the memory unit corresponding to the target address in the management server through the corresponding DMA channel based on the DMA descriptor.
[0050] Optionally, the configuration module is specifically used to determine the DMA channel corresponding to the reported data based on the reported data; determine the memory unit corresponding to the DMA channel based on the corresponding DMA channel; the memory unit is pre-allocated by the management server for each DMA channel; and configure the target address of the reported data based on the memory unit.
[0051] Optionally, the data transmission device further includes:
[0052] An information receiving module, used for receiving information of a memory cell array synchronized by a management server through PCIe ELBI, and storing the information of the memory cell array;
[0053] The configuration module is specifically used to configure the target address of the reported data based on the information of the memory unit corresponding to the DMA channel in the information of the stored memory unit array.
[0054] Compared with the prior art, the present application has the following beneficial effects: the multi-port chip locally configures and manages DMA descriptors, the management server does not need to participate in the configuration of DMA descriptors, and the synchronization of DMA descriptors is achieved through memory pointers, and the management server does not need additional communication to exchange and confirm DMA descriptors, thereby reducing the delay of data transmission and data processing, and improving the real-time management of multi-port chips. Furthermore, the multi-port chip itself controls the DMA transmission of reported data, realizes the real-time transmission of small packet data, and further shortens the delay of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0056] Figure 1 A flowchart of a data transmission method provided in an embodiment of the present application;
[0057] Figure 2 A schematic diagram of a process of allocating memory units to a management server provided in an embodiment of the present application;
[0058] Figure 3 A schematic diagram of a process for a management server to read reported data from a memory cell array provided in an embodiment of the present application;
[0059] Figure 4 A schematic diagram of the structure of a data transmission system provided in an embodiment of the present application;
[0060] Figure 5 An interactive schematic diagram of a data transmission method provided in an embodiment of the present application;
[0061] Figure 6 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0062] As described above, in the management architecture of many high-performance multi-port chips, Gigabit or 10 Gigabit Ethernet is used as the communication method of the management port, that is, the data generated by the various ports and components inside the multi-port chip are transmitted to the management server through the Ethernet port, so that the management server can process the data according to the data type, or issue new control instructions, so that an efficient and reliable data interaction channel is formed between the management server and the multi-port chip, ensuring that the multi-port chip can adjust the working mode according to the real-time status and external instructions, maintain or optimize its operating status, thereby meeting the needs of high-performance network applications.
[0063] With the rapid development of science and technology, the number of ports integrated in multi-port chips is increasing, which makes the data that needs to be uploaded by multi-port chips more and more complex; and users have higher and higher requirements for the rate at which multi-port chips transmit data to management servers, that is, the requirements for the delay of management servers processing data are also increasing. In order to meet users' requirements for the rate at which multi-port chips transmit reported data to management servers, the management port of multi-port chips uses the PCIe protocol and uses multi-channel DMA to transmit data to the management server to increase the data transmission rate.
[0064] Among them, DMA (Direct Memory Access) is a data transmission technology that allows data to be directly transferred between system memory and external devices without the direct participation of the central processing unit (CPU), with the purpose of reducing the burden on the CPU and improving the efficiency of data transmission.
[0065] The advantages of a data transmission method provided by the present application are explained below by comparison with the data transmission methods in the current technology.
[0066] The data types of the management ports of multi-port chips are complex, and most of them are small packets. Frequent transmission (upload) of small packets will greatly reduce the effective flow of data transmission, resulting in small packet data transmission blocking, which is generally called "Small Packet Performance Degradation". Therefore, the data transmission method in the current technology is to splice the small packet data of the multi-port chip and transmit it to the management server through DMA technology. During the splicing process, the small packet data transmitted first needs to wait until the splicing is completed before being transmitted to the management server, which increases the delay of data transmission, thereby reducing the real-time management of the multi-port chip.
[0067] And in the current technology, before the data transmission starts, the management server needs to configure or update the corresponding DMA descriptor. The DMA descriptor plays a key role in the DMA operation. It contains all the control information required by the DMA engine for data transmission, such as: source address, destination address, transmission length, transmission direction, and actions after the transmission is completed. The management server (i.e., the remote server) participates in the configuration or update of the DMA descriptor to realize cross-node DMA transmission, which means that in addition to the actual data transmission, additional communication is required to exchange and confirm the DMA descriptor information, so additional packet data transmission will be generated. On the one hand, a single DMA transmission requires multiple DMA descriptor transmissions, generating multiple additional packet data. The processing and queuing of the additional packet data will introduce additional data transmission delay, thereby increasing the data transmission delay and affecting the real-time management of the multi-port chip; on the other hand, the management server participates in the configuration or update of the DMA descriptor, which will increase the burden of the management server and affect the management server's processing of the data transmitted by the multi-port chip, that is, the data processing delay is large.
[0068] Furthermore, due to the large delay in data processing, unrecoverable errors may occur in the management port of the multi-port chip. For example, in order to optimize data transmission efficiency and processing delay, the multi-port chip will use an on-chip buffer to temporarily store data. This method can effectively handle bursty data transmission requests while reducing the pressure of frequent access to the main memory. However, due to the large delay in data processing in current technology, a large amount of data is temporarily stored in the on-chip cache, which may cause the on-chip cache to overflow, resulting in port congestion and data loss. The lost data cannot be retrieved and the error cannot be corrected.
[0069] In summary, in a data transmission method in the current technology, the delay of data transmission and data processing is large, thereby reducing the real-time management of the multi-port chip. Furthermore, due to the large delay of data transmission and data, in serious cases, irreparable errors may be caused.
[0070] The present application provides a data transmission method, including: configuring a DMA descriptor of the reported data based on the reported data; based on the DMA descriptor, transmitting the reported data to the memory unit corresponding to the target address in the management server through the corresponding DMA channel; when the reported data transmission is completed, triggering a message signal interrupt MSI, so that the management server responds to the MSI, and reads the reported data from the memory unit array according to the memory pointer. The present application configures (manages) the DMA descriptor locally through the multi-port chip, and the management server does not need to participate in the configuration of the DMA descriptor, and the synchronization of the DMA descriptor is achieved through the memory pointer. No additional communication is required between the management server and the multi-port chip to exchange and confirm the DMA descriptor, which can reduce the delay of data transmission and data processing. In the present application, the multi-port chip locally configures the DMA descriptor, that is, the multi-port chip itself controls the DMA transmission of the reported data, which realizes the real-time transmission of small packet data, further shortens the delay of data transmission, and thus improves the real-time management of the multi-port chip.
[0071] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0072] Embodiment 1:
[0073] Combine the following Figure 1-Figure 3 , a data transmission method provided in an embodiment of the present application is introduced in detail.
[0074] A data transmission method provided in an embodiment of the present application is applied to a multi-port chip, such as Figure 1 The steps shown include:
[0075] S101. Based on reported data, configure a DMA descriptor of the reported data.
[0076] The reported data is data transmitted from the management port of the multi-port chip to the management server.
[0077] The DMA descriptor at least includes a target address of the reported data, which is determined according to a memory unit corresponding to the reported data. The memory unit corresponding to the reported data is a memory unit pre-allocated when the management server is powered on.
[0078] In one possible implementation, the management port in the multi-port chip uses a PCIe 3.0 × 4 port. The PCIe 3.0 × 4 port provides a bidirectional data transfer rate of up to 32Gbit / s (8GT / s in each direction, 2GT / s per lane), with a total bandwidth of up to 32GB / s (bidirectional), which makes it very suitable for management tasks that require high bandwidth.
[0079] Combine the following Figure 2 , which details how the management server allocates memory units.
[0080] S201. In response to power-on, the management server enumerates multiple logical device units implementing DMA functions in the multi-port chip to determine corresponding multiple DMA channels.
[0081] Among them, enumeration usually refers to the process of a system or device discovering and listing all its subsystems, components or functions.
[0082] Specifically, when the host of the management server is powered on, the management server starts the enumeration function to enumerate multiple logical device units implementing DMA functions in the multi-port chip. It can also be understood that the management server enumerates multiple DMA functions in the multi-port chip in response to the power-on. According to the multiple enumerated logical device units implementing DMA functions, i.e., multiple DMA functions, the corresponding multiple DMA channels are determined.
[0083] In the PCIe architecture, DMA function refers to the DMA capability that can be independently configured and used on a device. In a PCIe device with multi-function characteristics, multiple logical devices and functions can be provided, which may include one or more DMA functions. Each DMA function can be regarded as an independent set of DMA resources on the device, which can be configured and used separately and has its own independent configuration space.
[0084] A DMA channel (DMAChannel) is responsible for an independent data stream, and can be configured to transfer data between a specific source address and a destination address. A DMA channel provides a mechanism to control DMA operations, such as transfer direction, data size, interrupt management, etc.
[0085] The relationship between DMA function and DMA channel: DMA function (i.e., the logical device unit implementing DMA function) may include one or more DMA channels. For example, in a multi-port chip, each DMA function may include a group of DMA channels, each channel can independently perform DMA operations, but multiple channels share the resources and configuration space of a DMA function. For example, a multi-port chip includes two logical device units implementing DMA function (i.e., DMA function), and each logical device unit of DMA function includes two DMA channels, then the corresponding four DMA channels are determined.
[0086] S202: The management server allocates corresponding memory unit arrays based on multiple DMA channels.
[0087] The memory cell array is used to receive reported data transmitted by multiple DMA channels.
[0088] The memory unit array includes independent memory units corresponding to a plurality of DMA channels one by one. The memory units are used to receive the reported data transmitted by the corresponding DMA channels.
[0089] The memory unit includes multiple memory blocks. The length of the reported data transmitted in a single transmission by the DMA channel corresponding to the memory unit cannot exceed the size of a single memory block.
[0090] S203: The management server synchronizes the information of the memory cell array to the multi-port chip through the PCIe external local bus interface.
[0091] The External Local Bus Interface (ELBI) is an interface mechanism in the PCIe architecture, mainly used for communication between the PCIe device memory controller and external application registers.
[0092] The information of the memory cell array includes: the base address of each memory cell, and the number and size of memory blocks in each memory cell.
[0093] The above-mentioned Figure 2 It is introduced that when the management server is started up, corresponding memory units are allocated to multiple DMA channels in a multi-port chip, a memory unit array composed of memory units corresponding to multiple DMA channels is obtained, and the information of the memory unit array is synchronized to the multi-port chip through PCIe ELBI.
[0094] In one possible implementation, since the management server allocates corresponding memory units to multiple DMA channels in advance (at startup), the target address of the reported data can be configured in the following manner: the multi-port chip determines the DMA channel corresponding to the reported data based on the reported data; based on the corresponding DMA channel, determines the memory unit corresponding to the DMA channel; based on the memory unit, configures the target address of the reported data.
[0095] Further, the multi-port chip receives the information of the memory cell array synchronized by the management server through the PCIe external local bus interface, and stores the information of the memory cell array. Then the multi-port chip can configure the target address of the reported data based on the information of the memory cell array stored, and the information of the memory cell corresponding to the DMA channel corresponding to the reported data. Exemplarily, taking the DMA channel corresponding to the reported data as DMA channel 1 as an example, the multi-port chip obtains the information of the memory cell array stored, and the information of the memory cell corresponding to DMA channel 1, including: the base address of memory cell 1 corresponding to DMA channel 1, the number and size of memory blocks, and configures the target address of the reported data.
[0096] S102 . Based on the DMA descriptor, the reported data is transmitted to a memory unit corresponding to the target address in the management server through a corresponding DMA channel.
[0097] Among them, DMA descriptors instruct the DMA controller in the multi-port chip how to read data from one storage location and write it to another storage location without the need for direct intervention from the central processor.
[0098] Specifically, based on the DMA descriptor, the DMA controller in the multi-port chip can be instructed to transmit the reported data to the memory unit corresponding to the target address in the management server through the corresponding DMA channel.
[0099] Furthermore, in a possible implementation, before transmitting the reported data to the memory unit corresponding to the target address in the management server, the method also includes: generating corresponding packet header information based on the reported data; encapsulating the reported data separately, and adding the corresponding packet header information to obtain a data packet corresponding to the reported data; based on the DMA descriptor, transmitting the corresponding data packet to the memory unit corresponding to the target address in the management server through the corresponding DMA channel.
[0100] S103: When the transmission of the reported data is completed, a message signal interrupt MSI is triggered, so that the management server responds to the message signal interrupt and reads the reported data from the memory cell array according to the memory pointer.
[0101] Among them, Message Signaled Interrupts (MSI) is a computer hardware technology used to improve the traditional line-based interrupt (IRQ) processing method. In the traditional interrupt mechanism, the hardware device sends an interrupt request to the processor through the IRQ line, and this request is usually implemented by changing the level state of the IRQ line. MSI is an information-based interrupt. MSI is triggered by the device writing to a specific memory address or I / O port. This writing action contains an interrupt message, which can carry more information about the interrupt source; MSI allows each device to generate and identify interrupts independently without sharing the IRQ line.
[0102] It should be noted that in the embodiment of the present application, the message signal interrupt is directly referred to as MSI. In other possible implementations, the message signal interrupt may also be referred to as MSI interrupt, MSI-type interrupt, etc., and the present application does not make any specific limitations.
[0103] In a possible implementation, the management server pre-registers MSI (Message Signal Interrupt) for DMA, and triggers DMA every time a DMA transfer is completed.
[0104] Furthermore, the message signal interrupt carries an interrupt vector identifier, and the interrupt vector identifier is used to indicate a DMA channel. The management server responds to the message signal interrupt and reads the reported data from the memory unit corresponding to the DMA channel through a memory pointer according to the DMA channel indicated by the interrupt vector identifier.
[0105] For ease of understanding, the following Figure 3 , it is described in detail how the management server responds to the message signal interrupt and reads the reported data from the memory cell array according to the memory pointer.
[0106] S301: The management server responds to the MSI and obtains the interrupt vector identifier of the MSI.
[0107] Among them, in the message signal interrupt mechanism, the interrupt vector identifier is the key information used to determine the entry point of the interrupt service routine (ISR). When the multi-port chip generates / triggers an MSI, it not only sends an interrupt request to the management server, but also attaches an interrupt vector value (i.e., interrupt vector identifier). This interrupt vector value is used to point to a specific interrupt service routine, so that the management server knows which interrupt handler should be called to respond to the interrupt.
[0108] In the embodiment of the present application, the interrupt vector identifier is used to indicate the DMA channel for transmitting the reported data. Exemplarily, the interrupt vector identifier may be a unique identifier of the DMA channel, including: the channel number of the DMA channel.
[0109] S302: The management server obtains a memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier based on the interrupt vector identifier.
[0110] Among them, memory pointers provide the ability to directly operate memory. A pointer is a special variable whose content is a memory address rather than the data value stored in an ordinary variable. Pointers can be used to access and manipulate data at a specific location in memory.
[0111] Specifically, in the embodiment of the present application, the memory pointer refers to the memory block index used for DMA channel data transmission in the memory of the management server. Specifically, the memory pointer includes a write memory pointer (write_ptr) and a read memory pointer (read_ptr). Specifically, the management server obtains the write memory pointer and the read memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier based on the interrupt vector identifier.
[0112] In one possible implementation, the management server reads the write memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier through PCIeELBI based on the interrupt vector identifier; and based on the interrupt vector identifier, obtains the read memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier from the local.
[0113] Specifically, the write memory pointer can be used to indicate the target address (i.e., target memory block) of the reported data. In the embodiment of the present application, the synchronization of the target address of the reported data can be achieved by writing the memory pointer, that is, the synchronization of the DMA descriptor to the management server is achieved by writing the memory pointer.
[0114] Furthermore, the synchronization mechanism of the write memory pointer is implemented by the management server through PCIe ELBI. That is, the management server reads the write memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier through PCIe ELBI, and can access internal resources more efficiently through ELBI, thereby reading the corresponding write memory pointer.
[0115] For ease of understanding, the following describes in detail how to synchronize write memory pointers through PCIe ELBI.
[0116] First, the BAR0 access is mapped to the internal configuration bus: the access to the first register BAR0 of the PCIe EP device integrated in the multi-port chip is mapped to the internal configuration bus of the PCIe EP device. For example, when the management server attempts to access BAR0 (the first register) of the PCIe EP device, it is actually accessing the address space mapped to the internal configuration bus of the PCIe EP device. Among them, BAR0 defines the base address of the PCIe EP device and is the starting point of the device memory space.
[0117] When the address of the accessed internal configuration bus is within a preset range (for example, 700h-800h), the PCIeEP device converts the access request into a PCIe ELBI bus command. This is because a specific address range is usually mapped to the device's internal configuration registers or control logic, and these internal resources can be accessed and controlled more efficiently through ELBI.
[0118] Furthermore, the internal logic of the PCIe EP device further converts the PCIe BLBI bus command into a logical direct line signal, which is directly connected to the corresponding internal components (for example, internal registers). This method bypasses the complex bus arbitration and addressing mechanism and improves the speed and real-time performance of data transmission. The internal logic of the multi-port chip further converts the PCIe ELBI command into a set of direct logical direct signals.
[0119] S303: The management server reads the reported data from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier according to the memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier.
[0120] In one possible implementation, the management server determines whether the write memory pointer and the read memory pointer corresponding to the DMA channel are consistent; when the management server determines that the write memory pointer and the read memory pointer corresponding to the DMA channel are inconsistent, the management server reads the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier; when the management server determines that the memory pointer and the read pointer corresponding to the DMA channel are consistent, it means that no reported data is transmitted to the memory unit array of the management server.
[0121] S304: After reading the reported data, the management server releases the memory pointer.
[0122] Specifically, after reading and processing the reported data, the management server releases the memory pointer through the PCIe ELBI to continue to execute the next DMA data transmission.
[0123] In a possible implementation, after the management server has read and processed the reported data, the management server updates the write memory pointer corresponding to the DMA channel identified by the interrupt indicator to the local read memory pointer, thereby releasing the memory pointer.
[0124] The embodiment of the present application provides a data transmission method, including: configuring a DMA descriptor of the reported data based on the reported data; based on the DMA descriptor, transmitting the reported data to the memory unit corresponding to the target address in the management server through the corresponding DMA channel; when the reported data transmission is completed, triggering a message signal interrupt MSI, so that the management server responds to the MSI, and reads the reported data from the memory unit array according to the memory pointer. In the embodiment of the present application, the multi-port chip locally configures the management DMA descriptor, and the management server does not need to participate in the configuration of the DMA descriptor, and the synchronization of the DMA descriptor is achieved through the memory pointer. The management server does not need additional communication to exchange and confirm the DMA descriptor, thereby reducing the delay of data transmission and data processing, and improving the real-time management of the multi-port chip. Further, in the embodiment of the present application, the multi-port chip itself controls the DMA transmission of the reported data, realizes the real-time transmission of small packet data, and further shortens the delay of data transmission.
[0125] Furthermore, the multi-port chip itself configures DMA descriptors to control multi-channel DMA data transmission, and there is no need for a management server to configure DMA descriptors, thereby reducing the occupancy of additional data traffic on the PCIe channel and increasing the effective bandwidth of PCIe.
[0126] Furthermore, the reported data can be packaged separately and header information can be added so that the header information of the reported data can assist the management server in managing and classifying the reported data. This reduces the overhead caused by the frequent operation of the management server on small packet data, improves the processing efficiency of the management server, and further shortens the delay of data transmission.
[0127] Embodiment 2:
[0128] Combine the following Figure 4 and Figure 5 , a data transmission system provided in an embodiment of the present application is introduced in detail.
[0129] like Figure 4 As shown, a data transmission system provided in an embodiment of the present application includes: a chip logic terminal and a management server. It should be noted that the chip logic is a logical function module implemented by hardware inside a multi-port chip, so the chip logic terminal can actually be understood as a multi-port chip.
[0130] Among them, the management server is integrated with a PCIe RC device. The PCIe RC (Root Complex) device is one of the core components in the PCIe architecture. In the PCIe system, the RC device plays the role of a hub, responsible for managing and controlling the operation of the entire PCIe bus, including key functions such as data transmission, error detection and correction, power management, and configuration space access. The PCIe RC device is usually integrated in the north bridge chip or central processing unit CPU of the system motherboard in the management server, and works closely with the CPU to provide a high-speed, low-latency communication channel for PCIe devices.
[0131] Among them, the PCIe EP device is integrated on the logic end of the chip. PCIe EP (Endpoint) device is one of the core components in the PCIe architecture, usually referring to any peripheral or functional module connected to the PCIe bus. EP devices can be a variety of hardware devices, such as graphics cards, network adapters, storage devices, sound cards, accelerator cards, etc., which communicate with PCIe RC devices through the PCIe interface. And the PCIe EP device on the logic end of the chip includes a DMA controller for controlling multi-channel DMA data transmission.
[0132] In summary, the relationship between PCIe RC devices and PCIe EP devices is that PCIe EP devices are endpoint devices in the PCIe architecture, connected to PCIe RC devices through the PCIe bus, and provide a variety of functions and servers.
[0133] Combine the following Figure 4 , introduce the management server in detail.
[0134] After the management server host is started, it will enumerate and enumerate multiple DMA functions on the chip logic end. Then the application on the PCIe RC device will allocate the corresponding memory cell array for DMA to receive data transmitted by multiple DMA channels. Each DMA channel corresponds to an independent memory unit, and each memory unit contains multiple memories. After the PCIe RC device allocates the memory cell array, the information of the memory cell array is synchronized to the chip logic end through PCIe ELBI.
[0135] Furthermore, the management server registers a message signal interrupt MSI for DMA, and each time a DMA channel completes a data transmission, MSI is triggered. In addition, MSI carries an interrupt vector identifier, which is used to indicate the DMA channel for data transmission.
[0136] When the chip logic end (i.e., multi-port chip) completes the transmission of reported data, it triggers a message signal interrupt MSI. The application in the management server responds to MSI (or receives MSI), reads the corresponding write memory pointer write_ptr according to the DMA indicated by the interrupt vector identifier of MSI, and compares the write memory pointer with the local read memory pointer read_ptr corresponding to the DMA channel. If the write memory pointer and the read memory pointer are inconsistent, read and process the reported data from all memory blocks between the read memory pointer and the write memory pointer. After the reported data is read and processed, update the write memory pointer to the read memory pointer, release the processed memory block, and release the memory pointer.
[0137] Combine the following Figure 4 , let’s take a closer look at the chip logic side.
[0138] The chip logic end includes a multi-function PCIe controller, where function0 is used to implement the function of the PCIeEP device, and the actual number of DMA functions can be set according to actual conditions. After DMA completes data transmission, MSI is triggered, which triggers the MSI controller to send a message signal interrupt.
[0139] The DMA controller in the chip logic end is used to configure the DMA descriptor. Specifically, the DMA controller calculates and configures the target address of the reported data according to the information of the memory cell array in the management server and the DMA channel corresponding to the reported data, thereby obtaining the DMA descriptor.
[0140] Furthermore, the DMA controller at the chip logic end configures the data length of this DMA transfer according to the reported data, generates header information according to the data length and statistical content of the reported data, and encapsulates the reported data separately, adds header information, and starts DMA transfer. When the chip logic end (i.e., multi-port chip) completes the transmission of the reported data, it triggers a message signal interrupt MSI. Specifically, the MSI interrupt controller in the PCIe EP device at the chip logic end sends an information signal interrupt.
[0141] For ease of understanding, the following Figure 5 The data transmission system is introduced in detail, and the overall process of executing data transmission is implemented. Among them, the chip logic end (i.e., multi-port chip) is divided into chip internal logic and DMA controller.
[0142] After the chip logic receives the reported data; the DMA controller configures the DMA descriptor according to the reported data; the DMA controller reads the reported data and starts DMA transmission, and transmits the reported data to the memory unit corresponding to the target address in the management server based on the DMA descriptor; after the DMA controller completes the transmission of the reported data, it sends a message signal interrupt to the management server; the management server responds to the message signal interrupt, reads and processes the reported data according to the memory pointer; after the management server completes reading and processing the reported data, it releases the memory pointer.
[0143] Embodiment three:
[0144] Combine the following Figure 6 , a data transmission device provided in an embodiment of the present application is introduced in detail.
[0145] like Figure 6 As shown, a data transmission device provided in an embodiment of the present application includes the following modules:
[0146] Configuration module 601, configured to configure a DMA descriptor of the reported data based on the reported data; wherein the DMA descriptor at least includes: a target address of the reported data;
[0147] A transmission module 602, configured to transmit the reported data to a memory unit corresponding to a target address in a management server through a corresponding DMA channel based on a DMA descriptor;
[0148] The interrupt module 603 is used to trigger a message signal interrupt MSI when the transmission of the reported data is completed, so that the management server responds to the MSI and reads the reported data from the memory cell array according to the memory pointer.
[0149] In one possible implementation, the data transmission device also includes: a packet header information generation module, which is used to generate corresponding packet header information based on the reported data; the packet header information at least includes: the data length of the reported data and the type of the reported data; a data packet encapsulation module, which is used to encapsulate the reported data separately and add the packet header information to obtain a data packet corresponding to the reported data; a transmission module 602, which is specifically used to transmit the corresponding data packet to the memory unit corresponding to the target address in the management server through the corresponding DMA channel based on the DMA descriptor.
[0150] In one possible implementation, the configuration module 601 is specifically used to determine the DMA channel corresponding to the reported data based on the reported data; determine the memory unit corresponding to the DMA channel based on the corresponding DMA channel; the memory unit is pre-allocated by the management server for each DMA channel; and configure the target address of the reported data based on the memory unit.
[0151] In a possible implementation, the data transmission device also includes: an information receiving module, which is used to receive information about the memory cell array synchronized by the management server through PCIe ELBI, and store the information about the memory cell array; a configuration module 601, which is specifically used to configure the target address of the reported data based on the information about the memory cell corresponding to the DMA channel in the stored information about the memory cell array.
[0152] The embodiment of the present application provides a data transmission device, including: a configuration module 601, which is used to configure the DMA descriptor of the reported data based on the reported data; wherein the DMA descriptor includes at least: the target address of the reported data; a transmission module 602, which is used to transmit the reported data to the memory unit corresponding to the target address in the management server through the corresponding DMA channel based on the DMA descriptor; an interrupt module 603, which is used to trigger the message signal interrupt MSI when the reported data transmission is completed; so that the management server responds to MSI and reads the reported data from the memory unit array according to the memory pointer. The multi-port chip locally configures the management DMA descriptor, and the management server does not need to participate in the configuration of the DMA descriptor, and the synchronization of the DMA descriptor is realized through the memory pointer. The management server does not need additional communication to exchange and confirm the DMA descriptor, thereby reducing the delay of data transmission and data processing, and improving the real-time management of the multi-port chip. Further, the multi-port chip itself controls the DMA transmission of the reported data, realizes the real-time transmission of the small packet data, and further shortens the delay of data transmission.
[0153] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method, system and device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. The method, system and device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0154] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A data transmission method, characterized in that: Applicable to multi-port chips, including: Based on the reported data, configuring a DMA descriptor of the reported data; wherein the DMA descriptor at least includes: a target address of the reported data, the target address being determined according to a memory unit corresponding to the reported data; Based on the DMA descriptor, transmitting the reported data to a memory unit corresponding to the target address in the management server through a corresponding DMA channel; When the transmission of the reported data is completed, a message signal interrupt MSI is triggered so that the management server responds to the MSI and reads the reported data from the memory cell array according to the memory pointer.
2. The method according to claim 1, characterized in that Before transmitting the reported data to the memory unit corresponding to the target address in the management server through the corresponding DMA channel based on the DMA descriptor, the method further includes: Generate corresponding packet header information according to the reported data; the packet header information at least includes: the data length of the reported data and the type of the reported data; Encapsulating the reported data separately and adding the header information to obtain a data packet corresponding to the reported data; The transmitting the reported data to the memory unit corresponding to the target address in the management server through the corresponding DMA channel based on the DMA descriptor includes: Based on the DMA descriptor, the corresponding data packet is transmitted to the memory unit corresponding to the target address in the management server through the corresponding DMA channel.
3. The method according to claim 1, characterized in that The target address of the reported data is configured as follows: Based on the reported data, determining a DMA channel corresponding to the reported data; Based on the corresponding DMA channel, determining a memory unit corresponding to the DMA channel; The memory unit is pre-allocated by the management server for each DMA channel; Based on the memory unit, a target address of the reported data is configured.
4. The method according to claim 3, characterized in that The memory cells are allocated as follows: In response to the power-on startup, the management server enumerates a plurality of logical device units implementing DMA functions in the multi-port chip to determine a corresponding plurality of DMA channels; The management server allocates corresponding memory cell arrays based on the multiple DMA channels, and the memory cell arrays are used to receive the reported data transmitted by the multiple DMA channels; The memory unit array includes: independent memory units corresponding to the multiple DMA channels one by one, and the memory unit includes multiple memory blocks.
5. The method according to claim 4, characterized in that After the management server allocates the corresponding memory cell array based on the multiple DMA channels, the method further includes: Receiving the information of the memory cell array synchronized by the management server through PCIe ELBI, and storing the information of the memory cell array; the information of the memory cell array includes: a base address of each memory cell, and the number and size of memory blocks in each memory cell; The configuring, based on the memory unit, a target address of the reported data includes: Based on the information of the memory unit corresponding to the DMA channel in the stored information of the memory unit array, the target address of the reported data is configured.
6. The method according to claim 4, characterized in that The message signal interrupt MSI includes an interrupt vector identifier, and the interrupt vector identifier is used to indicate a DMA channel; The management server responds to the MSI and reads the reported data from the memory cell array according to the memory pointer, including: The management server obtains an interrupt vector identifier of the MSI in response to the MSI; The management server obtains a memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier based on the interrupt vector identifier; The management server reads the reported data from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier according to the memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier.
7. The method according to claim 6, characterized in that The memory pointer includes a write memory pointer and a read memory pointer; The management server obtains, based on the interrupt vector identifier, a memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier, including: The management server reads the write memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier through the PCIe ELBI based on the interrupt vector identifier; The management server obtains, based on the interrupt vector identifier, a read memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier from a local computer; The management server reads the reported data from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier according to the memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier, including: The management server reads the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier.
8. The method according to claim 7, characterized in that Before the management server reads the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier, the method further includes: The management server determines whether the write memory pointer and the read memory pointer are consistent; The step of reading the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier comprises: When the management server determines that the write memory pointer and the read memory pointer are inconsistent, the management server reads the reported data stored in the memory block between the write memory pointer and the read memory pointer from the memory unit corresponding to the DMA channel indicated by the interrupt vector identifier.
9. The method according to claim 7, characterized in that: After reading the reported data stored in the memory block between the write memory pointer and the read memory pointer, the method further includes: The management server updates the write memory pointer corresponding to the DMA channel indicated by the interrupt vector identifier to the local read memory pointer to release the memory pointer.
10. A data transmission device, characterized in that: include: A configuration module, configured to configure a DMA descriptor of the reported data based on the reported data; wherein the DMA descriptor at least includes: a target address of the reported data, wherein the target address is determined according to a memory unit corresponding to the reported data; A transmission module, configured to transmit the reported data to a memory unit corresponding to the target address in the management server through a corresponding DMA channel based on the DMA descriptor; The interrupt module is used to trigger a message signal interrupt MSI when the reported data transmission is completed, so that the management server responds to the MSI and reads the reported data from the memory cell array according to the memory pointer.