EVTOL flight control system and control method of loosely coupled lockstep architecture

Abstract

The application provides an eVTOL flight control system and a control method of a loosely coupled lockstep architecture, comprising: a processor first core, used for calculating to-be-processed data to obtain a first calculation result; a processor second core, used for calculating to-be-processed data to obtain a second calculation result; and a processor third core, used for comparing the first calculation result and the second calculation result and sending an execution / rollback / reset instruction to the processor first core and the processor second core according to a comparison result. The system adopts a multi-core processor as a flight control calculation core according to the characteristics of an eVTOL model, realizes instruction / monitoring channel functions through the allocation of different cores, realizes an independent instruction / monitoring channel architecture, ensures that flight control instructions have high integrity, and has obvious advantages in terms of light weight, low power consumption and the like, can realize the verification and comparison of the calculation results of different application software, can discover instruction calculation errors in time and prevent fault spreading, and ensures the safety of flight control.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of aircraft technology, in particular to an eVTOL flight control system and control method of a loosely coupled lockstep architecture. BACKGROUND

[0002] The flight control computer is the core equipment of the fly-by-wire flight control system, mainly used for calculating and outputting flight control instructions, and interacting with related systems through interfaces to control the safe and stable flight of the aircraft. For transport category large aircraft, due to the large number of passengers and complex operating environment, the flight control computer needs to be designed to adapt to the harsh working environment and provide high integrity control instructions to achieve a high level of safety. For general unmanned aerial vehicles, the flight control computer mainly realizes general flight control functions, and is more sensitive to cost, weight and other factors, and the safety requirement is relatively low.

[0003] The electric vertical take-off and landing aircraft (eVTOL) is a new type of aircraft that supports vertical take-off and landing and realizes simplified maneuvering flight (SVO), and can be used in various scenarios such as passenger transport and logistics. At the current stage, large eVTOLs are usually designed to carry 2-6 passengers, with a maximum take-off weight of 2-3 tons, and have multiple designs such as multi-rotor, compound wing and tilt-rotor. According to the novel design scheme of eVTOL, new requirements are put forward for the flight control computer. For example: due to the technical bottleneck of battery endurance, the flight control computer should adopt a lightweight design scheme; due to the high safety requirement of eVTOL, the flight control computer should provide high integrity instruction calculation capability; the fly-by-wire flight control needs to control the rudder, tilt mechanism, and provide lift and thrust motor speed instructions, etc., and the flight control computer needs to perform more complex control law calculation and support rich interfaces.

[0004] Therefore, the design scheme of the eVTOL flight control computer needs to consider the technical characteristics of the existing flight control computer, combined with the technical characteristics of eVTOL, to optimize the design scheme to better match the various requirements of eVTOL. SUMMARY

[0005] The technical problem to be solved by the present application is to provide an eVTOL flight control system and control method of a loosely coupled lockstep architecture to meet the requirements of eVTOL aircraft for computing performance, lightweight and comprehensive safety.

[0006] To solve the above technical problems, the technical scheme adopted by the present application is: an eVTOL flight control system of a loosely coupled lockstep architecture, comprising:

[0007] The first core of the processor is used to calculate the to-be-processed data to obtain a first calculation result;

[0008] a second core of the processor, which is lockstep with the first core of the processor, and is configured to calculate the data to be processed to obtain a second calculation result;

[0009] a cache of the processor, configured to store the first calculation result and the second calculation result;

[0010] a third core of the processor, configured to compare the first calculation result and the second calculation result, and send an execution / rollback / reset instruction to the first core of the processor and the second core of the processor according to a comparison result.

[0011] Further, a counter is included, which is configured to add 1 to an error count when the third core of the processor sends the rollback instruction to the first core of the processor and the second core of the processor.

[0012] Further, the third core of the processor is further configured to obtain the error count before sending the rollback instruction to the first core of the processor and the second core of the processor, and determine whether the error count exceeds a preset value, and if yes, send a reset instruction to the first core of the processor and the second core of the processor.

[0013] Further, the third core of the processor is further configured to obtain an operation time before sending the rollback instruction to the first core of the processor and the second core of the processor, and determine whether the operation time exceeds a preset value, and if yes, send a reset instruction to the first core of the processor and the second core of the processor.

[0014] Further, the third core of the processor includes a first register and a second register, the first register is configured to store the first calculation result, and the second register is configured to store the second calculation result.

[0015] The application also relates to an eVTOL flight control method based on a loosely coupled lockstep architecture, which comprises the following steps:

[0016] calculating the data to be processed by the first core of the processor to obtain a first calculation result;

[0017] calculating the data to be processed by the second core of the processor to obtain a second calculation result;

[0018] comparing the first calculation result and the second calculation result by the third core of the processor to obtain a comparison result, and sending an execution / rollback / reset instruction to the first core of the processor and the second core of the processor according to the comparison result.

[0019] Further, in the step of sending the rollback instruction to the first core of the processor and the second core of the processor, the error count is added by 1.

[0020] Further, before the step of sending rollback instructions to the first core and the second core of the processor, further comprising obtaining an error count, and determining whether the error count exceeds a preset value, if yes, sending a reset instruction to the first core and the second core of the processor.

[0021] Further, before the step of sending rollback instructions to the first core and the second core of the processor, further comprising obtaining an operation time, and determining whether the operation time exceeds a preset value, if yes, sending a reset instruction to the first core and the second core of the processor.

[0022] Further, before the step of comparing the first calculation result and the second calculation result by the third core of the processor, further comprising storing the first calculation result in a first register of the third core of the processor, and storing the second calculation result in a second register of the third core of the processor.

[0023] The eVTOL flight control system of the loose coupling lockstep architecture has the advantages that: according to the characteristics of the eVTOL model, the eVTOL flight control system of the loose coupling lockstep architecture is proposed, the system adopts a multi-core processor as the core of flight control calculation, realizes the independent instruction / monitoring channel architecture by allocating different cores to realize the instruction / monitoring channel function, ensures that the flight control instruction has high integrity, and has obvious advantages in light weight, low power consumption and the like, the system can realize the verification and comparison of the calculation results of different application software, can discover the instruction calculation error in time and prevent fault spreading, and ensures the safety of flight control. BRIEF DESCRIPTION OF DRAWINGS

[0024] The specific architecture and implementation process of the present application will be described in detail below with reference to the accompanying drawings:

[0025] Figure 1 It is an architecture diagram of the eVTOL flight control system of the loose coupling lockstep architecture of the present application.

[0026] Figures 2 It is a flowchart of the eVTOL flight control method of the loose coupling lockstep architecture of the present application.

[0027] Figures 3 It is a schematic diagram of one sub-process of the eVTOL flight control method of the loose coupling lockstep architecture of the present application.

[0028] Figures 4 It is a schematic diagram of another sub-process of the eVTOL flight control method of the loose coupling lockstep architecture of the present application.

[0029] Figures 5 It is a structure block diagram of a computer of the present application. DETAILED DESCRIPTION

[0030] In the prior art, the flight control computer of a large transport aircraft needs to calculate a relatively simple control law, and the requirement for computing power is not high, so a single-core processor is usually used, and the flight control computer is too large in size and weight and has too high power consumption, which is not suitable for eVTOL aircraft. Small unmanned aerial vehicles have low safety requirements and are too simple to meet the airworthiness requirements of large eVTOL aircraft.

[0031] Therefore, in order to solve the problem that the flight control computer of a large transport aircraft and a general unmanned aerial vehicle is not suitable for an eVTOL aircraft, the present application provides an eVTOL flight control system with a loosely coupled lockstep architecture. The system uses a multi-core processor as the core of flight control calculation, and realizes the function of the instruction / monitoring channel by allocating different cores, realizes an independent instruction / monitoring channel architecture, ensures the high integrity of flight control instructions, and has obvious advantages in lightweight and low power consumption. This method can check and compare the calculation results of different application software, can discover instruction calculation errors in time and prevent fault propagation, and can ensure the safety of flight control.

[0032] In order to better understand the above technical solutions, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0033] Embodiments

[0034] Please refer to Figure 1 The present embodiment provides an eVTOL flight control system with a loosely coupled lockstep architecture, comprising:

[0035] A first core of a processor is configured to calculate to-be-processed data to obtain a first calculation result.

[0036] A second core of the processor is configured to run in lockstep with the first core of the processor and calculate the to-be-processed data to obtain a second calculation result.

[0037] A processor cache is configured to store the first calculation result and the second calculation result.

[0038] A third core of the processor is configured to compare the first calculation result and the second calculation result, and send an execute / rollback / reset instruction to the first core of the processor and the second core of the processor according to the comparison result.

[0039] In the present embodiment, a multi-core processor can achieve a better balance point among size, weight, power and cost.

[0040] The instruction / monitoring channel architecture of the flight control computer is realized based on different cores in the multi-core processor, which can realize the miniaturization of the device, ensure the independence of the control instruction and the monitoring function, and improve the integrity of the instruction.

[0041] After the system is started, the multi-core processor is initialized, different cores in the multi-core processor are identified by the core ID, the first core of the processor is designated as the instruction core, and the program is guided to load the instruction channel program, so that the first core of the processor runs the instruction calculation program;

[0042] The second core of the processor is designated as the monitoring core, and the program is guided to load the monitoring channel program, so that the second core of the processor runs the monitoring calculation program. The working process of the monitoring core is consistent with that of the instruction core, but the monitoring core is not used for control instruction output.

[0043] The third core of the processor is designated as the check / core core, and the program is guided to load the checker program, so that the third core of the processor runs the checker program. According to different application software requirements and fault handling mechanisms, the check and comparison can be configured in detail to realize the safety control of rollback / reset / disablement.

[0044] That is, the preparation work is completed.

[0045] The first core of the processor serves as the instruction calculation channel, can run the application program of the eVTOL flight control, and realizes the functions of flight control law calculation and control instruction output. The application program includes input processing software, main flight control software, health monitoring and other software modules. Specifically, the input processing software obtains sensor data as to-be-processed data, obtains first calculation results after the first core of the processor calculates, and sends the results to the main flight control software to generate new to-be-processed data if the results are consistent with second calculation results. The new to-be-processed data is calculated again by the first core of the processor to obtain new first calculation results, and the new results are sent to other software modules or corresponding IO interfaces as control instructions to make corresponding devices execute corresponding actions, so as to ensure the integrity of the flight control system function, improve the fault detection coverage rate, and at the same time, avoid the occurrence of incorrect control instructions as much as possible.

[0046] The second core of the processor runs in lockstep with the first core of the processor as a monitoring channel, can run the application program of the eVTOL flight control synchronously with the first core of the processor, realizes flight control law calculation, and does not serve as a control instruction output, but only provides comparison data for the calculation result of the first core of the processor, thereby ensuring the correctness of the calculation of the instruction channel. Specifically, the input processing software obtains sensor data as to-be-processed data, obtains a second calculation result after the second core of the processor calculates, and sends the result to the main flight control software to generate new to-be-processed data if the result is consistent with the first calculation result. After the second core of the processor calculates the new to-be-processed data again, a new second calculation result is obtained, and the first core of the processor sends the new result as a control instruction to other software modules or to a corresponding IO interface to make the corresponding device perform a corresponding action if the new result is consistent with the new first calculation result.

[0047] In the calculation process, the first core of the processor and the second core of the processor are in a loosely coupled physical isolation state, the caches between different cores are independent of each other, and the public resources do not compete for access.

[0048] Through the lockstep running mode, the first core of the processor and the second core of the processor check the result of each step calculation, effectively guarantee the correctness of the calculation result, and thereby realize output of a control instruction with high integrity.

[0049] The third core of the processor serves as a check / verification channel, can check and compare the calculation results of the instruction calculation channel and the monitoring channel, and sends execution / rollback / reset / disable instructions to the first core of the processor and the second core of the processor according to the comparison result, reduces the risk of calculation errors caused by random failures, timely intercepts the incorrect calculation instructions, and prevents fault propagation.

[0050] Specifically, when the third core of the processor judges that the first calculation result and the second calculation result are within the tolerance range, the results are considered consistent, and the first calculation result is output as the current calculation result at this time.

[0051] When the third core of the processor judges that the first calculation result and the second calculation result exceed the tolerance range, the results are considered inconsistent, and the third core of the processor sends a rollback or reset or disable instruction to the first core of the processor and the second core of the processor, so that the first core of the processor and the second core of the processor re-calculate the to-be-processed data, or calculate again after new to-be-processed data is re-acquired.

[0052] Further, the system comprises a counter, which is used to add 1 to the error count when the third core of the processor sends a rollback instruction to the first core of the processor and the second core of the processor.

[0053] The third core of the processor is further configured to acquire an error count before sending the rollback instruction to the first core and the second core of the processor, and determine whether the error count exceeds a preset value, and if so, send a reset instruction to the first core and the second core of the processor.

[0054] Through the function of the error count, it can be avoided that multiple rollback operations cannot obtain correct calculation results, thereby affecting the control of the system on the aircraft. Therefore, after the preset error count is reached, a reset instruction is sent to the first core and the second core of the processor for soft reset, so as to ensure the timeliness of processing the to-be-processed data.

[0055] During the period of sending the rollback instruction to the first core and the second core of the processor, the current calculation result is discarded, and the calculation result of the last period is continuously output.

[0056] During the period of sending the reset instruction to the first core and the second core of the processor, the current to-be-processed data and the current calculation result are discarded, and the calculation result of the last period is continuously output.

[0057] Further, the third core of the processor is further configured to acquire an operation time before sending the rollback instruction to the first core and the second core of the processor, and determine whether the operation time exceeds a preset value, and if so, send a reset instruction to the first core and the second core of the processor.

[0058] The system further comprises a timer, which starts timing when the first core and the second core of the processor acquire the to-be-processed data. Through the timing function, it can be avoided that the first core and the second core of the processor affect the control of the system on the aircraft due to calculation timeout. Therefore, after the preset time is reached, a reset instruction is sent to the first core and the second core of the processor for soft reset, so as to ensure the timeliness of processing the to-be-processed data.

[0059] During the period of sending the reset instruction to the first core and the second core of the processor, the current to-be-processed data and the current calculation result are discarded, and the calculation result of the last period is continuously output.

[0060] Further, the third core of the processor comprises a first register and a second register, the first register is used to store the first calculation result, and the second register is used to store the second calculation result.

[0061] In the initialization stage, the registers of the third core of the processor are divided into the first register and the second register. The first calculation result is stored in the first register, and the second calculation result is stored in the second register, so as to ensure the independence between the first calculation result and the second calculation result, and prevent fault propagation.

[0062] Please refer to Figures 2 to 4 The application also relates to an eVTOL flight control method of a loosely coupled lockstep architecture, comprising:

[0063] The first kernel of the processor calculates the to-be-processed data to obtain a first calculation result;

[0064] The second kernel of the processor calculates the to-be-processed data to obtain a second calculation result;

[0065] The third kernel of the processor compares the first calculation result and the second calculation result to obtain a comparison result, and sends an execution / rollback / reset instruction to the first kernel and the second kernel of the processor according to the comparison result.

[0066] After the system is started, the multi-core processor is initialized, different kernels in the multi-core processor are identified through a kernel ID, the first kernel of the processor is designated as an instruction kernel, and a program is guided to load an instruction channel program, so that the first kernel of the processor runs an instruction calculation program;

[0067] The second kernel of the processor is designated as a monitoring kernel, and a program is guided to load a monitoring channel program, so that the second kernel of the processor runs a monitoring calculation program; the working process of the monitoring kernel is consistent with that of the instruction kernel, but the monitoring kernel does not output control instructions;

[0068] The third kernel of the processor is designated as a checking / kernel kernel, and a program is guided to load a checker program, so that the third kernel of the processor runs the checker program; according to different application software requirements and fault processing mechanisms, the checking and comparison can be configured in detail to realize safety control such as rollback / reset / disablement, and the registers of the third kernel of the processor are divided into first registers and second registers.

[0069] That is, the preparation work is completed.

[0070] The to-be-processed data is input to the first kernel and the second kernel of the processor respectively, and the first kernel and the second kernel of the processor complete the calculation of the to-be-processed data in lockstep; the calculation result of the first kernel is a first calculation result, and the calculation result of the second kernel is a second calculation result. The first calculation result and the second calculation result are stored in the cache of the corresponding kernel, thereby ensuring the independence of the data and avoiding the competition for access to the public resources, so as to effectively guarantee the correctness of the calculation result and reduce the risk of calculation error caused by random failure.

[0071] After the first calculation result and the second calculation result are obtained, the third kernel of the processor stores the first calculation result in the first registers of the third kernel of the processor and stores the second calculation result in the second registers of the third kernel of the processor, checks and compares the first calculation result and the second calculation result to obtain a comparison result.

[0072] When the third core of the processor judges that the first calculation result and the second calculation result are within the tolerance range, it is considered that the results are consistent, at this time the first calculation result is output as the current calculation result;

[0073] When the third core of the processor judges that the first calculation result and the second calculation result exceed the tolerance range, it is considered that the results are inconsistent, at this time the third core of the processor sends a rollback or reset instruction to the first core and the second core of the processor, so that the first core and the second core of the processor recompute the to-be-processed data, or recompute after obtaining new to-be-processed data.

[0074] Further, in the step of sending the rollback instruction to the first core and the second core of the processor, the error count is also incremented by 1.

[0075] Before the step of sending the rollback instruction to the first core and the second core of the processor, the error count is obtained, and it is judged whether the error count exceeds a preset value, if so, a reset instruction is sent to the first core and the second core of the processor.

[0076] In order to avoid multiple rollback operations that cannot obtain correct calculation results, thereby affecting the control of the system on the aircraft, the step of incrementing the error count by 1 is further included, and after reaching a preset error count, a reset instruction is sent to the first core and the second core of the processor for soft reset, to ensure the timeliness of processing the to-be-processed data.

[0077] During the step of sending the rollback instruction to the first core and the second core of the processor, the current calculation result is discarded, and the calculation result of the last period is continuously output;

[0078] During the step of sending the reset instruction to the first core and the second core of the processor, the current to-be-processed data and the current calculation result are discarded, and the calculation result of the last period is continuously output.

[0079] Further, before the step of sending the rollback instruction to the first core and the second core of the processor, the operation time is obtained, and it is judged whether the operation time exceeds a preset value, if so, a reset instruction is sent to the first core and the second core of the processor.

[0080] In order to avoid calculation timeout affecting the control of the system on the aircraft, the step of judging whether the operation time exceeds a preset value is further included, and after reaching a preset time, a reset instruction is sent to the first core and the second core of the processor for soft reset, to ensure the timeliness of processing the to-be-processed data.

[0081] During sending reset instructions to the first core of the processor and the second core of the processor, the current to-be-processed data and the current calculation result are discarded, and the calculation result of the last period is continuously output.

[0082] From the above description, the beneficial effects of the present application are that: for the characteristics of eVTOL models, an eVTOL flight control system with a loosely coupled lockstep architecture is proposed, the system uses a multi-core processor as the core of flight control calculation, realizes the function of instruction / monitoring channel by distributing different cores, realizes an independent instruction / monitoring channel architecture, ensures that the flight control instruction has high integrity, and has obvious advantages in lightweight, low power consumption and the like, the system can realize the verification and comparison of the calculation results of different application software, can discover instruction calculation errors in time and prevent fault propagation, and ensures the safety of flight control.

[0083] Please refer to Figure 5 A computer device, comprising a memory and a processor;

[0084] The memory is configured to store a computer program.

[0085] The processor is configured to execute the computer program and implement the eVTOL flight control method with the loosely coupled lockstep architecture according to any one of claims 6 to 10 when executing the computer program.

[0086] Further comprising an FPGA, an I / O module, a power module and a hardware monitoring module.

[0087] The processor, the FPGA and the I / O module are connected in sequence, the power module is connected with the processor, the FPGA and the I / O module respectively, and the hardware monitoring module is connected with the CPU and the power module respectively.

[0088] The processor preferably adopts a multi-core processor with ARM architecture as a core calculation unit, and the processor is used to realize eVTOL flight control law calculation; the FPGA is used as a data interface expansion unit to realize data forwarding; the I / O module is used to realize data interaction with a crosslinking device; the power module is used to provide secondary power supply for the processor, the FPGA and the I / O module; and the hardware monitoring module is used to monitor the working states of the power supply and the CPU.

[0089] The calculation results generated by the first core of the processor and the second core of the processor are compared and confirmed by calling special software through the third core of the processor, so as to ensure the correctness of instruction calculation. The calculation results of different cores are output through different BANK ports of the FPGA, and are sent to corresponding IO interfaces through different data links, so as to realize the conversion of signals from the data link layer to the physical layer, and then make the corresponding devices perform corresponding actions.

[0090] A computer readable storage medium stores a computer program, which, when executed by a processor, causes the processor to implement the eVTOL flight control method of the loosely coupled lockstep architecture according to any one of claims 6 to 10.

[0091] It is easily understood by those skilled in the art that the above-mentioned embodiments can be freely combined and superimposed without conflict.

[0092] The above only describes the embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An eVTOL flight control system with a loosely coupled lockstep architecture, characterized in that: include: The first core of the processor is used to calculate the data to be processed and obtain a first calculation result; a second core of the processor, running in lockstep with the first core of the processor, and configured to calculate the data to be processed to obtain a second calculation result; a processor cache, configured to store the first calculation result and the second calculation result; The first calculation result and the second calculation result are respectively stored in the cache of the corresponding core to avoid competition for public resources; a third core of the processor, comprising a first register and a second register, wherein the first register is used to store the first calculation result, and the second register is used to store the second calculation result; a third processor core, configured to compare the first calculation result and the second calculation result, and send an execute / rollback / reset instruction to the first processor core and the second processor core according to the comparison result; During the period of sending the rollback instruction to the first processor core and the second processor core, the current calculation result is discarded, while the calculation result of the previous cycle is continuously output; During the period of sending a reset instruction to the first processor core and the second processor core, the current data to be processed and the current calculation result are discarded, and the calculation result of the previous cycle is continuously output; The second core of the processor is used as a monitoring core and is not used for outputting control instructions, but is centrally controlled by the third core of the processor; The FPGA and I / O modules are used to send the outputs of the two cores to the corresponding I / O interfaces through different BANK ports of the FPGA and along different data links, thereby achieving physical isolation of the output links.

2. The control system according to claim 1, characterized in that: A counter is included, and the counter is used to add 1 to an error count when the third processor core sends a rollback instruction to the first processor core and the second processor core.

3. The control system according to claim 2, characterized in that: The third processor core is further configured to obtain an error count before sending a rollback instruction to the first processor core and the second processor core, and determine whether the error count exceeds a preset value, and if so, send a reset instruction to the first processor core and the second processor core.

4. The control system according to claim 2, characterized in that: The third core of the processor is further configured to obtain operation time before sending a rollback instruction to the first core of the processor and the second core of the processor, and determine whether the operation time exceeds a preset value, and if so, send a reset instruction to the first core of the processor and the second core of the processor.

5. An eVTOL flight control method with a loosely coupled lockstep architecture, comprising: Calculating the data to be processed by the first core of the processor to obtain a first calculation result; Calculating the data to be processed by the second core of the processor to obtain a second calculation result; The first calculation result and the second calculation result are respectively stored in the cache of the corresponding core to avoid competition for public resources; storing the first calculation result in a first register of a third core of the processor, and storing the second calculation result in a second register of the third core of the processor; Comparing the first calculation result and the second calculation result by the third core of the processor to obtain a comparison result, and sending an execution / rollback / reset instruction to the first core of the processor and the second core of the processor according to the comparison result; During the period of sending the rollback instruction to the first processor core and the second processor core, the current calculation result is discarded, while the calculation result of the previous cycle is continuously output; During the period of sending a reset instruction to the first processor core and the second processor core, the current data to be processed and the current calculation result are discarded, and the calculation result of the previous cycle is continuously output; The second core of the processor is used as a monitoring core and is not used for outputting control instructions, but is centrally controlled by the third core of the processor; The outputs of the two cores are sent to the corresponding I / O interfaces through different BANK ports of the FPGA and along different data links to achieve physical isolation of the output links.

6. The control method according to claim 5, characterized in that: The step of sending a rollback instruction to the first core of the processor and the second core of the processor further includes adding 1 to an error count.

7. The control method according to claim 6, characterized in that: Before the step of sending the rollback instruction to the first processor core and the second processor core, the method further includes obtaining an error count and determining whether the error count exceeds a preset value, and if so, sending a reset instruction to the first processor core and the second processor core.

8. The control method according to claim 5, characterized in that: Before the step of sending the rollback instruction to the first processor core and the second processor core, the method further includes obtaining the operation time and determining whether the operation time exceeds a preset value. If so, a reset instruction is sent to the first processor core and the second processor core.

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