An isolated communication interface and its data transmission system

Abstract

The present invention discloses an isolated communication interface and its data transmission system, which relates to the field of communication technologies. The isolated communication interface includes: a window comparator, a current-regulated differential driver, data input / output pins, and transmit / receive pins; a mode selection pin sets the working mode for the isolated communication interface; the window comparator is configured to receive data sent by a host through the transmit / receive pins when the isolated communication interface is in slave mode, and send the data sent by the host to a slave through the data input / output pins; the current-regulated differential driver is configured to receive data sent by the host through the data input / output pins when the isolated communication interface is in host mode, and send the data sent by the host to the slave through the transmit / receive pins. The isolated communication interface can transmit and receive data simultaneously.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and particularly to an isolated communication interface and its data transmission system. Background Art

[0002] Currently, there are various physical interface standards related to serial data communication for instruments and control systems. Serial communication is a process of sending one bit of data sequentially at a time through a communication channel or a computer bus. Each interface standard defines electrical and mechanical details to enable devices from different manufacturers to connect and communicate. Among them, an isolated communication interface is an important component used in electronic devices, providing electrical isolation between different circuits, and capable of preventing dangerous direct current or uncontrolled transient currents from flowing between different circuits. When used in conjunction with a battery acquisition chip, it can achieve information acquisition and safety control of a lithium battery new energy system under complex working conditions, having significant advantages in improving the application safety of lithium batteries, and can be fully applied to electric or hybrid vehicles, backup battery systems, energy storage systems, industrial battery packs, etc.

[0003] Taking a battery management system as an example, for a battery management system in which multiple battery modules communicate with each other, serial communication needs to consider the characteristic of current isolation. The series-stacked battery modules operate at different voltage potentials, and current isolation can prevent charge from flowing between both sides of the isolation barrier, while allowing information to pass through the isolation layer. This isolation minimizes the influence of noise, allows a common-mode voltage difference, and prevents ground loops.

[0004] However, the battery management system needs to consider bidirectionality. In some traditional circuits, the isolated communication interface does not support full-duplex operation and cannot send and receive data simultaneously. Summary of the Invention

[0005] Based on this, it is necessary to provide an isolated communication interface and its data transmission system for the above technical problems, and this isolated communication interface can send and receive data simultaneously.

[0006] The present invention adopts the following technical solutions:

[0007] The present invention provides an isolated communication interface, which is connected between two isolation devices. The isolated communication interface includes: a window comparator, a current-regulated differential driver, a data input / output pin, and a transmit / receive pin; the data input / output pin is respectively connected to one end of the window comparator and one end of the current-regulated differential driver, and the other end of the window comparator and the other end of the current-regulated differential driver are both connected to the transmit / receive pin;

[0008] A window comparator for receiving data sent by a host through a transmit / receive pin and sending the data sent by the host to a slave through a data input / output pin when the isolated communication interface is in slave mode;

[0009] A current-regulated differential driver for receiving data sent by a host through a data input / output pin and sending the data sent by the host to a slave through a transmit / receive pin when the isolated communication interface is in host mode.

[0010] Preferably, the isolated communication interface further includes a timing control module, a port encoder / decoder module, and an analog-to-digital conversion module; one end of the analog-to-digital conversion module is connected to a resistor timeout pin, and the other end of the analog-to-digital conversion module is connected to the timing control module; the data input / output pin is connected to the port encoder / decoder module, and the other end of the port encoder / decoder module is respectively connected to one end of the window comparator and one end of the current-regulated differential driver;

[0011] The analog-to-digital conversion module for converting an analog signal sent by the resistor timeout pin into a digital signal and sending it to the timing control module;

[0012] The timing control module for generating a clock signal according to the received digital signal to drive the components in the isolated communication interface to work;

[0013] The port encoder / decoder module for encoding or decoding data.

[0014] Preferably, the isolated communication interface further includes a wake-up detection module and a wake-up pin, one end of the wake-up detection module is connected to the transmit / receive pin, and the other end of the wake-up detection module is connected to the timing control module; the wake-up pin is connected to the timing control module;

[0015] The wake-up pin for limiting the current output / input of the wake-up state of the isolated communication interface;

[0016] If the wake-up detection module does not receive a heartbeat message within a preset time period, a prompt signal is issued.

[0017] Preferably, the isolated communication interface further includes a mode selection pin. When the mode selection pin is connected to the power supply voltage, the isolated communication interface is in host mode. When the mode selection pin is grounded, the isolated communication interface is in slave mode.

[0018] Preferably, the data input / output pin includes a data input pin, a data output pin, a clock input / output pin, and a chip select input / output pin.

[0019] Preferably, the transmit / receive pins include a positive input / output pin and a negative input / output pin; the window comparator is an operational amplifier, the positive input / output pin is connected to the non-inverting input terminal of the operational amplifier, and the negative input / output pin is connected to the inverting input terminal of the operational amplifier.

[0020] The present invention provides a data transmission system, which includes a master serial peripheral interface device, a master isolation communication interface in host mode, a plurality of slave serial peripheral interface devices, and a slave isolation communication interface in slave mode; the master isolation communication interface and the plurality of slave isolation communication interfaces are both the isolation communication interfaces provided above;

[0021] The master isolation communication interface is connected to the master serial peripheral interface device through data input / output pins, the master isolation communication interface is connected to one side of the isolation barrier through transmit / receive pins, the other side of the isolation barrier is respectively connected to the transmit / receive pins of the plurality of slave isolation communication interfaces, and the data input / output pins of the plurality of slave isolation communication interfaces are connected to the corresponding slave serial peripheral interface devices.

[0022] The above at least one technical solution adopted by the present invention can achieve the following beneficial effects:

[0023] In the present invention, by setting a window comparator to receive the data sent by the host when the isolation communication interface is in slave mode and send it to the slave, and by setting a current-regulated differential driver to send data to the slave when the isolation communication interface is in host mode, such an isolation communication interface is set between two isolation devices, which can provide bidirectional isolation communication for each data link. Therefore, this isolation communication interface can achieve simultaneous data sending and receiving. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0025] Figure 1 is a schematic structural diagram of an isolation communication interface provided by the present invention;

[0026] Figure 2 is a schematic structural diagram of another isolation communication interface provided by the present invention;

[0027] Figure 3 is a schematic diagram of the timing specification of +1isoSPI pulses and -1isoSPI pulses provided by the present invention;

[0028] Figure 4 is a schematic structural diagram of 4 isolation communication interfaces configured to communicate with each other provided by the present invention;

[0029] Figure 5 This is a timing diagram of the interaction between the isolated communication interface in host mode and the isolated communication interface in slave mode provided by the present invention;

[0030] Figure 6 This is a schematic diagram of the application structure for low-power battery monitoring when the isolated transceiver provided by the present invention is paired with the BMS.

[0031] Description of the reference numerals:

[0032] 100. Isolated communication interface; 101. Window comparator; 102. Current regulation differential driver; 103. Data input / output pin; 104. Transmit / receive pin;

[0033] 201. Timing control module; 202. Port encoding / decoding module; 203. Analog-to-digital conversion module; 204. Resistance timeout pin; 205. Wake-up detection module; 206. Wake-up pin; 207. Data input pin; 208. Data output pin; 209. Clock input / output pin; 210. Chip select input / output pin; 211. Positive input / output pin; 212. Negative input / output pin; 213. PHAPOL pin; 214. XCVRMD pin; 215. INTR pin; 216. Mode selection pin. Detailed implementation manners

[0034] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] For a battery management system in which multiple battery modules communicate with each other, serial communication needs to consider the characteristics of current isolation. The battery modules in series stack operate at different voltage potentials. Current isolation can prevent the flow of charge between both sides of the isolation barrier while allowing information to pass through the isolation layer. This isolation minimizes the impact of noise, allows a common-mode voltage difference, and prevents ground loops. The battery management system also needs to consider balanced and impedance-matched differential signals. The cable used for the serial communication link can act as a transmission line. If the transmission line is not linked with an appropriate impedance, the communication signal may be reflected back and forth between the transmitter (at one end of the communication link) and the receiver (on the other side of the communication link), thus damaging the communication signal. Therefore, balance, differential, and impedance matching of serial communication are crucial. The battery management system also needs to consider bidirectionality. In some traditional circuits, the isolated communication interface does not support full-duplex operation and cannot send and receive data simultaneously.

[0036] The International Organization for Standardization Serial Peripheral Interface (ISO Serial Peripheral Interface, isoSPI) is a new type of high-speed isolated communication protocol, which has the advantages of long communication distance, fast communication rate, and stable communication. Traditionally, the isolated communication interface has a single mode, cannot meet data communication at multiple rates, has poor compatibility, does not support low-power operation, and has a large power consumption.

[0037] Based on this, the present invention provides an isolated communication interface, which can realize bidirectional transmission of the Serial Peripheral Interface (SPI) bus across an isolation barrier up to 100 meters long. This isolated communication interface supports isolated bidirectional serial data communication up to 2 Mbps and unidirectional serial data transmission up to 4 Mbps, supports pairing with a Battery Management System (BMS), and can also perform battery voltage and sensor detection during Low Power Cell Monitoring (LPCM) in the BMS. This isolated communication interface provides a timeout function, which can wake up or alert the system when no passing heartbeat information is received within the programmed time period. This isolated communication interface implements a completely independent dual transceiver, is compatible with single-channel and dual-channel data communication, has an extremely low idle current, provides a power supply voltage of 3V to 30V for the wake-up function and monitoring function, and is compatible with 12V battery packs.

[0038] The following will describe in detail the technical solutions provided by the embodiments of the present invention with reference to the accompanying drawings.

[0039] In an exemplary embodiment, as Figure 1 shown, Figure 1This is a schematic structural diagram of an isolation communication interface in the present invention. The isolation communication interface 100 includes: a window comparator 101, a current regulation differential driver 102, a data input / output pin 103, and a transmit / receive pin 104; the data input / output pin 103 is respectively connected to one end of the window comparator 101 and one end of the current regulation differential driver 102, and the other end of the window comparator 101 and the other end of the current regulation differential driver 102 are both connected to the transmit / receive pin 104.

[0040] The window comparator is used to receive the data sent by the host through the transmit / receive pin when the isolation communication interface is in the slave mode, and send the data sent by the host to the slave through the data input / output pin; the current regulation differential driver is used to receive the data sent by the host through the data input / output pin when the isolation communication interface is in the host mode, and send the data sent by the host to the slave through the transmit / receive pin.

[0041] The isolation communication interface uses a capacitor or a transformer to convert standard SPI signals (chip select (CS) signal, serial clock (SCK) signal, master out slave in (MOSI) signal, and master in slave out (MISO) signal) into pulses that can be sent back and forth through a twisted pair cable. The current regulation differential driver 102 is a differential driver that realizes the function of current driving to complete receiving the data sent by the host through the data input / output pin when the isolation communication interface is in the host mode, and sending the data sent by the host to the slave through the transmit / receive pin.

[0042] As Figure 2 shown, the isolation communication interface 100 further includes a timing control module 201, a port encoding / decoding module 202, and an analog-to-digital conversion module 203; one end of the analog-to-digital conversion module 203 is connected to a resistance timeout pin 204, and the other end of the analog-to-digital conversion module 203 is connected to the timing control module 201; the data input / output pin 103 is connected to the port encoding / decoding module 202, and the other end of the port encoding / decoding module 202 is respectively connected to one end of a window comparator 105 and one end of the current regulation differential driver 102.

[0043] The isolation communication interface 100 further includes a wake-up detection module 205 and a wake-up pin 206. One end of the wake-up detection module 205 is connected to the transmit / receive pin 104, and the other end of the wake-up detection module 205 is connected to the timing control module 201; the wake-up pin 206 is connected to the timing control module 201.

[0044] Specifically, the analog-to-digital conversion module is used to convert the analog signal sent by the resistor timeout pin into a digital signal and send it to the timing control module; the timing control module is used to generate a clock signal according to the received digital signal to drive the components in the isolation communication interface to work; the port encoding and decoding module is used to encode or decode data. The wake-up pin is used to limit the current output / input for the wake-up state of the isolation communication interface; if the wake-up detection module does not receive the heartbeat information within a preset time period, a prompt signal is issued.

[0045] In addition, the data input / output pin 103 includes a data input pin 207, a data output pin 208, a clock input / output pin 209, and a chip select input / output pin 210; the transmit / receive pin 104 includes a positive input / output pin 211 and a negative input / output pin 212; the window comparator 101 is an operational amplifier, the positive input / output pin 211 is connected to the non-inverting input terminal of the operational amplifier, and the negative input / output pin 212 is connected to the inverting input terminal of the operational amplifier.

[0046] Specifically, the resistor timeout pin is an LPCM resistor timeout pin, which can be called the RTO pin, and the LPCM timeout time is selected through the input resistor; the wake-up pin can be the WAKE pin, which is the current-limiting output / input for the transceiver wake-up state; the data input pin can be the MISO pin, which is the SPI host mode input / slave mode input data pin; the data output pin can be the MOSI pin, which is the host mode output or slave mode output data pin; the clock input / output pin can be the SCK pin, which is the host mode clock input / slave mode clock output pin; the chip select input / output pin can be the CS pin, which is the low-effective SPI chip select input (host mode) / chip select output (slave mode); the positive input / output pin can be the IP pin, which is the isolation communication positive input / output; the negative input / output pin can be the IM pin, which is the isolation communication negative input / output.

[0047] It should be noted that, please continue to refer to Figure 2 , the isolation communication interface further includes a PHAPOL pin 213, an XCVRMD pin 214, and an INTR pin 215; among them, the PHAPOL pin sets the working polarity of the isolation communication interface by detecting the pin input resistor; the XCVRMD pin sets the working mode of the isolation communication interface by detecting the pin input resistor; the INTR pin is the LPCM interrupt current-limiting output. Among them, Figure 2 the I pu and I PD are the pull-up current and the pull-down current respectively, which drive the INTR pin to high level / low level to judge the success / failure of the LPCM mode heartbeat information transmission.

[0048] Among them, the isolated communication interface further includes a mode selection pin 216. The mode selection pin 216 is the SPI mode selection bit. When the mode selection pin is connected to the power supply voltage, the isolated communication interface is in the host mode. When the mode selection pin is grounded, the isolated communication interface is in the slave mode. The mode selection pin can be the Master Mode Select (MSTR) pin.

[0049] The transmitter in the isolated communication interface of the present invention consists of a current-regulated differential driver. The voltage amplitude is determined by the drive current and the equivalent resistive load (cable characteristic impedance and termination resistor RM).

[0050] The receiver in this isolated communication interface has a differential voltage compared with a preset voltage value V RX by a window comparator. When V IP - V IM is greater than V RX , the comparator detects logic 1. V IP is the voltage of the negative input / output pin, and V IM is the voltage of the negative input / output pin. When V IP - V IM is less than V RX , the comparator detects logic -1. Logic 0 indicates that V IP - V IM is between the positive and negative thresholds. The output of the window comparator is sent to a pulse timer (filter) that differentiates short pulses and long pulses. Two identical and independent such isolated communication interfaces can be used as termination devices for a bidirectional isolated SPI system.

[0051] The isolated communication interface of the present invention supports four SPI polarity operating modes configured by the PHAPOL pin. At the same time, it has four operating modes, and the functions can be enhanced through different system configurations. The isolated communication interface is set by connecting to the XCVRMD pin. The specific settings are shown in Table 1 and Table 2. Table 1 is the SPI polarity phase setting, and Table 2 is the SPI operating mode.

[0052] Table 1

[0053]

[0054] Table 2

[0055] Description XCVRMD Pin Connection Standard Bidirectional isoSPI GND Standard Bidirectional isoSPI with LPCM Timeout Monitor Support 20KΩ Resistor to Ground 4Mbps Unidirectional Communication 100KΩ Resistor to Ground 2Mbps, 1Bit Delay Communication VDDS

[0056] Among them, when the XCVRMD pin is connected to the ground wire, the isolated communication interface is set to the standard bidirectional isoSPI. When the transceiver is configured in the host mode, it supports communication at a maximum speed of 2 Mbps. When the XCVRMD pin is connected to the ground wire through a 20 kΩ resistor and the isolated communication interface is configured in the host mode, its behavior is the same as that in the standard bidirectional isoSPI mode. When the isolated communication interface is configured in the slave mode, the LPCM feature is enabled, and communication can be received at a speed of 2 Mbps. The isolated communication interface receives data and decodes it to the SPI port. When the XCVRMD pin is connected to the ground wire through a 100 kΩ resistor, the isolated communication interface supports unidirectional data transmission at a rate of 4 Mbps. When the XCVRMD pin is connected to the power supply, the isolated communication interface is configured in a 2 Mbps rate transmission mode with a 1-bit delay. To achieve a rate of 2 Mbps, the isolated communication interface configured in the slave mode sends back data from the latched edge rather than the non-latched edge of its clock (SCK).

[0057] Among them, the current regulation differential driver 107 provides three logic levels: +VA, 0V, and -VA. To eliminate the DC signal component and improve reliability, the isoSPI pulse is defined as a symmetric pulse pair. The +1 pulse pair is defined as a +VA pulse followed by a -VA pulse. The -1 pulse pair is defined as a -VA pulse followed by a +VA pulse. The duration of each pulse is defined as t 1 / 2PW , (the total isoSPI pulse duration is 2 × t 1 / 2PW ). The isolated communication interface allows two different t 1 / 2PW values, so four types of pulses can be transmitted, which are further divided into CS (long) and data (short) parameters, as Figure 3 shown in the timing specifications of the +1 isoSPI pulse and the -1 isoSPI pulse. As shown in Table 3, Table 3 defines the timing specifications of the +1 isoSPI pulse and the -1 isoSPI pulse.

[0058] Table 3

[0059] Pulse Type First Level Second Level End Level Long +1 <![CDATA[+VA(t 1 / 2PW = 150 ns)]]> <![CDATA[-VA(t 1 / 2PW = 150 ns)]]> 0V Long -1 <![CDATA[-VA(t 1 / 2PW = 150 ns)]]> <![CDATA[+VA(t 1 / 2PW = 150 ns)]]> 0V Short +1 <![CDATA[+VA(t 1 / 2PW = 50 ns)]]> <![CDATA[-VA(t 1 / 2PW = 50 ns)]]> 0V Short +1 <![CDATA[-VA(t 1 / 2PW = 50 ns)]]> <![CDATA[+VA(t 1 / 2PW = 50ns)]]> 0V

[0060] Among them, long pulses are used to transmit CS changes. Short pulses transmit data (MOSI and MISO). The isolated communication interface of the present invention detects 4 communication events from the SPI host: the falling edge of CS, the rising edge of CS, SCK latches MOSI = 0, and SCK latches MOSI = 1. The isolated communication interface of the present invention converts each event into one of the four pulse types, as shown in Table 4.

[0061] Table 4

[0062]

[0063] The isolated communication interface device is used as a bridge between the microcontroller SPI port and the isoSPI port of the BMS monitor in a typical battery management system (BMS). The IP and IM on the isolated communication interface

[0064] (Transmit / Receive pins) are connected to the first BMS monitor in the daisy chain through the isolation barrier.

[0065] In a typical non - battery management system (BMS), two such isolated communication interfaces are used. The first one is paired with a microcontroller or other SPI host. The IP and IM (Transmit / Receive pins) of this isolated communication interface are connected to a second isolated communication interface through the isolation barrier, and the second isolated communication interface generates SPI signals for one or more slave devices.

[0066] Thus, in an exemplary embodiment, the present invention provides a data transmission system, which includes a master serial peripheral interface device, a master isolated communication interface in host mode, a plurality of slave serial peripheral interface devices, and a slave isolated communication interface in slave mode; the master isolated communication interface and the plurality of slave isolated communication interfaces are both the isolated communication interfaces provided above; the master isolated communication interface is connected to the master serial peripheral interface device through data input / output pins, the master isolated communication interface is connected to one side of the isolation barrier through transmit / receive pins, the other side of the isolation barrier is respectively connected to the transmit / receive pins of the plurality of slave isolated communication interfaces, and the data input / output pins of the plurality of slave isolated communication interfaces are connected to the corresponding slave serial peripheral interface devices.

[0067] In one embodiment, as Figure 4 shown, as Figure 4Shown is an example application of four isolated communication interfaces configured to communicate with each other. The isolated communication interfaces 100a, 100b, 100c, and 100d of the present invention communicate with each other in a master / slave mode, where the master SPI device 400 initiates data communication. The isolated communication interface 100a is connected to the master SPI device 400 through four pins: CS, SCK, MISO, and MOSI. The MSTR pin of the isolated communication interface 100a is connected to the power supply voltage and is set to the host mode. CS, SCK, and MOSI are used as inputs, and MISO is used as a push-pull output. The MSTR pins of the isolated communication interfaces 100b, 100c, and 100c are connected to the ground wire and are set to the slave mode. The isolated communication interfaces 100b, 100c, and 100d are respectively connected to the slave SPI devices 401, 402, and 403 through four pins: CS, SCK, MISO, and MOSI. Among them, CS, SCK, and MOSI are used as outputs, and MISO is used as a push-pull input. The master isolated communication interface 100a communicates with the slave isolated communication interfaces 100b, 100c, and 100d through twisted pairs. The twisted pair cables are respectively impedance-matched by the terminal resistors RM. It should be noted that in practical applications, the number of isolated communication interfaces that can be configured to communicate with each other is not limited.

[0068] As Figure 5 shown, Figure 5 is a timing diagram of the interaction between the isolated communication interface in the host mode and the isolated communication interface in the slave mode; the operations when PHA = 0 are described in detail in the figure (and the SCK signal when POL = 0 or 1 is shown), and different SPI modes, i.e., PHA and POL settings, can be used by the host device and the slave device.

[0069] According to Figure 4 the example application of several communication interfaces shown, the master SPI device 400 starts communication by lowering CS. The communication interface 100a converts this signal into a long - 1 pulse on the IP and IM pins. The pulse passes through the isolation barrier (with associated cable delay) and reaches the IP and IM pins of the slave communication interfaces 100b, 100c, and 100d. After verification, the long - 1 pulse is converted into a falling edge of CS for the slave SPI devices 401, 402, and 403.

[0070] Before the master SPI device 400 provides the first latched clock edge, the slave communication interfaces 100b, 100c, and 100d must transmit the initial slave data as SN. The value of SN is determined by sampling the state of MISO. If MISO = 0, the slave communication interfaces 100b, 100c, and 100d send a short pulse - 1 to the master communication interface 100a. The master communication interface 100a receives and decodes the pulse and sets the master MISO = 0 (matching the slave side).

[0071] If MISO = 1 for communication interfaces 100b, 100c, and 100d, no pulses are sent from communication interfaces 100b, 100c, and 100d. The master communication interface 100a interprets this empty response as 1 and sets host MISO = 1. This behavior makes it possible to connect multiple slave communication interfaces to a cable without conflicting signals.

[0072] After the falling edge of CS, each latch clock edge on the master communication interface 100a converts the state of the MOSI pin into an isoSPI data pulse (M N , M N-1 , …, M0), while latching the data bits of the slave communication interface. When the slave communication interface receives each data bit, it sets the slave MOSI pin to the appropriate state and then generates an SCK pulse (either as a short - 1 pulse or as an empty) before returning the MISO data from the slave side.

[0073] At the end of the communication, the final data bit (either as a pulse or an empty) sent by the slave communication interface is ignored by the master communication interface. (The slave communication interface must return a data bit because it cannot predict when the communication will stop.) Then, the master SPI device 300 can raise CS, and CS is transmitted to the slave communication interface in the form of a +1 long pulse.

[0074] As Figure 6 shown is a schematic diagram of the application structure for low - power battery monitoring when the isolated transceiver of the present invention is paired with a BMS. Among them, when the microcontroller 600 communicates with BMS devices 601_1 to 601_n through the isolated communication interface 100, it drives the MSTR pin high. When performing LPCM operations, the microcontroller 600 first configures the battery monitor for LPCM operations and then drives the MSTR pin low to activate the timeout monitor function of the isolated communication interface 100. The INTR pin of the isolated communication interface 100 is connected to the microcontroller for interrupting the current - limiting output. Its XCVRMD pin is connected to the ground through a 20kΩ resistor, and the RTO pin sets the timeout period for the timeout monitor.

[0075] When the isolated communication interface 100 is configured for low-power battery detection (LPCM), its INTR pin is asserted high. The isolated communication interface 100 assumes that there may be a fault in the system in its initial state before the first heartbeat message has fully propagated through the daisy chain. This transition of the INTR pin from low to high also serves as an indication that the microcontroller 600 timeout monitoring function has been activated. At this time, the INTR pin of the communication isolation interface 100 remains high until a passing heartbeat message is received from the BMS devices 601_1 to 601_n, at which point the INTR pin is set low, after which the internal timer is reset to 0. If a passing heartbeat message is received, the INTR pin remains low and the internal timer is reset again. If a failed heartbeat message is received, the INTR pin is set high to issue an alarm.

[0076] In summary, the isolated communication interface proposed by the present invention links two isolated devices through a single twisted pair, provides bidirectional isolated serial port interface (isoSPI) communication for each data link, can achieve isolation of hundreds of volts, uses a matched current to drive differential signals, eliminates the requirement for a center tap of the transformer, reduces electromagnetic interference, has extremely low radiation and idle current, has high compatibility, and has broad application prospects.

[0077] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded by the present invention.

Claims

1. An isolated communication interface is connected between two isolated devices, characterized in that, The isolation communication interface includes: a window comparator, a current-regulated differential driver, data input / output pins, and transmit / receive pins; the data input / output pins are respectively connected to one end of the window comparator and one end of the current-regulated differential driver, and the other end of the window comparator and the other end of the current-regulated differential driver are both connected to the transmit / receive pins; The window comparator is configured to receive data sent by the host through the transmit / receive pins when the isolation communication interface is in the slave mode, and send the data sent by the host to the slave through the data input / output pins; The current-regulated differential driver is configured to receive data sent by the host through the data input / output pins when the isolation communication interface is in the host mode, and send the data sent by the host to the slave through the transmit / receive pins; The isolation communication interface further includes a timing control module, a port encoder / decoder module, and an analog-to-digital conversion module; one end of the analog-to-digital conversion module is connected to a resistance timeout pin, and the other end of the analog-to-digital conversion module is connected to the timing control module; the data input / output pins are connected to the port encoder / decoder module, and the other end of the port encoder / decoder module is respectively connected to one end of the window comparator and one end of the current-regulated differential driver; The analog-to-digital conversion module is configured to convert the analog signal sent by the resistance timeout pin into a digital signal and send it to the timing control module; The timing control module is configured to generate a clock signal according to the received digital signal to drive the components in the isolation communication interface to work; The port encoder / decoder module is configured to encode or decode data.

2. The isolated communication interface according to claim 1, wherein The isolation communication interface further includes a wake-up detection module and a wake-up pin, one end of the wake-up detection module is connected to the transmit / receive pins, and the other end of the wake-up detection module is connected to the timing control module; the wake-up pin is connected to the timing control module; If the wake-up detection module does not receive heartbeat information within a preset time period, a prompt signal is issued.

3. The isolated communication interface according to claim 1, characterized in that, The isolation communication interface further includes a mode selection pin. When the mode selection pin is connected to the power supply voltage, the isolation communication interface is in the host mode. When the mode selection pin is grounded, the isolation communication interface is in the slave mode.

4. The isolated communication interface according to claim 1, wherein The data input / output pins include a data input pin, a data output pin, a clock input / output pin, and a chip select input / output pin.

5. The isolated communication interface according to claim 1, wherein The transmit / receive pins include a positive input / output pin and a negative input / output pin; the window comparator is an operational amplifier, the positive input / output pin is connected to the non-inverting input terminal of the operational amplifier, and the negative input / output pin is connected to the inverting input terminal of the operational amplifier.

6. A data transmission system, characterized in that, The system includes a main serial peripheral interface device, a main isolation communication interface in the host mode, a plurality of slave serial peripheral interface devices, and a slave isolation communication interface in the slave mode; The main isolation communication interface and the plurality of slave isolation communication interfaces are both the isolation communication interfaces according to any one of claims 1-5; The main isolation communication interface is connected to the main serial peripheral interface device through data input / output pins. The main isolation communication interface is connected to one side of the isolation barrier through transmit / receive pins. The other side of the isolation barrier is respectively connected to the transmit / receive pins of the multiple slave isolation communication interfaces. The data input / output pins of the multiple slave isolation communication interfaces are connected to corresponding slave serial peripheral interface devices.

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