Information processing method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention relates to an information processing method and device, electronic equipment and a computer readable storage medium. The information processing method comprises the following steps: determining a routing path between each of at least part of request nodes included in the processor system and each of at least part of response nodes included in the processor system according to on-chip layout information of an on-chip system included in the processor system and a routing algorithm; and determining delay information of each of at least part of response nodes and at least part of request nodes according to the performance parameters of the nodes related to the routing path. According to the method, the path from the request node to the response node can be determined according to the layout information and the routing algorithm, the communication delay is determined based on the path, and compared with related technologies, the delay calculation efficiency can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an information processing method and apparatus, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the development of computer technology, all walks of life have put forward higher and higher demands on the computing power of computer systems. For example, various AI businesses and various ecological simulations all require more computing power and computing resources.

[0003] When the computing power of a single processor is certain, the computing power and computing throughput of the computer system can be improved through parallel computing. Based on this, the application of system-on-chip (SoC) that integrates multiple processor cores on a single chip is becoming more and more widespread. It is also possible to build a processor system based on the SoC to further improve the computing power of the system. In the design process of the SoC, communication delay is one of the important factors that need to be considered. Summary of the invention

[0004] At least one embodiment of the present disclosure provides an information processing method, the method comprising: determining a routing path between each of at least some of the request nodes included in the processor system and each of at least some of the response nodes included in the processor system based on on-chip layout information of the on-chip system included in the processor system and a routing algorithm; and determining delay information of each of at least some of the response nodes in response to each of at least some of the request nodes based on performance parameters of the nodes involved in the routing path.

[0005] At least one embodiment of the present disclosure provides an information processing device, which includes: a path determination module, configured to determine a routing path between each of at least some of the request nodes included in the processor system and each of at least some of the response nodes included in the processor system based on on-chip layout information of the system-on-chip included in the processor system and a routing algorithm; and a delay determination module, configured to determine delay information of each of at least some of the response nodes in response to each of at least some of the request nodes based on performance parameters of the nodes involved in the routing path.

[0006] At least one embodiment of the present disclosure provides an electronic device, including a processor; and a memory, including one or more computer program instructions; wherein the one or more computer program instructions, when executed by the processor, execute the information processing method provided by any embodiment of the present disclosure.

[0007] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the information processing method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0009] Figure 1 A diagram schematically showing an application scenario of an information processing method and device according to at least one embodiment of the present disclosure;

[0010] Figure 2 A flowchart schematically shows an information processing method according to an embodiment of the present disclosure;

[0011] Figure 3 A flowchart schematically shows an information processing method according to another embodiment of the present disclosure;

[0012] Figure 4A A schematic diagram schematically illustrates the principle of optimizing on-chip layout information according to at least one embodiment of the present disclosure;

[0013] Figure 4B A schematic diagram schematically shows on-chip layout information of a system on chip according to an embodiment of the present disclosure;

[0014] Figure 4C A schematic diagram schematically shows on-chip layout information of a system on chip according to another embodiment of the present disclosure;

[0015] Figure 5 A schematic diagram showing the structure of a processor system according to an embodiment of the present disclosure is shown;

[0016] Figure 6 A schematic diagram schematically shows the structure of a processor system according to another embodiment of the present disclosure;

[0017] Figure 7 A schematic diagram schematically illustrates a principle diagram of constructing a topology diagram of a processor system according to at least one embodiment of the present disclosure;

[0018] Figure 8 A schematic diagram schematically illustrates a principle of determining delay information according to at least one embodiment of the present disclosure;

[0019] Fig. 9 The following schematically shows the implementation principle diagram of the information processing method of at least one embodiment of the present disclosure;

[0020] Fig.10 A block diagram schematically shows a structure of an information processing device according to at least one embodiment of the present disclosure;

[0021] Fig.11 A schematic block diagram schematically illustrates an electronic device according to at least one embodiment of the present disclosure; and

[0022] Fig.12 A schematic diagram schematically illustrates a computer-readable storage medium according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] The following is a description of the abbreviations and key terms involved in this disclosure:

[0026] SoC: System-on-Chip, also known as system on chip. In a narrow sense, SoC is obtained by integrating the key components of the system on a chip. In a broad sense, SoC is a micro system that integrates the processor, memory, communication interface and routing node on a chip.

[0027] NoC: Network on Chip, is a communication method of SoC and a major component of multi-core technology. NoC brings a new on-chip communication method that significantly outperforms the performance of traditional bus-based communication. The operation of NoC is based on the transmission of messages by interconnecting routing nodes (Router) in a certain topology.

[0028] UMA architecture: Uniform Memory Access architecture. In the UMA architecture, all processors share a unified physical memory, and all processors access the physical memory at basically the same time. Each processor can have its own private cache, and all peripherals have exactly the same access capabilities to the memory.

[0029] NUMA architecture: Non Uniform Memory Access architecture. In NUMA architecture, memory is no longer centralized for equal access by all processors, and each processor takes a different amount of time to access memory.

[0030] CPU core: Processor core. If the packaging and auxiliary circuits in the traditional CPU chip are excluded and only the core circuit that completes the control and information processing functions is retained, then the core circuit can constitute the CPU core. The CPU core is basically a completely independent processing unit that can read instructions from the internal memory and perform the control and computing tasks specified by the instructions. A single-core CPU includes a single CPU core, and a multi-core CPU includes multiple CPU cores.

[0031] Delay unit: It is equivalent to a register slice and is set up to improve the timing path. Its main function is to temporarily store data for a period of time, thereby introducing a delay of one or more clock cycles.

[0032] Chiplet: A miniaturized, function-specific chip that can be manufactured and designed independently, and multiple chiplets can be stacked and packaged and integrated together to form a more powerful chip. Chiplets can be processor cores, memory chips, sensors, or other types of integrated circuits. Chiplets are connected to each other through high-speed interfaces or connectors to form a complete system chip.

[0033] Skt: Socket, a processing unit is formed by packaging at least one core particle together. The processing unit can be understood as a Socket or a complete packaged chip on a slot.

[0034] Processor system: One or more Skts can constitute a processor system.

[0035] DRAM: Dynamic Random Access Memory.

[0036] Master: The initiator of the communication request in the system on chip, which can be understood as the requesting node, mainly the processor core.

[0037] Slave: The receiver of the communication request in the system on chip, which can be understood as the responding node that responds to the communication request, mainly a memory, and the memory can be, for example, a DRAM.

[0038] Multi-core processors can be interconnected, communicate between cores, and access memory (such as DRAM) through NoC. For example, when the number of processor cores included in the processor system is large, the delay overhead of communication between the host (such as the processor core) and the slave (such as DRAM) at different locations on the processor system is different. For example, in the stage of designing the system on chip, every time the position of the node in the system on chip changes, the delay performance of the entire NoC needs to be re-evaluated. However, under the MUMA architecture, since different processor cores and DRAM belong to different nodes, the delay evaluation between the host and the slave becomes more complicated. Furthermore, since the communication frequencies of different modules in the system on chip are different, the distances between modules are not necessarily the same, which further increases the difficulty of delay evaluation.

[0039] For example, in the UMA architecture, the communication delay between the host and the slave is calculated by manually counting the number of routing nodes set on the communication path between the host and the slave using a table or text, or by simulating using a performance simulator. However, in the NUMA architecture, the communication path is asymmetric, and there are a large number of hosts and slaves. Using the above method to calculate the communication delay requires a lot of time and the calculation efficiency of the communication delay is low.

[0040] At least one embodiment of the present disclosure provides an information processing method and device, an electronic device, and a computer-readable storage medium. Figure 1 The application scenarios of the information processing method and device provided by the present disclosure are described in detail.

[0041] Figure 1 The application scenario diagram of the information processing method and device according to at least one embodiment of the present disclosure is schematically shown.

[0042] like Figure 1 As shown, the application scenario 100 of this embodiment includes a user 101 and an electronic device 102 , and the electronic device 102 can provide an interactive interface for the user 101 .

[0043] The electronic device 102 may be, for example, a smart phone, a tablet computer, a laptop, a desktop, or a server, which has processing functions and can provide an interactive interface. The user 101 may input information through the interactive interface, and the electronic device 102 may process the input information and output the processing results for the user 101 to view.

[0044] In one embodiment, various client applications such as drawing applications and instant messaging applications may be installed in the electronic device 102. For example, in the process of designing the system on chip, the user may provide preliminary on-chip layout information of the system on chip by using a drawing application. The electronic device 102 may calculate the delay information 103 for communication between the host and the slave in the system on chip or the processor system including the system on chip based on the preliminary on-chip layout information, and output the delay information 103 for user reference.

[0045] In one embodiment, the preliminary on-chip layout information of the system on chip can be adjusted based on the delay information 103. The adjustment can be made by a user or automatically by an electronic device, thereby optimizing the on-chip layout information of the system on chip and obtaining the optimized on-chip layout information. Through at least one optimization, the design of the system on chip can be completed and a designed system on chip 104 can be obtained.

[0046] Chips and the like obtained based on the designed system-on-chip 104 are assembled and packaged, for example, a processor system can be obtained, and the processor system can be assembled into a server 105 with a hard disk, a motherboard, a power supply, an I / O expansion card, etc.

[0047] In one embodiment, the server may be a single-way server with a single CPU, or a multi-way server with at least two CPUs. The processor with the one or at least two CPUs constitutes a processor system.

[0048] It can be understood that the information processing method provided by the embodiment of the present disclosure can be executed by the electronic device 102 , and accordingly, the information processing device provided by the present disclosure can be set in the electronic device 102 . Figure 1 The structures of the electronic device 102 and the server 105 are only used as examples to facilitate understanding of the present disclosure, and the present disclosure does not limit this.

[0049] The following will be combined Figure 2 to Figure 9 The information processing method provided by the present disclosure is described in detail.

[0050] Figure 2 The flowchart of the information processing method according to at least one embodiment of the present disclosure is schematically shown.

[0051] like Figure 2 As shown, the information processing method of the embodiment 200 includes operations S201 to S202.

[0052] Operation S201 : determining a routing path between each of at least a portion of request nodes included in the processor system and each of at least a portion of response nodes included in the processor system according to on-chip layout information of the on-chip system included in the processor system and a routing algorithm.

[0053] Operation S202: Determine, according to performance parameters of nodes involved in a routing path, delay information of each of at least some of the responding nodes responding to each of at least some of the requesting nodes.

[0054] The processor system may include one or at least two systems on chip. The on-chip layout information may include, for example, the location information of each module in the system on chip. The modules in the system on chip may include a request node for sending a request, a request node for receiving a request, an on-chip interconnect (e.g., a routing network of a NOC), etc. The routing network of the on-chip interconnect includes a plurality of routing nodes for forwarding requests. Different systems on chip are connected via inter-chip interconnect communication.

[0055] Exemplarily, the on-chip layout information of the system on chip can be obtained by drawing using a drawing tool based on the number of processor cores, the number of memories, the area of ​​the system on chip, and other information included in the system on chip. The drawing tool may be, for example, a drawing tool that supports XML format, or a drawing tool that supports other formats, and the embodiments of the present disclosure are not limited to this. The on-chip layout information can be reflected by a drawing that can represent the placement of each node in the system on chip. In the drawing, each node in the system on chip has an independent number, and the placement position can be reflected by the position coordinates of the node in the system on chip. The memory may be a DRAM, for example, a double data rate synchronous dynamic random access memory (Double Data Rate, DDR), etc. may be used, and the present disclosure is not limited to this.

[0056] Exemplarily, the on-chip layout information of the system on chip may also be obtained by inputting the position information of each node in the system on chip.

[0057] The routing algorithm of the routing network may include any one of the shortest path algorithm and the distance vector algorithm, etc. The routing algorithm may be selected according to actual needs, and the present disclosure does not limit this. The shortest path algorithm may, for example, use the Dijkstra algorithm to determine the routing path between the request node and the response node. For example, when determining the routing path between the request node and the response node, the request node may be used as the source node and the response node may be used as the destination node. The routing path determined by the routing algorithm may, for example, be a communication path with the shortest communication delay between the request node and the response node.

[0058] Exemplarily, the requesting node may be a processor core that sends a request, or a communication interface (such as an I / O interface) that sends a request. The responding node may be a communication interface (such as an I / O interface) that receives a request, or a memory (such as a DRAM, etc.).

[0059] In the case where the processor system includes one system on chip, the determined routing path may be a communication path between a requesting node and a responding node in the same system on chip. In the case where the processor system includes at least two systems on chip, the determined routing path may be a communication path between a requesting node and a responding node in the same system on chip, or may be a communication path between a requesting node in one system on chip and a responding node in another system on chip.

[0060] Exemplarily, at least some of the request nodes can be selected from all the request nodes included in the processor system, and at least some of the response nodes can be selected from all the response nodes included in the processor system according to the actual performance requirements. Subsequently, the routing path between each selected request node and each selected response node is determined. For example, if the actual performance requirement is that the average delay of the processor core in the system-on-chip accessing the memory is minimized, the processor core can be selected from the system-on-chip as at least some of the request nodes, and the memory can be selected from the same system-on-chip as at least some of the response nodes. For example, if the actual performance requirement is that the average delay of the request sent by the processor core in the system-on-chip to the I / O interface is minimized, the processor core can be selected from the system-on-chip as at least some of the request nodes, and the I / O interface can be selected from the same system-on-chip as at least some of the response nodes.

[0061] It is understandable that the same node in the system on chip can act as a request node in some scenarios and as a response node in other scenarios.

[0062] The performance parameters of the nodes involved in the routing path may include, for example, the processing frequency of the node, the number of beats required for the node to receive or forward a request, etc. The number of beats is the number of clock ticks (OSTicks) required. The clock tick is the smallest unit of time in the operating system, which is used by the operating system to process all time-related events, such as thread delays and timer timeouts. The performance parameters of the node can be obtained through pre-configuration.

[0063] For example, based on the performance parameters, the time required for each node involved in the routing path to receive and forward the request sent by the requesting node and the time required for two adjacent nodes to transmit the request sent by the requesting node can be determined. By accumulating all the time durations, a delay value represented by the delay duration can be obtained, and the delay value can be used as delay information.

[0064] Exemplarily, the performance parameters of the nodes involved in the routing path may also include the communication frequency for communicating between the nodes and the adjacent nodes. In this embodiment, the time required for the request sent by the transmission request node between adjacent nodes can be determined based on the communication frequency, and the calculated time required for all adjacent nodes to transmit the request is accumulated to obtain the delay information. In the stage of optimizing the on-chip layout information of the system-on-chip, when determining the delay information, it can be selected whether to ignore the time required for the node to receive and forward the request according to actual needs, and the present disclosure does not limit this. The scenario of choosing to ignore the time required for the node to receive and forward the request can be, for example, a scenario of only adjusting the position of the node in the system-on-chip, etc., and the present disclosure does not limit this.

[0065] The method of at least one embodiment of the present disclosure determines the routing path between the request node and the response node according to the on-chip layout information and the routing algorithm of the system on chip when determining the delay information. Since there is no need to manually select the routing path, and the delay information can be automatically calculated based on the determined routing path and the performance parameters of the nodes involved in the routing path, the efficiency of determining the delay information can be effectively improved. In the scenario of designing the system on chip, the design efficiency of the system on chip can be effectively improved.

[0066] In one embodiment, the routing path between each of all request nodes and each of all response nodes in the processor system can be determined, and based on each determined routing path, the delay information of each response node in response to each request node can be determined. All delay information can, for example, constitute a delay information matrix. In an actual scenario, the delay information of actual concern can be selected from the delay information matrix according to actual needs. By determining the delay information of each response node in response to each request node, the delay information obtained can be used for a variety of scenarios, achieving the effect of calculating multiple scenarios at one time. For example, a variety of scenarios may include scenarios for evaluating intra-chip communication delays and scenarios for evaluating inter-chip communication delays, etc., which are not limited in the present disclosure. Among them, inter-chip communication delay may refer to the communication delay between two systems on chip in at least two systems on chip included in the processor system.

[0067] In the scenario of designing a system on chip, the embodiments of the present disclosure can adjust the on-chip layout information of the system on chip based on the determined delay information, in order to reduce the access delay in the system.

[0068] Figure 3 The flowchart of the information processing method of another embodiment of the present disclosure is schematically shown. Figure 3 This embodiment is described in detail.

[0069] like Figure 3 As shown, in this embodiment 300, the information processing method may include operations S301 to S304.

[0070] Operation S301 : determining a routing path between each of at least a portion of request nodes included in the processor system and each of at least a portion of response nodes included in the processor system according to on-chip layout information of the on-chip system included in the processor system and a routing algorithm.

[0071] Operation S302: Determine, according to performance parameters of nodes involved in a routing path, delay information of each of at least some of the responding nodes responding to each of at least some of the requesting nodes.

[0072] Operation S303, determining whether the delay information satisfies a predetermined condition. If not, operation S304 is performed. If the predetermined condition is met, the execution of the information processing method is terminated.

[0073] Operation S304: Optimize the on-chip layout information of the system on chip to obtain optimized on-chip layout information.

[0074] Operations S301 and S302 are similar to operations S201 and S202 described above, respectively, and are not described again herein.

[0075] Exemplarily, the delay information may include a delay value. The predetermined condition may include at least one of the following: an average delay value of a response node in the system-on-chip responding to a request node in the same system-on-chip is lower than a predetermined delay value; an average delay value of each response node in the processor system responding to each request node is lower than a predetermined delay value, etc. The predetermined condition and the predetermined delay value therein may be set according to actual needs, and the present disclosure does not limit this.

[0076] Exemplarily, the on-chip layout information can be optimized by adjusting the absolute position of the nodes in the system-on-chip or the relative position between the nodes in the system-on-chip. For example, the on-chip layout information can be optimized by randomly adjusting the above-mentioned absolute position or relative position, or by adjusting the position of the node by a unit length based on the current position of the node. This embodiment can use the layout information obtained after adjusting the position as the optimized on-chip layout information.

[0077] After obtaining the optimized on-chip layout information, this embodiment can use the optimized on-chip layout information as the on-chip layout information of the system on chip, and return to execute operation S301 to redetermine the routing path and redetermine the delay information until the determined delay information meets the predetermined condition.

[0078] Through the information processing method of at least one embodiment of the present disclosure, when the determined delay information does not meet the predetermined conditions, the on-chip layout information of the system on chip can be optimized, thereby facilitating the automatic iteration of the on-chip layout information of the system on chip and facilitating obtaining the optimal on-chip layout information of the system on chip.

[0079] Figure 4A The schematic diagram schematically shows the principle of optimizing on-chip layout information according to at least one embodiment of the present disclosure.

[0080] In one embodiment, the system on chip is provided with a plurality of routing nodes, and the plurality of routing nodes are connected to form a routing network, and a request sent by a requesting node in the system on chip can be transmitted through the routing network.

[0081] In one embodiment, an on-chip position range can be pre-set for at least part of the routing nodes in the on-chip system. This embodiment can optimize the on-chip layout information by adjusting the on-chip position of the corresponding routing node within the on-chip position range. At least part of the routing nodes can be selected according to actual needs, or the on-chip position range can be pre-set for all routing nodes. For example, the on-chip position range can be provided by the user when providing preliminary on-chip layout information, or it can be provided by the user after determining the delay information based on the preliminary on-chip layout information, and the present disclosure does not limit this.

[0082] For example, Figure 4A As shown, the multiple routing nodes in the system on chip 401 may include at least routing nodes R1 to R9, and the on-chip position range of the routing node R1 may be preset ( Figure 4A The dotted box marked with R1 in the figure) and the on-chip location range of routing node R9 ( Figure 4A The on-chip position range can be, for example, as follows: Figure 4A The dashed box shown is represented by vertex coordinates in a coordinate system built based on the on-chip system. It can be understood that Figure 4A The shape of the dashed-line frame shown is only an example to facilitate understanding of the present disclosure, and the present disclosure is not limited thereto.

[0083] For example, a target optimization algorithm may be used to adjust the on-chip position of the routing node. The target optimization algorithm may include a grid search method, a random search algorithm, a Bayesian optimization algorithm, or a greedy algorithm. The optimization target may be, for example, that the determined delay information is minimized, and the corresponding predetermined condition may be that the delay value representing the delay information no longer decreases. Alternatively, the optimization target may be that the delay value representing the delay information is less than the target delay value, and the corresponding predetermined condition may be that the delay value is less than the target delay value.

[0084] In one embodiment, the on-chip position range of each routing node in at least some of the routing nodes may include multiple optional on-chip position points of each routing node in the on-chip system. For example, the on-chip position range of each routing node may be represented by multiple optional coordinate points of each routing node in a coordinate system constructed based on the on-chip system. When the on-chip position of each routing node is adjusted using the target optimization algorithm, a position point other than the current position point of each routing node may be selected from the multiple optional on-chip position points as the position point of each routing node in the optimized on-chip layout information.

[0085] For example, the system on chip 400 may also include a memory (e.g., DRAM) that can serve as a response node. For example, the system on chip 400 may also include at least one cross-chip forwarding interface, through which the system on chip can transfer information with other systems on chip through the cross-chip forwarding interface and inter-chip interconnection. In at least one embodiment, the cross-chip forwarding interface may be an I / O interface, which may serve as a response node or a request node. For example, the system on chip may also include at least one CPU core, which may serve as a request node. It is understandable that the nodes included in the system on chip 400 other than routing nodes, memory (e.g., DRAM) and CPU cores may be selected according to actual needs, and the present disclosure does not limit this.

[0086] Figure 4B A schematic diagram schematically shows on-chip layout information of a system on chip according to an embodiment of the present disclosure, Figure 4C A schematic diagram schematically shows on-chip layout information of a system on chip according to another embodiment of the present disclosure.

[0087] like Figure 4B The system on chip 402 of one embodiment is shown. In this embodiment, the system on chip 402 includes a memory DRAM, at least four parts of the three-level cache (L3_P0, L3_P3, L3_P4 and L3_P7), 16 processor cores and 18 routing nodes (R0-R17) and three cross-chip forwarding interfaces. It can be understood that the connection relationship between the various parts in the system on chip 402 is only used as an example to facilitate the understanding of the present disclosure, and the present disclosure does not limit this.

[0088] In actual scenarios, when optimizing the on-chip layout information of the on-chip system, not only the on-chip position of the routing node can be adjusted, but also the on-chip position of the processor core, the third-level cache or the cross-chip forwarding interface can be adjusted, and the present disclosure does not limit this.

[0089] like Figure 4C As shown, it can be at least one embodiment of the Figure 4BThe system-on-chip 403 is obtained by optimizing the on-chip layout information of the system-on-chip 402. The on-chip layout information of the system-on-chip 403 is, for example, optimized on-chip layout information.

[0090] In one embodiment, based on Figure 4B The delay information determined by the on-chip layout information of the on-chip system 402 shown does not meet the predetermined condition, and based on Figure 4C The delay information determined by the on-chip layout information of the system on chip 403 shown meets the predetermined condition.

[0091] The following will be combined Figure 5-6 Further expand and describe the predetermined conditions set under different requirements.

[0092] In one embodiment, the processor system may include at least one system on chip. Each system on chip in the at least one system on chip includes a request node (e.g., a processor core or an I / O interface) and a response node (e.g., a DRAM or an I / O interface). When optimizing the on-chip layout information, the average delay value of the response node in response to the request node in the system on chip where it is located may be lower than the first target delay value. In other words, the predetermined condition in the above may be that the average delay value of the response node in response to the local request node is lower than the first target delay value, wherein the local request node and the response node that responds to the local request node belong to the same system on chip.

[0093] Exemplarily, this embodiment can filter out the delay information of the response node in a single system-on-chip responding to the local request node from all the determined delay information according to the numbers of the response node and the request node in the system-on-chip, and determine the average delay value according to the delay information. The average delay value is then compared with the first target delay value, and if the former is greater than or equal to the latter, the operation of optimizing the on-chip layout information of the system-on-chip is performed. The first target delay value can be set according to actual needs, and the present disclosure does not limit this.

[0094] At least one embodiment of the present disclosure optimizes on-chip layout information by setting a predetermined condition that the average delay value of the responding node in response to the local requesting node is lower than a first target delay value, which can effectively reduce the intra-chip communication delay of the optimized on-chip system.

[0095] Figure 5 The structural diagram of the processor system according to an embodiment of the present disclosure is schematically shown.

[0096] In at least one embodiment of the present disclosure, the processor system includes at least two core particles, and each of the at least two core particles includes at least one system on chip. Figure 5The processor system 500 includes four cores (ie, cores 501 to 504 ) and each core includes a system on chip. However, the embodiment of the present disclosure is not limited to this.

[0097] For example, Figure 5 The on-chip structure and on-chip layout information of the system on chip included in the four core particles are the same. Each system on chip includes a memory DRAM, at least four parts of the three-level cache (L3_P0, L3_P3, L3_P4 and L3_P7), 16 processor cores and 18 routing nodes (R0~R17) and three cross-chip forwarding interfaces. According to actual needs, the on-chip structure and on-chip layout information of the system on chip included in at least two of the four core particles may be different, and the present disclosure does not limit this.

[0098] Exemplarily, each of the at least one system-on-chip may include at least one of a request node (e.g., a processor core or an I / O interface) and a response node (e.g., a DRAM or an I / O interface). When optimizing the on-chip layout information, the target may be that the average delay value of the response node in response to the request nodes in other core particles other than the core particle in which the response node is located is lower than the second target delay value. In other words, the predetermined condition in the above may be that the average delay value of the response node in response to the first type of request node is lower than the second target delay value, wherein the first type of request node and the response node that responds to the first type of request node belong to different core particles.

[0099] Exemplarily, this embodiment can filter out the delay information of each response node responding to the first type of request node from all the determined delay information according to the numbers of the response nodes and the request nodes in the system on chip, and determine the average delay value according to the delay information. The average delay value is then compared with the second target delay value. If the former is greater than or equal to the latter, the operation of optimizing the on-chip layout information of the system on chip is performed. The second target delay value can be set according to actual needs. For example, the second target delay value can be greater than the first target delay value mentioned above, and the present disclosure does not limit this.

[0100] At least one embodiment of the present disclosure optimizes on-chip layout information by setting a predetermined condition that the average delay value of the responding node in response to the first type of request node is lower than a second target delay value, which can effectively reduce the communication delay between chiplets in a processor system composed of the optimized on-chip system.

[0101] Figure 6 A schematic diagram of the structure of a processor system according to another embodiment of the present disclosure is shown.

[0102] In this embodiment, the processor system includes at least two processing units, each of which can be understood as a socket. For example, each processing unit can include at least one core particle, and each of the at least one core particle includes at least one system on chip. Figure 6 The processor system 600 includes two processing units (i.e., processing units 601 and 602) and each processing unit includes six cores (e.g., processing unit 601 includes cores 0 to 5, and processing unit 602 includes cores 6 to 11) as an example for description, but the embodiments of the present disclosure are not limited to this.

[0103] For example, the structure of the core particles included in each processing unit can be Figure 5 The structure of the core particles described is similar and will not be repeated here.

[0104] Exemplarily, each system on chip in the system on chip may include at least one of a request node and a response node. When optimizing the on-chip layout information, the target may be that the average delay value of the response node in response to the request nodes in other processing units except the processing unit in which the response node is located is lower than the third target delay value. In other words, the predetermined condition in the above may be that the average delay value of the response node in response to the second type of request node is lower than the third target delay value, wherein the second type of request node and the response node that responds to the second type of request node belong to different core particles.

[0105] Exemplarily, this embodiment can filter out the delay information of each response node responding to the second type of request node from all the determined delay information according to the numbers of the response nodes and the request nodes in the system on chip, and determine the average delay value according to the delay information. The average delay value is then compared with the third target delay value. If the former is greater than or equal to the latter, the operation of optimizing the on-chip layout information of the system on chip is performed. The third target delay value can be set according to actual needs. For example, the third target delay value can be greater than the second target delay value mentioned above, and the present disclosure does not limit this.

[0106] At least one embodiment of the present disclosure optimizes on-chip layout information by setting a predetermined condition that the average delay value of the responding node in response to the second type of request node is lower than a third target delay value, which can effectively reduce the communication delay between processing units in a processor system composed of the on-chip system obtained based on the optimization.

[0107] The following will be combined Figure 7 The principle of determining the routing path is further expanded and described. Figure 7 The schematic diagram schematically shows the principle of constructing a topology diagram of a processor system according to at least one embodiment of the present disclosure.

[0108] According to an embodiment of the present disclosure, when determining a routing path between a requesting node and a responding node, a topology map of the processor system may be first constructed based on on-chip layout information, and then the topology map may be used as a basis for a routing algorithm to determine the routing path.

[0109] like Figure 7 As shown, in at least one embodiment 700, a processor system including a system on chip is used as an example to illustrate a method for constructing a topology map of a processor system. For example, after obtaining on-chip layout information of the system on chip, a topology map of the processor system can be constructed based on the on-chip layout information. The on-chip layout information of the system on chip can be obtained, for example, by Figure 7 The layout diagram 701 shown in FIG. 701 can be used to represent the positional relationship between nodes in the system on chip. The layout diagram 701 can be drawn by a user using a drawing tool, for example.

[0110] After obtaining the on-chip layout information, the connection relationship between the nodes in the processor system can also be obtained. For example, the connection relationship includes the connection relationship between the nodes in the on-chip system. In the case where the processor system includes at least two on-chip systems, the connection relationship can also include the connection relationship between the on-chip systems. According to the connection relationship, two cross-chip forwarding interfaces connected in two on-chip systems with a connection relationship can be determined, and the two cross-chip forwarding interfaces belong to different on-chip systems. The connection relationship can be input in the form of a two-dimensional matrix 702, for example, and the two-dimensional matrix 702 can represent the connection relationship between any two nodes in the processor system, and each row and each column in the two-dimensional matrix can represent the connection relationship between a node in the processor system and each node in all the nodes included in the processor system. For example, if two nodes have a connection relationship, the value of the element at the intersection corresponding to the two nodes in the two-dimensional matrix can be 1, otherwise the value can be 0. For example, the two-dimensional matrix 702 can be input by a user through an interactive interface, and the present disclosure does not limit this.

[0111] For example, if the processor system includes n nodes, the element at the intersection corresponding to the i-th node and the j-th node among the n nodes can be the element in the i-th row and j-th column of the two-dimensional matrix 702, or the element in the j-th row and i-th column of the two-dimensional matrix 702.

[0112] After the connection relationship is obtained, a topology map of the processor system can be constructed based on the connection relationship and the on-chip layout information to obtain a topology map 703. It should be noted that the difference between the topology map 703 and the traditional topology map is that the position of each node in the map can at least represent the relative position of each node in the processor system.

[0113] In one embodiment, after the connection relationship is obtained, the topology structure for the processor system can be determined based on the connection relationship. Then, the distance between two nodes with a connection relationship in the system-on-chip is determined based on the on-chip layout information. Then, based on the distance, the weight of the edge connecting the two nodes in the topology structure is determined to obtain a topology graph composed of the weight and the topology structure.

[0114] Exemplarily, the distance between two nodes may be proportional to the weight of the edge connecting the two nodes. For example, the length of the edge between the two nodes may be adjusted according to the weight, and the topological structure after the length adjustment may be used as the topological graph. In the topological structure determined based on the connection relationship, the edge connecting the two nodes may be an edge of unit length. In the final topological graph, the length of the edge connecting the two nodes in the system-on-chip may be the product of the unit length and the weight of the edge.

[0115] At least one embodiment of the present disclosure determines the weight of the edge connecting the two nodes in the topological structure based on the distance between the two nodes having a connection relationship in the system-on-chip, so that the final topological graph can reflect the physical distance between the two nodes having a connection relationship in the system-on-chip. The process of determining the routing path based on the topological graph takes the physical distance between the nodes into consideration, which is conducive to determining a reasonable routing path, and thus helps to improve the optimization efficiency of the on-chip layout information of the system-on-chip.

[0116] Figure 8 The following schematically shows the principle of determining delay information in at least one embodiment of the present disclosure. Figure 8 The principle of determining delay information is further expanded and described.

[0117] like Figure 8 As shown, taking the case where the requesting node is the processor core 0 numbered 0 in the first system on chip included in the processor system, and the responding node is the memory numbered 5 (e.g., DRAM 5) in the second system on chip included in the processor system as an example, the routing path between the processor core 0 numbered 0 and the memory numbered 5 can be, for example, path 801, which includes the processor core numbered 0 as the starting point and the memory numbered 5 as the end point, and sequentially connected to the routing node R0 numbered 0 in the first system on chip 811, the routing node R4 numbered 4, the routing node R5 numbered 5, the cross-chip forwarding interface I / O 2 numbered 2, the cross-chip forwarding interface I / O 2 numbered 2 in the second system on chip 821, the routing node R7 numbered 7, the routing node R6 numbered 6, and the DDR controller 5 numbered 5.

[0118] When determining the delay information of processor core 0 numbered 0 in the first system-on-chip accessing memory numbered 5 in the second system-on-chip based on path 801 (which can be understood as the delay information of DRAM 5 in the second system-on-chip responding to processor core 0 in the first system-on-chip), the first clock beat number of each node in path 801 responding to the request and the second clock beat number of the transmission request between adjacent nodes in the routing path can be determined first. At the same time or before or after determining the clock beat number, the processing frequency of each node in path 801 and the communication frequency between adjacent nodes in path 801 can also be determined. After obtaining the clock beat number and frequency, the delay information of processor core 0 numbered 0 in the first system-on-chip accessing memory numbered 5 in the second system-on-chip can be determined based on the first clock beat number and the processing frequency, and the second clock beat number and the communication frequency.

[0119] For example, the first clock beat number, the second clock beat number, the processing frequency, and the communication frequency may be input through an interactive interface, or may be obtained by querying performance parameters of nodes in the path, which is not limited in the present disclosure. For example, for path 801, the number of clock beats that need to be determined may include the number of clock beats required for processor core 0 to send an access request, the number of clock beats required for the access request sent by processor core 0 to be transmitted to routing node R0, the number of clock beats required for routing node R0 to receive and forward the access request, the number of clock beats required for the access request to be transmitted from routing node R0 to routing node R4, the number of clock beats required for routing node R4 to receive and forward the access request, the number of clock beats required for the access request to be transmitted from routing node R4 to routing node R5, the number of clock beats required for routing node R5 to receive and forward the access request, the number of clock beats required for the access request to be transmitted from routing node R5 to I / O 2 interface numbered 2 in the first system on chip 811, the number of clock beats required for the I / O 2 interface numbered 2 in the first system on chip 811 to receive and forward the access request, and the number of clock beats required for the access request to be transmitted from the I / O 2 interface numbered 2 in the first system on chip 811 to the I / O 2 interface numbered 2 in the second system on chip 821. 2 interface, the number of clock beats required for the I / O 2 interface numbered 2 in the second system-on-chip 821 to receive and forward the access request, the number of clock beats required for the access request to be transmitted from the I / O 2 interface numbered 2 in the second system-on-chip 821 to the routing node R7, the number of clock beats required for the routing node R7 to receive and forward the access request, the number of clock beats required for the access request to be transmitted from the routing node R7 to the routing node R6, the number of clock beats required for the routing node R6 to receive and forward the access request, the number of clock beats required for the access request to be transmitted from the routing node R7 to the DDR controller 5, the number of clock beats required for the DDR controller 5 to receive the access request and access the memory based on the access request. For example, for path 801, the frequency to be determined corresponds to the number of clock beats to be determined. After obtaining the number of clock beats and the frequency, a delay value can be obtained based on the number of clock beats and the frequency having a corresponding relationship. For example, by adding all the delay values ​​obtained, the delay information of the processor core 0 numbered 0 in the first system-on-chip accessing the memory numbered 5 in the second system-on-chip can be obtained.

[0120] For example, a ratio of the number of clock beats and the frequency having a corresponding relationship may be used as a delay value.

[0121] For example, for a single system on chip, the communication frequency between any two routing nodes is a fixed value, and the communication frequency between the routing node and other nodes can be determined according to the position of the frequency converter set between the two nodes. If the frequency converter is adjacent to other nodes, the communication frequency is the aforementioned fixed value. If the frequency converter is adjacent to the routing node, the communication frequency depends on the communication frequency of other nodes. For example, the fixed value can be the communication frequency of the NoC.

[0122] In one embodiment, the number of clock beats for transmission requests between two adjacent routing nodes can also be determined based on the distance between the two adjacent routing nodes in the routing path. This is because when the transmission distance is long, in order to improve the timing path, it is necessary to insert a delay unit in the longer transmission path, and inserting the delay unit will cause delay. The number of clock beats for transmission requests between two adjacent routing nodes determined by this embodiment is more accurate.

[0123] For example, the target adjacent node consisting of two routing nodes in the routing path may be determined first. Figure 8 In the path 801 shown, it is determined that the target adjacent nodes include the following three node pairs:<R0,R4> ,<R4,R5> ,<R7,R8> . After obtaining the target adjacent nodes, the number of delay units required to be inserted for communication between the target adjacent nodes can be determined based on the distance between the target adjacent nodes. For example, the distance between the target adjacent nodes can be determined based on the on-chip positions of the two nodes included in the target adjacent nodes in the on-chip layout information. For example, if a delay unit needs to be inserted every 1 mm, and the distance between routing node R0 and routing node R4 is 5 mm, then 4 delay units need to be inserted for communication between routing node R0 and routing node R4. After determining the number of delay units that need to be inserted, the number of clock beats for transmission requests between the target adjacent nodes can be determined based on the number of delay units. For example, if 4 delay units need to be inserted, the determined number of clock beats can be 4.

[0124] The following will be combined Fig. 9 The implementation principle of the information processing method provided by at least one embodiment of the present disclosure is further described.

[0125] like Fig. 9As shown, the embodiment 900 can first obtain the drawn initialization layout information 001 of the processor system and the constraint configuration file 002 indicating whether the routing nodes can be connected. The initialization layout information 001 can be obtained by drawing using a drawing tool, and the initialization layout information can be output in a file of any format, and the initialization layout information describes the position coordinates of each node in the processor system. The constraint configuration file describes whether the nodes in the processor system can be connected, and the constraint configuration file can be a file in the form of a two-dimensional array.

[0126] After obtaining the initialization layout information 001 and the constraint configuration file 002, operation S901 can be performed to determine the routing path between each request node and each response node using a routing algorithm. For example, the request node includes each processor core in the processor system, and the response node includes each DRAM in the processor system. Through operation S901, all C2D (CPU to DRAM) routing paths 003 can be obtained, that is, the routing path for each processor core to access each DRAM. For example, operation S901 can first generate a weighted undirected graph based on the initialization layout information 001 and the constraint configuration file 002, and the weight of the edge in the graph is determined based on the physical distance between the two nodes. Subsequently, based on the generated weighted undirected graph, a routing algorithm is used to generate the shortest routing path from each processor core to each DRAM to obtain all C2D routing paths 003.

[0127] For example, a routing path is obtained by using a routing algorithm. This embodiment can convert the routing path into a routing path in the format of A->B->C->D by parsing the routing path.

[0128] After obtaining the routing path, or at any time when the routing path is obtained, the system parameter description file 004 and the node characteristic description file 005 can be obtained, wherein the system parameter description file 004 may include the processing frequency of the node, the communication frequency between nodes, etc. The system parameter configuration file may be in text format or in chart format. The node characteristic description file 005 may include the number of beats required for each node to receive and forward requests, the time overhead required for request cross-chip forwarding, etc.

[0129] After obtaining the system parameter description file 004 and the node characteristic description file 005, the delay calculation can be performed on each routing path according to the processing frequency, communication frequency and beat number of the nodes involved in each routing path, and the delay value 006 of each C2D path can be obtained. The calculated delay value can be, for example, in nanoseconds, which is not limited in the present disclosure. The delay values ​​of all C2D paths can form a delay matrix 007.

[0130] After the delay matrix 007 is obtained, operation S902 may be performed to select the delay data of interest in the system-on-chip design process from the delay matrix 007, and determine whether the delay data of interest meets the design requirements. For example, if the average value of the selected delay data is higher than the expected delay value, operation S903 is performed. If the average value of the selected delay data is lower than the expected delay value, the information processing process is terminated. It is understood that the design requirements may be to meet the predetermined conditions described above.

[0131] Before executing operation S903, a configuration file 008 indicating the possible placement positions of routing nodes and the spatial coordinates of the possible placement positions may be obtained. Operation S903 is then executed based on the configuration file 008, i.e., the placement positions of routing nodes are automatically adjusted to obtain adjusted layout information. After the adjustment is completed through operation S903, operation S901 may be returned to perform the next iteration.

[0132] In one embodiment, in operation S903 of adjusting the placement of routing nodes, the connection constraint relationship between routing nodes may also be adjusted. The adjustment principle is similar to the principle of adjusting the placement of routing nodes.

[0133] In one embodiment, all possible on-chip locations of different routing nodes may be traversed until layout information of the routing nodes that meets the design requirements is found, or the layout position of the routing nodes and the routing path for the processor core to access the DRAM are obtained when the average value of the delay data of interest is minimized.

[0134] According to the information processing method of at least one embodiment of the present disclosure, for example, based on given on-chip layout information, a delay matrix between all request nodes and response nodes in a processor system composed of a system on chip with the on-chip layout information can be quickly obtained, thereby efficiently evaluating the communication performance of the processor system.

[0135] According to the information processing method of at least one embodiment of the present disclosure, for example, for an irregular NoC design, a reasonable layout position of the routing node and a reasonable routing path between the request node and the response node can be found from the on-chip layout strategy of the system-on-chip, which is conducive to automatically adjusting the layout position of the routing node and the routing path between the request node and the response node corresponding to the minimum delay.

[0136] Based on the information processing method provided by the present disclosure, the present disclosure also provides an information processing device. Fig.10 The device is described in detail.

[0137] Fig.10 The structure block diagram of the information processing device according to at least one embodiment of the present disclosure is schematically shown.

[0138] like Fig.10 As shown, the information processing device 1000 of this embodiment includes a path determination module 1001 and a delay determination module 1002 .

[0139] The path determination module 1001 is configured to determine a routing path between each of at least some of the request nodes included in the processor system and each of at least some of the response nodes included in the processor system according to the on-chip layout information of the on-chip system included in the processor system and the routing algorithm. The path determination module 1001 can be configured to perform the operation S201 described above, which will not be repeated here.

[0140] The delay determination module 1002 is configured to determine the delay information of each of at least some of the responding nodes responding to each of at least some of the requesting nodes according to the performance parameters of the nodes involved in the routing path. The delay determination module 1002 can be configured to perform the operation S202 described above, which will not be repeated here.

[0141] In some disclosed embodiments, the information processing device may further include a layout optimization module configured to optimize on-chip layout information of the system-on-chip with the goal of delay information satisfying predetermined conditions to obtain optimized on-chip layout information.

[0142] In some disclosed embodiments, the nodes in the processor system also include a routing network in the system on chip; the on-chip layout information of the system on chip includes at least on-chip location information of multiple routing nodes in the routing network. The layout optimization module can be configured to, for example, adjust the on-chip location of the routing node using a target optimization algorithm according to the on-chip location range of the routing node in the system on chip.

[0143] In some disclosed embodiments, the on-chip location range includes a plurality of selectable on-chip location points of each routing node of at least one routing node in the system-on-chip.

[0144] In some disclosed embodiments, the delay information includes a delay value; the processor system includes at least one system on chip. Each of the systems on chip includes a request node and a response node. The predetermined condition may include, for example, that an average delay value of the response node in response to the local request node is lower than a first target delay value, wherein the local request node and the response node that responds to the local request node belong to the same system on chip.

[0145] In some disclosed embodiments, the delay information includes a delay value, the processor system includes at least two core particles, each of the at least two core particles includes at least one system on chip, and the at least two core particles are connected by an inter-chip interconnect communication. For example, each of the system on chip includes at least one of a request node and a response node. The predetermined condition may, for example, include that an average delay value of a response node in response to a first type of remote request node is lower than a second target delay value, wherein the first type of remote request node and the response node that responds to the first type of remote request node belong to different core particles.

[0146] In some disclosed embodiments, the processor system includes at least two processing units, each of the processing units includes at least one core particle, and each of the at least one core particle includes at least one system on chip. For example, each of the systems on chip includes at least one of a request node and a response node. The predetermined condition may, for example, include that an average delay value of the response node in response to the second type of remote request node is lower than a second target delay value, and the second type of remote request node and the response node that responds to the second type of remote request node belong to different processing units.

[0147] In some disclosed embodiments, the path determination module may include a topology map construction unit and a path determination unit. The topology map construction unit may be configured to, in response to acquiring on-chip layout information of the system-on-chip, construct a topology map for the processor system based on the on-chip layout information. The path determination unit may be configured to, based on the topology map, use a routing algorithm to determine a routing path between at least some of the requesting nodes and at least some of the responding nodes.

[0148] In some disclosed embodiments, the topology map construction unit may be configured, for example, to construct a topology map for the processor system based on the connection relationship between nodes in the processor system and on-chip layout information of the system-on-chip.

[0149] In some disclosed embodiments, the topology map construction unit may include a structure determination subunit, a distance determination subunit, and a weight determination subunit. The structure determination subunit may be configured to determine the topology structure for the processor system based on the connection relationship between the nodes in the processor system. The distance determination subunit may be configured to determine the distance between two nodes with a connection relationship in the system-on-chip based on the on-chip layout information of the system-on-chip. The weight determination subunit may be configured to determine the weight of the edge connecting the two nodes in the topology structure based on the distance, and obtain a topology map consisting of the weight and the topology structure.

[0150] In some disclosed embodiments, the delay determination module may include a beat determination unit, a frequency determination unit, and a delay determination unit. The beat determination unit may be configured to, for example, determine a first clock beat number for each node in a routing path to respond to a request, and a second clock beat number for transmitting a request between adjacent nodes in the routing path. The frequency determination unit may be configured to, for example, determine a processing frequency for each node in a routing path, and a communication frequency between adjacent nodes in the routing path. The delay determination unit may be configured to, for example, determine the delay information of each of at least some of the responding nodes in response to at least some of the requesting nodes based on the first clock beat number and the processing frequency and the second clock beat number and the communication frequency.

[0151] In some disclosed embodiments, the nodes in the processor system also include routing nodes in the routing network of the system on chip. The beat determination unit may, for example, include a node determination subunit, a delay quantity determination subunit, and a beat determination subunit. The node determination subunit may, for example, be configured to determine a target adjacent node consisting of two routing nodes in a routing path. The delay quantity determination subunit may, for example, be configured to determine the number of delay units required to be inserted for communication between target adjacent nodes based on the distance between the target adjacent nodes. The beat determination subunit may, for example, be configured to determine the second clock beat number of the transmission request between the target adjacent nodes based on the number of delay units.

[0152] In some disclosed embodiments, the path determination module may be configured to determine a routing path between each requesting node included in the processor system and each responding node included in the processor system. The above-determined delay information includes a delay value of each responding node responding to each requesting node.

[0153] It should be noted that Fig.10 The components and structures shown are merely exemplary and non-limiting, and other components and structures may be included as needed.

[0154] At least some embodiments of the present disclosure also provide an electronic device. Fig.11 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

[0155] For example, Fig.11 As shown, the electronic device 1100 includes a processor 1110 and a memory 1120. The memory 1120 is used to store non-temporary computer-readable instructions (e.g., one or more computer program modules). The processor 1110 is used to run the computer program instructions, and the computer program instructions are executed by the processor 1110 to perform the information processing method provided by any embodiment of the present disclosure. The memory 1120 and the processor 1110 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0156] The processor 1110 may be a device having data processing capability and / or program execution capability, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. For example, the central processing unit (CPU) may be an X86 or ARM architecture, etc. The processor 1110 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 1100 to perform desired functions.

[0157] For example, the memory 1120 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 1110 may run one or more computer program modules to implement various functions of the electronic device 1100. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0158] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 1100 can refer to the above description of the information processing method, which will not be repeated here.

[0159] At least some embodiments of the present disclosure also provide a non-transitory storage medium. Fig.12 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure. Fig.12 As shown, the storage medium 1200 non-temporarily stores computer executable instructions 1201. When the non-temporary computer executable instructions 1201 are executed by a computer (including a processor), the information processing method provided by any embodiment of the present disclosure can be executed, which can improve the calculation efficiency of delay information.

[0160] For example, one or more computer instructions may be stored on the storage medium 1200. Some of the computer instructions stored on the storage medium 1200 may be, for example, instructions for implementing one or more steps in the above-mentioned information processing method.

[0161] For example, the storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media. For example, the storage medium 1200 may include the memory 1120 in the aforementioned electronic device 1100.

[0162] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding description of the information processing method in the above embodiments, which will not be repeated here.

[0163] There are a few points to note about this disclosure:

[0164] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0165] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0166] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An information processing method, comprising: Determine, based on on-chip layout information and a routing algorithm of a system-on-chip included in the processor system, a routing path between each of at least a portion of request nodes included in the processor system and each of at least a portion of response nodes included in the processor system; as well as Delay information for each of the at least some responding nodes to respond to each of the at least some requesting nodes is determined according to performance parameters of nodes involved in the routing path.

2. The method according to claim 1, further comprising: With the delay information satisfying a predetermined condition as a goal, the on-chip layout information of the system on chip is optimized to obtain optimized on-chip layout information.

3. The method according to claim 2, wherein: The nodes in the processor system also include a routing network in the system on chip; the on-chip layout information of the system on chip includes at least on-chip location information of a plurality of routing nodes in the routing network; The optimizing the on-chip layout information of the system on chip comprises: According to the on-chip position range of the routing node in the on-chip system, a target optimization algorithm is used to adjust the on-chip position of the routing node.

4. The method according to claim 3, wherein: The on-chip location range includes a plurality of selectable on-chip location points of each routing node of at least one of the routing nodes in the on-chip system.

5. The method according to claim 2 or 3, wherein: The delay information includes a delay value; the processor system includes at least one of the system-on-chip; Each of the systems on chip includes the request node and the response node, and the predetermined condition includes: An average delay value of the response node in responding to the local request node is lower than a first target delay value, and the local request node and the response node responding to the local request node belong to the same system on chip.

6. The method according to claim 2 or 3, wherein: The delay information includes a delay value; the processor system includes at least two core particles, each of the at least two core particles includes at least one of the system-on-chip, and the at least two core particles are connected through an inter-chip interconnect communication; Each of the systems on chip includes at least one of the requesting node and the responding node, and the predetermined condition includes: An average delay value of the response node in responding to a first type of remote requesting node is lower than a second target delay value, and the first type of remote requesting node and the response node responding to the first type of remote requesting node belong to different core particles.

7. The method according to claim 2 or 3, wherein: The processor system comprises at least two processing units, each of the processing units comprises at least one core particle, and each of the at least one core particle comprises at least one of the system-on-chip; Each of the systems on chip includes at least one of the requesting node and the responding node, and the predetermined condition includes: An average delay value of the response node in responding to the second type remote request node is lower than a second target delay value, and the second type remote request node and the response node responding to the second type remote request node belong to different processing units.

8. The method according to claim 1 or 2, wherein: The determining of a routing path between each of at least a portion of request nodes included in the processor system and each of at least a portion of response nodes included in the processor system comprises: In response to acquiring on-chip layout information of the system-on-chip, constructing a topology map for the processor system based on the on-chip layout information; and Based on the topology map, the routing algorithm is used to determine a routing path between each of the at least some of the requesting nodes and each of the at least some of the responding nodes.

9. The method according to claim 8, wherein: The constructing a topology map for the processor system based on the on-chip layout information includes: Based on the connection relationship between nodes in the processor system and the on-chip layout information of the system-on-chip, a topology map for the processor system is constructed.

10. The method according to claim 9, wherein: The constructing a topology map for the processor system based on the connection relationship between nodes in the processor system and the on-chip layout information of the system-on-chip includes: Determining a topology structure for the processor system based on a connection relationship between nodes in the processor system; Determining a distance between two nodes having a connection relationship in the system on chip based on the on-chip layout information of the system on chip; and Based on the distance, the weight of the edge connecting the two nodes in the topological structure is determined to obtain a topological graph consisting of the weight and the topological structure.

11. The method according to claim 1 or 2, wherein: The determining, according to the performance parameters of the nodes involved in the routing path, the delay information of each of the at least some responding nodes in responding to each of the at least some requesting nodes comprises: Determine a first clock beat number for each node in the routing path to respond to a request, and a second clock beat number for transmission requests between adjacent nodes in the routing path; determining a processing frequency of each node in the routing path and a communication frequency between adjacent nodes in the routing path; and Delay information of each of the at least some responding nodes responding to each of the at least some requesting nodes is determined based on the first clock tick number and the processing frequency and the second clock tick number and the communication frequency.

12. The method according to claim 11, wherein: The nodes in the processor system also include routing nodes in a routing network of the system on chip; Determining a second clock tick number of a transmission request between adjacent nodes in the routing path includes: Determining a target adjacent node consisting of two routing nodes in the routing path; Determining the number of delay units required to be inserted for communication between the target adjacent nodes according to the distance between the target adjacent nodes; and The second clock beat number of the transmission request between the target adjacent nodes is determined according to the number of the delay units.

13. The method according to claim 1, wherein: The determining of a routing path between each of at least a portion of request nodes included in the processor system and each of at least a portion of response nodes included in the processor system comprises: determining a routing path between each requesting node included in the processor system and each responding node included in the processor system, The delay information includes a delay value of each of the response nodes responding to each of the request nodes.

14. An information processing device, comprising: a path determination module configured to determine a routing path between each of at least a portion of request nodes included in the processor system and each of at least a portion of response nodes included in the processor system according to on-chip layout information of the system-on-chip included in the processor system and a routing algorithm; as well as The delay determination module is configured to determine delay information of each of the at least some responding nodes responding to each of the at least some requesting nodes according to performance parameters of the nodes involved in the routing path.

15. An electronic device, comprising: processor; as well as a memory including one or more computer program instructions; The one or more computer program instructions are executed by the processor to perform the method according to any one of claims 1-13.

16. A computer-readable storage medium non-transitorily storing computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the method according to any one of claims 1 to 13 is implemented.

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