Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are disclosed. The memory device includes: a memory cell array; an arithmetic unit including a logic circuit configured to perform an operation including a plurality of stages; and a plurality of buffers configured to store first data and second data respectively corresponding to a plurality of operation commands received from the host for each of the plurality of stages, in which the arithmetic unit includes a butterfly unit configured to perform a butterfly operation based on at least one of the first data and the second data.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2023-0110569 filed on August 23, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to a memory device and a method of operating the same. Background Art

[0003] The memory device can be used to store data and perform calculations using the data. For example, the memory device can be used to multiply polynomials. Multiplying polynomials is part of some homomorphic encryption techniques and lattice-based cryptography algorithms. Number Theoretic Transform (NTT) operations are used to efficiently process multiplications. In some examples, because performing NTT operations by software (SW) causes a lot of time, acceleration techniques are used.

[0004] For example, there are two methods for accelerating NTT operations: an acceleration method based on a graphics processing unit (GPU) and an acceleration method based on a field programmable gate array (FPGA). The GPU-based acceleration method results in high power consumption. Compared with the GPU-based acceleration method, the FPGA-based acceleration method has a similar processing speed, but results in relatively low power consumption. However, the FPGA-based acceleration method can only process NTT operations of a predetermined maximum length. In addition, considering the security level, most homomorphic encryption algorithms require high-precision operations, but the FPGA-based acceleration method is ineffective for high-precision operations.

[0005] The above descriptions have been possessed or acquired by one or more of the inventors in the process of conceiving the present disclosure and are not necessarily known technologies before filing the present application. Summary of the invention

[0006] According to an embodiment of the present disclosure, a memory device includes: a memory cell array; an operator including a logic circuit, the logic circuit being configured to perform an operation including multiple stages; and multiple buffers, configured to: store first data and second data corresponding to multiple operation commands received from a host for each of the multiple stages, respectively, wherein the operator includes a butterfly unit, and the butterfly unit is configured to perform a butterfly operation based on at least one of the first data and the second data.

[0007] According to an embodiment of the present disclosure, a method for operating a memory device includes an operator, and the operating method includes: receiving multiple commands from a host; determining multiple buffers among multiple buffers that store first data and second data corresponding to the multiple commands, respectively; storing the first data and the second data in the determined multiple buffers; and performing a butterfly operation based on at least one of the first data and the second data.

[0008] According to an embodiment of the present disclosure, a method includes: storing first data in a first buffer and storing second data in a second buffer through a memory device; performing a butterfly operation based on the first data in the first buffer and the second data in the second buffer through an operator of the memory device; and updating the first data and the second data based on the butterfly operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a memory device is shown.

[0010] Figure 2 An example of a number theoretic transform (NTT) operation is shown.

[0011] Figure 3A An example of a memory device is shown.

[0012] Figure 3B An example of an operator is shown.

[0013] Figure 4 An example of an in-place update is shown.

[0014] Figure 5 An example of a pipeline approach is shown.

[0015] Figure 6 An example of an operating method of a memory device is shown.

[0016] Figure 7 An example of a dynamic random access memory (DRAM) is shown.

[0017] Figure 8 An example of an operating method of a memory device is shown.

[0018] Throughout the drawings and detailed description, unless otherwise described or provided, the same figure reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative sizes, proportions, and depictions of the elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0019] The following disclosure relates to systems and processes for memory devices. Specifically, some embodiments of the disclosure relate to performing processing in memory (PIM) operations in memory devices. Aspects of the disclosure relate to performing number theoretic transform (NTT), discrete Fourier transform (DFT) operations. NTT can be used as a computational kernel in encryption and other applications.

[0020] Cryptographic kernels can be characterized by intensive memory usage, and can become bottlenecks in computation due to their long data dependency chains and irregular memory access patterns. These characteristics make optimizing performance both computationally intensive and challenging, especially in parallel computing environments where memory access patterns significantly affect efficiency. Efficiently performing NTT operations is a key consideration in the design and optimization of many computing systems.

[0021] Disclosed embodiments include a PIM architecture and mapping capable of performing NTT and related operations. Embodiments enable discovery of efficient mappings that reduce memory row activations, use of multiple atomic buffers to perform pipeline and in-place update optimizations, and save memory logic area. For example, some embodiments deliver improved processing speed with less hardware area overhead. Some examples are implemented without modifying the cell array, which improves production efficiency. Some embodiments support arbitrary polynomial lengths and modulus values.

[0022] The structural or functional descriptions in this disclosure are intended to describe examples of the disclosure, and examples can be implemented in various forms. Examples are not meant to be limiting. On the contrary, it is intended that various modifications, equivalents, and substitutes are also included within the scope of the claims.

[0023] In the disclosure, ordinal terms such as "first" and "second" are used to explain various components. However, the components according to the embodiments of the present disclosure are not limited to these terms. These terms should only be used to distinguish one component from another component. For example, within the scope of the rights according to the concept of the present disclosure, a "first" component may be referred to as a "second" component, or similarly, a "second" component may be referred to as a "first" component.

[0024] It should be noted that if it is described that one component is "connected," "coupled," or "engaged" to another component, although the first component may be directly connected, coupled, or engaged to the second component, a third component may be "connected," "coupled," and "engaged" between the first and second components. Conversely, it should be noted that if it is described that one component is "directly connected," "directly coupled," or "directly engaged" to another component, a third component may not exist. Expressions describing the relationship between components (e.g., "between," "directly between," or "directly adjacent," etc.) should be interpreted as being similar.

[0025] Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It should also be understood that the terms "include" and / or "comprising" when used in this specification indicate the presence of stated features, integers, steps, operations, elements, components and / or their combinations, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly so defined herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0027] The examples may be implemented as various types of products (such as, for example, personal computers (PCs), laptop computers, tablet computers, smart phones, televisions (TVs), smart home appliances, smart vehicles, self-service terminals, and wearable devices). Hereinafter, the examples will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements.

[0028] Figure 1 An example of a memory device is shown.

[0029] Reference Figure 1 , the present disclosure provides Figure 1 . According to an embodiment of the present disclosure, the memory system is configured to incorporate additional computing resources into the memory device 110. The memory system may include a memory device 110 connected to a host processor 150, such as a graphics processing unit (GPU) or a central processing unit (CPU). In some embodiments, the memory device 110 is configured to accelerate polynomial multiplication operations, which are suitable for post-quantum cryptography (e.g., lattice-based cryptography, homomorphic encryption technology, etc.), artificial intelligence (AI), and high-performance computing (HPC) applications using polynomial multiplication operations. The memory system can be applied to a server or a portable device.

[0030] In one embodiment, the memory device 110 may include a memory die 120. The host processor 150 may include a host memory controller 160 for interfacing with the memory device 110. In some examples, the host processor 150 may include a host controller for interfacing with the memory device 110. However, the present disclosure is not limited to the foregoing examples. For example, the host memory controller 160 may include a die separate from the host processor 150 or the same die as the host processor 150, and may be separate from the host processor 150. Alternatively, the memory device 110 may include a memory controller, and the memory die 120 may be connected to the memory controller via an internal memory bus.

[0031] In some embodiments, the host memory controller 160 may be configured to control the execution of instructions from the host processor 150. The instructions may include regular commands (or commands) and PIM commands. For example, regular commands (e.g., traditional load (read), store (write), and activate (ACT) functions that are not in-memory function commands) may be sent by the host memory controller 160 and may be executed in a typical manner. For example, regular commands may include a plurality of commands for storing data received via an external bus in the memory die 120, and a plurality of commands for searching data and sending data from the memory die 120 to the host processor 150 via an external bus. As described in detail below, PIM commands may be added for PIM operations. The PIM command may include a first operation command and a second operation command, wherein the first operation command indicates an operation between data in the same buffer, and the second operation command indicates an operation between data in different buffers. Hereinafter, the first operation command may be referred to as C1, and the second operation command may be referred to as C2.

[0032] Aspects of the present disclosure relate to the use of in-memory computing (IMC), and a memory system may include a memory bank 121 and an operator 123 in a memory die 120. Similar conventional systems, such as near memory processing (PNM), may place operators, such as arithmetic logic units (ALUs), outside the memory die. However, in a system according to an embodiment of the present disclosure, an operator shared by an array of memory cells in a memory bank performs operations directly on data within the memory die, thereby bypassing the need for an external bus.

[0033] Some aspects of the present disclosure relate to accelerating memory boundary operations by incorporating an operator 123 into a memory bank 121 of a memory die 120. For example, the operator 123 and the memory bank 121 are integrated within the same semiconductor die, thereby facilitating efficient data retention.

[0034] The memory bank 121 includes an array of memory cells organized systematically in rows and columns. For example, each row and column including a dynamic random access memory (DRAM) cell is aligned with a natural number index, thereby simplifying data organization. For example, the memory bank 121 may include a dynamic random access memory (DRAM) cell arranged in n rows (or pages) and m columns (here, n and m may be natural numbers greater than 0). A plurality of bit lines (e.g., B1 to Bm) may extend in the column direction. A plurality of row enable lines (R1 to Rn) may extend in the row direction of the array and may intersect the bit lines. Each bit line may be connected to all cells in the corresponding column (e.g., all cells in the i-th column of the array may be connected to the bit line Bi). Similarly, each of the row enable lines (e.g., R1 to Rn) may be connected to each memory cell in the corresponding row (e.g., all cells in the j-th row or page of the array may be connected to the row enable line Rj). The memory cells of the rows of the memory bank 121 may also be referred to as memory pages.

[0035] The operator 123 may perform complex number operations including number theoretic transforms (NTT) or fast Fourier transforms (FFT). These operations may be particularly effective for processing multiplication of two polynomials, a key task in post-quantum cryptography. Such cryptography includes advanced techniques such as lattice-based cryptography and homomorphic encryption methods. The NTT operation may be an FFT transform formula that operates in a finite ring. The ring condition may be , and n can be the degree of the polynomial calculated in NTT. A polynomial multiplier based on NTT operation may include FFT theory and convolution theory, and can perform polynomial calculation while reducing computational complexity. In this case, modular reduction is required to allow NTT to operate in a ring. Although the operator 123 that performs NTT operation is described below, the operation that can be performed in the operator 123 is not limited to NTT operation.

[0036] NTT operations are characterized by their irregular memory access patterns and large amounts of data usage. Therefore, achieving efficient memory access may be important for improving performance. However, data reuse may be very free in a row of a memory cell array in a DRAM, but access to another row or data transfer to another memory bank may be inefficient. Memory banks 121 can maximize data reuse in a row or memory bank by using multiple buffers.

[0037] Figure 2 An example of NTT operation is shown.

[0038] Reference Figure 2 , Figure 210 shows the data flow when an 8-point NTT operation is performed by using the Cooley-Tukey algorithm.

[0039] The NTT operation can be defined as follows. The polynomial A(x) can be closed in Rq (ring), and the member a has a length of n vectors. Therefore, the vector can be the coefficients of the polynomial A(x). NTT(a) can be defined as Equation 1, where the modulus q of the finite field can be an integer greater than 1.

[0040] Equation 1 Point-wise multiplication may be applied to coefficients of the same degree from the results of separate NTT operations on two input polynomials A and B. The result of the multiplication of the two polynomials A and B may be obtained by performing an INTT operation on the result of the point-wise multiplication. The inverse transform INTT(A) may be defined as Equation 2.

[0041] Equation 2 Regarding the variables n and w used in Equation 2, w may be the nth root of unity modulo q. In other words, Equation 2 may need to be satisfied. In addition, the variables n and w used in the inverse transform INTT may include satisfying and For example, NTT may involve an FFT algorithm structure.

[0042] The NTT operation may include multiple stages. For example, the NTT operation may be performed by the Cooley-Tukey algorithm. The Cooley-Tukey algorithm represents a technique for efficiently computing a fast Fourier transform (FFT). The algorithm uses a divide-and-conquer approach to decompose a discrete Fourier transform (DFT) of a composite size into smaller DFTs. It then recursively processes these smaller DFTs, significantly reducing computational complexity and time, especially for large data sets. The efficiency of the Cooley-Tukey algorithm in rearranging and combining the results of smaller DFTs makes it a key method in FFT calculations. In order to perform an FFT or NTT transform of size N by the Cooley-Tukey algorithm, logN stages (or stages) are required, and each stage may require a butterfly operation. Referring to FIG. 220, the butterfly operation of the Cooley-Tukey algorithm may include a modular addition (ModAdd) operation, a modular subtraction (ModSub) operation, and a modular multiplication (ModMult) operation.

[0043] However, the method of performing the NTT operation may not be limited to the Cooley-Tukey algorithm. For example, the NTT operation may also be performed by the Gentleman-Sande algorithm, and the butterfly operation of the Gentleman-Sande algorithm may be different from the butterfly operation of the Cooley-Tukey algorithm. The Gentleman-Sande algorithm represents a technique for calculating the Fast Fourier Transform (FFT). Similar to the Cooley-Tukey algorithm, it adopts a divide-and-conquer strategy, but differs in its method of data reordering. The Gentleman-Sande algorithm is efficient in its processing of data, thereby allowing in-place calculations without the need for additional memory for reordering. Figure 2 In the formula, w0 to w3 may represent rotation factors.

[0044] Figure 3A An example of a memory device is shown. Figure 1 and Figure 2 The description provided can also be applied to Figure 3A , and any repeated descriptions are omitted.

[0045] Reference Figure 3A , the memory device may include a memory cell array 310, a row buffer 320, a selector 330, a first atom buffer 340, a second atom buffer 350, and an operator 360. Terms such as "unit", "module", etc. used hereinafter may represent a component for processing a function or operation, and may be implemented as hardware, software, or a combination of hardware and software.

[0046] When reading data from a particular row in the memory cell array 310, the process involves sending voltages from the capacitors of the selected memory cells along the bit lines. These voltages, representing the stored data, are then captured and interpreted by the row buffer 320. The row buffer 320 may be connected to corresponding ones of the bit lines. The row buffer 320 may store the data read from the current row (or page) until the row is erased by a precharge command.

[0047] The selector 330 may be a device for selecting data corresponding to a row address from among data stored in the row buffer 320. For example, the selector 330 may be a multiplexer. However, the selector is not limited to the multiplexer and may include various devices for selecting specific data from among a plurality of data.

[0048] The memory device may include a plurality of atomic buffers (e.g., first atomic buffer 340 and second atomic buffer 350). The atomic buffer may be a buffer having a smaller size than row buffer 320 and may be used for efficient operation and memory access. In some examples, the atomic may be a unit size that is smaller than the size of a row and may be, for example, 32 bytes.

[0049] The first atomic buffer 340 may be a buffer included in a typical DRAM memory device. For example, the first atomic buffer 340 may be a global sense amplifier (GSA) for global input / output (global I / O). The first atomic buffer 340 may be referred to as a main atomic buffer to distinguish the first atomic buffer 340 from the second atomic buffer 350 as an additional buffer.

[0050] The second atomic buffer 350 may be referred to as a secondary atomic buffer, and may be one or more atomic buffers used in addition to the first atomic buffer 340 (eg, GSA).

[0051] Although butterfly operations can be performed in a typical structure with one row buffer per memory bank, the memory bank access efficiency may be very low. In NTT operations, which typically require interaction between data in different rows, the exclusive use of row buffers may result in quite low memory access efficiency. This limitation stems from the design of the row buffers, which are more optimized for accessing data within the same row rather than across multiple rows.

[0052] According to some embodiments, the memory device can solve the above problem by adding a second atomic buffer 350 having a size significantly smaller than that of the row buffer. The additional use of the second atomic buffer 350 can firstly implement an in-place update for overwriting the corresponding buffer with the operation result; and secondly, implement parallel operation processing through a pipeline.

[0053] First, for in-place updates, since each segment of data is used twice in each stage, in addition to the buffer for storing input data, a buffer for storing output data may be required. However, when scheduling is performed in stages (the stage unit is the same as the butterfly operation unit), the data used for each butterfly operation may no longer be used in the corresponding stage (that is, the input data of the current stage may no longer be used for the operation of the subsequent stage), so the input data may be deleted. For in-place updates, since each data segment is reused in different stages, the role of the buffer alternates between storing input data and storing output data. Specifically, the data from the butterfly operation can be rewritten into its original input buffer, thereby improving data reuse efficiency. In other words, the result of the butterfly operation can be stored again in the buffer for storing the input of the butterfly operation (that is, by overwriting the input), and the data can be fully reused.

[0054] In butterfly operations, having a separate buffer for each input prevents the overwrite problem. If only one buffer is used, the output from one operation may overwrite the input required for the next operation, thereby compromising processing and efficiency. However, in this case, the input has already been overwritten by the output of the previous operation, so the second butterfly operation may not be performed. When in-place updates are not performed, additional row activations are required to store the outputs, so memory access efficiency may become very low.

[0055] However, when the second atomic buffer 350 is used, in addition to the intra-atomic case (the two input data are in the same atomic buffer), the in-place update of the butterfly operation can also be performed in the intra-row case (the two input data are in the same row buffer 320) or the inter-row case (the two input data are in different row buffers 320). For example, the second atomic buffer 350 is used to implement a more flexible in-place update applicable to various scenarios (data resides in the same row, across different rows, or in the same atomic buffer).

[0056] Second, parallel operation processing by pipelining is a technique for processing input cells having a size larger than the size of the atomic buffer or the row buffer using a plurality of second atomic buffers 350. For example, pipelining can shorten the total execution time by overlapping the time caused by operation with the time caused by memory access. In other words, by pipelining, operation and memory read / write can be performed simultaneously. For example, in the case of inter-row, pipelining can also shorten the execution time by reducing the number of row activations. Figure 5 A method for processing parallel operations through a pipeline is described in detail.

[0057] Figure 3B An example of an operator is shown.

[0058] Reference Figure 3B, the operator 360 may include a twiddle factor generator (TFG) 361, a butterfly unit (BU) 363, and a load storage unit (LSU) 365. The twiddle factor generator (TFG) represents a component that generates complex exponential values ​​called twiddle factors used in the Fast Fourier Transform (FFT) algorithm. These factors are necessary to manipulate and combine input data in various stages of FFT processing.

[0059] The TFG 361 may be a device for generating a rotation factor, which is a complex-valued coefficient of a rotation concept used in an algorithm related to an NTT operation or an FFT operation. The TFG 361 may send the rotation factor to the BU 363 so that a butterfly operation is performed in the BU 363.

[0060] The LSU 365 may be a device for managing interaction between a memory and data, and may allow the BU 363 to access the atomic buffer. The atomic buffer may include a first atomic buffer 340 and a second atomic buffer 350.

[0061] The BU 363 may be a device for performing a butterfly operation, and may include a modular addition operator, a modular subtraction operator, and a modular multiplication operator. However, components of the BU 363 are not limited to the aforementioned example.

[0062] Figure 4 An example of an in-place update is shown.

[0063] Reference Figure 4 , FIG. 410 shows an in-place update operation in an intra-atom case (two input data are in the same atomic buffer), FIG. 420 shows an in-place update operation in an intra-row case (two input data are in the same row buffer), and FIG. 430 shows an in-place update operation in an inter-row case (two input data are in different row buffers). Here, RD, WR, and PR / ACT respectively represent load (read), store (write), precharge / activate as typical DRAM commands. C1 and C2 respectively represent a first operation command and a second operation command as a PIM command.

[0064] The memory device can divide the entire operation into DRAM atomic-sized operations by dividing the NTT of the big data into three stages and execute the divided operations. The memory device can store the DRAM atomic-sized data in the atomic buffer using a standard DRAM command, execute the operation using a C1 command or a C2 command, and then update the data in the DRAM by updating in place.

[0065] For example, the host processor (e.g., CPU) may copy the data to be NTT-operated to the memory area where the PIM function is activated, and may send a read / write command and an operation command (e.g., C1 or C2) to the memory area where the PIM function is activated by using the NTT parameter information. After all commands related to the NTT operation are completed, the host processor may read the data on which the NTT operation is completed through a memory read command.

[0066] Referring to 410 , for example, in the intra-atomic case, two data are stored in the second atomic buffer S according to the RD command, an operation may be performed in the operator C according to the C1 command, and the second atomic buffer S may be overwritten with the operation result according to the WR command.

[0067] Referring to 420, for example, in an intra-row case, the first data is stored in the second atomic buffer S according to the RD command, and the second data is stored in the first atomic buffer P, the operation can be performed in the operator C according to the C2 command, the second atomic buffer S can be overwritten with the operation result corresponding to the first data according to the WR command, and the operation result corresponding to the second data can be overwritten in the first atomic buffer P.

[0068] Referring to 430, for example, in the inter-row case, first, the first data is stored in the second atomic buffer S using a read command (RD). Then, the precharge / activate command (PR / ACT) changes the target row. Subsequently, the second data is stored in the first atomic buffer P using the RD command again in the new target row. The operator C performs an operation using a second operation command (C2). The result of the operation results in: using a write command (WR) to overwrite the first atomic buffer P with a result related to the second data, and using the WR command again to overwrite the second atomic buffer S with a result related to the first data after the row change via the PR / ACT command.

[0069] Figure 5 An example of a pipeline approach is shown.

[0070] Reference Figure 5 , FIG. 510 shows an example of performing two operations in an intra-atomic case without using a pipeline, and FIG. 515 shows an example of performing two operations in an intra-atomic case through a pipeline using two atomic buffers.

[0071] Referring to FIG. 510 , in an atomic intra case using one atomic buffer (atomic buffer 0), when an operation on a first data pair is completed, an operation on a second data pair may be performed. In some examples, referring to FIG. 515 , in an atomic intra case using two atomic buffers (atomic buffers 0 and 1), when an operation is performed on a first data pair stored in atomic buffer 0, a second data pair may be stored in atomic buffer 1, and when an operation is performed on the second data pair, an operation result of the first data pair may be overwritten in atomic buffer 0. Referring to FIGS. 510 and 515 , it may be determined that the latency of receiving data through a pipeline is reduced.

[0072] Diagram 520 shows an example of performing two operations in an in-line case without using a pipeline, and Diagram 525 shows an example of performing two operations in an in-line case through a pipeline using four atomic buffers.

[0073] Referring to FIG. 520, in the case of an intra-row using two atomic buffers (atomic buffers 0 and 1), when an operation on a first data pair is completed, an operation on a second data pair may be performed. In some examples, referring to FIG. 525, in the case of an intra-row using four atomic buffers (atomic buffers 0 to 3), when an operation is performed on a first data pair stored in atomic buffers 0 and 1, the second data pair may be stored in atomic buffers 2 and 3, respectively, and when an operation is performed on the second data pair, the operation result of the first data pair may be overwritten in atomic buffers 0 and 1, respectively. Referring to FIGS. 520 and 525, it may be determined that the latency of receiving data through the pipeline is reduced.

[0074] Diagram 530 shows an example of performing two operations without using a pipeline in an inter-line case, and Diagram 535 shows an example of performing two operations through a pipeline using four atomic buffers in an inter-line case.

[0075] Referring to FIG. 530 , in an inter-row case using two atomic buffers (atomic buffers 0 and 1), when an operation on a first data pair is completed, an operation on a second data pair may be performed. In some examples, referring to FIG. 535 , in an inter-row case using four atomic buffers (atomic buffers 0 to 3), the first data of the first data pair may be stored in atomic buffer 0, and the first data of the second data pair may be stored in atomic buffer 2. Then, the target row may be changed, and in the changed row, the second data of the first data pair may be stored in atomic buffer 1, and the second data of the second data pair may be stored in atomic buffer 3. When the second data of the second data pair is stored in atomic buffer 3, an operation on the first data pair may be performed. When the operation on the second data pair is performed, the operation result of the second data of the first data pair may be stored (e.g., overwritten) in atomic buffer 1. Then, the operation result of the second data of the second data pair may be stored (e.g., overwritten) in atomic buffer 3. After changing the target row, the operation result is stored in a specific atomic buffer. For example, the operation result of the first data from the first data pair is stored (eg, overwritten) in atomic buffer 0, and the operation result of the first data from the second data pair is placed (eg, overwritten) in atomic buffer 2. This arrangement can facilitate orderly post-data storage operations.

[0076] Referring to Figures 530 and 535, the total execution time can be reduced by overlapping the time caused by operations with the time caused by memory accesses via pipelining. In addition, the execution time can also be reduced by reducing the number of row activations. For example, an execution involving four row activations as shown in Figure 530 can be optimized to only two row activations as shown in Figure 535, thereby improving overall efficiency.

[0077] Figure 6 An example of an operating method of a memory device is shown.

[0078] For ease of description, the following will describe Figure 1 1 to perform operations 610 to 640 using the memory device 110 shown in FIG. However, operations 610 to 640 may be performed by another suitable electronic device in any suitable system.

[0079] also, Figure 6 The operations of the embodiment of the present invention may be performed in the order and manner shown. However, without departing from the spirit and scope of the illustrated examples, the order of some operations may be changed, or some operations may be omitted. Figure 6 The operations shown in may be performed in parallel or simultaneously.

[0080] In operation 610, the memory device 110 may receive a command from a host. The memory device 110 may receive a first operation command and a second operation command, wherein the first operation command indicates an operation between data in the same buffer and the second operation command indicates an operation between data in different buffers. For example, the first operation command may instruct the device to add two numbers in the same buffer and the second operation command may indicate a multiplication between data in separate buffers.

[0081] In operation 620, the memory device 110 may determine a buffer among a plurality of buffers that will store the first data and the second data corresponding to the command. For example, based on the command, the memory device 110 may select a buffer that currently stores the required data for the upcoming operation. In one example, the memory device 110 may first determine a row buffer (see FIG. 1 ) that stores the first data and the second data corresponding to the command. Figure 3A ), and then loads the first data and the second data corresponding to the command from the determined row buffer to the buffer determined in operation 620 (for example, referring to Figure 3A In one example, the size of the first data and the size of the second data may be determined based on the size of each of the plurality of buffers (atomic buffers).

[0082] In operation 630, the memory device 110 may store the first data and the second data in a determined buffer. In one example, the operator may include a logic circuit that performs an operation including multiple stages. In the memory device 110, when the operator performs an operation including multiple stages, multiple buffers may store at least one of the input data and output data of the operation including multiple stages. For example, if the operation is a multi-stage calculation, the first data may be an initial value, and the second data may be an intermediate result from a previous stage. In one example, the operation including multiple stages may include at least one of an NTT operation and an FFT operation.

[0083] In operation 640, the memory device 110 may perform a butterfly operation based on at least one of the first data and the second data. For example, the memory device 110 may combine the data in a specific manner (eg, using FFT) to efficiently process the first data and the second data.

[0084] In the memory device 110 , when the operation of the corresponding stage is completed, the buffer storing the first data may update the first data with the result of the butterfly operation corresponding to the first data, and the buffer storing the second data may update the second data with the result of the butterfly operation corresponding to the second data.

[0085] Upon receiving the second operation command, the memory device 110 stores the first data in a dedicated first buffer and stores the second data in a separate second buffer. After completing the phase-specific operation (e.g., the operation of the phase including the second operation command), the first buffer updates the contents of the first buffer with the result from the butterfly operation associated with the first data. Similarly, the second buffer is updated with the result corresponding to the second data. This approach ensures that each data set is processed and updated independently within its corresponding buffer.

[0086] When the memory device 110 receives a first operation command from the host, the first data and the second data may be stored in the second buffer. When the operation of the corresponding stage (e.g., the stage including the first operation command) is completed, the second buffer may update the first data to the result of the butterfly operation corresponding to the first data, and the second buffer may update the second data to the result of the butterfly operation corresponding to the second data.

[0087] Figure 7 An example of a dynamic random access memory (DRAM) 700 is shown.

[0088] Reference Figure 7 , word line 705 specifically targets rows of memory cells to enable reading or writing of data (including performing PIM operations such as NTT / FFT). For example, when a memory read operation is initiated, word line 705 activates the corresponding row, allowing data stored in the cells of the row to become accessible. The activation determines which particular row of cells is used for subsequent data transfer. For example, during a memory read operation, word line 705 activates the row for data access. This operation can be modified for efficient PIM processing (such as NTT / FFT operations).

[0089] The bit lines 710 are directly connected to the memory cells along the columns. The bit lines 710 are responsible for the actual data transfer to and from these cells. For example, during a memory read operation, the bit lines 710 transfer a tiny charge from an activated memory cell to a sense amplifier, thereby efficiently delivering the stored data. Conversely, during a write operation, the bit lines 710 send data to be stored in the memory cell. For example, the bit lines 710 may be responsible for transmitting data that is critical to a PIM operation, such as performing a butterfly operation on data stored in a buffer. For example, during a read operation, the bit lines 710 transfer charge from the memory cell to the sense amplifier, which is fundamental in a process based on a butterfly operation to perform and update data.

[0090] The bit line precharge circuit 715 prepares the bit line 710 for data operations. For example, the bit line precharge circuit 715 sets the bit line to a predefined voltage level before any read operation or write operation is performed. For example, in a read operation, the precharge process ensures that the bit line can accurately detect slight changes in voltage representing the data stored in the memory cell.

[0091] The primary sense amplifier 720 amplifies small voltage changes on the bit line 710, which indicate binary data stored in the memory cell. For example, when a "1" is stored in the memory cell, the corresponding change in voltage on the bit line 710, although small, is detected and amplified by the sense amplifier, thereby enabling the digital circuit to recognize and process the data.

[0092] Figure 8 An example of an operating method of a memory device is shown.

[0093] In operation 805, the memory device stores the data in the designated buffer for processing. For example, the first data set is placed in the first buffer, and the second data set is allocated to the second buffer. This step ensures that each data set is placed in a specific buffer for targeted processing.

[0094] In operation 810, an operator of the memory device performs a butterfly operation. This process involves combining first data from a first buffer with second data from a second buffer. Such an example may be merging two data streams for calculations necessary in signal processing or cryptographic algorithms.

[0095] Finally, in operation 815, the stored data is updated based on the result of the butterfly operation. The first data set and the second data set in the corresponding buffers of the first data set and the second data set are modified to reflect the result of the processing. This may involve adjusting the data value based on the calculation output to ensure that the buffer contains the latest and processed data. In one example, a transform operation including at least one of an NTT operation and an FFT operation may be performed based on the result of the butterfly operation. In one example, the memory device may perform a first preliminary butterfly operation based on the data in the first buffer during the first stage of the transform operation, and perform a second preliminary butterfly operation based on the data in the second buffer during the first stage of the transform operation, wherein the butterfly operation is performed during the second stage of the transform operation.

[0096] The examples described herein can be implemented using hardware components, software components, and / or combinations thereof. The processing device can be implemented using one or more general or special computers (such as processors, controllers, and arithmetic logic units (ALUs), digital signal processors (DSPs), microcomputers, field programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device capable of responding to and executing instructions in a defined manner). The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing unit can also access, store, manipulate, process, and generate data in response to the execution of the software. In some cases, the description of the processing unit is used as a singular form; however, those skilled in the art will understand that the processing unit may include multiple processing elements and multiple types of processing elements. For example, the processing device may include multiple processors, or a processor and a controller. In addition, different processing configurations are feasible (such as parallel processors).

[0097] Software may include computer programs, code segments, instructions, or a combination thereof, to individually or collectively instruct or configure a processing device to operate as desired. Software and data may be permanently or temporarily contained in a machine, component, physical or virtual device, computer storage medium or device, or permanently or temporarily contained in a propagating signal wave capable of providing instructions or data to a processing device or capable of being interpreted by a processing device. Software may also be distributed on networked computer systems so that the software is stored and executed in a distributed manner. Software and data may be stored by one or more non-transitory computer-readable recording media.

[0098] The method according to the above example may be recorded in a non-transitory computer-readable medium including program instructions for implementing various operations of the above-mentioned embodiments. In addition, these media may include data files, data structures and similar elements as independent items, or may include data files, data structures and similar elements combined with program instructions. The program instructions recorded on the medium may be program instructions specially designed and constructed for the purpose of the example embodiment, or they may be known and available to technicians in the field of computer software. Examples of non-transitory computer-readable media include: magnetic media (such as hard disks, floppy disks and tapes); optical media (such as CD-ROM disks and / or DVDs); magneto-optical media (such as optical disks); hardware devices (such as read-only memory (ROM), random access memory (RAM), flash memory) and the like that are specially configured to store and execute program instructions. Examples of program instructions include both machine codes such as those generated by a compiler and files containing high-level codes that can be executed by a computer using an interpreter.

[0099] A number of embodiments have been described above. However, it should be understood that various modifications may be made to these embodiments. For example, effective results may generally be achieved by applying the described techniques in an alternative order, and / or if components in the described systems, architectures, devices, or circuits are combined in a different manner, or replaced or supplemented by other components or their equivalents, effective results may generally be achieved.

[0100] Accordingly, other implementations, other examples, and equivalents are within the scope of the appended claims.

Claims

1. A memory device, comprising: a memory cell array; An operator including a logic circuit configured to perform an operation including a plurality of stages; as well as a plurality of buffers configured to store first data and second data respectively corresponding to each of a plurality of operation commands received from the host for each of the plurality of stages, The operator includes a butterfly unit, and the butterfly unit is configured to perform a butterfly operation based on at least one of the first data and the second data.

2. The memory device according to claim 1, wherein: When the operator performs the operation including the plurality of stages, The plurality of buffers are configured to store input data and output data of the operation including the plurality of stages.

3. The memory device according to claim 1, wherein: When the operation of the corresponding stage in the plurality of stages is completed, The first buffer storing the first data updates the first data to a result of a first butterfly operation corresponding to the first data, and The second buffer storing the second data updates the second data to a result of a second butterfly operation corresponding to the second data.

4. The memory device according to claim 1, wherein: The multiple operation commands include a first operation command and a second operation command, The first operation command indicates an operation between data in the same buffer, and the second operation command indicates an operation between data in different buffers.

5. The memory device according to claim 4, wherein: When a second operation command is received from the host, first data corresponding to the second operation command is stored in the first buffer, and second data corresponding to the second operation command is stored in a second buffer different from the first buffer, and When the operation of the corresponding stage including the second operation command among the multiple stages is completed, the first buffer updates the first data to the result of the butterfly operation corresponding to the first data, and the second buffer updates the second data to the result of the butterfly operation corresponding to the second data.

6. The memory device according to claim 4, wherein: When a first operation command is received from the host, first data and second data corresponding to the first operation command are stored in the second buffer, and When the operation of the corresponding stage including the first operation command among the multiple stages is completed, the second buffer updates the first data to the result of the butterfly operation corresponding to the first data, and the second buffer updates the second data to the result of the butterfly operation corresponding to the second data.

7. The memory device according to any one of claims 1 to 6, wherein: The operation comprising the plurality of stages comprises at least one of a number theoretic transform operation and a fast Fourier transform operation.

8. The memory device according to any one of claims 1 to 6, wherein: The size of the first data and the size of the second data are determined based on a size of each of the plurality of buffers.

9. The memory device according to any one of claims 1 to 6, further comprising: A line buffer is provided, wherein each of the plurality of buffers has a size smaller than a size of the line buffer.

10. The memory device according to any one of claims 1 to 6, wherein: The memory cell array includes a memory cell array based on a plurality of dynamic random access memories.

11. A method for operating a memory device, the memory device comprising an operator, the method comprising: Receive multiple commands from the host; determining at least one buffer among a plurality of buffers that will store first data and second data corresponding to each of the plurality of commands, respectively; storing the first data and the second data in the determined at least one buffer; as well as A butterfly operation is performed based on at least one of the first data and the second data.

12. The operating method according to claim 11, wherein: The step of storing the first data and the second data in the determined at least one buffer includes: when the operator performs an operation including a plurality of stages, the plurality of buffers store at least one of input data and output data of the operation including the plurality of stages.

13. The operating method according to claim 11, further comprising: When the operation of the corresponding stage of the corresponding command among the plurality of commands is completed, the first buffer storing the first data updates the first data to the result of the first butterfly operation corresponding to the first data, and The second buffer storing the second data updates the second data to a result of a second butterfly operation corresponding to the second data.

14. The operating method according to claim 11, wherein: The step of receiving the plurality of commands from the host comprises receiving a first operation command and a second operation command, The first operation command indicates an operation between data in the same buffer, and the second operation command indicates an operation between data in different buffers.

15. The operating method according to claim 14, wherein: The step of receiving the plurality of commands from the host includes receiving a second operation command from the host, and the step of storing the first data and the second data in the determined at least one buffer includes storing the first data corresponding to the second operation command in the first buffer and storing the second data corresponding to the second operation command in a second buffer different from the first buffer, and The operation method further includes: when the operation of the corresponding stage including the second operation command is completed, the first buffer updates the first data to the result of the butterfly operation corresponding to the first data, and the second buffer updates the second data to the result of the butterfly operation corresponding to the second data.

16. The operating method according to claim 14, wherein: The step of receiving the plurality of commands from the host includes receiving a first operation command from the host, and the step of storing the first data and the second data in the determined at least one buffer includes storing the first data and the second data corresponding to the first operation command in the second buffer, and The operation method further includes: when the operation of the corresponding stage including the first operation command is completed, the second buffer updates the first data to the result of the butterfly operation corresponding to the first data, and the second buffer updates the second data to the result of the butterfly operation corresponding to the second data.

17. The operating method according to claim 12, wherein: The operation comprising the plurality of stages comprises at least one of a number theoretic transform operation and a fast Fourier transform operation.

18. The operating method according to any one of claims 11 to 17, wherein: The size of the first data and the size of the second data are determined based on a size of each of the plurality of buffers.

19. The operating method according to any one of claims 11 to 17, wherein: The memory device includes a row buffer, wherein the plurality of buffers have a size smaller than a size of the row buffer.

20. The operating method according to any one of claims 11 to 17, wherein: The memory device includes a memory cell array based on a plurality of dynamic random access memories.

21. A non-transitory computer-readable storage medium storing instructions, which, when executed by a processor, cause the processor to perform the operating method according to any one of claims 11 to 20.

22. A method of operating a memory device, comprising: storing, by a memory device, first data in a first buffer and second data in a second buffer; performing a butterfly operation based on first data in the first buffer and second data in the second buffer by an operator of the memory device; as well as The first data and the second data are updated based on the butterfly operation.

23. The method according to claim 22, further comprising: Based on the result of the butterfly operation, a transform operation including at least one of a number theoretic transform operation and a fast Fourier transform operation is performed.

24. The method according to claim 23, wherein: The steps to perform the transformation operation include: During a first stage of the transform operation, performing a first preliminary butterfly operation based on data in the first buffer; and During the first stage of the transform operation, a second preliminary butterfly operation is performed based on the data in the second buffer, wherein the butterfly operation is performed during the second stage of the transform operation.

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