Expansion card time sequence management device and method, computer equipment and storage medium

Abstract

The invention relates to an expansion card time sequence management device and method, computer equipment and a storage medium. The device comprises an expansion chip module and a complex programmable logic device which are arranged on an expansion card module, the complex programmable logic device is connected with a mainboard through a bus, the expansion card module is further provided with a power supply module, the power supply module comprises a power supply output end, and the power supply output end is connected with the expansion chip module. The complex programmable logic device comprises a power supply input end, a reset signal output end, a debugging signal output end and a heartbeat signal input end, and the expansion chip module comprises a heartbeat signal output end, a reset signal input end and a debugging signal input end. By adopting the method, the use of a hardware circuit can be reduced, the layout space can be optimized, and logic time sequence control can be completed.

Description

Technical Field

[0001] The present application relates to the field of chip timing control technology, and in particular to an expansion card timing management device, method, computer equipment and storage medium. Background Art

[0002] SAS (Serial Attached SCSI) is a disk connection technology. An expansion card can connect multiple SAS devices to a limited number of Host ports. In complex computer systems, servers, and embedded devices, expansion cards are a key component for expanding interfaces and resources, and are usually used to connect and manage multiple peripheral devices. The expansion chip on the expansion card is the core main control chip, and its own power-on and management have corresponding timing requirements. The specific hardware representation is that some specific pins of the Expander chip have input and output requirements under specific timing, such as: Reset signal, DFT_IN pin, etc. In order to meet the input and output timing requirements of the expansion chip for pins and signals, the requirements of logical timing control are completed by adding hardware delay circuits.

[0003] However, the expansion card timing in this method cannot be adjusted freely, and an additional peripheral circuit is required, which increases the cost and occupies the design space of the PCB. Therefore, it is very necessary to provide a new expansion card logic timing management device to address the above defects in the prior art. Summary of the invention

[0004] Based on this, it is necessary to provide an expansion card timing management device, method, computer equipment and storage medium that can not only reduce hardware circuits but also complete logical timing control in order to solve the above technical problems.

[0005] In one aspect, an expansion card timing management device is provided, the device comprising:

[0006] An expansion chip module and a complex programmable logic device are arranged on the expansion card module, the complex programmable logic device is connected to the main board via a bus, the expansion card module is also provided with a power module, the power module includes a power output terminal, the complex programmable logic device includes: a power input terminal, a reset signal output terminal, a debug signal output terminal, and a heartbeat signal input terminal, and the expansion chip module includes: a heartbeat signal output terminal, a reset signal input terminal, and a debug signal input terminal;

[0007] Among them, the power output end of the power module is connected to the power input end of the complex programmable logic device, the reset signal output end of the complex programmable logic device is connected to the reset signal input end of the expansion chip module, the debug signal output end of the complex programmable logic device is connected to the signal input end of the expansion chip module, and the heartbeat signal output end of the expansion chip module is connected to the heartbeat signal input end of the complex programmable logic device.

[0008] In one embodiment, it also includes:

[0009] The mainboard is provided with a baseboard management controller connected to the complex programmable logic device through the bus, and the baseboard management controller is used to control the complex programmable logic device.

[0010] In one embodiment,

[0011] The expansion card module is provided with an external crystal oscillator clock module, the output end of which is connected to the clock signal input end of the complex programmable logic device, wherein the complex programmable logic device is also provided with a timer and a counter for measuring time.

[0012] In one embodiment, an expansion card timing management method for the expansion card timing management device is provided, the method comprising:

[0013] The power module sends a power good signal to the power input terminal of the complex programmable logic device through the output terminal;

[0014] After receiving the power good signal, the complex programmable logic device detects the power good signal to obtain a detection result, wherein the detection result includes: normal power-on and abnormal power-on;

[0015] In response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device;

[0016] A second delay time is set, and a timer is started after the first signal is sent. The complex programmable logic device generates a debugging signal according to the second delay time and an external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module, wherein the second delay time is greater than the first delay time;

[0017] The expansion chip module performs corresponding operations according to the received reset signal and the debugging signal.

[0018] In one embodiment, the invention further includes: after receiving the power good signal, the complex programmable logic device detects the power good signal to obtain a detection result, wherein the detection result includes: normal power-on and abnormal power-on, including:

[0019] The complex programmable logic device initializes a counter and sets a threshold value for the counter;

[0020] The complex programmable logic device periodically samples and detects the power good signal and records each detection result;

[0021] In response to the detection result that the power-on is normal, the counter is incremented by one;

[0022] In response to the detection result being a power-on abnormality, the counter is cleared and the detection is restarted;

[0023] In response to the detection result that the power-on is normal and the value does not reach the threshold of the counter, the next sampling is performed;

[0024] In response to the detection result being that the value of the power-on normal reaches the threshold of the counter, the power good signal is stable power-on normal;

[0025] In response to the detection result indicating that the power-on is normal and the value does not reach the threshold of the counter within the set time period, the power-good signal indicates that the power-on is abnormal.

[0026] In one of the embodiments, in response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device, including:

[0027] Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock;

[0028] The complex programmable logic device starts the timer according to the clock signal to start timing, determines the first trigger time according to the first delay time, and in response to the timer reaching the first trigger time, the complex programmable logic device generates a reset signal;

[0029] The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

[0030] In one embodiment, the complex programmable logic device generates a debugging signal according to a second delay time and an external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module, wherein the second delay time is greater than the first delay time, including:

[0031] Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock;

[0032] The complex programmable logic device starts the timer according to the clock signal to start timing, and determines the second trigger time according to the second delay time;

[0033] In response to the timer time reaching the second trigger time, the complex programmable logic device generates a debugging signal;

[0034] The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

[0035] In one embodiment, the expansion chip module performs corresponding operations according to the received reset signal and the debug signal, and further includes:

[0036] The baseboard management controller sends a detection command to the complex programmable logic device through the bus, wherein the detection command is to detect the operating state of the expansion chip module;

[0037] The complex programmable logic device determines the operating state of the expansion chip module by receiving the heartbeat signal sent by the expansion chip module, including: setting the firmware heartbeat signal frequency of the expansion chip module to indicate the operating state of the expansion chip module firmware;

[0038] Setting the hardware configuration heartbeat signal frequency of the extension chip module to indicate the hardware status of the extension chip module;

[0039] Setting the working mode heartbeat signal frequency of the extension chip module to indicate the current working mode state of the extension chip module;

[0040] Set the abnormal frequency threshold range;

[0041] Measure, by means of the counter and the timer, whether the frequency of each heartbeat signal is within an abnormal frequency threshold range, and obtain a comparison result;

[0042] In response to the firmware heartbeat signal frequency of the expansion chip module exceeding the abnormal frequency threshold range, it indicates that there is a problem with the current working state of the firmware of the expansion chip module;

[0043] In response to an abnormality occurring during the operation of the expansion chip module, the complex programmable logic device reports an abnormality detection result to the baseboard management controller.

[0044] In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0045] The power module sends a power good signal to the power input terminal of the complex programmable logic device through the output terminal;

[0046] After the complex programmable logic device receives the power good signal, the power good signal is detected to obtain a detection result, and the detection result includes: normal power-on and abnormal power-on;

[0047] In response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the delay logic and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device;

[0048] The complex programmable logic device generates a debugging signal according to the delay logic and the external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module;

[0049] The expansion chip module performs corresponding operations according to the received reset signal and the debugging signal.

[0050] In another aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0051] The power module sends a power good signal to the power input terminal of the complex programmable logic device through the output terminal;

[0052] After the complex programmable logic device receives the power good signal, the power good signal is detected to obtain a detection result, and the detection result includes: normal power-on and abnormal power-on;

[0053] In response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the delay logic and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device;

[0054] The complex programmable logic device generates a debugging signal according to the delay logic and the external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module;

[0055] The expansion chip module performs corresponding operations according to the received reset signal and the debugging signal.

[0056] In the above-mentioned expansion card timing management device, the reset signal output end of the complex programmable logic device is connected to the reset signal input end of the expansion chip module, so that the complex programmable logic device can control the reset of the expansion chip module. The debug signal output end of the complex programmable logic device is connected to the debug signal input end of the expansion chip module, so that the complex programmable logic device can control and diagnose the expansion chip module through the debug signal. The complex programmable logic device module and the expansion chip module have clear division of labor on the expansion card. The complex programmable logic device is responsible for control functions such as reset, debugging and heartbeat monitoring, and the expansion chip module provides specific expansion functions. Through this modular design, the system can flexibly replace or upgrade the expansion chip module, so that the expansion card can adapt to the needs of different application scenarios, thereby improving the scalability and flexibility of the system. Timing control is achieved by the time sequence of the two signals. Hardware integration and function sharing are achieved through reasonable port connection relationships, which not only reduces system cost and power consumption, but also improves system reliability, response speed and maintainability. This optimized design is suitable for various application scenarios with high requirements for cost, energy efficiency and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 An application environment diagram of an expansion card timing management method in an embodiment;

[0058] Figure 2 is a structural diagram of an expansion card timing management device in an embodiment;

[0059] Figure 3 A schematic diagram of a flow chart of an expansion card timing management method in one embodiment;

[0060] Figure 4 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0062] In one embodiment, Figure 2As shown, an expansion card timing management device is provided, comprising: an expansion chip module and a complex programmable logic device arranged on the expansion card module, the complex programmable logic device being connected to the main board via a bus, a power module being further arranged on the expansion card module, the power module comprising a power output terminal, the complex programmable logic device comprising: a power input terminal, a reset signal output terminal, a debug signal output terminal, and a heartbeat signal input terminal, the expansion chip module comprising: a heartbeat signal output terminal, a reset signal input terminal, and a debug signal input terminal;

[0063] Among them, the power output end of the power module is connected to the power input end of the complex programmable logic device, the reset signal output end of the complex programmable logic device is connected to the reset signal input end of the expansion chip module, the debug signal output end of the complex programmable logic device is connected to the signal input end of the expansion chip module, and the heartbeat signal output end of the expansion chip module is connected to the heartbeat signal input end of the complex programmable logic device.

[0064] Among them, the power output terminal, power input terminal, reset signal output terminal, debug signal output terminal, heartbeat signal input terminal, heartbeat signal output terminal, reset signal input terminal, and debug signal input terminal realize input and output through OD. OD (Open-Drain) configuration is used to realize the driving and communication of input and output signals. Open-Drain is a type of output configuration, which is generally widely used in digital circuit design. In scenarios such as reset signals and heartbeat signals, it allows multiple devices to share a signal line and pull down the signal when needed. In the high-impedance state, the OD output will not drive the level, and the signal line is pulled to a high level by an external pull-up resistor. Multiple devices can be connected to this line to share the signal; when the OD output is pulled low, the OD configuration will actively pull down the signal line level (output 0), drive the signal line to a low level, and indicate a valid signal. OD allows the device to actively pull down the signal when needed, and return to the high-impedance state when not needed, which avoids the level conflict caused by multiple devices driving the signal at the same time.

[0065] Specifically, through the connection relationship between each port, function integration and resource sharing are achieved, thereby reducing the use of hardware components. Function reuse between modules is achieved, thereby reducing the need for independent hardware components. While reducing manufacturing costs, the circuit layout space is also optimized. Complex programmable logic devices can directly control reset, debug, and heartbeat signals through port connections, thereby reducing design complexity. The design of hardware circuits is simplified, and the dependence of various application requirements on hardware changes is reduced. It can be applied to a variety of scenarios, reducing development and verification work, and reducing operation and maintenance costs.

[0066] In the above-mentioned expansion card timing management device, the reset signal output end of the complex programmable logic device is connected to the reset signal input end of the expansion chip module, so that the complex programmable logic device can control the reset of the expansion chip module. The debug signal output end of the complex programmable logic device is connected to the debug signal input end of the expansion chip module, so that the complex programmable logic device can control and diagnose the expansion chip module through the debug signal. The complex programmable logic device module and the expansion chip module have clear division of labor on the expansion card. The complex programmable logic device is responsible for control functions such as reset, debugging and heartbeat monitoring, and the expansion chip module provides specific expansion functions. Through this modular design, the system can flexibly replace or upgrade the expansion chip module, so that the expansion card can adapt to the needs of different application scenarios, thereby improving the scalability and flexibility of the system. Timing control is achieved by the time sequence of the two signals. Hardware integration and function sharing are achieved through reasonable port connection relationships, which not only reduces system cost and power consumption, but also improves system reliability, response speed and maintainability. This optimized design is suitable for various application scenarios with high requirements for cost, energy efficiency and reliability.

[0067] In one embodiment, a baseboard management controller connected to the complex programmable logic device through the bus is disposed on the mainboard, and the baseboard management controller is used to control the complex programmable logic device.

[0068] Specifically, the motherboard is connected to the complex programmable logic device through the baseboard management controller and the bus, wherein the baseboard management controller can monitor the status of the complex programmable logic device in real time through the bus, such as power status, heartbeat signal, reset signal, etc. This enables the system administrator to remotely obtain the operation status of the system, which greatly enhances the controllability of the system. The combination of the baseboard management controller and the complex programmable logic device not only simplifies the hardware design and improves the system integration, but also significantly enhances the stability, maintainability and adaptability of the system.

[0069] In one embodiment, the expansion card module is provided with an external crystal oscillator clock module, the output end of the external crystal oscillator clock module is connected to the clock signal input end of the complex programmable logic device, wherein the complex programmable logic device is also provided with a timer and a counter for measuring time.

[0070] Specifically, by configuring an external crystal oscillator clock module on the expansion card module and connecting it to a complex programmable logic device, the timer and counter of the complex programmable logic device can measure time more accurately and achieve precise time interval control. The system obtains a high-precision time reference, which significantly enhances the system's time control accuracy, response speed, stability and reliability. In addition, this design enhances the independence and scalability of the system, so that the expansion card module no longer relies on the motherboard clock, and is suitable for scenarios with high requirements for high precision and stability.

[0071] The expansion card timing management method based on the expansion card timing management device provided in this application can be applied to Figure 1 In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The complex programmable logic device detects the power good signal sent by the power module, and after the detection result is that the power is normal, it generates a reset signal and a debug signal through the delay logic and the external crystal oscillator clock signal, and sends the reset signal and the debug signal to the expansion chip, and the expansion chip performs corresponding operations according to the signal. Among them, the terminal 102 can be but not limited to various personal computers and laptops, and the server 104 can be implemented by an independent server or a server cluster composed of multiple servers.

[0072] In one embodiment, an expansion card timing management method based on an expansion card timing management device includes:

[0073] Step 202: The power module sends a power good signal to the power input terminal of the complex programmable logic device through the output terminal.

[0074] Specifically, the power module generates a power good signal when powered on and transmits it to the complex programmable logic device. This signal indicates that the power supply has reached a stable working state and indicates to the complex programmable logic device that the system can start the startup process.

[0075] Step 204: After the complex programmable logic device receives the power good signal, the power good signal is detected to obtain a detection result, and the detection result includes: normal power-on and abnormal power-on.

[0076] Specifically, by detecting the power signal status, the CPLD can accurately determine whether the startup conditions are met. If the power supply is abnormal, such as unstable or low voltage, the CPLD will prevent the startup process to avoid potential risks. This detection step provides critical fault protection for the system and improves safety during startup.

[0077] Step 206, in response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device.

[0078] Specifically, when the complex programmable logic device detects that the power-on is normal, a waiting time value is set. When the waiting time value is reached, the power signal is stable, and a reset signal is generated through delay logic and an external crystal oscillator clock to ensure that the system resets the expansion chip module only after the power supply is stable. The external crystal oscillator clock provides a high-precision time reference for the generation of the reset signal to ensure the accuracy of the timing of the reset signal. Through the delay logic, the complex programmable logic device can send a reset signal only after the power supply has been stable for a period of time, avoiding false resets caused by transient power fluctuations or unstable power rise. This mechanism can significantly improve the startup stability of the system and ensure that the expansion chip module enters the correct startup state.

[0079] Step 208, setting a second delay time, starting a timer after the first signal is sent, the complex programmable logic device generates a debugging signal according to the second delay time and the external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic module, wherein the second delay time is greater than the first delay time.

[0080] Specifically, after completing the reset signal, the complex programmable logic device generates a debug signal through delay logic and an external crystal oscillator clock to instruct the expansion chip module to enter the debug state or perform initialization configuration. The generation of the debug signal is also precisely controlled by the crystal oscillator clock to ensure that it enters the debug state according to the set timing after the reset is completed, avoiding conflicts between the reset and debug signals. This step ensures that the expansion chip module receives the debug signal at the correct time so that the necessary initialization, configuration and self-test operations can be performed, thereby improving the debugging effect and the overall startup success rate of the system.

[0081] Step 210: The expansion chip module performs corresponding operations according to the received reset signal and the debugging signal.

[0082] Specifically, the reset signal and the debug signal cooperate with each other to enable the expansion chip module to complete reset and initialization in sequence and enter the correct working state. The signal sequence ensures that the state of the expansion chip module is clear and the configuration is correct, reducing failures caused by operational confusion or initialization errors during the startup process, thereby improving the stability and reliability of the system.

[0083] Specifically, the complex programmable logic device generates reset signals and debug signals based on delay logic and an external crystal oscillator clock. This timing mechanism ensures that the control signal is sent after the power supply is completely stable, effectively reducing the impact of power supply fluctuations or interference during the startup process on the system and improving the stability of the system. The reset signals and debug signals generated by the complex programmable logic device are precisely delayed to ensure that the expansion chip module completes initialization according to the specified timing. This design avoids initialization failures or abnormalities caused by signal asynchrony or timing errors, and ensures that the expansion chip module can start correctly and enter the working state. Through the detection of the power state and precise delay control, the correct timing of the signal is ensured, and the impact of transient power supply fluctuations on the system is reduced, thereby improving the anti-interference ability of the system. The external crystal oscillator provides a stable frequency reference, so that the generation of reset and debug signals is not easily affected by external interference, especially under complex electromagnetic environment conditions, it can still operate stably, improving the overall reliability of the system. The complex programmable logic device automatically generates reset and debug signals without manual intervention, greatly reducing the complexity of daily maintenance, while improving the ease of use and reliability of the system.

[0084] This design makes the system more stable and reliable during startup and operation through real-time detection of power supply status, precise control of delay logic, and synchronous signal transmission. The centralized management function of complex programmable logic devices not only optimizes the signal transmission path and reduces hardware requirements, but also improves the system's self-monitoring and automatic recovery capabilities, making the overall maintenance of the system easier.

[0085] In one embodiment, after receiving the power good signal, the complex programmable logic device detects the power good signal to obtain a detection result, wherein the detection result includes: normal power-on and abnormal power-on, including:

[0086] The complex programmable logic device initializes a counter and sets a threshold value for the counter;

[0087] The complex programmable logic device periodically samples and detects the power good signal and records each detection result;

[0088] In response to the detection result that the power-on is normal, the counter is incremented by one;

[0089] In response to the detection result being a power-on abnormality, the counter is cleared and the detection is restarted;

[0090] In response to the detection result that the power-on is normal and the value does not reach the threshold of the counter, the next sampling is performed;

[0091] In response to the detection result being that the value of the power-on normal reaches the threshold of the counter, the power good signal is stable power-on normal;

[0092] In response to the detection result indicating that the power-on is normal and the value does not reach the threshold of the counter within the set time period, the power-good signal indicates that the power-on is abnormal.

[0093] Specifically, assuming that the counter threshold of the complex programmable logic device is set to 5, the sampling period is 10 milliseconds, and the system sets a 50 millisecond detection time window for the detection of the power good signal. The specific detection process is as follows:

[0094] Counter initialization: After receiving the power good signal, the complex programmable logic device initializes the counter to 0 and sets the threshold to 5. Periodic sampling and detection: The complex programmable logic device samples the power good signal every 10 milliseconds and records the sampling results each time.

[0095] Testing process:

[0096] The first sampling: the detection result is that the power-on is normal, the counter increases by 1, and the counter value is 1.

[0097] Second sampling: The detection result is power-on abnormality, the counter is cleared, and the detection starts again.

[0098] The third sampling: the detection result is that the power-on is normal, the counter increases by 1, and the counter value is 1.

[0099] From the 4th to the 8th sampling: the detection result continues to be normal power-on, and the counter accumulates successively and reaches 5 (that is, reaches the threshold).

[0100] Determine the power supply status: When the counter value reaches the threshold, that is, the five consecutive sampling results are normal power-on, the complex programmable logic device determines the power-good signal as stable power-on normal.

[0101] If the counter value fails to reach the threshold value within the detection time of 50 milliseconds, the complex programmable logic device determines that the power-on is abnormal.

[0102] By adjusting the threshold and sampling period of the counter, the stability requirements of the power supply detection can be flexibly set according to the specific system requirements. For example, in an environment with high stability requirements, a higher threshold and a longer detection time can be set to enhance the strictness of power supply detection; in a low-power system, the requirements can be appropriately lowered to improve the response speed. This flexibility makes the power supply detection design more adaptable. If the system frequently misjudges the power-on state, the reset signal will be frequently triggered, thus affecting the normal operation of the system. Through the above detection mechanism, the complex programmable logic device will not generate a reset signal before confirming the stability of the power supply, preventing the frequent reset problem caused by short-term fluctuations in the power supply state, and ensuring smooth startup and stable operation of the system.

[0103] In one embodiment, in response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device, including:

[0104] Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock;

[0105] The complex programmable logic device starts the timer according to the clock signal to start timing, determines the first trigger time according to the first delay time, and in response to the timer reaching the first trigger time, the complex programmable logic device generates a reset signal;

[0106] The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

[0107] Specifically, the following parameter configurations are set: the frequency of the external crystal oscillator clock is 10 MHz (i.e., each clock cycle is 0.1 microseconds). The first timing duration is set to 50 milliseconds, which is used to wait for the power supply to further stabilize. Clock signal transmission: The external crystal oscillator generates a 10 MHz high-precision clock signal, which is transmitted to the clock signal input terminal of the complex programmable logic device through its output terminal as the system time base. Timer starts timing: When the complex programmable logic device detects a good power signal (PG signal) and confirms that the power-on state is normal, the timer starts timing driven by the 10 MHz clock signal. The timer sets the first timing end time to 50 milliseconds, that is, the timer needs to accumulate 500,000 clock cycles before reaching the set delay time. Timing is completed and a reset signal is generated: When the timer reaches 50 milliseconds (accumulated 500,000 clock cycles), the complex programmable logic device generates a reset signal to ensure that the reset process of the expansion chip module is started after the power supply is completely stable. Send a reset signal: The complex programmable logic device transmits the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal, thereby resetting and initializing the expansion chip module.

[0108] Through the delayed reset design combining an external crystal oscillator clock and a timer, this embodiment ensures that the expansion chip module is reset after the power supply is completely stable, improves the startup security and anti-interference capability of the system, optimizes the control accuracy of the reset timing, has good compatibility and maintainability, and is suitable for a variety of complex application scenarios.

[0109] In one embodiment, the complex programmable logic device generates a debugging signal according to a second delay time and an external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module, wherein the second delay time is greater than the first delay time, including:

[0110] Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock;

[0111] The complex programmable logic device starts the timer according to the clock signal to start timing, and determines the second trigger time according to the second delay time;

[0112] In response to the timer time reaching the second trigger time, the complex programmable logic device generates a debugging signal;

[0113] The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

[0114] Specifically, it should be understood that the debug signal generating step is the same as the reset signal generating step described above, so it will not be described in detail here.

[0115] By delaying the generation of debugging signals, the system is ensured to enter the debugging state only after completing the power-on stability detection and reset. Through the delay logic, the debugging process is prevented from being affected by startup fluctuations, and the stability and reliability of system debugging are improved.

[0116] In one embodiment, the expansion chip module performs corresponding operations according to the received reset signal and the debug signal, and further includes:

[0117] The baseboard management controller sends a detection command to the complex programmable logic device through the bus, wherein the detection command is to detect the operating state of the expansion chip module;

[0118] The complex programmable logic device determines the operating state of the extension chip module by receiving the heartbeat signal sent by the extension chip module, including:

[0119] Setting the firmware heartbeat signal frequency of the expansion chip module to indicate the working status of the expansion chip module firmware;

[0120] Setting the hardware configuration heartbeat signal frequency of the extension chip module to indicate the hardware status of the extension chip module;

[0121] Setting the working mode heartbeat signal frequency of the extension chip module to indicate the current working mode state of the extension chip module;

[0122] Set the abnormal frequency threshold range;

[0123] Measure, by means of the counter and the timer, whether the frequency of each heartbeat signal is within an abnormal frequency threshold range, and obtain a comparison result;

[0124] In response to the firmware heartbeat signal frequency of the expansion chip module exceeding the abnormal frequency threshold range, it indicates that there is a problem with the current working state of the firmware of the expansion chip module;

[0125] In response to an abnormality occurring during the operation of the expansion chip module, the complex programmable logic device reports an abnormality detection result to the baseboard management controller.

[0126] Specifically, assume that the system sets the following heartbeat signal monitoring parameters:

[0127] Firmware heartbeat signal frequency: set to 10Hz, used to indicate the firmware running status of the expansion chip.

[0128] Hardware configuration heartbeat signal frequency: set to 5Hz, indicating whether the expansion chip hardware configuration is normal.

[0129] Working mode heartbeat signal frequency: set to 1Hz, indicating the status of the current working mode of the expansion chip.

[0130] Abnormal frequency threshold range: Each heartbeat signal is allowed to have a deviation of ±10%.

[0131] In the actual monitoring process, the complex programmable logic device will perform the following steps: The baseboard management controller sends a detection command: The baseboard management controller sends a detection command to the complex programmable logic device through the bus, requesting to monitor the various operating states of the expansion chip. Heartbeat signal frequency measurement: When the expansion chip module is operating normally, the complex programmable logic device receives various heartbeat signals at regular intervals and measures the frequency of each heartbeat signal through a counter and a timer. For example: The firmware heartbeat signal should be close to 10Hz, and the complex programmable logic device verifies that the receiving frequency is within the range of 9-11Hz. The hardware configuration heartbeat signal should be close to 5Hz, and the verification range is 4.5-5.5Hz. The working mode heartbeat signal should be 1Hz, and the verification range is 0.9-1.1Hz. Frequency abnormality judgment: The complex programmable logic device compares the actual frequency of each heartbeat signal with the set frequency range. For example: If the firmware heartbeat signal frequency is 8Hz (lower than the threshold range), the complex programmable logic device identifies that the firmware state is abnormal. If the hardware configuration heartbeat signal frequency is abnormal (such as 3Hz), it is judged as a hardware configuration abnormality. Abnormal result reporting: When any heartbeat signal exceeds the set threshold range, the complex programmable logic device immediately reports the abnormal detection result to the baseboard management controller so that the baseboard management controller can respond in time and may take measures such as restarting or isolating the faulty chip.

[0132] By detecting different types of heartbeat signal frequencies, multi-level status monitoring of firmware, hardware, and working modes can be achieved, greatly improving the accuracy of monitoring and enabling the system to quickly capture abnormal conditions. Complex programmable logic devices can quickly identify firmware or hardware anomalies by monitoring heartbeat frequencies in real time, preventing potential faults from spreading further, thereby ensuring the overall stable operation of the system. Real-time heartbeat detection uses a feedback mechanism to warn when a fault occurs, which can reduce the impact of interruptions caused by restarting the entire system and improve system continuity. Allowing adjustment of the frequency and threshold range of different heartbeat signals allows the monitoring solution to be extended to more types of expansion chip modules or other hardware units, enhancing the compatibility of the system.

[0133] This embodiment uses complex programmable logic devices to monitor the frequency of the heartbeat signal of the expansion chip module, and provides an accurate and real-time abnormal warning mechanism based on multi-level detection of firmware, hardware configuration and working mode. This method not only improves the stability and reliability of the system, but also significantly reduces maintenance costs and operating risks, and is suitable for a variety of complex system management scenarios.

[0134] In one embodiment, in response to the firmware heartbeat signal frequency of the expansion chip module exceeding the abnormal frequency threshold range, it indicates that there is a problem with the current firmware working state of the expansion chip module, and further includes:

[0135] In response to the complex programmable logic device detecting that the firmware heartbeat signal of the expansion chip module exceeds the abnormal frequency threshold range;

[0136] The complex programmable logic device reports the abnormal situation to the baseboard management controller;

[0137] Specifically, when an abnormality is detected, the complex programmable logic device reports the abnormality to the baseboard management controller through the bus, notifying it that there is a problem with the firmware of the expansion chip module.

[0138] After receiving the report, the baseboard management controller sends a reset instruction to the complex programmable logic device through the bus, wherein the reset instruction is to perform a reset operation on the expansion chip;

[0139] Specifically, after receiving the abnormality report, the baseboard management controller sends a reset instruction to the complex programmable logic device through the bus, requesting a reset operation to be performed on the expansion chip module.

[0140] The complex programmable logic device receives a reset instruction, lowers the signal strength of the reset signal outputted from the reset signal output terminal of the complex programmable logic device, and triggers a reset operation;

[0141] Specifically, after receiving the reset instruction, the complex programmable logic device controls the reset signal strength of the reset signal output terminal and pulls it down to trigger the reset operation of the expansion chip. Through logic design, the complex programmable logic device can control the reset signal to remain at a low level for a period of time (for example, several clock cycles) to ensure that the reset of the expansion chip module can be effectively triggered.

[0142] After the complex programmable logic device waits for a preset time to arrive, the signal strength of the reset signal is released;

[0143] Specifically, the complex programmable logic device waits for a preset period of time to ensure that the reset process of the expansion chip is completed. After the reset is completed, the complex programmable logic device restores the reset pin to a high level or a high impedance state, so that the expansion chip restarts normally.

[0144] The complex programmable logic device re-detects the firmware heartbeat signal frequency of the expansion chip module; obtains a detection result, wherein the detection result includes: a normal heartbeat signal and an abnormal heartbeat signal;

[0145] In response to the detection result of the complex programmable logic device being that the heartbeat signal is normal, reporting to the baseboard management controller;

[0146] In response to the detection result of the complex programmable logic device being that the heartbeat signal is abnormal, the error is recorded and reported to the baseboard management controller.

[0147] Specifically, after the expansion chip is reset, the complex programmable logic device restarts the heartbeat signal detection process and monitors the frequency of its firmware heartbeat signal. If the detected heartbeat signal frequency returns to the normal range, the complex programmable logic device reports to the baseboard management controller that the reset is successful and the expansion chip returns to normal. If the heartbeat signal is still abnormal, the complex programmable logic device records the error and reports the abnormal state to the baseboard management controller for further processing.

[0148] Through the automatic detection and fast recovery mechanism, the system realizes the rapid response and reset control to the abnormal state, and improves the reliability and automation level of the system. As the core control unit, the complex programmable logic device ensures the stable operation of the expansion chip module through the monitoring of the heartbeat signal, the control of the reset pin and the cooperation with the baseboard management controller.

[0149] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0150] The specific definition of the expansion card timing management device can be found in the definition of the expansion card timing management method above, which will not be repeated here. Each module in the above expansion card timing management device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0151] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 4As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store expansion card data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for managing the timing of an expansion card is implemented.

[0152] Those skilled in the art will understand that Figure 2 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0153] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0154] The power module sends a power good signal to the power input terminal of the complex programmable logic device through the output terminal;

[0155] After receiving the power good signal, the complex programmable logic device detects the power good signal to obtain a detection result, wherein the detection result includes: normal power-on and abnormal power-on;

[0156] In response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device;

[0157] The complex programmable logic device generates a debugging signal according to the second delay time and the external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module, wherein the second delay time is greater than the first delay time;

[0158] The expansion chip module performs corresponding operations according to the received reset signal and the debugging signal.

[0159] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0160] The complex programmable logic device initializes a counter and sets a threshold value for the counter;

[0161] The complex programmable logic device periodically samples and detects the power good signal and records each detection result;

[0162] In response to the detection result that the power-on is normal, the counter is incremented by one;

[0163] In response to the detection result being a power-on abnormality, the counter is cleared and the detection is restarted;

[0164] In response to the detection result that the power-on is normal and the value does not reach the threshold of the counter, the next sampling is performed;

[0165] In response to the detection result being that the value of the power-on normal reaches the threshold of the counter, the power good signal is stable power-on normal;

[0166] In response to the detection result indicating that the power-on is normal and the value does not reach the threshold of the counter within the set time period, the power-good signal indicates that the power-on is abnormal.

[0167] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0168] Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock;

[0169] The complex programmable logic device starts the timer according to the clock signal to start timing, sets the first timing end time, and obtains the first timing duration;

[0170] In response to the timer reaching the first timing end time, the complex programmable logic device generates a reset signal according to the first timing duration;

[0171] The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

[0172] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0173] The power module sends a power good signal to the power input terminal of the complex programmable logic device through the output terminal;

[0174] After receiving the power good signal, the complex programmable logic device detects the power good signal to obtain a detection result, wherein the detection result includes: normal power-on and abnormal power-on;

[0175] In response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device;

[0176] The complex programmable logic device generates a debugging signal according to the second delay time and the external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module, wherein the second delay time is greater than the first delay time;

[0177] The expansion chip module performs corresponding operations according to the received reset signal and the debugging signal.

[0178] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0179] Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock;

[0180] The complex programmable logic device starts the timer according to the clock signal to start timing, sets a second timing end time, and obtains a second timing duration, wherein the second timing duration is greater than the first timing duration;

[0181] In response to the timer reaching the second timing end time, the complex programmable logic device generates a debugging signal according to the second timing duration;

[0182] The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

[0183] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0184] The baseboard management controller sends a detection command to the complex programmable logic device through the bus, wherein the detection command is to detect the operating state of the expansion chip module;

[0185] The complex programmable logic device determines the operating state of the expansion chip module by receiving the heartbeat signal sent by the expansion chip module, including: setting the firmware heartbeat signal frequency of the expansion chip module to indicate the operating state of the expansion chip module firmware;

[0186] Setting the hardware configuration heartbeat signal frequency of the extension chip module to indicate the hardware status of the extension chip module;

[0187] Setting the working mode heartbeat signal frequency of the extension chip module to indicate the current working mode state of the extension chip module;

[0188] Set the abnormal frequency threshold range;

[0189] Measure, by means of the counter and the timer, whether the frequency of each heartbeat signal is within an abnormal frequency threshold range, and obtain a comparison result;

[0190] In response to the firmware heartbeat signal frequency of the expansion chip module exceeding the abnormal frequency threshold range, it indicates that there is a problem with the current working state of the firmware of the expansion chip module;

[0191] In response to an abnormality occurring during the operation of the expansion chip module, the complex programmable logic device reports an abnormality detection result to the baseboard management controller.

[0192] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the computer program may be stored in a non-volatile computer-readable storage medium, and the computer program may include the process of the embodiments of the above-mentioned methods when it is executed. Among them, any reference to memory, storage, database or other medium used in the embodiments provided in the present application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0193] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An expansion card timing management device, characterized in that: include: An expansion chip module and a complex programmable logic device are arranged on the expansion card module, the complex programmable logic device is connected to the main board via a bus, the expansion card module is also provided with a power module, the power module includes a power output terminal, the complex programmable logic device includes: a power input terminal, a reset signal output terminal, a debug signal output terminal, and a heartbeat signal input terminal, and the expansion chip module includes: a heartbeat signal output terminal, a reset signal input terminal, and a debug signal input terminal; Among them, the power output end of the power module is connected to the power input end of the complex programmable logic device, the reset signal output end of the complex programmable logic device is connected to the reset signal input end of the expansion chip module, the debug signal output end of the complex programmable logic device is connected to the signal input end of the expansion chip module, and the heartbeat signal output end of the expansion chip module is connected to the heartbeat signal input end of the complex programmable logic device.

2. The expansion card timing management device according to claim 1, characterized in that: include: The mainboard is provided with a baseboard management controller connected to the complex programmable logic device through the bus, and the baseboard management controller is used to control the complex programmable logic device.

3. The expansion card timing management device according to claim 1, characterized in that: include: The expansion card module is provided with an external crystal oscillator clock module, the output end of which is connected to the clock signal input end of the complex programmable logic device, wherein the complex programmable logic device is also provided with a timer and a counter for measuring time.

4. An expansion card timing management method used in the expansion card timing management device according to any one of claims 1 to 3, characterized in that: include: The power module sends a power good signal to the power input terminal of the complex programmable logic device through the output terminal; After receiving the power good signal, the complex programmable logic device detects the power good signal to obtain a detection result, wherein the detection result includes: normal power-on and abnormal power-on; In response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device; A second delay time is set, and a timer is started after the first signal is sent. The complex programmable logic device generates a debugging signal according to the second delay time and an external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module, wherein the second delay time is greater than the first delay time; The expansion chip module performs corresponding operations according to the received reset signal and the debugging signal.

5. The expansion card timing management method according to claim 4, characterized in that: After receiving the power good signal, the complex programmable logic device detects the power good signal to obtain a detection result, wherein the detection result includes: normal power-on and abnormal power-on, including: The complex programmable logic device initializes a counter and sets a threshold value for the counter; The complex programmable logic device periodically samples and detects the power good signal and records each detection result; In response to the detection result that the power-on is normal, the counter is incremented by one; In response to the detection result being a power-on abnormality, the counter is cleared and the detection is restarted; In response to the detection result that the power-on is normal and the value does not reach the threshold of the counter, the next sampling is performed; In response to the detection result being that the value of the power-on normal reaches the threshold of the counter, the power good signal is stable power-on normal; In response to the detection result indicating that the power-on is normal and the value does not reach the threshold of the counter within the set time period, the power-good signal indicates that the power-on is abnormal.

6. The expansion card timing management method according to claim 5, characterized in that: In response to the detection result that the power-on is normal, the complex programmable logic device generates a reset signal according to the first delay time and the external crystal oscillator clock, and sends the reset signal to the reset signal input end of the expansion chip module through the reset signal output end of the complex programmable logic device, including: Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock; The complex programmable logic device starts the timer according to the clock signal to start timing, determines the first trigger time according to the first delay time, and in response to the timer reaching the first trigger time, the complex programmable logic device generates a reset signal; The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

7. The expansion card timing management method according to claim 6, characterized in that: The complex programmable logic device generates a debugging signal according to a second delay time and an external crystal oscillator clock, and sends the debugging signal to the debugging signal input end of the expansion chip module through the debugging signal output end of the complex programmable logic device module, wherein the second delay time is greater than the first delay time, including: Sending a clock signal to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock; The complex programmable logic device starts the timer according to the clock signal to start timing, and determines the second trigger time according to the second delay time; In response to the timer time reaching the second trigger time, the complex programmable logic device generates a debugging signal; The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

8. The expansion card timing management method according to claim 4, characterized in that: The expansion chip module performs corresponding operations according to the received reset signal and the debug signal, and further includes: The baseboard management controller sends a detection command to the complex programmable logic device through the bus, wherein the detection command is to detect the operating state of the expansion chip module; The complex programmable logic device determines the operating state of the expansion chip module by receiving the heartbeat signal sent by the expansion chip module, including: setting the firmware heartbeat signal frequency of the expansion chip module to indicate the operating state of the expansion chip module firmware; Setting the hardware configuration heartbeat signal frequency of the extension chip module to indicate the hardware status of the extension chip module; Setting the working mode heartbeat signal frequency of the extension chip module to indicate the current working mode state of the extension chip module; Set the abnormal frequency threshold range; Measure, by means of the counter and the timer, whether the frequency of each heartbeat signal is within an abnormal frequency threshold range, and obtain a comparison result; In response to the firmware heartbeat signal frequency of the expansion chip module exceeding the abnormal frequency threshold range, it indicates that there is a problem with the current working state of the firmware of the expansion chip module; In response to an abnormality occurring during the operation of the expansion chip module, the complex programmable logic device reports an abnormality detection result to the baseboard management controller.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 4 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 4 to 8 are implemented.

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