Memory device, control method thereof, and memory system

Abstract

The embodiment of the invention discloses a memory device, a control method thereof and a memory system, and the memory device comprises a memory array which comprises a plurality of memory planes; the plurality of first micro control units (MCU) are coupled with the plurality of storage surfaces in a one-to-one correspondence manner; the calculation sub-circuits are coupled with the plurality of first MCUs; wherein the calculation sub-circuit is configured to sequentially generate a plurality of operation parameters according to a preset sequence in response to an operation control signal; the multiple operation parameters are sent to a corresponding first MCU in a serial mode; and each first MCU in the plurality of first MCUs is configured to execute an operation on the storage surface coupled with the first MCU according to the received corresponding operation parameter.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory device and a control method thereof, and a memory system. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems thereof. Summary of the invention

[0004] According to some aspects of the embodiments of the present disclosure, there is provided a memory device, including:

[0005] A storage array, the storage array comprising a plurality of storage planes;

[0006] A plurality of first microcontroller units (MCUs) coupled to the plurality of storage surfaces in a one-to-one correspondence and a computing subcircuit coupled to the plurality of first MCUs; wherein,

[0007] The calculation subcircuit is configured to: generate a plurality of operation parameters in sequence according to a preset order in response to an operation control signal; and send the plurality of operation parameters in series to a corresponding first MCU;

[0008] Each first MCU among the plurality of first MCUs is configured to perform an operation on a storage plane coupled to the first MCU according to the received corresponding operation parameter.

[0009] In some embodiments, the calculation subcircuit is further configured to sequentially perform the following processes:

[0010] Generate a first operating parameter among the multiple operating parameters, and send the first operating parameter to the corresponding first MCU;

[0011] Generate a second operating parameter among the multiple operating parameters, and send the second operating parameter to the corresponding first MCU;

[0012] Until each of the first MCUs obtains the corresponding operating parameters.

[0013] In some embodiments, the calculation subcircuit includes:

[0014] state machine, computing unit and cache; among them,

[0015] The cache is configured to: store relevant data required to obtain the plurality of operating parameters;

[0016] The state machine is coupled to the computing unit and the cache, respectively, and is configured to: in response to the operation control signal, sequentially obtain the relevant data from the cache in accordance with the preset order, and transmit the relevant data to the computing unit;

[0017] The calculation unit is configured to: perform calculation according to the relevant data to generate the multiple operating parameters; and send the multiple operating parameters in series to the corresponding first MCU.

[0018] In some embodiments, the preset order is a priority order corresponding to each first MCU among the plurality of first MCUs;

[0019] The higher the priority corresponding to the first MCU is, the earlier the state machine obtains the relevant data corresponding to the first MCU from the cache.

[0020] In some embodiments, the memory device further includes a second MCU; the second MCU is configured to: generate the operation control signal in response to an operation request, and control the computing sub-circuit and the first MCU.

[0021] In some embodiments, the state machine includes: at least one first state and at least one second state corresponding to each first state; wherein,

[0022] The second MCU is configured to: write operation information related to the plurality of operation parameters into the state machine in response to the operation control signal; the operation information at least includes: a trigger signal;

[0023] The state machine is configured to: enter the first state corresponding to the operating parameter according to the trigger signal corresponding to the operating parameter in the preset order; enter the corresponding second state in sequence according to the preset state execution order in the first state corresponding to the operating parameter; in each second state, obtain the corresponding related data from the cache, and control the calculation unit to perform calculations according to the corresponding related data; until the last second state is executed, the operating parameter is obtained; and the operating parameter is transmitted to the corresponding first MCU according to the operation address corresponding to the operating parameter.

[0024] In some embodiments, the operation control signal includes an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter includes a read parameter; the calculation subcircuit is configured to: respond to the AMPI read operation control signal of the second MCU, sequentially generate a plurality of read parameters in a preset order; and send the plurality of read parameters serially to the corresponding first MCU;

[0025] Each first MCU among the plurality of first MCUs is configured to perform an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter.

[0026] In some embodiments, when the first MCU performs an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter, the second MCU is configured to perform other operations.

[0027] In some embodiments, the operating parameter comprises one of: a read voltage, a pass voltage.

[0028] In some embodiments, the first MCU includes a first register configured to store an operation parameter sent by the computing sub-circuit.

[0029] In some embodiments, the cache includes: static random access memory.

[0030] According to some aspects of the embodiments of the present disclosure, a control method for a memory device is provided, the memory device comprising:

[0031] A storage array, the storage array comprising a plurality of storage planes;

[0032] a plurality of first micro control units (MCUs) coupled to the plurality of storage surfaces correspondingly and a computing sub-circuit coupled to the plurality of first MCUs;

[0033] The control method comprises:

[0034] In response to the operation control signal, the calculation subcircuit generates a plurality of operation parameters in a preset order; and the calculation subcircuit sends the plurality of operation parameters in series to the corresponding first MCU;

[0035] Each of the plurality of first MCUs is enabled to perform an operation on a storage plane coupled to the first MCU according to the received corresponding operation parameter.

[0036] In some embodiments, the control method further includes causing the calculation subcircuit to sequentially perform the following steps:

[0037] Generate a first operating parameter among the multiple operating parameters, and send the first operating parameter to the corresponding first MCU;

[0038] Generate a second operating parameter among the multiple operating parameters, and send the second operating parameter to the corresponding first MCU;

[0039] Until each of the first MCUs obtains the corresponding operating parameters.

[0040] In some embodiments, the calculation subcircuit includes:

[0041] A state machine, a computing unit and a cache; wherein the state machine is coupled to the computing unit and the cache respectively; and the control method comprises:

[0042] enabling the cache to store relevant data required to obtain the plurality of operating parameters;

[0043] In response to the operation control signal, the state machine sequentially obtains the relevant data from the cache in the preset order and transmits the relevant data to the computing unit;

[0044] The calculation unit is enabled to perform calculation according to the relevant data to generate the multiple operating parameters; and the multiple operating parameters are sent serially to the corresponding first MCU.

[0045] In some embodiments, the preset order is a priority order corresponding to each first MCU among the plurality of first MCUs;

[0046] The higher the priority corresponding to the first MCU is, the earlier the state machine obtains the relevant data corresponding to the first MCU from the cache.

[0047] In some embodiments, the control method further includes:

[0048] The operation control signal is generated in response to an operation request, so that the second MCU of the memory device controls the calculation sub-circuit and the first MCU.

[0049] In some embodiments, the state machine includes: at least one first state and at least one second state corresponding to each first state; the control method includes:

[0050] In response to the operation control signal, the second MCU writes operation information related to the plurality of operation parameters into the state machine; the operation information at least includes: a trigger signal;

[0051] According to the preset sequence, the state machine enters the first state corresponding to the operating parameter according to the trigger signal corresponding to the operating parameter; in the first state corresponding to the operating parameter, the state machine enters the corresponding second state in sequence according to the preset state execution sequence; in each second state, the corresponding related data is obtained from the cache, and the calculation unit is controlled to perform calculations according to the corresponding related data; until the last second state is executed, the operating parameter is obtained; and the operating parameter is transmitted to the corresponding first MCU according to the operation address corresponding to the operating parameter.

[0052] In some embodiments, the operation control signal comprises an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter comprises a read parameter;

[0053] The control method comprises:

[0054] In response to the AMPI read operation control signal of the second MCU, the calculation subcircuit generates a plurality of the read parameters in sequence according to a preset order; and sends the plurality of read parameters in series to the corresponding first MCU;

[0055] Each of the plurality of first MCUs is enabled to perform an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter.

[0056] In some embodiments, the control method further includes:

[0057] When the first MCU performs an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter, the second MCU is configured to perform other operations.

[0058] In some embodiments, the operating parameter comprises one of: a read voltage, a pass voltage.

[0059] In some embodiments, the first MCU includes a first register; and the control method further includes:

[0060] The first register is enabled to store the operation parameter sent by the calculation sub-circuit.

[0061] In some embodiments, the cache includes:

[0062] Static random access memory.

[0063] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0064] at least one memory device as described above; and

[0065] A memory controller is coupled to the memory device and controls the memory device.

[0066] The embodiment of the present disclosure provides a memory device, which is provided with a plurality of first microcontroller units (MCUs) coupled to a plurality of storage planes in a storage array in a one-to-one correspondence, and a computing subcircuit coupled to the plurality of first MCUs; the computing subcircuit is configured to: generate a plurality of operating parameters in sequence in accordance with a preset order in response to an operation control signal such as reading, programming or erasing; and send the plurality of operating parameters in series to the corresponding first MCU; each of the plurality of first MCUs is configured to: perform an operation on the storage plane coupled to the first MCU according to the received corresponding operating parameters. On the one hand, a first MCU is configured for each storage plane, and the first MCU can be used to realize a separate control of the storage plane corresponding to it, which is conducive to realizing the synchronous operation of the plurality of storage planes and the separate asynchronous operation of each storage plane, thereby improving the operation rate of the memory device. On the other hand, the operation parameters of the memory device are stored in a cache to reduce the setting of registers in the computing subcircuit, reduce the occupied area of ​​the computing subcircuit, and the serial computing subcircuit and the serial operation parameter sending method can reduce the circuit area occupied by the computing subcircuit and the interconnection line between the computing subcircuit and the first MCU; and the operation parameters are generated in sequence and sent to the first MCU, which can reduce the calculation conflict and data transmission blockage. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0068] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0069] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0070] Figure 3 is a schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0071] Figure 4 is a cross-sectional schematic diagram of a memory array including a NAND memory string according to an embodiment of the present disclosure;

[0072] Figure 5 A schematic diagram of an exemplary memory device including a memory array and a peripheral circuit according to an embodiment of the present disclosure;

[0073] Figure 6 A schematic diagram of a memory device including a computing subcircuit for parallel computing according to an embodiment of the present disclosure;

[0074] Figure 7 A schematic diagram of a memory device including a computing subcircuit for serial computing according to an embodiment of the present disclosure;

[0075] Figure 8 A schematic diagram of the state flow of a state machine according to an embodiment of the present disclosure;

[0076] Fig. 9 FIG. 4 is a flow chart of a control method of a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0078] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0079] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0080] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0081] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0082] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0083] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0085] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0086] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0087] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0088] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0089] Figure 3 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0090] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0091] like Figure 3As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0092] like Figure 3As shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data unit for programming operations. The size of one page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in one memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates.

[0093] Figure 4 1 shows a cross-sectional schematic diagram of an exemplary memory array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory array 301.

[0094] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0095] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0096] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0097] Return to reference Figure 3, the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0098] The page buffer / sense amplifier 504 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0099] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the selected word line(s) 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boost voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0100] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boosting stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boosting voltage, etc.; in the channel boosting stage, the channel boosting voltage may be applied to the selected word line; in the programming pulse stage, the target voltage for each programming may be applied to the selected word line. In the recovery stage, the voltage of both the unselected word line and the selected word line may be reduced to the corresponding voltage, such as Vcc, Vdd. In the recovery stage, the voltage may be reduced to the corresponding voltage by one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage, and maintaining the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0101] The control logic 512 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the storage array 301 or relay or buffer data from the storage array 301.

[0102] In some embodiments, Figure 3 As shown, the memory device 104 (or memory device 300) may include a memory array 301 and a peripheral circuit 302. The memory array 301 and the peripheral circuit 302 may be arranged on the same wafer, that is, the memory array and the peripheral circuit 302 are arranged on the same die to form a chip. The memory array 301 and the peripheral circuit 302 may be arranged on different wafers, that is, the memory array Die and the peripheral circuit Die are hybrid-bonded to form a chip. A memory device 104 may be packaged into multiple chips according to the designed storage capacity. In the semiconductor manufacturing process, a wafer includes multiple Dies, and adjacent Dies are separated by cutting paths. The wafer is cut along the cutting paths to obtain Dies, and then the Dies are packaged to form chips for use in integrated circuits.

[0103] A Die of the embodiment of the present disclosure may or may not include the peripheral circuit 302. The memory array 301 may include at least one memory plane. Each Plane may include multiple pages 320. The memory cells on each page 320 share a word line. Each page 320 may be used as the minimum unit of read and write operations. Each Plane may be divided into multiple memory blocks according to the diagram. Each block may be used as the minimum unit of erase operation. It should be noted that the peripheral circuit 302 of the embodiment of the present disclosure is an integral device defined for the entire memory array 301. For each memory plane, there may be a corresponding identical partial circuit or a shared partial circuit, which all belong to the integral peripheral circuit 302. Exemplarily, multiple memory planes may be coupled to one peripheral circuit 302; or each memory plane may be coupled to one peripheral circuit 302. The memory controller 106 controls each peripheral circuit 302 to access the corresponding memory plane.

[0104] According to some aspects of the embodiments of the present disclosure, Figure 6 A schematic diagram of a memory device 104 is provided, referring to Figure 6 As shown, the memory device 104 may include:

[0105] A storage array, wherein the storage array includes a plurality of storage planes; the storage array may include Figure 3 The storage array 301 in;

[0106] A plurality of first microcontroller units (MCUs) coupled to the plurality of storage surfaces in one-to-one correspondence, and a computing subcircuit 620 coupled to the plurality of first MCUs 610; wherein the computing subcircuit 620 is configured to: generate a plurality of operating parameters in sequence according to a preset order in response to an operation control signal, and send the plurality of operating parameters to the corresponding first MCU 610 in parallel; each of the plurality of first MCUs 610 is configured to: perform an operation on the storage surface coupled to the first MCU 610 according to the received corresponding operating parameters. The plurality of first MCUs 610 and the computing subcircuit 620 may be part of the peripheral circuit 302.

[0107] In some embodiments, reference Figure 6 As shown, each first MCU 610 includes a first register 611 for storing the operating parameters sent by the calculation subcircuit 620. The operating parameters can be sent to each first MCU 610 in a parallel connection manner and written into the first register 611 for storage and use. In this way, the first MCU 610 can be used to realize the individual control of the storage plane corresponding to it, which is conducive to the synchronous operation of multiple storage planes and the individual asynchronous operation of each storage plane, thereby improving the operation rate of the memory device 104. The peripheral circuit 302 also includes a second register 641 coupled to the calculation subcircuit 620. The second register 641 can be coupled to Figure 6 In the first bus 641 (MBUS) shown in FIG. , a plurality of first MCUs 610 may also be coupled to the first bus 641, and the first bus 641 may be used to transmit operation control signals, initial parameters, and operation parameters or other parameters. In some other embodiments, the second register 641 may be a part of the calculation subcircuit 620, in which case the calculation subcircuit 620 includes the second register 641 and a calculation unit coupled to the second register 641, and the second register 641 is coupled to the first bus 641.

[0108] In some specific embodiments, when the memory device 104 is powered on and reset (Power On Reset, POR), the second register 641 may be configured to store initial parameters obtained from at least one storage plane, for example, from one or more storage blocks in the storage plane; the calculation subcircuit 620 is configured to obtain the initial parameters from the second register 641 and process and generate operating parameters. The calculation subcircuit 620 includes a hardware calculation module, including but not limited to hardware accelerators, adders, or multipliers. The initial parameters may include the initial parameters or timing of the operating voltage for the storage unit of the memory device 104 after testing or optimization at the time of shipment. The operating parameters may include the operating parameters or timing adjusted or calculated based on the initial parameters for the current specific usage situation. For example, the operating parameters may be a read voltage or a corresponding timing, a read voltage or timing after temperature compensation or offset, or a re-read voltage determined after error correction based on the read voltage after a read failure. The first bus 641 may be used to transmit logic control signals such as control commands. The computing subcircuit 620 may be coupled to the plurality of first MCUs 610 in parallel, and may be coupled via a single bus-port (e.g., the first bus 641) and transmit the operating parameters in parallel, or each first MCU 610 and the computing subcircuit 620 may be coupled via a data line, and the plurality of first MCUs 610 and the computing subcircuit 620 may have a plurality of data lines to implement parallel transmission of the operating parameters. Figure 6 An example of data flow between the computing sub-circuit 620 and the first MCU 610 is shown, and no specific limitation is imposed on the physical wiring connection.

[0109] In some other specific embodiments, the peripheral circuit 302 further includes a second MCU 630 coupled to the first bus 641, and the second MCU 630 is configured to generate an operation control signal in response to an operation request, and the operation control signal can be sent to the computing sub-circuit 620 and at least one of the plurality of first MCUs 610 through the first bus 641, and controls the computing sub-circuit 620 to generate an operation parameter, and controls the first MCU 610 to obtain the operation parameter to operate the storage plane; the operation request may come from the memory controller 106. The second MCU 630 may include a third register 631 for storing the operation request sent by the memory controller 106, or storing the operation control signal of the second MCU 630 to the computing sub-circuit 620 and the first MCU 610.

[0110] Combination Figure 5As shown, the first MCU 610 and the second MCU 630 may be part of the control logic 512 of the peripheral circuit 302, and the second MCU 630 is used to receive the operation request of the memory controller 106. In addition, the control logic 512 may also include other control circuits. The first MCU 610 is coupled with the storage surface to control a storage surface, and the second MCU 630 controls each first MCU 610, including but not limited to the operation mode and operation sequence of multiple first MCUs 610 on the storage surface. The first MCU 610 may not be part of the control logic 512, and may be set in the peripheral circuit area close to the storage surface. The second MCU 630 is part of the control logic 512 and is used to control multiple first MCUs 610, thereby optimizing the layout design of the peripheral circuit to reduce the wiring difficulty. It can be understood that the actual physical location of the first MCU 610 and the second MCU 630 in the peripheral circuit of the embodiment of the present disclosure does not limit the realization of its control function.

[0111] Multiple first MCUs 610 are coupled to the second bus 642 (CBUS). After receiving the operation parameters, the first MCU 610 generates relevant control signals according to the operation parameters and the address information of the selected storage unit, page or storage block, and sends them to the voltage generator 510, the row decoder 508 or the column decoder 506 through the second bus 642 to generate corresponding operation voltages to operate the storage plane. The first MCU 610 can be used to control the storage plane corresponding to it separately, which is conducive to the synchronous operation of multiple storage planes and the separate asynchronous operation of each storage plane, thereby improving the operation rate of the memory device 104. The second bus 642 can be used to transmit analog signals such as voltage magnitude, waveform, and application timing, or transmit analog signals such as control instructions to devices that generate analog signals such as different waveforms and timings, such as voltage generators.

[0112] In some specific embodiments, the synchronization operation may be to map the physical addresses of multiple storage planes as a whole to the logical addresses of the host to perform read, program or erase operations. When there are multiple operation requests, the memory device 104 may execute them sequentially. Taking a read operation request as an example, a read operation may be performed on a page of a storage plane, or a read operation may be performed on pages in multiple storage planes that are coupled to the same layer of word lines or located in the same row. The next read operation may be performed after the current read operation is completed.

[0113] In some specific embodiments, the asynchronous operation may be to map each storage plane as a physical address to the logical address of the host to perform a read, program or erase operation. When there are multiple operation requests, the memory device 104 may perform multiple operations simultaneously, and each storage plane may be operated separately according to different logical address-physical address mappings. Taking multiple read operation requests as an example, any page in multiple storage planes may be read separately and simultaneously, thereby improving the response rate of the memory device 104. This read mode may be referred to as asynchronous multi-plane independent (AMPI) reading, which is beneficial to improving the parallel operation efficiency of the memory device 104, and is particularly beneficial to improving the random read performance of the memory device 104. Each storage plane may also perform programming operations and erase operations independently.

[0114] In order to speed up the independent parallel operation of each storage plane in the multiple storage planes, especially when the multiple storage planes need to be operated at the same time, the embodiment of the present disclosure connects the calculation subcircuit 620 to each storage plane in parallel, and the calculation subcircuit 620 also performs parallel calculations inside to generate the operation parameters required by each first MCU 610 and send them to the corresponding first MCU 610 in parallel. For example, Figure 6 The second register 641 and the calculation subcircuit 620 are connected in parallel, so that the calculation subcircuit 620 can simultaneously obtain multiple initial parameters, calculate and generate multiple operation parameters, and send them to the corresponding multiple first MCUs 610 respectively.

[0115] In some actual use embodiments of the memory device 104, as the 3D NAND design becomes more and more complex, the calculation logic of the operating parameters such as the voltage and timing of the device waveform becomes more and more complex with the increase of the integration of the storage surface, the number of second registers increases, the data line setting for realizing the parallel connection between the calculation subcircuit 620 and the second register 641 becomes more and more complex, the data line setting for realizing the parallel connection between the calculation subcircuit 620 and the multiple first MCUs 610 becomes more and more complex, and the number of calculators inside the calculation subcircuit 620 for realizing parallel calculation also increases, all of which will increase the area occupied by the chip device and increase the manufacturing cost. In other actual use embodiments of the memory device 104, the calculation subcircuit 620 adopts parallel calculation to increase the processing speed of the calculation node, but with the increase of the number of calculation levels and the increase of parallel calculation paths, it is more difficult for the calculation subcircuit 620 to unify or converge the timing (or calculation clock cycle) in physical implementation. When the computing subcircuit 620 sends the operation parameters to the multiple first MCUs 610, the address information will be attached, and each first MCU 610 will select the required operation parameters from the sent data according to the address, so even if the operation parameters are sent in parallel, the use of the operation parameters is equivalent to using them in serial mode. Therefore, although the parallel calculation of the computing subcircuit 620 speeds up the calculation speed, the speed of the first MCU 610 controlling the storage plane to perform operations is not improved much, or in other words, the performance is improved by increasing the occupied circuit area, but the operation rate improvement brought by the parallel calculation of the computing subcircuit 620 and the parallel sending of data to the first MCU 610 is over-performance to a certain extent.

[0116] In view of this, according to some aspects of the embodiments of the present disclosure, Figure 7 A memory device 104 is provided, comprising:

[0117] A storage array includes a plurality of storage planes; the storage array may be Figure 3 The storage array 301 in;

[0118] A plurality of first microcontroller units (MCUs) coupled to the plurality of storage surfaces in a one-to-one correspondence and a computing subcircuit 620 coupled to the plurality of first MCUs 610; wherein,

[0119] The calculation subcircuit 620 is configured to: generate a plurality of operation parameters in sequence according to a preset order in response to the operation control signal; and send the plurality of operation parameters in series to the corresponding first MCU 610;

[0120] Each of the plurality of first MCUs 610 is configured to: perform an operation on a storage surface coupled to the first MCU 610 according to the received corresponding operation parameter. The plurality of first MCUs 610 and the computing subcircuit 620 may be Figure 5 A portion of the peripheral circuit 302.

[0121] The calculation subcircuit 620 of the embodiment of the present disclosure performs serial calculations to generate corresponding operation parameters in response to operation control signals such as read, program or erase, and sends the operation parameters in sequence to each of the multiple first MCUs 610 in series. Each first MCU 610 performs operations on the storage plane coupled to it according to the operation parameters, which can realize synchronous operation of multiple storage planes or separate asynchronous operation of each storage plane, thereby improving the operation rate of the memory device 104; the serial calculation subcircuit 620 and the serial operation parameter sending method can reduce the circuit area occupied by the calculation subcircuit 620 and the interconnection lines between the calculation subcircuit 620 and the first MCU 610.

[0122] In some embodiments, reference Figure 7 As shown, the first MCU 610 includes a first register 611, which is configured to store the operation parameters sent by the computing sub-circuit 620. In some embodiments, the memory device 104 further includes a second MCU 630; the second MCU 630 is configured to: generate an operation control signal in response to an operation request, and control the computing sub-circuit 620 and the first MCU 610.

[0123] The calculation subcircuit 620 and the plurality of first MCUs 610 and the second MCU 630 may be coupled to the first bus 641. The second MCU 630 generates an operation control signal in response to an operation request of the memory controller 106, and sends the signal to the selected at least one first MCU 610 and the calculation subcircuit 620 through the first bus 641. The calculation subcircuit 620 may set a second register 641 or a cache 622 to obtain initial parameters from the first bus 641 when the memory device 104 is powered on and reset (Power On Reset, POR), so as to generate operation parameters for the calculation circuit to calculate.

[0124] The calculation subcircuit 620 sends the generated operating parameters, including the address addr_2 of the write register and the write enable signal wr_en, to the corresponding first MCU 610 through the first bus 641, and the first MCU 610 writes the operating parameters into the corresponding first register 611. The calculation subcircuit 620 may also send data such as operating parameters to the first MCU 610 through other data lines or ports. The initial parameters may include the initial parameters or timing of the operating voltage for the storage unit after testing or optimization of the memory device 104 at the time of leaving the factory, a voltage offset reference, etc. The operating parameters may include the operating parameters or timing adjusted or calculated based on the initial parameters for the current specific use situation. Alternatively, the initial parameters are equivalent to the operators for each operating parameter of the storage unit at the time of leaving the factory, and the operating parameters are formed after calculation by the calculation subcircuit 620, and the calculation includes but is not limited to: temperature compensation, parameter offset or error correction, etc.; the specific calculation method includes but is not limited to: addition, multiplication or parity conversion. The initial parameter data volume is small, and the calculation of the calculation subcircuit 620 can obtain operating parameters with more data volume and adapt to a variety of real-time usage conditions, thereby reducing the storage area occupied by the operating parameters. For example, the operating parameter can be a read voltage or a corresponding timing, a read voltage or timing after temperature compensation or offset, or a re-read voltage determined after error correction based on the read voltage after a read failure. The second MCU 630 may include a third register 631 for storing an operation request sent by the memory controller 106, or storing an operation control signal of the second MCU 630 to the calculation subcircuit 620 and the first MCU 610.

[0125] In some specific embodiments, the first register 611 storing timing parameters is used by the first MCU 610 to wait for a certain period of time through a timing control instruction at a specific waveform moment, and the first register 611 storing voltage parameters is written by the first MCU 610 at a specific waveform moment into the corresponding voltage register of the analog module on the second bus 642 through a data transmission instruction to achieve voltage control of the waveform. The analog module may include a voltage generator. The first bus 641 can be used to transmit operation control signals, initial parameters and operation parameters or other parameters. The second bus 642 can be used to transmit analog signals such as voltage magnitude, waveform, and application timing, or transmit analog signals such as control instructions to devices that generate analog signals such as different waveforms and timings.

[0126] In some embodiments, reference Figure 7 As shown, the calculation subcircuit 620 is further configured to sequentially perform the following processes:

[0127] Generate a first operating parameter from among a plurality of operating parameters, and send the first operating parameter to the corresponding first MCU 610;

[0128] Generate a second operating parameter from among the plurality of operating parameters, and send the second operating parameter to the corresponding first MCU 610;

[0129] Until each first MCU 610 obtains the corresponding operating parameters.

[0130] In one clock cycle, the calculation subcircuit 620 completes obtaining the initial parameters of the corresponding operation associated with the host-side logical address from the first bus 641, calculates the initial parameters to obtain the operation parameters, and writes the operation parameters into the first register 611 in the corresponding first MCU 610, that is, the operation is performed in a serial pipeline manner of: reading the initial parameters-calculating the operation parameters-writing into the first register 611. There is no limit on the size of the data volume completed in one clock cycle, and there is no limit on how many first MCUs 610 the calculated and generated operation parameters correspond to; for example, a short clock cycle can calculate the operation parameters of a page or a storage block of a storage plane, and a long clock cycle can calculate the operation parameters required for multiple storage planes. There is a limit on the operation sequence of the calculation subcircuit 620, that is, when it is necessary to perform multiple cycles of reading the initial parameters-calculating the operation parameters-writing into the first register 611 in multiple clocks and multiple steps, after the generation of the first operation parameters and writing into the first register 611 are completed in one clock cycle, the initial parameters are read to generate the second operation parameters and write into the first register 611. The operation sequence of the first subcircuit for the initial parameters and the clock cycle management are controlled by the internal state machine 621 (Finite State Machine, FSM), and the calculation is performed by the calculation unit 623 (Arithmetic Control Unit, ACU). The calculation unit 623 is a time-sharing shared calculation unit 623, that is, the calculation is performed according to the clock cycle, including an adder or a multiplier. Different calculation modes can be called under the control of the state machine 621 for each calculation.

[0131] In some embodiments, reference Figure 7 As shown, the calculation subcircuit 620 includes:

[0132] State machine 621, computing unit 623 and cache 622; wherein,

[0133] Cache 622, configured to: store relevant data required to obtain multiple operation parameters;

[0134] The state machine 621 is coupled to the computing unit 623 and the cache 622 respectively, and is configured to: in response to the operation control signal, sequentially obtain relevant data from the cache 622 in a preset order, and transmit the relevant data to the computing unit 623;

[0135] The calculation unit 623 is configured to: perform calculations according to relevant data to generate multiple operating parameters; and send the multiple operating parameters serially to the corresponding first MCU 610. The state machine 621 is coupled to each first MCU 610, and can be coupled through the first bus 641 or other data lines, and the data transmission mode is serial.

[0136] The cache 622 and the state machine 621 may be coupled to the first bus 641. The cache 622 is used to obtain the initial parameters stored on any storage plane through the first bus 641 during power-on reset. After the state machine 621 receives the operation control signal sent by the second MCU 630 through the first bus 641, it triggers its control setting and accesses the cache 622 to obtain the initial parameters. Under the control of the operation control signal, the second MCU 630 also generates operation information for the state machine 621, including but not limited to: the address of the storage unit, page, and storage block to be operated in the storage array 301, the address addr_1 of the initial parameters stored in the cache 622, the operation mode, the operation parameter category, and the state machine 621 trigger signal, etc. The operation information can be written into the internal control register of the state machine 621 for the state machine 621 to call. The state machine 621 sends a read request and the address addr_1 of the initial parameters to the cache 622, obtains the relevant initial parameters stored in the cache 622, and then forwards the obtained initial parameters to the calculation unit 623 for calculation. Different calculation models are required for different operating parameters. In different calculation processes, the initial parameters need to be sent to different calculation modules (for example, adders or multipliers) or different input terminals in the calculation unit 623. This selection process is judged and controlled by the state machine according to the different operation modes corresponding to the current operation control signal. After receiving the initial parameters, the calculation unit 623 performs multiplication or addition operations. The calculation circuit can use a pure combinational logic circuit. Multiple calculation results (i.e., operation parameters) can be obtained within one clock cycle and sent to the state machine 621. The operation parameters within one clock cycle can have multiple calculation results with different data amounts. The state machine 621 can temporarily store the calculation results within one clock cycle in an internal register, constitute an operation parameter (for example, voltage / timing parameter), and then send it to the first MCU 610 with a write request signal. The write request signal includes a write enable signal wr_en and the address addr_2 of the first register 611 corresponding to the write.

[0137] In some embodiments, the cache 622 includes: static random access memory (SRAM); or may also include dynamic random access memory, phase change memory, resistive random access memory or magnetic random access memory, etc.

[0138] Figure 7 The cache 622 shown in FIG. 4 may be an SRAM. Figure 6The architecture using the second register 641 can reduce circuit area by 50%, thus reducing costs. Furthermore, the number of transistors stored per bit of the SRAM is 1 / 5-1 / 6 of the number of storage transistors of the register, further reducing circuit area and transistor manufacturing costs.

[0139] In some embodiments, the preset order is a priority order corresponding to each first MCU 610 among the plurality of first MCUs 610;

[0140] The higher the priority level corresponding to the first MCU 610 is, the earlier the state machine 621 acquires the relevant data corresponding to the first MCU 610 from the cache 622 .

[0141] Since the calculation subcircuit 620 operates in a serial pipeline manner of reading initial parameters-calculating operation parameters-writing into the first register 611, generally, the process that sends the task request (or trigger signal) first will first calculate and generate the operation parameters and send them to the corresponding first MCU 610, and the process that sends the task request later will wait in the queue. When there are multiple first MCUs 610 that need operation parameters at the same time, the state machine 621 in the calculation subcircuit 620 can sort them according to the priority of the current first MCU 610, and calculate the operation parameters required by each first MCU 610 in order from high to low according to the priority, so as to reduce calculation conflicts and data transmission blockages.

[0142] In some embodiments, the state machine 621 includes: at least one first state and at least one second state corresponding to each first state; wherein,

[0143] The second MCU 630 is configured to: write operation information related to a plurality of operation parameters into the state machine 621 in response to the operation control signal; the operation information at least includes: a trigger signal;

[0144] The state machine 621 is configured to: enter the first state corresponding to the operation parameter according to the trigger signal corresponding to the operation parameter in a preset order; in the first state corresponding to the operation parameter, enter the corresponding second state in sequence according to the preset state execution order; in each second state, obtain the corresponding relevant data from the cache 622, and control the calculation unit 623 to calculate according to the corresponding relevant data; until the last second state is executed, the operation parameter is obtained; and the operation parameter is transmitted to the corresponding first MCU 610 according to the operation address corresponding to the operation parameter. The operation address may include the address of the selected storage unit, page or storage block, and the first register address addr_2 in the corresponding first MCU can be determined according to the address to avoid errors and conflicts in the transmission of the operation parameters.

[0145] Figure 8A schematic diagram of the flow operation of the state machine 621 in different states of the embodiment of the present disclosure is shown. After receiving the operation request of the memory controller 106, the second MCU 630 generates an operation control signal or an operation control instruction, and in response to the generation of the operation control signal, generates operation information of the state machine 621, which may include but is not limited to: the address of the storage unit, page, and storage block to be operated in the storage array 301, the address of the initial parameter stored in the cache 622, the operation mode, the operation parameter category, and the state machine 621 trigger signal, etc. The operation information can be written into the internal control register of the state machine 621 for the state machine 621 to call.

[0146] The state machine 621 enters the sequential flow of different states under the triggering signal. The state machine 621 adopts a nested manner, and the small state machine 621 is nested in the large state machine 621. For example, the state machine 621 in the first state can be a large state machine 621, and the state machine 621 in the second state can be a small state machine 621. Each large state represents the calculation and storage of a final result data, such as the read voltage (VRD voltage) state, the pass voltage (VPASS voltage) state, etc., which is also the category of the operating parameter; the specific calculation is completed by the small state machine 621, and the small state machine 621 reads data from the cache 622 and performs calculations according to the specific calculation items. Taking the temperature compensation calculation of the VRD voltage as an example, it is necessary to read the initial parameters such as the vrd_base base value and the vrd_tco_offset temperature compensation value for calculation. The process of the state machine 621 flow calculation can be understood as first determining the category of the operating parameters in the first state, obtaining the corresponding operator (initial parameters) and the calculation method in the second state, and then controlling the different calculation circuits in the calculation unit 623 according to the calculation method to complete the calculation and output it to the corresponding first MCU 610.

[0147] The flow order of the first state can start from the idle IDLE state, and after the operation information is written, it flows sequentially from the idle IDLE state. Each first state corresponds to multiple second states, and the second states are also carried out in sequence. The flow of the second state generally includes searching the storage address to obtain data-calculating data, etc.

[0148] Specifically, taking the calculation of VRD as an example, after receiving the trigger signal, the first state enters the VRD state, and the VRD state control state machine 621 enters each second state in turn, enters the calculation state of vrd_tco_offset, submits the address of the vrd_tco temperature coefficient in the cache 622 (such as SRAM), and after reading the data of the temperature coefficient, performs a multiplication operation in the calculation unit 623, multiplying the temperature by the temperature coefficient to obtain vrd_tco_offset. Then the small state machine 621 enters vrd_ftr_offset, submits the address of the data in the fixed feature register (feature register), and after reading the data, performs an accumulation operation in the calculation unit 623, and adds the temperature compensation originally temporarily stored in the calculation unit 623 to the feature compensation value. Then the small state machine 621 enters the vrd_base state, submits the address of the vrd_base base value in the cache 622, and after reading the data, performs an accumulation operation in the calculation unit 623, adds the compensation value originally temporarily stored in the calculation unit 623 to the vrd_base base value, and then enters the next state, and repeats the above steps similarly. After the calculation of VRD is completed, it enters the vrd_plane_offset state, submits the address of the first register 611 of the first MCU 610 to which vrd will be written, and then writes the final calculation result of vrd into the first register 611.

[0149] In some embodiments, the operation control signal includes an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter includes a read parameter; the calculation subcircuit 620 is configured to: respond to the AMPI read operation control signal of the second MCU 630, generate a plurality of read parameters in sequence according to a preset order; and send the plurality of read parameters serially to the corresponding first MCU 610;

[0150] Each first MCU 610 of the plurality of first MCUs 610 is configured to perform an AMPI read operation on a storage plane coupled to the first MCU 610 according to the received corresponding read parameter.

[0151] When the first MCU 610 controls each corresponding storage plane to perform AMPI reading, each storage plane is mapped to the logical address of the host as a physical address. Taking multiple read operation requests as an example, any page in multiple storage planes can be read separately and simultaneously, thereby improving the response rate of the memory device 104, which is beneficial to improving the parallel operation efficiency of the memory device 104, and is particularly beneficial to improving the random read performance of the memory device 104. Each storage plane can also perform programming operations and erasing operations independently.

[0152] In some embodiments, when the first MCU 610 performs an AMPI read operation on a memory plane coupled to the first MCU 610 according to the received corresponding read parameters, the second MCU 630 is configured to perform other operations.

[0153] In some practical use embodiments of the memory device 104, the second MCU 630 controls the first MCU and the calculation subcircuit in response to the operation request of the memory controller 106 to perform an AMPI read operation to give full play to the parallel reading capability of the storage surface and improve the reading rate. The calculation subcircuit is a serial pipeline calculation, and the calculation subcircuit and the first MCU also transmit data in a serial manner, and the second MCU can be parallel to the operation of the calculation subcircuit and the first MCU. After the second MCU sends the control signal such as the operation control instruction, the calculation subcircuit and the first MCU will run for a period of time. During this time, the second MCU can perform other operations, such as data migration and bad block management for other storage surfaces that do not perform the AMPI read operation, and also for example, perform partial operations on other queued operation processes, reduce the process pressure of serial calculation and serial transmission of the calculation subcircuit, so as to improve the overall operation rate of the memory device. In some embodiments, the operation parameter includes one of the following: read voltage, pass voltage.

[0154] Return to reference Figure 3 As shown, in a NAND memory string 308, the read voltage can be applied to the voltage of the selected word line in the AMPI read mode or other read modes to distinguish the threshold voltage distribution of the storage cell to determine which storage state the storage cell is in; the pass voltage is applied to other unselected word lines to turn on the unselected storage cells, and the pass voltage can generally be greater than the read voltage. It should be pointed out that the voltage and voltage timing can be in the parameter form of logical data, which is sent by the first MCU 610 to a device that generates analog signals such as a voltage generator through the second bus 642. The voltage generator generates a voltage of a specific volt and applies it to the word line or bit line of the corresponding address; the timing controls the duration and interval of the voltage time, thereby completing the waveform control of the read voltage.

[0155] According to some aspects of the embodiments of the present disclosure, a control method of a memory device 104 is provided, referring to Figure 7 As shown, the memory device comprises:

[0156] A storage array 301, wherein the storage array 301 includes a plurality of storage planes;

[0157] a plurality of first micro control units (MCUs) coupled to the plurality of storage surfaces and a computing sub-circuit 620 coupled to the plurality of first MCUs 610;

[0158] Reference Fig. 9 As shown, the control method includes:

[0159] In response to the operation control signal, the calculation subcircuit 620 generates a plurality of operation parameters in a preset order; and the calculation subcircuit 620 sends the plurality of operation parameters in series to the corresponding first MCU 610;

[0160] Each of the plurality of first MCUs 610 is enabled to perform an operation on a storage plane coupled to the first MCU 610 according to the received corresponding operation parameter.

[0161] In some embodiments, the control method further includes causing the calculation subcircuit 620 to sequentially perform the following steps:

[0162] Generate a first operating parameter among the multiple operating parameters, and send the first operating parameter to the corresponding first MCU 610;

[0163] Generate a second operating parameter from among the plurality of operating parameters, and send the second operating parameter to the corresponding first MCU 610;

[0164] Until each of the first MCUs 610 obtains the corresponding operating parameters.

[0165] In some embodiments, the calculation subcircuit 620 includes:

[0166] A state machine 621, a computing unit 623 and a cache 622; wherein the state machine 621 is coupled to the computing unit 623 and the cache 622 respectively; the control method comprises:

[0167] Enable the cache 622 to store relevant data required to obtain the multiple operating parameters;

[0168] In response to the operation control signal, the state machine 621 sequentially obtains the relevant data from the cache 622 according to the preset order, and transmits the relevant data to the calculation unit 623;

[0169] The calculation unit 623 is enabled to perform calculation according to the relevant data to generate the multiple operating parameters; and the multiple operating parameters are sent serially to the corresponding first MCU 610.

[0170] In some embodiments, the preset order is a priority order corresponding to each first MCU 610 of the plurality of first MCUs 610;

[0171] The higher the priority level of the first MCU 610 , the earlier the state machine 621 acquires the relevant data corresponding to the first MCU 610 from the cache 622 .

[0172] In some embodiments, the control method further includes:

[0173] The operation control signal is generated in response to the operation request, so that the second MCU 630 of the memory device 104 controls the calculation sub-circuit 620 and the first MCU 610 .

[0174] In some embodiments, the state machine 621 includes: at least one first state and at least one second state corresponding to each first state; the control method includes:

[0175] In response to the operation control signal, the second MCU 630 writes the operation information related to the plurality of operation parameters into the state machine 621; the operation information at least includes: a trigger signal;

[0176] According to the preset sequence, the state machine 621 enters the first state corresponding to the operation parameter according to the trigger signal corresponding to the operation parameter; in the first state corresponding to the operation parameter, the corresponding second state is entered in sequence according to the preset state execution sequence; in each second state, the corresponding related data is obtained from the cache 622, and the calculation unit 623 is controlled to perform calculations according to the corresponding related data; until the last second state is executed, the operation parameter is obtained; and the operation parameter is transmitted to the corresponding first MCU 610 according to the operation address corresponding to the operation parameter.

[0177] In some embodiments, the operation control signal comprises an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter comprises a read parameter;

[0178] The control method comprises:

[0179] In response to the AMPI read operation control signal of the second MCU 630, the calculation subcircuit 620 generates a plurality of the read parameters in sequence according to a preset order; and sends the plurality of read parameters in series to the corresponding first MCU 610;

[0180] Each of the plurality of first MCUs 610 is enabled to perform an AMPI read operation on a storage plane coupled to the first MCU 610 according to the received corresponding read parameter.

[0181] In some embodiments, the control method further includes:

[0182] When the first MCU 610 performs an AMPI read operation on a storage plane coupled to the first MCU 610 according to the received corresponding read parameter, the second MCU 630 is configured to perform other operations.

[0183] In some embodiments, the operating parameter comprises one of: a read voltage, a pass voltage.

[0184] In some embodiments, the first MCU 610 includes a first register 611; the control method further includes:

[0185] The first register 611 is enabled to store the operation parameters sent by the calculation sub-circuit 620 .

[0186] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and when the computer program is executed, the control method described in the above embodiments is implemented. The readable storage medium may include a NAND memory, and a storage cell of the NAND memory may include a floating gate type storage cell of a floating gate transistor, or a charge capture type storage cell including a charge capture transistor.

[0187] In some embodiments, the cache 622 includes:

[0188] Static random access memory.

[0189] According to some aspects of the embodiments of the present disclosure, a memory system 102 is provided, including:

[0190] at least one of the above-mentioned memory devices 104; and

[0191] The memory controller 106 is coupled to the memory device 104 and controls the memory device 104 .

[0192] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory device, characterized in that: include: A storage array, the storage array comprising a plurality of storage planes; A plurality of first microcontroller units MCU coupled to the plurality of storage surfaces in a one-to-one correspondence and a computing subcircuit coupled to the plurality of first MCUs; wherein, The calculation subcircuit is configured to: generate a plurality of operation parameters in sequence according to a preset order in response to an operation control signal; and send the plurality of operation parameters in series to a corresponding first MCU; Each first MCU among the plurality of first MCUs is configured to perform an operation on a storage plane coupled to the first MCU according to the received corresponding operation parameter.

2. The memory device according to claim 1, wherein: The calculation subcircuit is further configured to sequentially perform the following processes: Generate a first operating parameter among the multiple operating parameters, and send the first operating parameter to the corresponding first MCU; Generate a second operating parameter among the multiple operating parameters, and send the second operating parameter to the corresponding first MCU; Until each of the first MCUs obtains the corresponding operating parameters.

3. The memory device according to claim 2, wherein: The calculation subcircuit comprises: state machine, computing unit and cache; among them, The cache is configured to: store relevant data required to obtain the plurality of operating parameters; The state machine is coupled to the computing unit and the cache, respectively, and is configured to: in response to the operation control signal, sequentially obtain the relevant data from the cache in accordance with the preset order, and transmit the relevant data to the computing unit; The calculation unit is configured to: perform calculation according to the relevant data to generate the multiple operating parameters; and send the multiple operating parameters in series to the corresponding first MCU.

4. The memory device according to claim 3, wherein: The preset order is a priority order corresponding to each first MCU among the plurality of first MCUs; The higher the priority corresponding to the first MCU is, the earlier the state machine obtains the relevant data corresponding to the first MCU from the cache.

5. The memory device according to claim 3, wherein: The memory device further includes a second MCU; the second MCU is configured to generate the operation control signal in response to an operation request, and control the calculation sub-circuit and the first MCU.

6. The memory device according to claim 5, characterized in that The state machine comprises: at least one first state and at least one second state corresponding to each first state; wherein, The second MCU is configured to: write operation information related to the plurality of operation parameters into the state machine in response to the operation control signal; the operation information at least includes: a trigger signal; The state machine is configured to: enter the first state corresponding to the operating parameter according to the trigger signal corresponding to the operating parameter in the preset order; enter the corresponding second state in sequence according to the preset state execution order in the first state corresponding to the operating parameter; in each second state, obtain the corresponding related data from the cache, and control the calculation unit to perform calculations according to the corresponding related data; until the last second state is executed, the operating parameter is obtained; and the operating parameter is transmitted to the corresponding first MCU according to the operation address corresponding to the operating parameter.

7. The memory device according to claim 5, wherein: The operation control signal includes an asynchronous multi-plane independent AMPI read control signal; the operation parameter includes a read parameter; the calculation subcircuit is configured to: respond to the AMPI read operation control signal of the second MCU, generate a plurality of read parameters in sequence according to a preset order; and send the plurality of read parameters in series to the corresponding first MCU; Each first MCU among the plurality of first MCUs is configured to perform an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter.

8. The memory device according to claim 7, wherein: When the first MCU performs an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter, the second MCU is configured to perform other operations.

9. The memory device according to claim 1, wherein: The operating parameter includes one of the following: a read voltage, a pass voltage.

10. The memory device according to claim 1, wherein: The first MCU includes a first register configured to store the operation parameters sent by the calculation sub-circuit.

11. The memory device according to claim 3, wherein: The cache includes: static random access memory.

12. A method for controlling a memory device, characterized in that: The memory device comprises: A storage array, the storage array comprising a plurality of storage planes; A plurality of first micro control units MCU coupled to the plurality of storage surfaces and a computing sub-circuit coupled to the plurality of first MCUs; The control method comprises: In response to the operation control signal, the calculation subcircuit generates a plurality of operation parameters in a preset order; and the calculation subcircuit sends the plurality of operation parameters in series to the corresponding first MCU; Each of the plurality of first MCUs is enabled to perform an operation on a storage plane coupled to the first MCU according to the received corresponding operation parameter.

13. The control method according to claim 12, characterized in that: The control method further includes causing the calculation subcircuit to sequentially perform the following steps: Generate a first operating parameter among the multiple operating parameters, and send the first operating parameter to the corresponding first MCU; Generate a second operating parameter among the multiple operating parameters, and send the second operating parameter to the corresponding first MCU; Until each of the first MCUs obtains the corresponding operating parameters.

14. The control method according to claim 13, characterized in that: The calculation subcircuit comprises: A state machine, a computing unit and a cache; wherein the state machine is coupled to the computing unit and the cache respectively; and the control method comprises: enabling the cache to store relevant data required to obtain the plurality of operating parameters; In response to the operation control signal, the state machine sequentially obtains the relevant data from the cache in the preset order and transmits the relevant data to the computing unit; The calculation unit is enabled to perform calculation according to the relevant data to generate the multiple operating parameters; and the multiple operating parameters are sent serially to the corresponding first MCU.

15. The control method according to claim 14, characterized in that: The preset order is a priority order corresponding to each first MCU among the plurality of first MCUs; The higher the priority corresponding to the first MCU is, the earlier the state machine obtains the relevant data corresponding to the first MCU from the cache.

16. The control method according to claim 15, characterized in that: The control method further comprises: The operation control signal is generated in response to an operation request, so that the second MCU of the memory device controls the calculation sub-circuit and the first MCU.

17. The control method according to claim 16, characterized in that: The state machine comprises: at least one first state and at least one second state corresponding to each first state; the control method comprises: In response to the operation control signal, the second MCU writes operation information related to the plurality of operation parameters into the state machine; the operation information at least includes: a trigger signal; According to the preset sequence, the state machine enters the first state corresponding to the operating parameter according to the trigger signal corresponding to the operating parameter; in the first state corresponding to the operating parameter, the state machine enters the corresponding second state in sequence according to the preset state execution sequence; in each second state, the corresponding related data is obtained from the cache, and the calculation unit is controlled to perform calculations according to the corresponding related data; until the last second state is executed, the operating parameter is obtained; and the operating parameter is transmitted to the corresponding first MCU according to the operation address corresponding to the operating parameter.

18. The control method according to claim 16, characterized in that: The operation control signal includes an asynchronous multi-plane independent AMPI read control signal; the operation parameter includes a read parameter; The control method comprises: In response to the AMPI read operation control signal of the second MCU, the calculation subcircuit generates a plurality of the read parameters in sequence according to a preset order; and sends the plurality of read parameters in series to the corresponding first MCU; Each of the plurality of first MCUs is enabled to perform an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter.

19. The control method according to claim 18, characterized in that: The control method further comprises: When the first MCU performs an AMPI read operation on a storage plane coupled to the first MCU according to the received corresponding read parameter, the second MCU is configured to perform other operations.

20. The control method according to claim 12, characterized in that: The operating parameter includes one of the following: a read voltage, a pass voltage.

21. The control method according to claim 12, characterized in that: The first MCU includes a first register; the control method further includes: The first register is enabled to store the operation parameter sent by the calculation sub-circuit.

22. The control method according to claim 14, characterized in that: The cache includes: Static random access memory.

23. A memory system, characterized in that: include: At least one memory device as claimed in claims 1 to 11; as well as A memory controller is coupled to the memory device and controls the memory device.

Images