Memory system, method of reading data, and method of finding read threshold

Abstract

A memory system, a method of reading data, and a method of finding a read threshold are provided. The method of finding a read threshold includes selecting a channel distribution corresponding to a read page to be read of a memory device among a plurality of channel distributions in response to a read command; generating a grid map based on the decoding scheme and the type of the read page; determining an optimal path through the grid chart using the selected channel distribution according to a dynamic programming algorithm; and searching a read threshold according to the optimal path.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept generally relate to reading data from a memory, and more particularly, to setting an optimal threshold voltage level for reading the data. Background Art

[0002] Modern NAND flash memory devices allow for the storage of several bits of data in each memory cell, thereby providing improvements in manufacturing cost and performance. Memory cells that store multiple bits of data may be referred to as multi-level memory cells (MLCs). Multi-level memory cells divide the threshold voltage range of a memory cell into several voltage states, and the data value written to the memory cell is extracted using the memory cell voltage level.

[0003] However, the aggressive scaling of multi-level NAND flash memory and the growth of the number of bits per cell leads to higher bit error rates. Error correction codes are needed to handle more errors while requiring less circuit area and power consumption. Therefore, there is a need for low-complexity, efficient error reduction methods. Summary of the invention

[0004] According to an embodiment of the present disclosure, a memory system is provided, the memory system comprising a memory device having a plurality of memory cells, and a memory controller. The memory controller is configured to: determine a channel distribution of each page of the memory device to generate a plurality of channel distributions; in response to a read command, select a channel distribution corresponding to a read page to be read of the memory device from the plurality of channel distributions; generate a grid diagram based on a decoding scheme and a type of read page; determine an optimal path through the grid diagram using the selected channel distribution according to a dynamic programming algorithm; find a read threshold according to the optimal path; and read the read page from the memory device using the read threshold. For example, the dynamic programming algorithm may be a Viterbi algorithm.

[0005] According to an embodiment of the present disclosure, a method for reading data from a memory device of a memory system includes: a memory controller of the memory system determines a channel distribution of each page of the memory device to generate a plurality of channel distributions; in response to a read command, selects a channel distribution corresponding to a read page to be read of the memory device from the plurality of channel distributions; generates a grid map based on a decoding scheme and a type of the read page; determines an optimal path through the grid map using the selected channel distribution according to a dynamic programming algorithm; finds a read threshold according to the optimal path; and reads the read page from the memory device using the read threshold. For example, the dynamic programming algorithm may be a Viterbi algorithm.

[0006] According to an embodiment of the present disclosure, a memory system is provided, the memory system comprising a memory device having a plurality of memory cells, and a memory controller. The memory controller is configured to: in response to a read command, select a channel distribution corresponding to a read page to be read of the memory device from among the plurality of channel distributions; generate a grid map based on a decoding scheme and a type of the read page; determine an optimal path through the grid map using the selected channel distribution according to a dynamic programming algorithm; and use the optimal path to find an optimal read threshold for performing a read of the read page.

[0007] According to an embodiment of the present disclosure, a method for finding a read threshold for reading a memory device of a memory system includes: a memory controller of the memory system selects a channel distribution corresponding to a read page to be read of the memory device from among a plurality of channel distributions in response to a read command; a grid diagram is generated based on a decoding scheme and a type of the read page; an optimal path is determined through the grid diagram using the selected channel distribution according to a dynamic programming algorithm; and the read threshold is found according to the optimal path. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating an implementation of a data processing system including a memory system according to an exemplary embodiment of the inventive concept;

[0010] Figure 2 According to an exemplary embodiment of the inventive concept Figure 1 A detailed block diagram of a non-volatile memory device;

[0011] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A block diagram of a memory system;

[0012] Figure 4 According to an exemplary embodiment of the inventive concept Figure 2 A block diagram of a memory cell array;

[0013] Figure 5 According to an exemplary embodiment of the inventive concept Figure 4 A circuit diagram of a memory block;

[0014] Figure 6 An exemplary balanced Gray code mapping for SLC, MLC, and TLC is shown;

[0015] Figure 7 shows an exemplary hard decision threshold setting for TLC;

[0016] Figure 8 shows an exemplary soft decision (SD) threshold setting for TLC;

[0017] Fig. 9 A method of reading data from a memory device according to an exemplary embodiment of the inventive concept is shown;

[0018] Fig.10 shows exemplary TLC thresholds when 2SD is used for various pages;

[0019] Fig.11 illustrates generation of a grid map according to an exemplary embodiment of the inventive concept;

[0020] Fig.12 A process for calculating an optimal threshold value according to an exemplary embodiment of the inventive concept is shown;

[0021] FIG. 13A to FIG. 13C A method of calculating an optimal threshold according to an exemplary embodiment of the inventive concept is shown;

[0022] Fig.14 A method of calculating an optimal threshold according to an exemplary embodiment of the inventive concept is shown;

[0023] Fig.15 An example of calculating a branch metric for a branch for use in one of the methods according to an exemplary embodiment of the inventive concept is shown;

[0024] Fig.16 1. A calculation method according to an exemplary embodiment of the inventive concept is shown. Fig.11 The branch metric results of the grid graph;

[0025] Fig.17 shows an exemplary calculation of an LLR table that may be used to correct errors in data read using the above method;

[0026] Fig.18 An exemplary pseudo code showing a Viterbi algorithm that may be used in the above method according to an exemplary embodiment of the inventive concept; and

[0027] Fig.19 A block diagram illustrating a computing system including a nonvolatile memory system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0028] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.Like reference numerals may refer to like elements throughout the drawings.

[0029] It should be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0030] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0031] Here, when a value is described as being approximately equal to another value or being substantially the same as another value or being substantially equal to another value, it will be understood that these values ​​are equal to each other within the measurement error, or if they are not equal measurably, they are close enough in value to be functionally equal to each other as will be understood by those of ordinary skill in the art. For example, the term "approximately" as used herein includes the value and means within the acceptable deviation range of the specific value determined by those of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "approximately" may be expressed as within one or more standard deviations as will be understood by those of ordinary skill in the art. In addition, it will be understood that although a parameter may be described herein as having a specific value "approximately", according to an exemplary embodiment, the parameter may be exactly the specific value or approximate the specific value within the measurement error as will be understood by those of ordinary skill in the art.

[0032] Figure 1 is a block diagram illustrating an implementation of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.

[0033] Reference Figure 1 , the data processing system 10 may include a host 100 and a memory system 200 . Figure 1 The memory system 200 shown in FIG. 2 may be used in various systems including a data processing function. The various systems may be various devices including, for example, a mobile device such as a smart phone or a tablet computer. However, the various devices are not limited thereto.

[0034] The memory system 200 may include various types of memory devices. Here, the exemplary embodiments of the inventive concept will be described as including a memory device as a non-volatile memory. However, the exemplary embodiments are not limited thereto. For example, the memory system 200 may include a memory device as a volatile memory.

[0035] According to an exemplary embodiment, the memory system 200 may include a nonvolatile memory device (such as, for example, a read-only memory (ROM), a magnetic disk, an optical disk, a flash memory, etc.). The flash memory may be a memory that stores data according to a change in the threshold voltage of a metal oxide semiconductor field effect transistor (MOSFET), and may include, for example, a NAND flash memory and a NOR flash memory. The memory system 200 may be implemented using a memory card including a nonvolatile memory device (such as, for example, an embedded multimedia card (eMMC), a secure digital (SD) card, a micro SD card, or a universal flash storage (UFS)), or the memory system 200 may be implemented using, for example, an SSD including a nonvolatile memory device. Here, the configuration and operation of the memory system 200 will be described assuming that the memory system 200 is a nonvolatile memory system. However, the memory system 200 is not limited thereto. The host 100 may include, for example, a system on chip (SoC) application processor (AP) installed on, for example, a mobile device, or a central processing unit (CPU) included in a computer system.

[0036] As described above, the host 100 may include the AP 110. The AP 110 may include various intellectual property (IP) blocks. For example, the AP 110 may include a memory device driver 111 that controls the memory system (e.g., nonvolatile memory system) 200. The host 100 may communicate with the memory system 200 to send commands related to memory operations (e.g., read commands, write commands, erase commands, etc.) and receive confirmation commands in response to the sent commands.

[0037] The memory system 200 may include, for example, a memory controller 210 and a memory device 220. The memory controller 210 may receive a command related to a memory operation from the host 100, generate an internal command and an internal clock signal using the received command, and provide the internal command and the internal clock signal to the memory device 220. The memory device 220 may store write data in a memory cell array in response to the internal command, or may provide read data to the memory controller 210 in response to the internal command.

[0038] The memory device 220 may include a memory cell array that retains data stored therein even when the memory device 220 is not powered on. The memory cell array may include memory cells (e.g., NAND or NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric access memory (FRAM), or phase change memory (PCM)). For example, when the memory cell array includes a NAND flash memory, the memory cell array may include a plurality of blocks and a plurality of pages. Data may be programmed and read in units of pages, and data may be erased in units of blocks. Figure 4An example of a memory block included in a memory cell array is shown in FIG.

[0039] Figure 2 According to an exemplary embodiment of the inventive concept Figure 1 Detailed block diagram of a memory device (eg, a non-volatile memory device) 220.

[0040] Reference Figure 2 , the memory device 220 may include, for example, a memory cell array 221 , a control logic 222 , a voltage generating unit 223 , a row decoder 224 , and a page buffer 225 .

[0041] The memory cell array 221 may be connected to one or more string selection lines SSL, a plurality of word lines WL, one or more ground selection lines GSL, and a plurality of bit lines BL. The memory cell array 221 may include a plurality of memory cells disposed at intersections between the plurality of word lines WL and the plurality of bit lines BL.

[0042] The control logic 222 may receive a command CMD (e.g., an internal command) and an address ADD from the memory controller 210, and receive a control signal CTRL for controlling various functional blocks within the memory device 220 from the memory controller 210. The control logic 222 may output various control signals for writing data to the memory cell array 221 or reading data from the memory cell array 221 based on the command CMD, the address ADD, and the control signal CTRL. In this manner, the control logic 222 may control the overall operation of the memory device 220.

[0043] Various control signals output by the control logic 222 may be provided to the voltage generation unit 223, the row decoder 224, and the page buffer 225. For example, the control logic 222 may provide the voltage control signal CTRL_vol to the voltage generation unit 223, provide the row address X-ADD to the row decoder 224, and provide the column address Y-ADD to the page buffer 225.

[0044] The voltage generating unit 223 may generate various voltages for performing programming, reading and erasing operations on the memory cell array 221 based on the voltage control signal CTRL_vol. For example, the voltage generating unit 223 may generate a first driving voltage VWL for driving a plurality of word lines WL, a second driving voltage VSSL for driving a plurality of string selection lines SSL, and a third driving voltage VGSL for driving a plurality of ground selection lines GSL. In this case, the first driving voltage VWL may be a programming voltage (e.g., a write voltage), a read voltage, an erase voltage, a pass voltage, or a programming verification voltage. In addition, the second driving voltage VSSL may be a string selection voltage (e.g., a turn-on voltage or a turn-off voltage). In addition, the third driving voltage VGSL may be a ground selection voltage (e.g., a turn-on voltage or a turn-off voltage).

[0045] The row decoder 224 may be connected to the memory cell array 221 through a plurality of word lines WL, and may activate a portion of the plurality of word lines WL in response to a row address X-ADD received from the control logic 222. For example, in a read operation, the row decoder 224 may apply a read voltage to a selected word line and a pass voltage to unselected word lines.

[0046] In a programming operation, row decoder 224 may apply a program voltage to a selected word line and a pass voltage to unselected word lines. In one exemplary embodiment, in at least one of a plurality of programming loops, row decoder 224 may apply a program voltage to a selected word line and additional selected word lines.

[0047] The page buffer 225 may be connected to the memory cell array 221 through a plurality of bit lines BL. For example, in a read operation, the page buffer 225 may operate as a sense amplifier that outputs data stored in the memory cell array 221. Alternatively, in a program operation, the page buffer 225 may operate as a write driver that writes desired data to the memory cell array 221.

[0048] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 2 is a block diagram of a memory system 200.

[0049] Reference Figure 3 , the memory system 200 includes a memory device 220 and a memory controller 210. The memory controller 210 may also be referred to herein as a controller circuit. The memory device 220 may perform a write operation, a read operation, or an erase operation under the control of the memory controller 210.

[0050] The memory controller 210 may control the memory device 220 according to a request received from the host 100 or an internally specified schedule. The memory controller 210 may include a controller core 121, an internal memory 124, a host interface block 125, and a memory interface block 126.

[0051] The controller core 121 may control and access the memory device 220 according to a request received from the host 100 or an internally specified schedule. The controller core 121 may manage and execute various metadata and codes for managing or operating the memory system 200. In an exemplary embodiment of the inventive concept, the controller core 121 includes an error correction code (ECC) circuit for performing error detection and correction on data read from memory cells of the memory device 220. For example, the controller core 121 may sense a read voltage from a subset of memory cells in response to a read command and address information received from the host, convert the read voltage into a codeword (including data and redundant information), and perform an ECC decoding operation on the codeword using an error correction code (ECC) decoder.

[0052] According to an exemplary embodiment of the inventive concept, for each page of the memory device, the controller core 121 initially calculates a channel distribution for each page of the memory device 220, and then, in response to a read command for a given page, the controller core 121 uses the corresponding channel distribution and a required decoding scheme (e.g., hard decoding or soft decoding) to calculate a threshold voltage and a log-likelihood ratio (LLR) table for the given page, and then uses the calculated threshold voltage and LLR table to read data from the page.

[0053] The internal memory 124 may be used as, for example, a system memory used by the controller core 121, a cache memory storing data of the memory device 220, or a buffer memory temporarily storing data between the host 100 and the memory device 220. The internal memory 124 may further store a mapping table MT indicating a relationship between a logical address assigned to the memory system 200 from the host 100 and a physical address of the memory device 220. The internal memory 124 may include, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM). The internal memory 124 may be a buffer.

[0054] In one exemplary embodiment, a level assignment in which two immediately adjacent levels both have high cell counts relative to other levels may have more errors than a level assignment in which the two levels with high cell counts are kept as far away from each other as possible.

[0055] The host interface block 125 may include a component (such as, for example, a physical block) for communicating with the host 100. The memory interface block 126 may include a component (such as, for example, a physical block) for communicating with the memory device 220.

[0056] The host interface block 125 may provide a first request REQ1 received from the host 100 to the controller core 121. The first request REQ1 may include a command (eg, a read command or a write command) and a logical address. The controller core 121 may convert the first request REQ1 into a second request REQ2 suitable for the memory device 220.

[0057] For example, the controller core 121 may convert the format of the command. The controller core 121 may refer to the mapping table MT stored in the internal memory 124 to obtain the address information AI. The controller core 121 may convert the logical address into the physical address of the memory device 220 by using the address information AI. The controller core 121 may provide the second request REQ2 suitable for the memory device 220 to the memory interface block 126.

[0058] The memory interface block 126 may register the second request REQ2 from the controller core 121 at the queue. The memory interface block 126 may transmit the request first registered at the queue to the memory device 220 as the third request REQ3.

[0059] When the first request REQ1 is a write request, the host interface block 125 may write data received from the host 100 to the internal memory 124. When the third request REQ3 is a write request, the memory interface block 126 may transmit data stored in the internal memory 124 to the memory device 220.

[0060] When the data is completely written, the memory device 220 may send a third response RESP3 to the memory interface block 126. In response to the third response RESP3, the memory interface block 126 may provide the controller core 121 with a second response RESP2 indicating that the data is completely written.

[0061] After the data is stored in the internal memory 124 or after receiving the second response RESP2 , the controller core 121 may transmit a first response RESP1 indicating request completion to the host 100 through the host interface block 125 .

[0062] When the first request REQ1 is a read request, the read request may be transmitted to the memory device 220 through the second request REQ2 and the third request REQ3. The memory interface block 126 may store the data received from the memory device 220 in the internal memory 124. When the data is completely transmitted, the memory device 220 may transmit a third response RESP3 to the memory interface block 126.

[0063] When receiving the third response RESP3, the memory interface block 126 may provide the controller core 121 with a second response RESP2 indicating that the data is completely stored. When receiving the second response RESP2, the controller core 121 may send the first response RESP1 to the host 100 through the host interface block 125.

[0064] The host interface block 125 may transmit data stored in the internal memory 124 to the host 100. In one exemplary embodiment, in a case where data corresponding to the first request REQ1 is stored in the internal memory 124, transmission of the second request REQ2 and the third request REQ3 may be omitted.

[0065] Figure 4 and Figure 5 An example of implementing the memory system 200 using a three-dimensional flash memory is shown. The three-dimensional flash memory may include a three-dimensional (e.g., vertical) NAND (e.g., VNAND) memory cell. An implementation of a memory cell array 221 including a three-dimensional memory cell is described below. Each of the memory cells described below may be a NAND memory cell.

[0066] Figure 4 According to an exemplary embodiment of the inventive concept Figure 2 A block diagram of a memory cell array 221 is shown.

[0067] Reference Figure 4 , the memory cell array 221 according to the exemplary embodiment includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz has a three-dimensional structure (e.g., a vertical structure). For example, each of the memory blocks BLK1 to BLKz may include a structure extending in the first direction to the third direction. For example, each of the memory blocks BLK1 to BLKz may include a plurality of NAND strings extending in the second direction. The plurality of NAND strings may be arranged, for example, in the first direction to the third direction.

[0068] Each of the plurality of NAND strings is connected to a bit line BL, a string selection line SSL, a ground selection line GSL, a word line WL, and a common source line CSL. That is, each of the memory blocks BLK1 to BLKz may be connected to a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of ground selection lines GSL, a plurality of word lines WL, and a common source line CSL. Figure 5 The memory blocks BLK1 to BLKz are described in further detail.

[0069] Figure 5 is a circuit diagram of a memory block BLKi according to an exemplary embodiment of the inventive concept. Figure 5 Show Figure 4 An example of one of the memory blocks BLK1 to BLKz in the memory cell array 221.

[0070] The memory block BLKi may include a plurality of cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42. A plurality of cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42 may be arranged in a column direction and a row direction to form columns and rows. Each of the cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42 may include a ground selection transistor GST, memory cells MC1 to MC6, and a string selection transistor SST. The ground selection transistor GST, memory cells MC1 to MC6, and the string selection transistor SST included in each of the cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42 may be stacked in a height direction substantially perpendicular to the substrate.

[0071] Columns of a plurality of cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42 may be connected to different string selection lines SSL1 to SSL4, respectively. For example, string selection transistors SST of cell strings CS11 and CS12 may be commonly connected to string selection line SSL1. String selection transistors SST of cell strings CS21 and CS22 may be commonly connected to string selection line SSL2. String selection transistors SST of cell strings CS31 and CS32 may be commonly connected to string selection line SSL3. String selection transistors SST of cell strings CS41 and CS42 may be commonly connected to string selection line SSL4.

[0072] The rows of the plurality of cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42 may be connected to different bit lines BL1 and BL2, respectively. For example, the string selection transistors SST of the cell strings CS11, CS21, CS31, and CS41 may be connected in common to the bit line BL1. The string selection transistors SST of the cell strings CS12, CS22, CS32, and CS42 may be connected in common to the bit line BL2.

[0073] Columns of a plurality of cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42 may be connected to different ground selection lines GSL1 to GSL4, respectively. For example, the ground selection transistors GST of the cell strings CS11 and CS12 may be connected in common to the ground selection line GSL1. The ground selection transistors GST of the cell strings CS21 and CS22 may be connected in common to the ground selection line GSL2. The ground selection transistors GST of the cell strings CS31 and CS32 may be connected in common to the ground selection line GSL3. The ground selection transistors GST of the cell strings CS41 and CS42 may be connected in common to the ground selection line GSL4.

[0074] Memory cells arranged at the same height from the substrate (or ground selection transistor GST) may be connected in common to a single word line, and memory cells arranged at different heights from the substrate may be connected to different word lines WL1 to WL6, respectively. For example, a plurality of memory cells MC1 may be connected in common to the word line WL1. A plurality of memory cells MC2 may be connected in common to the word line WL2. A plurality of memory cells MC3 may be connected in common to the word line WL3. A plurality of memory cells MC4 may be connected in common to the word line WL4. A plurality of memory cells MC5 may be connected in common to the word line WL5. A plurality of memory cells MC6 may be connected in common to the word line WL6. The ground selection transistors GST of the cell strings CS11, CS21, CS31, CS41, CS12, CS22, CS32, and CS42 may be connected in common to the common source line CSL.

[0075] Figure 5 Each word line (e.g., WL1, WL2, etc.) of may include one page or several pages. For a single-level cell (SLC), each word line includes one page, and each of the memory cells connected to the word line stores one bit. For a multi-level cell (MLC), each word line includes two pages (i.e., a least significant bit (LSB) page and a most significant bit (MSB) page), and each of the memory cells connected to the word line stores two bits. When a given memory cell is a three-level cell (TLC), each word line includes three pages (i.e., an LSB page, a center significant bit (CSB) page, and an MSB page), and each of the memory cells connected to the word line stores three bits.

[0076] exist Figure 6, the mapping of bits to cell voltage levels is shown for SLC, MLC, and TLC. For example, a TLC memory cell is interpreted as bit "111" when its voltage Vth is less than a first voltage, as bit "011" when its voltage Vth is between a first voltage and a second voltage, as bit "001" when its voltage Vth is between a second voltage and a third voltage, and so on. In flash memory, the mapping from bits to voltage levels is based on a Balanced Gray Code (BGC). For example, each chunk of information of data may be 4 kilobytes (KB), 16KB, etc., and is stored in pages with some additional overhead bits. The read process in flash memory is accomplished by setting a voltage threshold (i.e., a read threshold) for reading the bits of the desired page. Each page can be decoded using hard decoding (HD) or soft decoding (SD).

[0077] In HD, such as Figure 7 As shown in FIG. 1 for TLC, there is a threshold for each change between "0" and "1". For example, the LSB page has two thresholds, the CSB page has three thresholds, and the MSB page has two thresholds. In SD, as Figure 8 As shown in , there are additional thresholds for each HD threshold. In 2SD (two-bit soft decision), there are two additional thresholds for each HD threshold, for a total of 2 2 = 4 decision regions. In 3SD (three-bit soft decision), there are 6 additional thresholds for each HD threshold (i.e., 2 3 =8 decision regions). For example, the total number of thresholds (ie, read thresholds) may be determined based on the decoding scheme, the type of desired page, and the mapping from bits to voltage levels.

[0078] Embodiments of the inventive concept provide an optimal end-to-end solution for reading the cell voltage of a memory cell to the input of an ECC decoder. The embodiment is optimal in the sense that it maximizes mutual information (MI), which can be used as a measure to maximize communication capacity and storage capacity.

[0079] Fig. 9 A method of reading data from a memory device according to an exemplary embodiment of the inventive concept is shown. The method may be performed by the memory controller 210 and / or the controller core 121 .

[0080] Fig. 9The method includes: determining a channel distribution for each page of the memory device 220 to generate a plurality of channel distributions (S300). The channel distribution P (y|b) includes M values, where y is a cell voltage of the page, b is storage data having a value of 0 or 1, and M is a positive integer greater than 0 determined based on a selected voltage resolution (e.g., 20mv) and a range of possible read voltages (e.g., -2v to 4v). For example, when the voltage range is -2v to 4v and the voltage resolution is 20mv, there will be 300 discrete voltages between the voltage ranges, and M will be 300. The M values ​​indicate the probability that each of the discrete voltages is set to "1" (i.e., b=1) and the probability that each of the discrete voltages is set to "0" (i.e., b=0). For example, if the memory device 220 includes N word lines and the memory device 220 is a TLC, there will be 3×N pages and therefore 3×N channel distributions.

[0081] In one embodiment, the classifier operates on the characteristics of each of the 3×N pages to estimate each corresponding channel distribution. In one embodiment, the characteristic of a given page of the 3×N pages is the page type (e.g., N is the page type because there are LSB, CSB, and MSB in the case of TLC). page =3), the page number of a given page (e.g., N loc ), an endurance quantity associated with a given page (such as a program / erase (P / E) count (e.g., N P / E )), and the retention time associated with a given page (e.g., N ret ), but is not limited thereto. For example, one of the above characteristics may be omitted. The page number may indicate a physical area in a specific block of the memory device 220. For example, if there are 100 TLC memory cells in a page with the page number, each type of page has a size of 100 bits. The retention time may indicate a value associated with a given page indicating the time since the given page was last written. Therefore, in general, there are N ch-type =N page ×N loc ×N P / E ×N ret The estimated channels for a given page can be used to find the optimal read threshold for the desired decoding scheme (eg, HD or SD).

[0082] The estimation of the channel distribution may be performed in an offline manner. For example, the step of generating may occur just after the memory system 200 is powered on and before new data is written to or read from it. The step of estimating may be referred to as initial channel estimation.

[0083] Subsequently, since the electrical characteristics of non-volatile memory, such as flash memory, change over time for several reasons, such as P / E cycles (endurance) and retention time, an adaptive channel estimation scheme may be performed to update the channel distribution.

[0084] In one embodiment, the adaptive scheme uses data correctly extracted from a particular page to update the channel distribution. For a page that is correctly read using a calculated read threshold, the data stored in the page is known and can be used to improve the corresponding channel distribution for future reads. Adaptive channel estimation can be performed as part of a low priority process after a read process. Adaptive channel estimation can include: saving data after a successful page read, setting a read threshold according to a desired voltage resolution, obtaining cell voltage levels for all word lines, estimating the channel distribution of a successful page, and updating the estimated channel distribution. For example, if a page has 100 TLC memory cells and the page has been successfully read, P(y|b=0) and P(y|b=1) can be statistically updated based on the actual read voltage level of each of the 100 cells. For 100 cells, there may be approximately 50 cells in the case of b=0, and there may be approximately 50 cells in the case of b=1. The channel estimation can then be updated based on the updated P(y|b=0) and P(y|b=1).

[0085] Fig. 9 The method further includes: in response to a read command for a read page to be read of the memory, selecting one of the plurality of channel distributions corresponding to the read page (S301). For example, the read command may be received together with a read address indicating a word line position to be read of the memory device 220, and the memory system 200 may store information indicating the number of bits of data stored by each page at the word line position, the P / E count of each page, and the retention time of each page; and then the type of channel distribution may be determined according to the word line position, the number of bits, the P / E count, and the retention time. Then, the channel distribution may be selected from the previously estimated channel distribution that matches the determined type.

[0086] Fig. 9 The method further includes calculating a read threshold suitable for a given decoding scheme (e.g., HD, SD (e.g., 2SD, 3SD), etc.) considering the selected channel distribution (S302). Next, a log likelihood ratio (LLR) table may be calculated according to the read threshold (S303). Then, the read page is read from the memory device using the read threshold to generate a codeword (S304), and the codeword may be corrected using the LLR table (S305).

[0087] The threshold calculator of the controller core 121 may be used to find the optimal read threshold. The threshold calculator may be implemented offline or in real time. The memory controller 210 or the controller core 121 may quantize the cell voltage read from the page of the memory device 220 according to the read threshold calculated by the threshold calculator. The result of the quantization may be referred to as Z and has K different values ​​(symbols). For example, for HD, K=2, for 2SD, K=4, and for 3SD, K=8. Z may then be mapped to a log-likelihood ratio (LLR).

[0088] Fig.10 2SD decoding is shown when the memory cell is TLC. Fig.10 Part (a) shows a TLC with 2SD for the LSB page, Fig.10 Part (b) shows a TLC with 2SD for the CSB page, and Fig.10 Part (c) shows a TLC with 2SD for the MSB page. Fig.10 The lines in are thresholds, and the areas between the lines are decision areas. The longer lines are HD thresholds, and the shorter lines are SD thresholds. When the read voltage falls in the S1 (strong '1') region, the read voltage has a high confidence that the corresponding value is '1'. When the read voltage falls in the S0 (strong '0') region, the read voltage has a high confidence that the corresponding value is '0'. When the read voltage falls in the W1 (weak '1') region, the read voltage has a low confidence that the corresponding value is '1'. When the read voltage falls in the W0 (weak '0') region, the read voltage has a low confidence that the corresponding value is '0'. The threshold with the longer line (HD threshold) distinguishes between the determination of zero and one. Each interval (e.g., the S1 region, S0 region, W1 region, W0 region, etc. above) appears once or is repeated twice in the MSB / LSB page, and is repeated twice or three times in the CSB page.

[0089] The optimal threshold for each page can be determined by using a Trellis diagram, where, for example, two or three thresholds are set simultaneously at each stage of the trellis diagram. Dynamic programming techniques can find the best path by presenting a trellis diagram of the optimal threshold settings. This technique maximizes the mutual information I(b; Z). The maximization problem is defined by Equation 1,

[0090]

[0091] Among them, z (t z ,t z+1 ) is a rectangular function defining the intervals of the MSB page and the LSB page with BGC mapping. Since these thresholds define the intervals mapped to the output symbol Z, then t zis the set of thresholds in stage z and t z+1 is the interval t of the set of thresholds at stage z+1 z ,t z+1 can be determined. We define the function Z = G(u) as the interval mapped to Z. For each output symbol Z and for a different mapping function G(u), the rectangular mapping Π z (·) is different. This rectangular mapping is many-to-one (that is, several intervals are mapped to the quantized output symbol Z). At the same time, y represents the channel output. In other words, y is modeling the cell voltage. In addition, u is a parameter that enumerates the intervals separated by the read threshold of the cell voltage.

[0092] The optimal search for the threshold t is the optimal partition of the voltage axis that maximizes the mutual information. The inner summation is defined by Equation 2,

[0093]

[0094] As defined by Equation 1, the maximization is defined by searching for the best t using multiple thresholds,

[0095]

[0096] The optimal solution is found by searching through the grid graph.

[0097] Fig.11 A trellis diagram is shown to illustrate possible paths through candidate nodes. The trellis diagram is shown for an input size equal to M=8. The trellis diagram includes a plurality of stages, wherein each stage contains input states and output states for all options for computing a first output symbol. For example, the number of stages of the trellis diagram may be determined based on the decoding scheme and the type of read page. The plurality of stages is given by T=(t 1 ,t 2 ) indicates that, among which, t 1 ,t 2 is the threshold position in y. The optimal threshold can be determined based on the grid diagram by using a dynamic programming technique such as the Viterbi algorithm. The Viterbi algorithm maximizes the term I(b; Z). For M>>1 and LSB / MSB, the number of states in each stage is all possible ways to set the two thresholds at the channel output, which is approximately M 2 / 2 states.

[0098] Fig.12 A process for calculating an optimal threshold according to a disclosed embodiment is shown.

[0099] Fig.12The method includes: building a trellis diagram (Bulid_Trellis_Diagram) (S401). In an exemplary embodiment, a trellis diagram may be created or generated based on a decoding scheme and a type of page. A different trellis diagram may be created for each different type of page. For example, there may be a first building function for building a trellis diagram for an LSB page, a second building function for building a trellis diagram for a CSB page, and a third building function for building a trellis diagram for an MSB page. Each building function takes into account the number of states, the number of output symbols K, the page number, and the number of bits per memory cell. The building function may take into account the size of y or the fine resolution of the voltage axis (such as 20mV), the number of symbols K at the output, the page type, the number of bits per memory cell (for example, TLC is three bits per cell, and quad-level cell (QLC) is four bits per cell). The output of the function is a trellis structure including all states, stages, and branches. For TLC using 2SD and M=8, the branches remain as follows Fig.11 The input and output states of the connections shown in .

[0100] Fig.12 The method further includes: calculating a branch metric (Calc_Branches_Metric) from the branches of the grid graph (S402). Each branch is a connection between an input state and an output state. Step S402 can be performed by a function that uses equation 2 to calculate the association metric of each branch in the grid graph for a given mapping function G(u).

[0101] Fig.12 The method further includes: using the Viterbi algorithm and the branch metric to determine an optimal path (Viterbi_Algorithm) through the nodes of the trellis graph (S403).

[0102] Fig.12 The method further includes: performing a traceback operation on the best path to generate an optimal threshold and mutual information (Traceback) (S404). The traceback function runs backward on the winning path to extract the optimal threshold and mutual information.

[0103] The function used to calculate the branch metric can calculate the partial mutual information i(t_L, t_R) for all possible options of thresholds t_L, t_R on all edges in the grid graph as shown in Equation 2. Each branch metric consists of a number of intervals, t_L and t_R are vectors that hold the lower (left) and upper (right) thresholds for all intervals, respectively. Fig. 13B and Fig. 13C In FIG. 1 , branch metric calculations for the MSB or LSB page in a 2SD TLC are shown. In this example, there are two types of branch metric calculations: (i) for Fig. 13C 0, 1, 2 as shown in ; and (ii) for Fig. 13B 3. In this example, for phases 0, 1, 2, there are two intervals in the branch metric calculation, so t_L, t_R are vectors of size two. For phase 3, there is a single interval, so t_L, t_R are scalars.

[0104] Fig.13A A method of calculating a read threshold voltage for a TLC of an MSB page or LSB page with 2SD decoding according to an exemplary embodiment of the disclosure is shown. The method is performed in stages. In each stage after stage 0, two thresholds (i.e., a lower threshold and an upper threshold) are selected together as candidates. The method can operate on the page based on the number of thresholds available for the corresponding page according to the decoding scheme. Since the MSB page and the LSB page include 6 thresholds for 2SD, Fig.13A Applicable to MSB page and LSB page. In the first stage (stage 1), a first lower threshold and a first upper threshold are selected within an available voltage range (e.g., -2v to 4v); in the second stage (stage 2), a second lower threshold and a second upper threshold are selected between the first lower threshold and the first upper threshold, and a corresponding first branch metric among a plurality of first branch metrics is calculated according to the first lower threshold, the first upper threshold, the second lower threshold, and the second upper threshold. A first node may be represented by a first lower threshold and a first upper threshold, a second node may be represented by a second lower threshold and a second upper threshold, and a line connecting a first node and a second node may be referred to as a corresponding first branch (or edge) among a plurality of first branches. The first stage and the second stage may be re-executed for all possible combinations to generate remaining first branches and remaining first branch metrics.

[0105] Next, in the third stage (stage 3), a third lower threshold and a third upper threshold are selected between the second lower threshold and the second upper threshold, and a corresponding second branch metric among the plurality of second branch metrics is calculated according to the second lower threshold, the second upper threshold, the third lower threshold, and the third upper threshold. The third node may be represented by a third lower threshold and a third upper threshold, and a line connecting the second node and the third node may be referred to as a corresponding second branch among the plurality of second branches. The second stage and the third stage may be re-executed for all possible combinations to generate the remaining second branches and the remaining second branch metrics.

[0106] Finally, in the fourth stage (Stage 4), the final path through the node is selected based on all branch metrics to determine the optimal read threshold.

[0107] Fig.14A method for calculating a read threshold voltage for a TLC of a CSB page with 2SD decoding according to an exemplary embodiment of the disclosure is shown. The method is performed in stages. At each stage after the initial stage, three thresholds (i.e., a lower threshold, an upper threshold, and an intermediate threshold between the upper threshold and the lower threshold) are selected together as candidates. The method can operate on the page based on the number of thresholds available for the corresponding page according to the decoding scheme. Since the CSB page includes 9 thresholds for 2SD, Fig.14 Applicable to CSB pages. In the first stage (stage 0), a first lower threshold, a first intermediate threshold, and a first upper threshold are selected within an available voltage range (e.g., -2v to 4v); in the second stage (stage 1), a second lower threshold and a second intermediate threshold are selected between the first lower threshold and the first intermediate threshold, and a second upper threshold is selected above the first upper threshold, and a corresponding first branch metric among a plurality of first branch metrics is calculated based on a plurality of first thresholds (i.e., the first lower threshold, the first intermediate threshold, and the first upper threshold) and a plurality of second thresholds (i.e., the second lower threshold, the second intermediate threshold, and the second upper threshold). A first node may be represented by a plurality of first thresholds, a second node may be represented by a plurality of second thresholds, and a line connecting a first node and a second node may be referred to as a corresponding first branch (or edge) among a plurality of first branches. The first stage and the second stage may be re-executed for all possible combinations to generate remaining first branches and remaining first branch metrics.

[0108] Next, in the third stage (stage 2), a third lower threshold and a third intermediate threshold are selected between the second lower threshold and the second intermediate threshold, a third upper threshold is selected above the second upper threshold, and a corresponding second branch metric among a plurality of second branch metrics is calculated according to a plurality of second thresholds and a plurality of third thresholds (i.e., a third lower threshold, a third intermediate threshold, and a third upper threshold). The third node may be represented by a plurality of third thresholds, and a line connecting the second node and the third node may be referred to as a corresponding second branch among a plurality of second branches. The second stage and the third stage may be re-executed for all possible combinations to generate remaining second branches and remaining second branch metrics.

[0109] Finally, in the fourth stage (stage 3), the final path through the node is selected based on all branch metrics to determine the optimal read threshold.

[0110] The calculation of the LLR of the ECC decoder is based on the optimal threshold calculation and the estimated channel distribution p(y|b). For p(b=0)=p(b=1)=0.5, the relationship between LLR(z) and P(y|b) is given by Equation 4,

[0111]

[0112] The LLR table has K entries, and each entry is calculated according to Equation 5,

[0113]

[0114] in, is the estimated channel probability, and the sum is over all y belonging to z. The y belonging to z is determined by the best threshold calculated previously.

[0115] Provide use Fig.11 An example of finding the optimal threshold using a grid plot and LLR table.

[0116] In this example, it is assumed that the threshold is set for the MSB page of 2SD decoding (eg, K=4), and M=8 (eg, the number of values ​​of the channel output Y). The conditional channel probabilities according to Table 1 are assumed.

[0117] P(y|b) y＝0 y＝1 y＝2 y＝3 y＝4 y＝5 y＝6 y＝7 b＝0 0.5 0.25 0.125 0.05 0.04 0.02 0.01 0.005 b＝1 0.005 0.01 0.02 0.04 0.05 0.125 0.25 0.5

[0118] Table 1

[0119] The channel outputs (8 values) are enumerated as values ​​between 0, 1, 2, ..., 7. The stored data is b with two values ​​0, 1. Table 1 is read as follows: given b = 0, the probability of y = 0 is 0.5; given b = 0, the probability of y = 1 is 0.25; and so on. Due to the probability rule, each row sums to 1. As shown by Table 2, it is assumed that the stored bits (b) have uniform probability.

[0120] b＝0 b＝1 P(b) 0.5 0.5

[0121] Table 2

[0122] According to the probability rule, P(y) = ∑ b p(b)P(y|b)=p(b=0)p(y|b=0)+p(b=1)p(y|b=1), and therefore, P(y) is given by Table 3.

[0123] y＝0 y＝1 y＝2 y＝3 y＝4 y＝5 y＝6 y＝7 P(y) 0.2525 0.13 0.0725 0.045 0.045 0.0725 0.13 0.2525

[0124] Table 3

[0125] The branch metric function may be used based on Equation 2 using Equation 6 to calculate all metrics associated with all edges in the trellis graph.

[0126]

[0127] Fig.15 An example of using the Viterbi algorithm to calculate the branch metric for the branch between nodes (0,8) and (1,6) is shown. Fig.11 The results of all branch metrics of the grid graph are Fig.16The Viterbi algorithm starts from an initial state where the cumulative metric is zero. The cumulative metric (e.g., cumulative mutual information) for all nodes is determined. In each branch, the Viterbi algorithm sums the cumulative metric and the appropriate branch metric. When two or more branches are merged in a node, the path with the maximum value is the cumulative metric and the winning edge is saved. The Viterbi algorithm runs through all stages and states. At the end state, the winning path is determined and Fig.16 In the example shown in , the metric of the winning path is 0.0464.

[0128] exist Fig.16 In the backtracking of , we run backwards from the end state to the initial state to extract the winning path. In this way, the optimal threshold setting is extracted. Fig.16 In the example, the optimal thresholds are: (2,7), (3,6), (4,5), and the final mapping from Y to Z is given by express.

[0129] The calculation of the LLR table using base-2 logarithms is performed using Equation 5. Fig.17 The LLR table calculated when the optimal thresholds are (2,7), (3,6), and (4,5) is shown.

[0130] Fig.18 An exemplary pseudocode for the Viterbi algorithm is shown. The last step in the state loop holds a pointer to the previous state through which the backtracking function will extract the winning path (i.e., the optimal solution). The winning_path variable holds a pointer to the previous winning state of all states throughout all stages. The winning path is the path that survives the last stage and reaches the last state. The winning path is maintained as a sequence of states throughout all stages.

[0131] In this example, the channel distribution P(y|b) described above can be estimated offline. The offline estimation can include determining, for each page, the number of bits it stores, its page number, its endurance (e.g., the number of program / erase cycles) up to a limited resolution, and its retention time up to a limited resolution, and then classifying the page according to the determined values.

[0132] Fig.19 is a block diagram of a computing system 1200 including a nonvolatile memory system according to an exemplary embodiment of the inventive concept.

[0133] Fig.19 The non-volatile memory system in Figure 1 Memory system 200 shown in FIG. In computing system 1200, which may be, for example, a mobile device or a desktop computer, a nonvolatile memory system may be installed as nonvolatile memory system 1201, however exemplary embodiments are not limited thereto.

[0134] The computing system 1200 may include, for example, a host 1202 including a CPU, a RAM 1203, a user interface 1204, and a device driver 1205. The host 1202 may be Figure 1 The host 100 shown in FIG. 1 and the device driver 1205 may be Figure 1 1204. The host 1202 may control the entire computing system 1200 and perform operations corresponding to user commands input through the user interface 1204. The RAM 1203 may be used as a data storage for the host 1202. The host 1202 may write user data to the nonvolatile storage system 1201 or read user data from the nonvolatile storage system 1201 through the device driver 1205. Fig.19 In the embodiment, the device driver 1205 that controls the operation and management of the nonvolatile storage system 1201 is shown as being disposed outside the host 1202, however, the exemplary embodiment is not limited thereto. For example, in one exemplary embodiment, the device driver 1205 may be disposed inside the host 1202.

[0135] In an exemplary embodiment of the inventive concept, a three-dimensional (3D) memory array is provided. A 3D memory array is monolithically formed in one or more physical levels of an array of memory cells and has active areas disposed above a silicon substrate and circuits associated with the operation of those memory cells, whether such associated circuits are above or within such a substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array.

[0136] In an exemplary embodiment of the inventive concept, a 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located above another memory cell. The at least one memory cell includes a charge trapping layer. The following patent documents incorporated herein by reference describe suitable configurations for a three-dimensional memory array, wherein the three-dimensional memory array is configured as multiple levels and word lines and / or bit lines are shared between levels: U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0137] As is conventional in the field of the inventive concept, exemplary embodiments are described and shown in the accompanying drawings in terms of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of implementing blocks, units and / or modules by microprocessors or the like, software (e.g., microcode) can be used to program blocks, units and / or modules to perform various functions discussed herein, and blocks, units and / or modules can be selectively driven by firmware and / or software. Optionally, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuit systems). In addition, without departing from the scope of the inventive concept, each block, unit and / or module of the exemplary embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of the exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0138] Exemplary embodiments of the present invention may be implemented directly in hardware, in software modules executed by a processor, or in a combination of the two. The software modules may be tangibly implemented in a non-transitory program storage device (such as, for example, a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, or any other form of storage medium known in the art). An exemplary storage medium may be incorporated into a processor so that the processor may read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated into the processor. In addition, in some aspects, the processor and the storage medium may reside in an application specific integrated circuit (ASIC).

[0139] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A memory system, comprising: A memory device comprising a plurality of memory cells; as well as The memory controller is configured as: determining a channel distribution for each page of the memory device to generate a plurality of channel distributions, In response to a read command, selecting a channel distribution corresponding to a read page of the memory device to be read from among the plurality of channel distributions, Generates a grid map based on the decoding scheme and the type of page being read, According to the dynamic programming algorithm, the optimal path is determined through the grid graph using the selected channel distribution. Find the read threshold based on the best path, and A read page is read from the memory device using a read threshold.

2. The memory system according to claim 1, wherein: The total number of read thresholds is determined based on the decoding scheme, the type of page being read, and the mapping from bits to voltage levels.

3. The memory system according to claim 1, wherein: The number of stages of the trellis diagram is determined based on the decoding scheme and the type of page being read.

4. The memory system according to claim 3, wherein: At each stage, the memory controller determines several of the read thresholds simultaneously.

5. The memory system according to claim 1, wherein: The process of determining the best path includes traversing the grid graph and calculating the cumulative mutual information.

6. The memory system according to claim 1, wherein: The plurality of channel distributions are initially estimated for each page according to a page number of the corresponding page, a program / erase count of the corresponding page, and a retention time of the corresponding page.

7. The memory system according to claim 1, wherein: The memory controller updates the channel distribution for the read page based on the results of a successful previous read of the read page.

8. The memory system according to claim 1, wherein: The memory controller uses the channel distribution and the read threshold to calculate a log-likelihood ratio.

9. The memory system according to any one of claims 1 to 8, wherein: The dynamic programming algorithm is the Viterbi algorithm.

10. A method for reading data from a memory device of a memory system, the method comprising: determining, by a memory controller of the memory system, a channel distribution for each page of the memory device to generate a plurality of channel distributions; selecting, by the memory controller in response to a read command, a channel distribution corresponding to a read page of the memory device to be read from among the plurality of channel distributions; generating, by the memory controller, a grid map based on a decoding scheme and a type of read page; determining, by the memory controller, an optimal path through the grid graph using the selected channel distribution according to a dynamic programming algorithm; The memory controller searches for a read threshold based on the best path; as well as A read page is read from the memory device by the memory controller using the read threshold.

11. The method according to claim 10, wherein: The total number of read thresholds is determined based on the decoding scheme, the type of page being read, and the mapping from bits to voltage levels.

12. The method according to claim 10, wherein: The number of stages of the trellis diagram is determined based on the decoding scheme and the type of page being read.

13. The method according to claim 10, wherein: The steps of determining the best path include traversing the grid graph and calculating the cumulative mutual information.

14. The method according to claim 10, further comprising: The channel distribution for the read page is updated based on the results of a successful previous read of the read page.

15. A memory system comprising: A memory device comprising a plurality of memory cells; as well as The memory controller is configured as: In response to a read command, selecting a channel distribution corresponding to a read page of the memory device to be read from among a plurality of channel distributions, Generates a grid map based on the decoding scheme and the type of page being read, According to a dynamic programming algorithm, the selected channel distribution is used to determine the best path through the grid graph, and The best path is used to find a read threshold for performing a read of the read page.

16. The memory system of claim 15, wherein: The total number of read thresholds is determined based on the decoding scheme, the type of page being read, and the mapping from bits to voltage levels.

17. The memory system according to claim 15, wherein: The plurality of channel distributions are initially estimated for each page of the memory device according to a page number of the corresponding page, a program / erase count of the corresponding page, and a retention time of the corresponding page.

18. The memory system according to claim 15, wherein: The memory controller updates the channel distribution for the read page based on the results of a successful previous read of the read page.

19. A method for finding a read threshold for reading a memory device of a memory system, the method comprising: selecting, by the memory controller in response to a read command, a channel distribution corresponding to a read page of the memory device to be read from among a plurality of channel distributions; generating, by the memory controller, a grid map based on a decoding scheme and a type of read page; determining, by the memory controller, an optimal path through the grid graph using the selected channel distribution according to a dynamic programming algorithm; as well as The memory controller finds the read threshold based on the best path.

20. The method according to claim 19, wherein: The plurality of channel distributions are initially estimated for each page of the memory device according to a page number of the corresponding page, a program / erase count of the corresponding page, and a retention time of the corresponding page.

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