Memory sub-array unit, memory chip, memory bank and aging test method
By introducing a detection module and a switching module into the memory sub-array unit, the short circuit between the dummy bit line and the bit line is detected and disconnected, the voltage abnormality caused by the short circuit between the dummy bit line and the bit line in traditional aging tests is solved, and the accuracy of the test results is improved.
Patent Information
- Application Number
- CN202311009250.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-08
- Publication Date
- 2025-02-25
AI Technical Summary
In traditional aging testing methods, the short circuit between the bit line and the pseudo bit line will cause abnormal voltage on the bit line, affecting the test results.
A storage sub-array unit is designed, including a detection module and a switching module, by detecting a short circuit between the dummy bit line and the bit line, and disconnecting the corresponding switch during the short circuit, avoiding the access of the dummy bit line and the first power supply voltage.
Effectively reduce the impact of short circuits between pseudo-bit lines and bit lines on aging tests, ensure the accuracy of test results, and thus accelerate the progress of research and development.
Smart Images
Figure CN119517142A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a storage subarray unit, a storage chip, a memory stick, and an aging test method. Background Art
[0002] In the memory chip manufacturing process, in order to ensure that the bit lines at the edge of the memory array are uniform with the bit lines located inside, dummy bit lines are usually set on both sides of the bit line setting area. At the same time, in the actual process, due to process reasons, the bit line and the dummy bit line may be short-circuited.
[0003] However, in the conventional aging test method, the bit line and the dummy bit line are usually directly connected to power supplies with different voltages, which will cause abnormal voltage on the bit line when a short circuit occurs between the dummy bit line and the bit line, thus affecting the aging test. Summary of the invention
[0004] Based on this, it is necessary to provide a storage subarray unit, a storage chip, a memory stick and an aging test method that can reduce the impact of a short circuit between a pseudo word line and a word line on an aging test in order to solve the above technical problems.
[0005] A storage subarray unit, comprising:
[0006] A plurality of memory cells are arranged in a plurality of rows and columns, wherein the memory cells include transistors and capacitors, wherein within the same memory cell, a first region of the transistor is connected to a first electrode of the capacitor, and the first region is one of a source region and a drain region;
[0007] A plurality of bit lines extending along the column direction of the memory cells and arranged along the row direction of the memory cells, wherein the same bit line is connected to the second region of the transistor located in the same column, the second region being the other of the source region and the drain region;
[0008] A plurality of dummy bit lines extending along the column direction of the memory cells and arranged along the row direction of the memory cells, wherein in the row direction, the plurality of dummy bit lines are distributed on both sides of the region where the plurality of bit lines are located, and the plurality of dummy bit lines include a first detection dummy bit line, and the first detection dummy bit line is adjacent to the bit line;
[0009] The switch module comprises a first switch, one end of which is connected to the first detection pseudo bit line, and the other end of which is used to access a first power supply voltage.
[0010] In one embodiment, the plurality of pseudo bit lines further include a second detection pseudo bit line, the second detection pseudo bit line and the bit line are respectively located on both sides of the first detection pseudo bit line, and the second detection pseudo bit line is connected to the switch module to access the first power supply voltage through the switch module.
[0011] In one embodiment, the switch module further includes a second switch, one end of the second switch is connected to the second detection pseudo bit line, and the other end of the second switch is used to access the first power supply voltage.
[0012] In one embodiment, the second detection pseudo bit line is connected to a terminal of the first switch connected to the first detection pseudo bit line.
[0013] In one embodiment, the second detection dummy bit line is adjacent to the first detection dummy bit line.
[0014] In one embodiment, the switch module is a transistor-type switch module, and is formed in the same layer as the transistor of the memory cell.
[0015] In one embodiment, the voltage value of the first power supply voltage is 0.5V.
[0016] A memory chip, comprising:
[0017] The storage sub-array unit described in any one of the above items;
[0018] A detection module, used for detecting whether there is a short circuit between the first detection dummy bit line and the bit line;
[0019] The control module is connected to the detection module and the switch module, and is used to disconnect the first switch when there is a short circuit between the first detection pseudo bit line and the bit line.
[0020] In one embodiment, the storage sub-array unit includes a sensing amplifier circuit, which is connected to the control module and is used to sense and amplify the voltage on the bit line.
[0021] A memory stick, comprising:
[0022] A plurality of memory chips as described in any one of the above items;
[0023] A memory controller is connected to each of the memory chips and is used to control the memory chips.
[0024] An aging test method, applied to any of the above-mentioned storage sub-array units, comprising:
[0025] Turning on the transistor of the memory cell, applying a reference voltage to the second electrode of the capacitor, turning on the first switch, and applying a second power supply voltage to the bit line;
[0026] Detecting whether there is a short circuit between the first detection dummy bit line and the bit line;
[0027] When the first detection pseudo bit line is short-circuited with the bit line, the corresponding first switch is turned off to perform an aging test on the memory sub-array unit.
[0028] In one embodiment, when there is no short circuit between the first detection dummy bit line and the bit line, the first switch is kept turned on to perform an aging test on the memory sub-array unit.
[0029] In one embodiment, the detecting whether there is a short circuit between the first detection dummy bit line and the bit line comprises:
[0030] A voltage on the bit line adjacent to the first detection dummy bit line is detected.
[0031] In one embodiment, while the first switch is turned on, the second switch is also turned on, and,
[0032] When the first detection pseudo bit line is short-circuited with the bit line, the corresponding first switch is turned off to perform an aging test on the storage sub-array unit, including:
[0033] When the voltage on the bit line adjacent to the first detection pseudo bit line is abnormal, disconnecting the corresponding first switch and second switch to perform an aging test on the memory sub-array unit;
[0034] Among them, one end of the second switch is connected to the second detection pseudo bit line among the multiple pseudo bit lines, and the other end is used to access the first power supply voltage. The second detection pseudo bit line and the bit line are respectively located on both sides of the first detection pseudo bit line.
[0035] In one embodiment, the voltage value of the first power supply voltage is 0.5V.
[0036] The above-mentioned storage sub-array unit, storage chip, memory bar and aging test method can effectively detect the short circuit between the first detection pseudo bit line and the bit line. At the same time, when there is a short circuit between the first detection pseudo bit line and the bit line, the first switch can be disconnected, thereby disconnecting the circuit between the first detection pseudo bit line and the access end of the first power supply voltage. At this time, the first detection pseudo bit line is no longer connected to the first power supply voltage, so that the voltage on the bit line will not be affected by the first power supply voltage and become abnormal. At this time, when the aging test is continued, the impact of the short circuit between the pseudo bit line and the bit line on the aging test can be effectively reduced, which is convenient for effectively discovering other hidden problems, thereby accelerating the research and development progress. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0038] Figure 1 is a structural block diagram of a memory bar in one embodiment;
[0039] Figure 2 A structural block diagram of a storage chip in one embodiment;
[0040] Figure 3 Another structural block diagram of a storage chip in one embodiment;
[0041] Figure 4 is a structural block diagram of a memory bank in another embodiment;
[0042] Figure 5 is a schematic diagram of the structure of a storage sub-array unit in one embodiment;
[0043] Figure 6 is a simplified structural diagram of a storage subarray unit in one embodiment;
[0044] Figure 7 is a schematic diagram of a circuit structure of a storage unit in one embodiment;
[0045] Figure 8 is a partial top view schematic diagram of a storage subarray unit in one embodiment;
[0046] Fig. 9 FIG. 4 is a flow chart of an aging test method in an embodiment.
[0047] Description of reference numerals:
[0048] 100-memory chip, 110-memory sub-array unit, 111-memory unit, 1111-transistor, 1111a-first area, 1111b-second area, 1112-capacitor, 1112a-first electrode, 1112b-second electrode, 112-bit line, 113-dummy bit line, 1131-first detection dummy bit line, 1132-second detection dummy bit line, 114-switch module, 1141-first switch, 1142-second switch, 115-word line, 116-sense amplifier circuit, 120-detection module, 130-control module, 140-global bit line, 150-global word line, 200-memory controller, 10-memory bank, 20-active area. DETAILED DESCRIPTION
[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0051] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.
[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0053] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.
[0054] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.
[0055] In one embodiment, see Figure 1 , a memory bar is provided, and includes a plurality of memory chips 100 and a memory controller 200. The memory controller 200 can be connected to each memory chip 100 at the same time, so as to control each memory chip 100.
[0056] It can be understood that, in the embodiments of the present application, "plurality", "multiples" and the like mean two or more than two.
[0057] As an example, the memory bar may be a dual inline memory module (DIMM). In this case, the memory bar may include eight memory chips 100 .
[0058] In one embodiment, see Figure 2 The memory chip 100 includes a memory sub-array unit 110 , a detection module 120 , and a control module 130 .
[0059] The number of the memory sub-array units 110 in the memory chip 100 may be multiple.
[0060] As an example, see Figure 3 , the memory chip 100 may include a plurality of memory banks 10 (BANK). For example, the memory chip 100 may include eight memory banks 10. Figure 4 Each memory bank 10 may have a plurality of storage sub-array units 110 arranged in an array. At the same time, each column of storage sub-array units 110 is connected to the same global bit line 140 , and each row of storage sub-array units 110 is connected to the same global word line 150 .
[0061] Also, see Figure 5 as well as Figure 6 The memory sub-array unit 110 may include a plurality of memory cells 111 , a plurality of bit lines 112 , a plurality of dummy bit lines 113 , and a switch module 114 .
[0062] The plurality of storage cells 111 may be arranged in a plurality of rows and columns. For example, the plurality of storage cells 111 in the storage sub-array unit 110 may be arranged in 512 rows and 512 columns. In this case, the storage sub-array unit 110 includes (512×512) storage cells 111 .
[0063] Also, see Figure 7 , each storage unit 111 may include a transistor 1111 and a capacitor 1112 .
[0064] See also Figure 8 In the process of preparing the memory chip 100, a shallow trench isolation structure (not shown) may be first formed on the semiconductor substrate. The shallow trench isolation structure separates the semiconductor substrate into a plurality of active regions 20. The transistor 1111 may be formed based on the active region 20. The first region 1111a and the second region 1111b of the transistor 1111 may be doped regions formed by doping the active region 20. The first region 1111a is one of the source region and the drain region, and the second region 1111b is the other of the source region and the drain region.
[0065] In the same memory cell 111 , the first region 1111 a of the transistor 111 is connected to the first electrode 1112 a of the capacitor 1112 . The transistor 111 is used to control the charging and discharging of the capacitor 1112 , that is, to control the switching of the memory cell 111 .
[0066] The bit lines 112 may extend along the column direction of the memory cells 111. At the same time, a plurality of bit lines 112 extending in the same direction are arranged along the row direction of the memory cells 111. As an example, each bit line 112 may pass through the memory sub-array unit 110 in its extending direction. The same bit line 112 may connect the second region 1111b of the transistor 1111 located in the same column.
[0067] Also, see Figure 5 The storage sub-array unit 110 may further include a plurality of word lines 115 and a sense amplifier circuit 116 .
[0068] The plurality of word lines 115 may be arranged along the column direction of the memory cells 111. At the same time, the plurality of word lines 115 may all extend along the row direction of the memory cells 111. As an example, each word line 115 may penetrate the memory sub-array unit 110 in its extending direction. The same word line 115 connects the gates of the transistors 1111 in the same row.
[0069] As an example, see Figure 8 , the second regions 1111b of the transistors 1111 of adjacent columns can be connected to the same bit line 112, thereby improving storage density.
[0070] At this time, two transistors 1111 can be formed based on the same active area 20. The gates of the two transistors 1111 are respectively connected to two adjacent word lines 115. As an example, the word line 115 can be reused as the gate of the transistor 1111. At the same time, the active area 20 between the word lines 115 of the two transistors 1111 can be used as a common second area 1111b for the two. The two transistors 1111 can be connected to the same bit line 112 through the common second area 1111b. Therefore, the two columns of transistors 1111 formed by the active area 20 in the same column can be connected to the same bit line 112.
[0071] Of course, in other examples, a transistor 1111 may be provided for each column, and a bit line 112 may be independently provided for each column.
[0072] See also Figure 5 , the sense amplifier circuit 116 is connected to the bit line 112. As an example, each bit line 112 may be connected to a sense amplifier circuit 116.
[0073] During the reading process of the memory cell 111, a first preset voltage can be applied to the corresponding word line 115 to turn on the transistor 1111 in the memory cell 111; then the voltage in the capacitor 1112 can be output to the bit line 112; then the voltage on the bit line 112 is sensed and amplified by the sensing amplifier circuit 116 and output to the external circuit, thereby reading the data stored in the memory cell 111.
[0074] During the writing process of the memory cell 111, a first preset voltage can be applied to the corresponding word line 115 to turn on the transistor 1111 in the memory cell 111; then the voltage of the external circuit can be amplified by the sensing amplifier and output to the bit line 112; then the voltage is transmitted to the capacitor 1112 through the bit line 112, thereby writing data to the memory cell 111.
[0075] When the memory cell 111 is not performing data reading or writing, a second preset voltage may be applied to the corresponding word line 115 , thereby turning off the transistor 1111 in the memory cell 111 .
[0076] See also Figure 6 The number of the dummy bit lines 113 may also be multiple, and each dummy bit line 113 may extend in the same direction as the bit line 112. That is, each dummy bit line 113 may extend along the column direction in which the memory cells 111 are arranged.
[0077] Meanwhile, the plurality of dummy bit lines 113 may also be arranged along the row direction of the memory cells 111. In the row direction of the memory cells 111, the plurality of dummy bit lines 113 are located on both sides of the region where the plurality of bit lines 113 are distributed.
[0078] During the preparation of the memory chip 100, the bit line 112 and the dummy bit line 113 can be formed simultaneously by a photolithography process. During the photolithography process, since the dummy bit lines 113 are designed on both sides of the bit line 112, the process processing environment of the bit line 113 located at the edge and the bit line 113 located in the middle can be similar, so that each bit line 113 can be uniform.
[0079] The plurality of dummy bit lines 113 include a first detection dummy bit line 1131. The first detection dummy bit line 1131 is adjacent to the bit line 112.
[0080] See also Figure 6 The switch module 114 includes a first switch 1141. One end of the first switch 1141 is connected to the first detection pseudo bit line 1131, and the other end is used to access the first power supply voltage V1. As an example, the first switch 114 can be connected to the access end of the first power supply voltage V1 through a metal interconnection line.
[0081] As an example, dummy bit lines 113 are provided on both sides of the region where the plurality of bit lines 112 are located. At this time, the plurality of dummy bit lines 113 may include two first detection dummy bit lines 1131. Correspondingly, the switch module 114 includes two first switches 1141.
[0082] When performing an aging test, the transistor 1111 of the memory cell 111 may be turned on, a reference voltage may be applied to the second electrode 1112b of the capacitor 1112, and a second power supply voltage V2 may be applied to the bit line 113. The second power supply voltage V2 may have a different voltage value from the reference voltage. At the same time, the second power supply voltage V2 may have a different voltage value from the first power supply voltage V1.
[0083] At this time, since the first switch 1141 is provided between the first detection dummy bit line 1131 and the access terminal of the first power supply voltage V1 , the first switch 1141 can be used to control whether the first detection dummy bit line 1131 is connected to the first power supply voltage V1 .
[0084] The detection module 120 is used to detect whether there is a short circuit between the first detection dummy bit line 1131 and the bit line 112 in the memory sub-array unit 110 .
[0085] During the preparation of the memory chip 100, multiple dummy bit lines 113 are formed on both sides of the region where the multiple bit lines 112 are located, thereby improving the uniformity of the multiple bit lines 112. However, at the same time, when there is a deviation in the process, a short circuit will occur between the dummy bit line 113 and the bit line 112. Among them, the first detection dummy bit line 1131 adjacent to the bit line 112 and closest to the bit line 112 is most likely to be short-circuited with the bit line 112, so the short circuit between the first detection dummy bit line 1131 and the bit line 112 is the main reason for the abnormal voltage of the bit line 112.
[0086] Therefore, as an example, by detecting the voltage on the bit line 112 (such as the bit line 112 adjacent to the first detection dummy bit line 1131 ), it is determined whether there is a short circuit between the first detection dummy bit line 1131 and the bit line 112 .
[0087] In the initial state of the aging test, the first switch 1141 can be in the on state, and the first detection pseudo bit line 1131 is connected to the first power supply voltage V1. At the same time, the second power supply voltage V2 is connected to the bit line 112. When there is a short circuit between the first detection pseudo bit line 1131 and the bit line 112, a leakage connection path will be generated between the first detection pseudo bit line 1131 and the bit line 112, resulting in abnormal voltage values of the two. Based on this, it can be determined whether there is a short circuit between them by detecting the voltage of the first detection pseudo bit line 1131 and / or the bit line 112.
[0088] The control module 130 is connected to the detection module 120 and the switch module 114. The control module 130 may turn off the first switch 1141 when a short circuit exists between the first detection dummy bit line 1131 and the bit line 112.
[0089] It is understandable that when the plurality of pseudo bit lines 113 include two first detection pseudo bit lines 1131, the short circuit conditions between the two first detection pseudo bit lines 1131 and the bit line 112 may be different. At this time, it is possible to detect whether there is a short circuit between the two first detection pseudo bit lines 1131 and the bit line 112. For example, by detecting the voltage on the two bit lines 112 adjacent to the two first detection pseudo bit lines 1131, it is possible to detect and determine whether there is a short circuit between the two first detection pseudo bit lines 1131 and the bit line 112.
[0090] At this time, the control module 130 can control the on and off of the corresponding two first switches 1141 respectively according to the short circuit status of the two first detection pseudo bit lines 1131 and the bit line 112 .
[0091] As an example, the control module 130 may be a control circuit for controlling the sense amplifier circuit 116 . At this time, the sense amplifier circuit 116 is connected to the control module 130 .
[0092] Of course, the configuration of the control module 130 is not limited thereto. Other control circuits may also be used as the control module 130, or a control module 130 for controlling the switch module 114 may also be separately configured.
[0093] In this embodiment, the short circuit between the first detection pseudo bit line 1131 and the bit line 112 can be effectively detected through the setting of the detection module 120. At the same time, through the setting of the control module 130 and the switch module 114, when there is a short circuit between the first detection pseudo bit line 1131 and the bit line 112, the first switch 1141 can be disconnected, thereby disconnecting the circuit between the first detection pseudo bit line 1131 and the access end of the first power supply voltage V1. At this time, the first detection pseudo bit line 1131 is no longer connected to the first power supply voltage V1, so that the voltage on the bit line 112 will not be abnormal due to the influence of the first power supply voltage V1. At this time, when the aging test is continued, the influence of the short circuit between the pseudo bit line 113 and the bit line 112 on the aging test can be effectively reduced, which is convenient for effectively discovering other hidden problems, thereby accelerating the research and development progress.
[0094] In one embodiment, see Figure 6 , the plurality of dummy bit lines 113 also include a second detection dummy bit line 1132 .
[0095] The second detection dummy bit line 1132 and the bit line 112 are respectively located on both sides of the first detection dummy bit line 1131. That is, compared with the first detection dummy bit line 1131, the second detection dummy bit line 1132 is farther from the bit line 112.
[0096] The second detection dummy bit line 1132 is connected to the switch module 114 to access the first power supply voltage V1 through the switch module 114 .
[0097] As an example, both sides of the region where the plurality of bit lines 112 are located may also be provided with second detection dummy bit lines 1132. At this time, both second detection dummy bit lines 1132 located on both sides of the region where the plurality of bit lines 112 are located may be connected to the switch module 114.
[0098] Meanwhile, on the same side of the region where the plurality of bit lines 112 are located, the number of the second detection dummy bit lines 1132 may be one or more, and there is no limitation thereto.
[0099] The short circuit between the first detection dummy bit line 1131 and the bit line 112 is the main reason for the abnormal voltage of the bit line 112. Meanwhile, other dummy bit lines 113 and the bit line 112 may also be short-circuited to cause the abnormal voltage of the bit line 112.
[0100] Therefore, as an example, it is possible to determine whether a short circuit exists between the second detection dummy bit line 1132 and the bit line 112 by detecting a voltage on the bit line 112 (eg, the bit line 112 adjacent to the first detection dummy bit line 1131 ).
[0101] In the initial state of the aging test, the relevant switches in the switch module 114 can be turned on, so that the second detection pseudo bit line 1132 can be connected to the first power supply voltage V1. At the same time, the second power supply voltage V2 is connected to the bit line 112. Therefore. When there is a short circuit between the second detection pseudo bit line 1132 and the bit line 112, a leakage connection path will also be generated between the second detection pseudo bit line 1132 and the bit line 112, resulting in abnormal voltage values of the two. Based on this, it can be determined whether there is a short circuit between them by detecting the voltage of the second detection pseudo bit line 1132 and / or the bit line 112.
[0102] When a short circuit is detected between the second detection pseudo bit line 1132 and the bit line 112, the control module 130 can control the switch module 114 to disconnect the second detection pseudo bit line 1132 from the access end of the first power supply voltage V1, thereby effectively reducing the impact of the short circuit between the second detection pseudo bit line 1132 and the bit line 112 on the aging test results.
[0103] It is understandable that if the voltage on the bit line 112 (such as the bit line 112 adjacent to the first detection pseudo bit line 1131) is detected to determine whether there is a short circuit between the second detection pseudo bit line 1132 and the bit line 112, when the voltage on the bit line 112 is abnormal, it may be due to the short circuit between the first detection pseudo bit line 1131 and the bit line 112, or it may be due to the short circuit between the second detection pseudo bit line 1132 and the bit line 112. Therefore, at this time, the switch module 114 can be controlled by the control module 130 to disconnect the second detection pseudo bit line 1132 and the first detection pseudo bit line 1131 from the access end of the first power supply voltage V1, thereby ensuring that the voltage on the bit line 112 is maintained at the second power supply voltage V2 during the aging test.
[0104] In this embodiment, the second detection dummy bit line 1132 and the first detection dummy bit line 1131 are both connected to the switch module 114 , so that the reliability of the aging test can be further ensured.
[0105] In one embodiment, see Figure 6 The switch module 114 further includes a second switch 1142. One end of the second switch 1142 is connected to the second detection pseudo bit line 1132, and the other end is used to access the first power supply voltage V1.
[0106] As an example, both sides of the region where the plurality of bit lines 112 are located may also be provided with second detection dummy bit lines 1132. At this time, each second detection dummy bit line 1132 located on both sides of the region where the plurality of bit lines 112 are located may be connected to a corresponding second switch 1142.
[0107] When a short circuit occurs between the second detection pseudo bit line 1132 and the bit line 112, the second switch 1142 can be disconnected to disconnect the second detection pseudo bit line 1132 from the access end of the first power supply voltage V1, so that the second detection pseudo bit line 1132 is no longer connected to the first power supply voltage V1, thereby preventing it from affecting the voltage on the bit line 112.
[0108] The first detection dummy bit line 1131 and the second detection dummy bit line 1132 are connected to the first switch 1141 and the second switch 1142 respectively. The first switch 1141 and the second switch 1142 can be switched independently, so that the first detection dummy bit line 1131 and the second detection dummy bit line 1132 can be connected to or disconnected from the first power supply voltage V1 independently.
[0109] At this time, the first switch 1141 and the second switch 1142 can be switched on and off at the same time. For example, when determining whether there is a short circuit between the first detection dummy bit line 1131 (or the second detection dummy bit line 1132) and the bit line 112 by detecting the voltage on the bit line 112 (such as the bit line 112 adjacent to the first detection dummy bit line 1131), the first switch 1141 and the second switch 1142 can be turned off at the same time when the voltage on the bit line 112 is abnormal.
[0110] Of course, the first switch 1141 and the second switch 1142 may not be turned on and off at the same time. For example, when the voltage on the first detection pseudo bit line 1131 is detected to determine whether there is a short circuit between the first detection pseudo bit line 1131 and the bit line 112, and the voltage on the second detection pseudo bit line 1132 is detected to determine whether there is a short circuit between the second detection pseudo bit line 1132 and the bit line 112, the first switch 1141 and the second switch 1142 may be turned off independently of each other.
[0111] In one embodiment, the second detection dummy bit line 1132 is connected to an end of the first switch 1141 connected to the first detection dummy bit line 1131 .
[0112] At this time, the first detection dummy bit line 1131 and the second detection dummy bit line 1132 can both be controlled by the first switch 1141 to be connected to the first power supply voltage V1 , thereby effectively simplifying the circuit.
[0113] As an example, at this time, by detecting the voltage on the bit line 112 (such as the bit line 112 adjacent to the first detection pseudo bit line 1131), it can be determined whether there is a short circuit between the first detection pseudo bit line 1131 (or the second detection pseudo bit line 1132) and the bit line 112. Moreover, when the voltage on the bit line 112 is abnormal, the first switch 1141 can be turned off, so that the second detection pseudo bit line 1132 and the first detection pseudo bit line 1131 are both disconnected from the access terminal of the first power supply voltage V1.
[0114] In one embodiment, see Figure 6 , the second detection dummy bit line 1132 is adjacent to the first detection dummy bit line 1131 .
[0115] In the actual process, when the voltage on the bit line 112 is abnormal, the short circuit between the first detection pseudo bit line 1131 and the bit line 112 is the main reason for the abnormal voltage of the bit line 112. At the same time, other pseudo bit lines 113 and the bit line 112 may also be short-circuited to cause the abnormal voltage of the bit line 112. Moreover, the pseudo bit line 113 closer to the bit line 112 has a higher risk of short-circuiting with the bit line 112.
[0116] Therefore, the second detection dummy bit line 1132 is designed to be adjacent to the first detection dummy bit line 1131 , and the dummy bit line 113 with a greater risk of short circuit with the bit line 112 can be used as a detection dummy bit line, thereby improving the reliability of the aging test.
[0117] Of course, in other embodiments, a dummy bit line 1132 that is not adjacent to the first detection dummy bit line 1131 may also be set as the second detection dummy bit line 1132. The specific setting may be based on actual product requirements.
[0118] In one embodiment, the switch module 114 is a transistor-type switch module and is formed in the same layer as the transistor 1111 of the memory cell 111 .
[0119] For example, the first switch 1141 and / or the second switch 1142 are switch transistors. Also, the first switch 1141 and / or the second switch 1142 may be P-type switch transistors. Alternatively, the first switch 1141 and / or the second switch 1142 may also be N-type switch transistors.
[0120] At this time, the manufacturing process of the memory chip 100 can be simplified.
[0121] In one embodiment, see Fig. 9 , an aging test method is also provided, which is applied to any of the above-mentioned storage sub-array units 110. The aging test method can be, but is not limited to, executed by the control module 130 of the storage chip 100, and the aging test method includes:
[0122] Step S100, turning on the transistor 1111 of the memory cell 111, applying a reference voltage to the second electrode 1112b of the capacitor 1112, turning on the first switch 1141, and applying a second power supply voltage V2 to the bit line 112;
[0123] Step S200, detecting whether there is a short circuit between the first detection dummy bit line 1131 and the bit line 112;
[0124] Step S300 , when the first detection dummy bit line 1131 is short-circuited with the bit line 112 , the corresponding first switch 1141 is turned off to perform an aging test on the memory sub-array unit 110 .
[0125] In step S100, the transistor 1111 of the memory cell 111 may be a P-type transistor or an N-type transistor. When the transistor 1111 of the memory cell 111 is a P-type transistor, a low-level voltage may be applied to the gate of the transistor 1111 through the corresponding word line 115, thereby turning on the transistor 1111 of the memory cell 111. When the transistor 1111 of the memory cell 111 is an N-type transistor, a high-level voltage may be applied to the gate of the transistor 1111 through the corresponding word line 115, thereby turning on the transistor 1111 of the memory cell 111.
[0126] After the transistor 1111 of the memory cell 111 is turned on, the second power supply voltage V2 applied to the bit line 112 can be transmitted to the first electrode 1112a of the capacitor 1112. At the same time, the reference voltage is applied to the second electrode 1112b of the capacitor 1112.
[0127] At the same time, the first switch 1141 is turned on, so that in the initial state of the aging test, the first detection dummy bit line 1131 is connected to the first power supply voltage V1. The voltage value of the first power supply voltage V1 can be, for example, 0.5V, which is used to detect the reliability of the dummy bit line and the memory cell and provide a test voltage.
[0128] In step S200 , it is detected whether there is a short circuit between the first detection dummy bit line 1131 and the bit line 112 .
[0129] As an example, dummy bit lines 113 are provided on both sides of the region where the plurality of bit lines 112 of the storage sub-array unit 110 are located. At this time, the plurality of dummy bit lines 113 may include two first detection dummy bit lines 1131. The short circuit conditions of the two first detection dummy bit lines 1131 and the bit line 112 may be different. At this time, it is possible to detect whether there is a short circuit between the two first detection dummy bit lines 1131 and the bit line 112, so as to respectively detect and determine whether there is a short circuit between the two first detection dummy bit lines 1131 and the bit line 112.
[0130] In step S300 , when there is a short circuit between the first detection dummy bit line 1131 and the bit line 112 , the first switch 1141 corresponding to the first detection dummy bit line 1131 may be turned off first, and then the memory sub-array unit 110 may be subjected to an aging test.
[0131] When the plurality of dummy bit lines 113 may include two first detection dummy bit lines 1131, the switch module 114 correspondingly includes two first switches 1141. At this time, the two first switches 1141 can be turned on or off independently according to the short circuit between the corresponding first detection dummy bit line 1131 and the bit line 112.
[0132] After the first switch 1141 is turned off, the first detection pseudo bit line 1131 is no longer connected to the first power supply voltage V1. At this time, the voltage on the bit line 112 is abnormal due to the influence of the first power supply voltage V1, thereby effectively reducing the influence of the short circuit between the pseudo bit line 113 and the bit line 112 on the aging test, facilitating the effective discovery of other hidden problems, thereby accelerating the detection progress.
[0133] In one embodiment, after step S200, the method further includes:
[0134] Step S400 , when there is no short circuit between the first detection dummy bit line 1131 and the bit line 112 , the first switch 1141 is kept turned on to perform an aging test on the memory sub-array unit 110 .
[0135] When there is no short circuit between the first detection dummy bit line 1131 and the bit line 112 , the second power supply voltage V2 on the bit line 112 is not affected by the first power supply voltage V1 on the first detection dummy bit line 1131 .
[0136] At this time, the first switch 1141 is kept turned on, so that the first detection dummy bit line 1131 can be connected to the first power supply voltage V1 and maintain its related functions. For example, the first detection dummy bit line 1131 can continue to be used for the original reliability test.
[0137] In one embodiment, step S200 includes:
[0138] Step S210 , detecting a voltage on the bit line 112 adjacent to the first detection dummy bit line 1131 .
[0139] The short circuit between the first detection dummy bit line 1131 and the bit line 112 is the main reason for the abnormal voltage of the bit line 112 (especially the bit line 112 adjacent to the first detection dummy bit line 1131). Therefore, by detecting the voltage on the bit line 112 adjacent to the first detection dummy bit line 1131, it can be determined whether there is a short circuit between the first detection dummy bit line 1131 and the bit line 112.
[0140] At this time, since the first switch 1141 is turned on in step S100, the first detection pseudo bit line 1131 is connected to the first power supply voltage V1. At the same time, the second power supply voltage V2 is connected to the bit line 112. When there is a short circuit between the first detection pseudo bit line 1131 and the bit line 112, a leakage connection path will be generated between the two, resulting in abnormal voltage values of the two. Based on this, by detecting the voltage on the bit line 112 adjacent to the first detection pseudo bit line 1131, it can be determined whether there is a short circuit between the first detection pseudo bit line 1131 and the bit line 112.
[0141] In one embodiment, step S200 includes step S210 , ie, detecting whether the first detection dummy bit line 1131 and the bit line 112 are short-circuited by detecting a voltage on the bit line 112 adjacent to the first detection dummy bit line 1131 .
[0142] Meanwhile, in step S100 , while the first switch 1141 is turned on, the second switch 1142 is also turned on.
[0143] And, step S300 includes:
[0144] Step S310 , when the voltage on the bit line 112 adjacent to the first detection dummy bit line 1131 is abnormal, the corresponding first switch 1141 and the second switch 1142 are turned off to perform an aging test on the memory sub-array unit 110 .
[0145] One end of the second switch 1142 is connected to the second detection pseudo bit line 1132 of the plurality of pseudo bit lines 113, and the other end is used to access the first power supply voltage V1. The second detection pseudo bit line 1132 and the bit line 112 are located on both sides of the first detection pseudo bit line 1131 respectively.
[0146] As an example, both sides of the region where the plurality of bit lines 112 are located may also be provided with second detection dummy bit lines 1132. Meanwhile, on the same side of the region where the plurality of bit lines 112 are located, the number of second detection dummy bit lines 1132 may be one or more. Each second detection dummy bit line 1132 is connected to a corresponding second switch 1142.
[0147] During the preparation of the memory chip 100, multiple dummy bit lines 113 are formed on both sides of the region where the multiple bit lines 112 are located, thereby improving the uniformity of the multiple bit lines 112. However, at the same time, when there is a deviation in the process, a short circuit will occur between the dummy bit line 113 and the bit line 112. Among them, the first detection dummy bit line 1131 adjacent to the bit line 112 and closest to the bit line 112 is most likely to be short-circuited with the bit line 112, so the short circuit between the first detection dummy bit line 1131 and the bit line 112 is the main reason for the abnormal voltage of the bit line 112.
[0148] At the same time, other dummy bit lines 113 (such as the second detection dummy bit line 1132 ) and the bit line 112 may also be short-circuited, causing an abnormal voltage on the bit line 112 .
[0149] Therefore, when the voltage on the bit line 112 adjacent to the first detection pseudo bit line 1131 is detected to be abnormal, it may be due to a short circuit between the first detection pseudo bit line 1131 and the bit line 112 , or it may be due to a short circuit between other pseudo bit lines 113 and the bit line 112 .
[0150] Therefore, by simultaneously turning off the corresponding first switch 1141 and second switch 1142 , it is possible to effectively ensure that the voltage on the bit line 112 is normal.
[0151] It can be understood that when second detection pseudo bit lines 1132 are also provided on both sides of the area where the multiple bit lines 112 are located, when an abnormal voltage is detected on the bit line 112 adjacent to the first detection pseudo bit line 1131, the first switch 1141 and the second switch 1142 located on the same side of the area where the multiple bit lines 112 are located can be disconnected.
[0152] For example, when the voltage on the bit line 112 adjacent to the first detection pseudo bit line 1131 on one side is abnormal, the first switch 1141 and the second switch 1142 on one side of the region where the plurality of bit lines 112 are located may be disconnected. When the voltage on the bit line 112 adjacent to the first detection pseudo bit line 1131 on the other side is abnormal, the first switch 1141 and the second switch 1142 on the other side of the region where the plurality of bit lines 112 are located may be disconnected.
[0153] Meanwhile, as an example, when the voltage on the bit line 112 adjacent to the first detection dummy bit line 1131 is normal, the corresponding first switch 1141 and the second switch 1142 are kept turned on to perform an aging test on the memory sub-array unit 110 .
[0154] For example, when the voltage on the bit line 112 adjacent to the first detection pseudo bit line 1131 on one side is normal, the first switch 1141 and the second switch 1142 on one side of the region where the plurality of bit lines 112 are located can be kept turned on. When the voltage on the bit line 112 adjacent to the first detection pseudo bit line 1131 on the other side is normal, the first switch 1141 and the second switch 1142 on the other side of the region where the plurality of bit lines 112 are located can be kept turned on.
[0155] It should be understood that although Fig. 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Fig. 9At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0156] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0157] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0158] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A storage sub-array unit, characterized in that: include: A plurality of memory cells are arranged in a plurality of rows and columns, wherein the memory cells include transistors and capacitors, wherein within the same memory cell, a first region of the transistor is connected to a first electrode of the capacitor, and the first region is one of a source region and a drain region; A plurality of bit lines extending along the column direction of the memory cells and arranged along the row direction of the memory cells, wherein the same bit line is connected to the second region of the transistor located in the same column, the second region being the other of the source region and the drain region; A plurality of dummy bit lines extending along the column direction of the memory cells and arranged along the row direction of the memory cells, wherein in the row direction, the plurality of dummy bit lines are distributed on both sides of the region where the plurality of bit lines are located, and the plurality of dummy bit lines include a first detection dummy bit line, and the first detection dummy bit line is adjacent to the bit line; The switch module comprises a first switch, one end of which is connected to the first detection pseudo bit line, and the other end of which is used to access a first power supply voltage.
2. The storage subarray unit according to claim 1, characterized in that: The plurality of pseudo bit lines further include a second detection pseudo bit line, which is located on both sides of the first detection pseudo bit line and the bit line, and is connected to the switch module to access the first power supply voltage through the switch module.
3. The storage subarray unit according to claim 2, characterized in that: The switch module further includes a second switch, one end of which is connected to the second detection pseudo bit line, and the other end of which is used to access the first power supply voltage.
4. The storage subarray unit according to claim 2, characterized in that: The second detection dummy bit line is connected to one end of the first switch connected to the first detection dummy bit line.
5. The storage subarray unit according to claim 2, characterized in that: The second detection dummy bit line is adjacent to the first detection dummy bit line.
6. The storage subarray unit according to claim 1, characterized in that: The switch module is a transistor-type switch module and is formed in the same layer as the transistor of the storage unit.
7. The storage subarray unit according to claim 1, characterized in that: The voltage value of the first power supply voltage is 0.5V.
8. A memory chip, characterized in that: include: The storage subarray unit according to any one of claims 1 to 7; A detection module, used for detecting whether there is a short circuit between the first detection dummy bit line and the bit line; The control module is connected to the detection module and the switch module, and is used to disconnect the first switch when there is a short circuit between the first detection pseudo bit line and the bit line.
9. The memory chip according to claim 8, characterized in that: The storage sub-array unit comprises a sensing amplifier circuit, which is connected to the control module and is used for sensing and amplifying the voltage on the bit line.
10. A memory stick, characterized in that: include: A plurality of memory chips according to claim 8 or 9; A memory controller is connected to each of the memory chips and is used to control the memory chips.
11. An aging test method, applied to the storage sub-array unit according to any one of claims 1 to 7, characterized in that: include: Turning on the transistor of the memory cell, applying a reference voltage to the second electrode of the capacitor, turning on the first switch, and applying a second power supply voltage to the bit line; Detecting whether there is a short circuit between the first detection dummy bit line and the bit line; When the first detection pseudo bit line is short-circuited with the bit line, the corresponding first switch is turned off to perform an aging test on the memory sub-array unit.
12. The aging test method according to claim 11, characterized in that: When there is no short circuit between the first detection dummy bit line and the bit line, the first switch is kept turned on to perform an aging test on the memory sub-array unit.
13. The aging test method according to claim 11, characterized in that: The detecting whether there is a short circuit between the first detection dummy bit line and the bit line comprises: A voltage on the bit line adjacent to the first detection dummy bit line is detected.
14. The aging test method according to claim 13, characterized in that: While the first switch is turned on, the second switch is also turned on, and, When the first detection pseudo bit line is short-circuited with the bit line, the corresponding first switch is turned off to perform an aging test on the storage sub-array unit, including: When the voltage on the bit line adjacent to the first detection pseudo bit line is abnormal, disconnecting the corresponding first switch and second switch to perform an aging test on the memory sub-array unit; Among them, one end of the second switch is connected to the second detection pseudo bit line among the multiple pseudo bit lines, and the other end is used to access the first power supply voltage. The second detection pseudo bit line and the bit line are respectively located on both sides of the first detection pseudo bit line.
15. The aging test method according to claim 11, characterized in that: The voltage value of the first power supply voltage is 0.5V.